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Second Round Of Renesas ARM Based SoC DT Updates For v3.18

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* Tidy up interrupt-parents
 * Add clocks register defines for r8a7740 SoC
 * Add JPU clock to r8a7791 and r8a7790 SoCs
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Merge tag 'renesas-dt2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Second Round Of Renesas ARM Based SoC DT Updates For v3.18" from Simon Horman:

* Tidy up interrupt-parents
* Add clocks register defines for r8a7740 SoC
* Add JPU clock to r8a7791 and r8a7790 SoCs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* tag 'renesas-dt2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: sh73a0 dtsi: Move interrupt-parent to the top
  ARM: shmobile: r8a7791 dtsi: Remove superfluous interrupt-parent
  ARM: shmobile: r8a7790 dtsi: Remove superfluous interrupt-parent
  ARM: shmobile: r8a7779 dtsi: Remove superfluous interrupt-parent
  ARM: shmobile: r8a7740: clock register bits
  ARM: shmobile: r8a7791: Add JPU clock dt and CPG define.
  ARM: shmobile: r8a7790: Add JPU clock dt and CPG define.
This commit is contained in:
Arnd Bergmann 2014-09-05 16:28:56 +02:00
commit f60e660c5a
7 changed files with 86 additions and 37 deletions
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6
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -199,7 +199,6 @@
scif0: serial@ffe40000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe40000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
@ -209,7 +208,6 @@
scif1: serial@ffe41000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe41000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
@ -219,7 +217,6 @@
scif2: serial@ffe42000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe42000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
@ -229,7 +226,6 @@
scif3: serial@ffe43000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe43000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
@ -239,7 +235,6 @@
scif4: serial@ffe44000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe44000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";
@ -249,7 +244,6 @@
scif5: serial@ffe45000 {
compatible = "renesas,scif-r8a7779", "renesas,scif";
reg = <0xffe45000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg_clocks R8A7779_CLK_P>;
clock-names = "sci_ick";

7
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -836,17 +836,17 @@
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
<&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
>;
clock-output-names =
"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
"jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
"vsp1-du0", "vsp1-rt", "vsp1-sy";
};
mstp2_clks: mstp2_clks@e6150138 {
@ -1126,7 +1126,6 @@
rcar_sound: rcar_sound@0xec500000 {
#sound-dai-cells = <1>;
compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
interrupt-parent = <&gic>;
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */

7
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -857,16 +857,16 @@
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
renesas,clock-indices = <
R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
>;
clock-output-names =
"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
"jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
"vsp1-du0", "vsp1-sy";
};
mstp2_clks: mstp2_clks@e6150138 {
@ -1124,7 +1124,6 @@
rcar_sound: rcar_sound@0xec500000 {
#sound-dai-cells = <1>;
compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
interrupt-parent = <&gic>;
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */

24
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -14,6 +14,7 @@
/ {
compatible = "renesas,sh73a0";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
@ -54,7 +55,6 @@
<0xe6900020 1>,
<0xe6900040 1>,
<0xe6900060 1>;
interrupt-parent = <&gic>;
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
0 2 IRQ_TYPE_LEVEL_HIGH
0 3 IRQ_TYPE_LEVEL_HIGH
@ -74,7 +74,6 @@
<0xe6900024 1>,
<0xe6900044 1>,
<0xe6900064 1>;
interrupt-parent = <&gic>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
0 10 IRQ_TYPE_LEVEL_HIGH
0 11 IRQ_TYPE_LEVEL_HIGH
@ -95,7 +94,6 @@
<0xe6900028 1>,
<0xe6900048 1>,
<0xe6900068 1>;
interrupt-parent = <&gic>;
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
0 18 IRQ_TYPE_LEVEL_HIGH
0 19 IRQ_TYPE_LEVEL_HIGH
@ -115,7 +113,6 @@
<0xe690002c 1>,
<0xe690004c 1>,
<0xe690006c 1>;
interrupt-parent = <&gic>;
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
0 26 IRQ_TYPE_LEVEL_HIGH
0 27 IRQ_TYPE_LEVEL_HIGH
@ -131,7 +128,6 @@
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6820000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
0 168 IRQ_TYPE_LEVEL_HIGH
0 169 IRQ_TYPE_LEVEL_HIGH
@ -144,7 +140,6 @@
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6822000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
0 52 IRQ_TYPE_LEVEL_HIGH
0 53 IRQ_TYPE_LEVEL_HIGH
@ -157,7 +152,6 @@
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6824000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
0 172 IRQ_TYPE_LEVEL_HIGH
0 173 IRQ_TYPE_LEVEL_HIGH
@ -170,7 +164,6 @@
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6826000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
0 184 IRQ_TYPE_LEVEL_HIGH
0 185 IRQ_TYPE_LEVEL_HIGH
@ -183,7 +176,6 @@
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xe6828000 0x425>;
interrupt-parent = <&gic>;
interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
0 188 IRQ_TYPE_LEVEL_HIGH
0 189 IRQ_TYPE_LEVEL_HIGH
@ -194,7 +186,6 @@
mmcif: mmc@e6bd0000 {
compatible = "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
0 141 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
@ -204,7 +195,6 @@
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee100000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
0 84 IRQ_TYPE_LEVEL_HIGH
0 85 IRQ_TYPE_LEVEL_HIGH>;
@ -216,7 +206,6 @@
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee120000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
0 89 IRQ_TYPE_LEVEL_HIGH>;
toshiba,mmc-wrprotect-disable;
@ -227,7 +216,6 @@
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-sh73a0";
reg = <0xee140000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
0 105 IRQ_TYPE_LEVEL_HIGH>;
toshiba,mmc-wrprotect-disable;
@ -238,7 +226,6 @@
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6c40000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -246,7 +233,6 @@
scifa1: serial@e6c50000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6c50000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -254,7 +240,6 @@
scifa2: serial@e6c60000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6c60000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -262,7 +247,6 @@
scifa3: serial@e6c70000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6c70000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -270,7 +254,6 @@
scifa4: serial@e6c80000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6c80000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -278,7 +261,6 @@
scifa5: serial@e6cb0000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6cb0000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -286,7 +268,6 @@
scifa6: serial@e6cc0000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6cc0000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -294,7 +275,6 @@
scifa7: serial@e6cd0000 {
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
reg = <0xe6cd0000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -302,7 +282,6 @@
scifb8: serial@e6c30000 {
compatible = "renesas,scifb-sh73a0", "renesas,scifb";
reg = <0xe6c30000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -328,7 +307,6 @@
#sound-dai-cells = <1>;
compatible = "renesas,sh_fsi2";
reg = <0xec230000 0x400>;
interrupt-parent = <&gic>;
interrupts = <0 146 0x4>;
status = "disabled";
};

77
include/dt-bindings/clock/r8a7740-clock.h Normal file
View File

@ -0,0 +1,77 @@
/*
* Copyright 2014 Ulrich Hecht
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
#define __DT_BINDINGS_CLOCK_R8A7740_H__
/* CPG */
#define R8A7740_CLK_SYSTEM 0
#define R8A7740_CLK_PLLC0 1
#define R8A7740_CLK_PLLC1 2
#define R8A7740_CLK_PLLC2 3
#define R8A7740_CLK_R 4
#define R8A7740_CLK_USB24S 5
#define R8A7740_CLK_I 6
#define R8A7740_CLK_ZG 7
#define R8A7740_CLK_B 8
#define R8A7740_CLK_M1 9
#define R8A7740_CLK_HP 10
#define R8A7740_CLK_HPP 11
#define R8A7740_CLK_USBP 12
#define R8A7740_CLK_S 13
#define R8A7740_CLK_ZB 14
#define R8A7740_CLK_M3 15
#define R8A7740_CLK_CP 16
/* MSTP1 */
#define R8A7740_CLK_CEU21 28
#define R8A7740_CLK_CEU20 27
#define R8A7740_CLK_TMU0 25
#define R8A7740_CLK_LCDC1 17
#define R8A7740_CLK_IIC0 16
#define R8A7740_CLK_TMU1 11
#define R8A7740_CLK_LCDC0 0
/* MSTP2 */
#define R8A7740_CLK_SCIFA6 30
#define R8A7740_CLK_SCIFA7 22
#define R8A7740_CLK_DMAC1 18
#define R8A7740_CLK_DMAC2 17
#define R8A7740_CLK_DMAC3 16
#define R8A7740_CLK_USBDMAC 14
#define R8A7740_CLK_SCIFA5 7
#define R8A7740_CLK_SCIFB 6
#define R8A7740_CLK_SCIFA0 4
#define R8A7740_CLK_SCIFA1 3
#define R8A7740_CLK_SCIFA2 2
#define R8A7740_CLK_SCIFA3 1
#define R8A7740_CLK_SCIFA4 0
/* MSTP3 */
#define R8A7740_CLK_CMT1 29
#define R8A7740_CLK_FSI 28
#define R8A7740_CLK_IIC1 23
#define R8A7740_CLK_USBF 20
#define R8A7740_CLK_SDHI0 14
#define R8A7740_CLK_SDHI1 13
#define R8A7740_CLK_MMC 12
#define R8A7740_CLK_GETHER 9
#define R8A7740_CLK_TPU0 4
/* MSTP4 */
#define R8A7740_CLK_USBH 16
#define R8A7740_CLK_SDHI2 15
#define R8A7740_CLK_USBFUNC 7
#define R8A7740_CLK_USBPHY 6
/* SUBCK* */
#define R8A7740_CLK_SUBCK 9
#define R8A7740_CLK_SUBCK2 10
#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */

1
include/dt-bindings/clock/r8a7790-clock.h
View File

@ -26,6 +26,7 @@
#define R8A7790_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7790_CLK_JPU 6
#define R8A7790_CLK_TMU1 11
#define R8A7790_CLK_TMU3 21
#define R8A7790_CLK_TMU2 22

1
include/dt-bindings/clock/r8a7791-clock.h
View File

@ -25,6 +25,7 @@
#define R8A7791_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7791_CLK_JPU 6
#define R8A7791_CLK_TMU1 11
#define R8A7791_CLK_TMU3 21
#define R8A7791_CLK_TMU2 22