Commit Graph

224 Commits

Author SHA1 Message Date
YueHaibing
5da42a3d25 pinctrl: qcom: Remove duplicated include from pinctrl-msm.c
Remove duplicated include.

Fixes: 13bec8d49b ("pinctrl: qcom: use scm_call to route GPIO irq to Apps")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200408070504.134847-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-04-17 12:24:52 +02:00
Linus Torvalds
bc3b3f4bfb This is the bulk of pin control changes for the v5.7 kernel cycle.
There are no core changes this time, only driver developments.
 
 - New driver for the Dialog Semiconductor DA9062 Power Management
   Integrated Circuit (PMIC).
 
 - Renesas SH-PFC has improved consistency, with group and
   register checks in the configuration checker.
 
 - New subdriver for the Qualcomm IPQ6018.
 
 - Add the RGMII pin control functionality to Qualcomm IPQ8064.
 
 - Performance and code quality cleanups in the Mediatek
   driver.
 
 - Improve the Broadcom BCM2835 support to cover all the GPIOs
   that exist in it.
 
 - The Allwinner/Sunxi driver properly masks non-wakeup IRQs on
   suspend.
 
 - Add some missing groups and functions to the Ingenic driver.
 
 - Convert some of the Freescale device tree bindings to use the
   new and all improved JSON YAML markup.
 
 - Refactorings and support for the SFIO/GPIO in the Tegra194
   SoC driver.
 
 - Support high impedance mode in the Spreadtrum/Unisoc driver.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl6FlRoACgkQQRCzN7AZ
 XXPiAxAAuAvY07H739YF4ANvtLpfbtz0KBK4M2XGiD41VMcp5MhZtT9TdXAIRisb
 W4QMHbMxhwO4gdxmhVOetXeQNQnHch4oPsFyd1UdyuwNEtvlm8qst99VcdQPz7Jv
 zyL4cat1fTrwdcnLQl5eaJR7a9bKLqAd4rlb/suQZsaVf+URUWJyZBuU41GEx9A+
 w+EPv8doxTWRaE0NpafIwNCLxTR3i2Vt59fkRT4pSi8fTu9/Zv5yW8yWvbYZdlaO
 2bUaFjN65oyiikjPTgyQxb95A8yDJHkNnkgfTw4ghCY/k8u3GvMfKS7V1tO+nq6B
 bkv9E3jR1u7Ktkq1rLshS2eycl02uSJ3OmzyfL8S/GQxVdUPi3+X3hmyv2ctbEvC
 qy+7F6zx/Pt/WdPnAisdsVai9T3/YGoSN1C3n7Ufltjcrt0w5xP7/AgEVR4nHHMP
 NMWNoauGWsBDKtYPG7beX3thjkm3mUpezcEOxho7+r5tOtBaU623pWr+NHEPZu48
 8oKOCILaUkacUmmMjjOzraAeOxV7Ut+xumu0mgMj0EjZfJZDrgQsqkmfMbGcU5Fa
 y4S5+tAd+cELXveLVJB3Ml9u1R037x8VtAv+Z2a7qVnf1gSgf0bpAJ+SnfC/XbLX
 fBpSCsIMXSpioVNuS9gbkpnfsRPcTOrOXyxinP5onI8AHlIj1Rg=
 =1ZKq
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.7 kernel cycle.

  There are no core changes this time, only driver developments:

   - New driver for the Dialog Semiconductor DA9062 Power Management
     Integrated Circuit (PMIC).

   - Renesas SH-PFC has improved consistency, with group and register
     checks in the configuration checker.

   - New subdriver for the Qualcomm IPQ6018.

   - Add the RGMII pin control functionality to Qualcomm IPQ8064.

   - Performance and code quality cleanups in the Mediatek driver.

   - Improve the Broadcom BCM2835 support to cover all the GPIOs that
     exist in it.

   - The Allwinner/Sunxi driver properly masks non-wakeup IRQs on
     suspend.

   - Add some missing groups and functions to the Ingenic driver.

   - Convert some of the Freescale device tree bindings to use the new
     and all improved JSON YAML markup.

   - Refactorings and support for the SFIO/GPIO in the Tegra194 SoC
     driver.

   - Support high impedance mode in the Spreadtrum/Unisoc driver"

* tag 'pinctrl-v5.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (64 commits)
  pinctrl: qcom: fix compilation error
  pinctrl: qcom: use scm_call to route GPIO irq to Apps
  pinctrl: sprd: Add pin high impedance mode support
  pinctrl: sprd: Use the correct pin output configuration
  pinctrl: tegra: Add SFIO/GPIO programming on Tegra194
  pinctrl: tegra: Renumber the GG.0 and GG.1 pins
  pinctrl: tegra: Do not add default pin range on Tegra194
  pinctrl: tegra: Pass struct tegra_pmx for pin range check
  pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo
  pinctrl: tegra: Fix whitespace issues for improved readability
  pinctrl: mediatek: Use scnprintf() for avoiding potential buffer overflow
  pinctrl: freescale: drop the dependency on ARM64 for i.MX8M
  Revert "pinctrl: mvebu: armada-37xx: use use platform api"
  dt-bindings: pinctrl: at91: Fix a typo ("descibe")
  pinctrl: meson: add tsin pinctrl for meson gxbb/gxl/gxm
  pinctrl: sprd: Fix the kconfig warning
  pinctrl: ingenic: add hdmi-ddc pin control group
  pinctrl: sirf/atlas7: Replace zero-length array with flexible-array member
  pinctrl: sprd: Allow the SPRD pinctrl driver building into a module
  pinctrl: Export some needed symbols at module load time
  ...
2020-04-02 15:47:18 -07:00
Ansuel Smith
c42f69b420 pinctrl: qcom: fix compilation error
pinctrl: qcom: use scm_call to route GPIO irq to Apps has a typo in the
patch and introduced a compilation error.

Fixes: 13bec8d4 pinctrl: qcom: use scm_call to route GPIO irq to Apps
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200331134603.13513-1-ansuelsmth@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-31 16:43:54 +02:00
Ajay Kishore
13bec8d49b pinctrl: qcom: use scm_call to route GPIO irq to Apps
For IPQ806x targets, TZ protects the registers that are used to
configure the routing of interrupts to a target processor.
To resolve this, this patch uses scm call to route GPIO interrupts
to application processor. Also the scm call interface is changed.

Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-28 00:36:18 +01:00
Linus Walleij
1cada2f307 pinctrl: qcom: Assign irq_eoi conditionally
The hierarchical parts of MSM pinctrl/GPIO is only
used when the device tree has a "wakeup-parent" as
a phandle, but the .irq_eoi is anyway assigned leading
to semantic problems on elder Qualcomm chipsets.

When the drivers/mfd/qcom-pm8xxx.c driver calls
chained_irq_exit() that call will in turn call chip->irq_eoi()
which is set to irq_chip_eoi_parent() by default on a
hierachical IRQ chip, and the parent is pinctrl-msm.c
so that will in turn unconditionally call
irq_chip_eoi_parent() again, but its parent is invalid
so we get the following crash:

 Unnable to handle kernel NULL pointer dereference at
 virtual address 00000010
 pgd = (ptrval)
 [00000010] *pgd=00000000
 Internal error: Oops: 5 [#1] PREEMPT SMP ARM
 (...)
 PC is at irq_chip_eoi_parent+0x4/0x10
 LR is at pm8xxx_irq_handler+0x1b4/0x2d8

If we solve this crash by avoiding to call up to
irq_chip_eoi_parent(), the machine will hang and get
reset by the watchdog, because of semantic issues,
probably inside irq_chip.

As a solution, just assign the .irq_eoi conditionally if
we are actually using a wakeup parent.

Cc: David Heidelberg <david@ixit.cz>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: stable@vger.kernel.org
Fixes: e35a6ae0eb ("pinctrl/msm: Setup GPIO chip in hierarchy")
Link: https://lore.kernel.org/r/20200306121221.1231296-1-linus.walleij@linaro.org
Link: https://lore.kernel.org/r/20200309125207.571840-1-linus.walleij@linaro.org
Link: https://lore.kernel.org/r/20200309152604.585112-1-linus.walleij@linaro.org
Tested-by: David Heidelberg <david@ixit.cz>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-09 16:31:34 +01:00
Linus Walleij
f98371476f pinctrl: qcom: ssbi-gpio: Fix fwspec parsing bug
We are parsing SSBI gpios as fourcell fwspecs but they are
twocell. Probably a simple copy-and-paste bug.

Tested on the APQ8060 DragonBoard and after this ethernet
and MMC card detection works again.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: stable@vger.kernel.org
Reviewed-by: Brian Masney <masneyb@onstation.org>
Fixes: ae436fe810 ("pinctrl: ssbi-gpio: convert to hierarchical IRQ helpers in gpio core")
Link: https://lore.kernel.org/r/20200306143416.1476250-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-03-09 13:52:37 +01:00
Ansuel Smith
8d8cec9bf6 ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
Add missing gpio definition for mdio and rgmii2.

Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-21 16:23:26 +01:00
Matti Vaittinen
3c82787359 pinctrl: Use new GPIO_LINE_DIRECTION
Use newly added GPIO defines GPIO_LINE_DIRECTION_IN and
GPIO_LINE_DIRECTION_OUT instead of using hard-coded 1 and 0.

Main benefit is to make it easier to see which values mean IN and which
OUT. As a side effect this helps GPIO framework to change the direction
defines to something else if ever needed.

Please note that return value from get_direction call on
pinctrl-axp209 driver was changed. Previously pinctrl-axp209 might have
returned value 2 for direction INPUT.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Reported-by: kbuild test robot <lkp@intel.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Link: https://lore.kernel.org/r/20200214135712.GA14557@localhost.localdomain
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-21 15:19:42 +01:00
Sricharan R
ef1ea54eab pinctrl: qcom: Add ipq6018 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for ipq6018.

Co-developed-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Link: https://lore.kernel.org/r/1579439601-14810-3-git-send-email-sricharan@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-02-14 11:17:04 +01:00
Linus Torvalds
6ba3d7066c This is the bulk of pin control changes for the v5.6 kernel cycle:
Core changes:
 
 - Dropped the chained IRQ setup callback into GPIOLIB as we
   got rid of the last users of that in this changeset.
 
 New drivers:
 
 - New driver for Ingenic X1830.
 
 - New driver for Freescale i.MX8MP.
 
 Driver enhancements:
 
 - Fix all remaining Intel drivers to pass their IRQ chips
   along with the GPIO chips.
 
 - Intel Baytrail allocates its irqchip dynamically.
 
 - Intel Lynxpoint is thoroughly rewritten and modernized.
 
 - Aspeed AST2600 pin muxing and configuration is much
   improved.
 
 - Qualcomm SC7180 functions are updated and wakeup interrupt
   map is provided.
 
 - A whole slew of Renesas SH-PFC cleanups and improvements.
 
 - Fix up the Intel DT bindings to use the generic YAML
   DT bindings schema. (A first user of this.)
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl4xQIkACgkQQRCzN7AZ
 XXNchQ/8C4+SAMMcDQm4sIWV1duebynrXuebISqWMhAtYDRjCsRpGCqVSt+iSWod
 z29pJ/sm0xpG1Bz0bmDZ4oFv7u7+J89a/0Kl4OqI1pbO97Uadu2qGmYxZf2tMtlH
 CwWVOUAldU9scogRD6Z+qixYdRRpKufpaVaU7ooubHocmgRtzd/VCT2MX76c3w7j
 1+yHjoAKM59jpOD/8oEucEYB+5ngyTiMXo3Nms/6ciq52GdtMLE8nK+t7dM+xNLL
 hMQP95iQ2Xb+cM/bv+vdMyKF6vRxKkkeQ/hWcivGWgdI/BSFg0vCq0mWdc8qWp8k
 VeIBaTVh5wuaAdkir9dHX/zt6TsRV8ktv88jW773/z4jHr/8PmQUyFMyEA1u1haP
 yrC/vm4eL6QWCAZeATra5+5FoH2ljzwaY2rgeU0hNixjaF/aIp3GPci7+YmKHTIr
 5zZTXKAeuC/nV7g77w4O9iwn+SHWPytWBrfNZ7unyV5fl4XHckY2vNBa/g8xkYyb
 FBk642EwHRGCULb8m40+cB7TMUzk9aluXge1detJDbqlr2i+tSOWp1c3GSavLl1L
 4qRAAS2j6de1H/EaoO7EcArVrSMdPgLdpRmwCMc2xvL0HOprl6y+5iL7x86ZtQHu
 NHvgnjtw6Z6t9n28f5ZI1iEXUA6EHOHHc/sPPUqScCj4v85B25A=
 =PnK5
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes, nothing too exciting about
  this.

  Some changes hit arch/sh and arch/arm but are well isolated and
  acknowledged by the respective arch maintainers.

  Core changes:

   - Dropped the chained IRQ setup callback into GPIOLIB as we got rid
     of the last users of that in this changeset.

  New drivers:

   - New driver for Ingenic X1830.

   - New driver for Freescale i.MX8MP.

  Driver enhancements:

   - Fix all remaining Intel drivers to pass their IRQ chips along with
     the GPIO chips.

   - Intel Baytrail allocates its irqchip dynamically.

   - Intel Lynxpoint is thoroughly rewritten and modernized.

   - Aspeed AST2600 pin muxing and configuration is much improved.

   - Qualcomm SC7180 functions are updated and wakeup interrupt map is
     provided.

   - A whole slew of Renesas SH-PFC cleanups and improvements.

   - Fix up the Intel DT bindings to use the generic YAML DT bindings
     schema (a first user of this)"

* tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: madera: Remove extra blank line
  pinctrl: qcom: Don't lock around irq_set_irq_wake()
  pinctrl: mvebu: armada-37xx: use use platform api
  gpio: Drop the chained IRQ handler assign function
  pinctrl: freescale: Add i.MX8MP pinctrl driver support
  dt-bindings: imx: Add pinctrl binding doc for i.MX8MP
  pinctrl: tigerlake: Tiger Lake uses _HID enumeration
  pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID
  pinctrl: iproc: Use platform_get_irq_optional() to avoid error message
  pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema
  pinctrl: intel: Pass irqchip when adding gpiochip
  pinctrl: intel: Add GPIO <-> pin mapping ranges via callback
  pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output
  pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins
  pinctrl: sunrisepoint: Add missing Interrupt Status register offset
  pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers
  pinctrl: artpec6: fix __iomem on reg in set
  pinctrl: ingenic: Use devm_platform_ioremap_resource()
  pinctrl: ingenic: Factorize irq_set_type function
  pinctrl: ingenic: Remove duplicated ingenic_chip_info structures
  ...
2020-01-29 09:51:36 -08:00
Stephen Boyd
1d44616e75 pinctrl: qcom: Don't lock around irq_set_irq_wake()
We don't need to hold the local pinctrl lock here to set irq wake on the
summary irq line. Doing so only leads to lockdep warnings instead of
protecting us from anything. Remove the locking.

 WARNING: possible circular locking dependency detected
 5.4.11 #2 Tainted: G        W
 ------------------------------------------------------
 cat/3083 is trying to acquire lock:
 ffffff81f4fa58c0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94

 but task is already holding lock:
 ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c

 which lock already depends on the new lock.

 the existing dependency chain (in reverse order) is:

 -> #1 (&pctrl->lock){-.-.}:
        _raw_spin_lock_irqsave+0x64/0x80
        msm_gpio_irq_ack+0x68/0xf4
        __irq_do_set_handler+0xe0/0x180
        __irq_set_handler+0x60/0x9c
        irq_domain_set_info+0x90/0xb4
        gpiochip_hierarchy_irq_domain_alloc+0x110/0x200
        __irq_domain_alloc_irqs+0x130/0x29c
        irq_create_fwspec_mapping+0x1f0/0x300
        irq_create_of_mapping+0x70/0x98
        of_irq_get+0xa4/0xd4
        spi_drv_probe+0x4c/0xb0
        really_probe+0x138/0x3f0
        driver_probe_device+0x70/0x140
        __device_attach_driver+0x9c/0x110
        bus_for_each_drv+0x88/0xd0
        __device_attach+0xb0/0x160
        device_initial_probe+0x20/0x2c
        bus_probe_device+0x34/0x94
        device_add+0x35c/0x3f0
        spi_add_device+0xbc/0x194
        of_register_spi_devices+0x2c8/0x408
        spi_register_controller+0x57c/0x6fc
        spi_geni_probe+0x260/0x328
        platform_drv_probe+0x90/0xb0
        really_probe+0x138/0x3f0
        driver_probe_device+0x70/0x140
        device_driver_attach+0x4c/0x6c
        __driver_attach+0xcc/0x154
        bus_for_each_dev+0x84/0xcc
        driver_attach+0x2c/0x38
        bus_add_driver+0x108/0x1fc
        driver_register+0x64/0xf8
        __platform_driver_register+0x4c/0x58
        spi_geni_driver_init+0x1c/0x24
        do_one_initcall+0x1a4/0x3e8
        do_initcall_level+0xb4/0xcc
        do_basic_setup+0x30/0x48
        kernel_init_freeable+0x124/0x1a8
        kernel_init+0x14/0x100
        ret_from_fork+0x10/0x18

 -> #0 (&irq_desc_lock_class){-.-.}:
        __lock_acquire+0xeb4/0x2388
        lock_acquire+0x1cc/0x210
        _raw_spin_lock_irqsave+0x64/0x80
        __irq_get_desc_lock+0x64/0x94
        irq_set_irq_wake+0x40/0x144
        msm_gpio_irq_set_wake+0x5c/0x7c
        set_irq_wake_real+0x40/0x5c
        irq_set_irq_wake+0x70/0x144
        cros_ec_rtc_suspend+0x38/0x4c
        platform_pm_suspend+0x34/0x60
        dpm_run_callback+0x64/0xcc
        __device_suspend+0x310/0x41c
        dpm_suspend+0xf8/0x298
        dpm_suspend_start+0x84/0xb4
        suspend_devices_and_enter+0xbc/0x620
        pm_suspend+0x210/0x348
        state_store+0xb0/0x108
        kobj_attr_store+0x14/0x24
        sysfs_kf_write+0x4c/0x64
        kernfs_fop_write+0x15c/0x1fc
        __vfs_write+0x54/0x18c
        vfs_write+0xe4/0x1a4
        ksys_write+0x7c/0xe4
        __arm64_sys_write+0x20/0x2c
        el0_svc_common+0xa8/0x160
        el0_svc_handler+0x7c/0x98
        el0_svc+0x8/0xc

 other info that might help us debug this:

  Possible unsafe locking scenario:

        CPU0                    CPU1
        ----                    ----
   lock(&pctrl->lock);
                                lock(&irq_desc_lock_class);
                                lock(&pctrl->lock);
   lock(&irq_desc_lock_class);

  *** DEADLOCK ***

 7 locks held by cat/3083:
  #0: ffffff81f06d1420 (sb_writers#7){.+.+}, at: vfs_write+0xd0/0x1a4
  #1: ffffff81c8935680 (&of->mutex){+.+.}, at: kernfs_fop_write+0x12c/0x1fc
  #2: ffffff81f4c322f0 (kn->count#337){.+.+}, at: kernfs_fop_write+0x134/0x1fc
  #3: ffffffe89a641d60 (system_transition_mutex){+.+.}, at: pm_suspend+0x108/0x348
  #4: ffffff81f190e970 (&dev->mutex){....}, at: __device_suspend+0x168/0x41c
  #5: ffffff81f183d8c0 (lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94
  #6: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c

 stack backtrace:
 CPU: 4 PID: 3083 Comm: cat Tainted: G        W         5.4.11 #2
 Hardware name: Google Cheza (rev3+) (DT)
 Call trace:
  dump_backtrace+0x0/0x174
  show_stack+0x20/0x2c
  dump_stack+0xc8/0x124
  print_circular_bug+0x2ac/0x2c4
  check_noncircular+0x1a0/0x1a8
  __lock_acquire+0xeb4/0x2388
  lock_acquire+0x1cc/0x210
  _raw_spin_lock_irqsave+0x64/0x80
  __irq_get_desc_lock+0x64/0x94
  irq_set_irq_wake+0x40/0x144
  msm_gpio_irq_set_wake+0x5c/0x7c
  set_irq_wake_real+0x40/0x5c
  irq_set_irq_wake+0x70/0x144
  cros_ec_rtc_suspend+0x38/0x4c
  platform_pm_suspend+0x34/0x60
  dpm_run_callback+0x64/0xcc
  __device_suspend+0x310/0x41c
  dpm_suspend+0xf8/0x298
  dpm_suspend_start+0x84/0xb4
  suspend_devices_and_enter+0xbc/0x620
  pm_suspend+0x210/0x348
  state_store+0xb0/0x108
  kobj_attr_store+0x14/0x24
  sysfs_kf_write+0x4c/0x64
  kernfs_fop_write+0x15c/0x1fc
  __vfs_write+0x54/0x18c
  vfs_write+0xe4/0x1a4
  ksys_write+0x7c/0xe4
  __arm64_sys_write+0x20/0x2c
  el0_svc_common+0xa8/0x160
  el0_svc_handler+0x7c/0x98
  el0_svc+0x8/0xc

Fixes: 6aced33f49 ("pinctrl: msm: drop wake_irqs bitmap")
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Brian Masney <masneyb@onstation.org>
Cc: Lina Iyer <ilina@codeaurora.org>
Cc: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20200121180950.36959-1-swboyd@chromium.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-24 00:31:41 +01:00
Kevin Hao
2425876167 gpiolib: Add support for the irqdomain which doesn't use irq_fwspec as arg
Some gpio's parent irqdomain may not use the struct irq_fwspec as
argument, such as msi irqdomain. So rename the callback
populate_parent_fwspec() to populate_parent_alloc_arg() and make it
allocate and populate the specific struct which is needed by the
parent irqdomain.

Signed-off-by: Kevin Hao <haokexin@gmail.com>
Link: https://lore.kernel.org/r/20200114082821.14015-3-haokexin@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-15 11:17:44 +01:00
Julia Lawall
8b1704bde1 pinctrl: qcom: ssbi-gpio: constify copied structure
The pm8xxx_pinctrl_desc structure is only copied into another
structure, so make it const.

The opportunity for this change was found using Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>

Link: https://lore.kernel.org/r/1577864614-5543-15-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07 13:55:55 +01:00
Julia Lawall
a2800cdb43 pinctrl: ssbi-mpp: constify copied structure
The pm8xxx_pinctrl_desc structure is only copied into another structure,
so make it const.

The opportunity for this change was found using Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>

Link: https://lore.kernel.org/r/1577864614-5543-9-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07 13:55:55 +01:00
Ben Dooks (Codethink)
a9a79514c2 pinctrl: qcom: make 'm_voc_groups' static
The m_voc_groups is not declared outside of the
driver, so make it static to avoid the following
sparse wanrning:

drivers/pinctrl/qcom/pinctrl-msm8976.c:592:12: warning: symbol 'm_voc_groups' was not declared. Should it be static?

Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20191218102804.2487374-1-ben.dooks@codethink.co.uk
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-07 10:40:13 +01:00
Rajendra Nayak
f4a73f5e26 pinctrl: qcom: sc7180: Add new qup functions
on sc7180 we have cases where multiple functions from the same
qup instance share the same pin. This is true for qup02/04/11 and qup13.
Add new function names to distinguish which qup function to use.

The device tree files for this platform haven't landed in mainline yet,
so there aren't any users upstream who should break with this change
in function names, however, anyone using the devicetree files that were
posted on the lists and using these specific function names will need
to update their changes.

Reported-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/0101016ef36a9118-f2919277-effa-4cd5-adf8-bbc8016f31df-000000@us-west-2.amazonses.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-16 09:39:21 +01:00
Maulik Shah
6ece6d15c0 pinctrl: qcom: sc7180: Add GPIO wakeup interrupt map
GPIOs that can be configured as wakeup sources, have their
interrupt lines routed to PDC interrupt controller.

Provide the interrupt map of the GPIO to its wakeup capable
interrupt parent.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Link: https://lore.kernel.org/r/1572419178-5750-2-git-send-email-mkshah@codeaurora.org
Reviewed-by: Lina Iyer <ilina@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-16 09:19:00 +01:00
Linus Torvalds
b22bfea7f1 Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Ingo Molnar:
 "Most of the IRQ subsystem changes in this cycle were irq-chip driver
  updates:

   - Qualcomm PDC wakeup interrupt support

   - Layerscape external IRQ support

   - Broadcom bcm7038 PM and wakeup support

   - Ingenic driver cleanup and modernization

   - GICv3 ITS preparation for GICv4.1 updates

   - GICv4 fixes

  There's also the series from Frederic Weisbecker that fixes memory
  ordering bugs for the irq-work logic, whose primary fix is to turn
  work->irq_work.flags into an atomic variable and then convert the
  complex (and buggy) atomic_cmpxchg() loop in irq_work_claim() into a
  much simpler atomic_fetch_or() call.

  There are also various smaller cleanups"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
  pinctrl/sdm845: Add PDC wakeup interrupt map for GPIOs
  pinctrl/msm: Setup GPIO chip in hierarchy
  irqchip/qcom-pdc: Add irqchip set/get state calls
  irqchip/qcom-pdc: Add irqdomain for wakeup capable GPIOs
  irqchip/qcom-pdc: Do not toggle IRQ_ENABLE during mask/unmask
  irqchip/qcom-pdc: Update max PDC interrupts
  of/irq: Document properties for wakeup interrupt parent
  genirq: Introduce irq_chip_get/set_parent_state calls
  irqdomain: Add bus token DOMAIN_BUS_WAKEUP
  genirq: Fix function documentation of __irq_alloc_descs()
  irq_work: Fix IRQ_WORK_BUSY bit clearing
  irqchip/ti-sci-inta: Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(...))
  irq_work: Slightly simplify IRQ_WORK_PENDING clearing
  irq_work: Fix irq_work_claim() memory ordering
  irq_work: Convert flags to atomic_t
  irqchip: Ingenic: Add process for more than one irq at the same time.
  irqchip: ingenic: Alloc generic chips from IRQ domain
  irqchip: ingenic: Get virq number from IRQ domain
  irqchip: ingenic: Error out if IRQ domain creation failed
  irqchip: ingenic: Drop redundant irq_suspend / irq_resume functions
  ...
2019-12-03 09:29:50 -08:00
Krzysztof Kozlowski
2635adb48b pinctrl: Fix Kconfig indentation
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
	$ sed -e 's/^        /\t/' -i */Kconfig

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

Link: https://lore.kernel.org/r/1574306382-32516-1-git-send-email-krzk@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-21 15:06:07 +01:00
Lina Iyer
585d1183ff pinctrl/sdm845: Add PDC wakeup interrupt map for GPIOs
Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC.

Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-10-git-send-email-ilina@codeaurora.org
2019-11-16 10:23:48 +00:00
Lina Iyer
e35a6ae0eb pinctrl/msm: Setup GPIO chip in hierarchy
Some GPIOs are marked as wakeup capable and are routed to another
interrupt controller that is an always-domain and can detect interrupts
even when most of the SoC is powered off. The wakeup interrupt
controller wakes up the GIC and replays the interrupt at the GIC.

Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller
and ensure the wakeup GPIOs are handled correctly.

Co-developed-by: Maulik Shah <mkshah@codeaurora.org>

Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1573855915-9841-9-git-send-email-ilina@codeaurora.org

----
Changes in v2:
	- Address review comments
	- Fix Co-developed-by tag
Changes in v1:
	- Address minor review comments
	- Remove redundant call to set irq handler
	- Move irq_domain_qcom_handle_wakeup() to this patch
Changes in RFC v2:
	- Rebase on top of GPIO hierarchy support in linux-next
	- Set the chained irq handler for summary line
2019-11-16 10:23:15 +00:00
YueHaibing
4b024225c4 pinctrl: use devm_platform_ioremap_resource() to simplify code
devm_platform_ioremap_resource() internally have platform_get_resource()
and devm_ioremap_resource() in it. So instead of calling them separately
use devm_platform_ioremap_resource() directly.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191104142654.39256-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-05 15:33:40 +01:00
AngeloGioacchino Del Regno
90dc30f9ba pinctrl: qcom: spmi-mpp: Add PM/PMI8950 compatible strings
PM8950 and PMI8950 have four MPPs and this driver is compatible.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191031103507.30678-4-kholk11@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-05 11:18:30 +01:00
AngeloGioacchino Del Regno
ba5b9c857b pinctrl: qcom: spmi-gpio: Add PM/PMI8950 compatibility
The PM8950 features 8 GPIOs with hole in 3 and PMI8950 has
only two; these PMICs are totally compatible with this driver.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191031103507.30678-2-kholk11@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-05 11:17:44 +01:00
Rajendra Nayak
81898a44f2 pinctrl: qcom: sc7180: Add missing tile info in SDC_QDSD_PINGROUP/UFS_RESET
The SDC_QDSD_PINGROUP/UFS_RESET macros are missing the .tile info needed to
calculate the right register offsets. Adding them here and also
adjusting the offsets accordingly.

Fixes: f2ae04c45b ("pinctrl: qcom: Add SC7180 pinctrl driver")

Reported-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/20191021141507.24066-1-rnayak@codeaurora.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-04 16:03:50 +01:00
AngeloGioacchino Del Regno
bcd11493f0 pinctrl: qcom: Add a pinctrl driver for MSM8976 and 8956
Add the pinctrl driver to support pin configuration with the
pinctrl framework on MSM8976, MSM8956, APQ8056, APQ8076.

Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
Link: https://lore.kernel.org/r/20191005105936.31216-2-kholk11@gmail.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:56:18 +02:00
Kiran Gunda
b587c30a5f dt-bindings: pinctrl: qcom-pmic-gpio: Add support for pm6150/pm6150l
Add support for the PM6150 and PM6150L GPIO support to the
Qualcomm PMIC GPIO binding.

Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
Link: https://lore.kernel.org/r/1570188039-22122-1-git-send-email-kgunda@codeaurora.org
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16 15:56:07 +02:00
Brian Masney
ae436fe810 pinctrl: ssbi-gpio: convert to hierarchical IRQ helpers in gpio core
Now that the GPIO core has support for hierarchical IRQ chips, convert
Qualcomm's ssbi-gpio over to use these new helpers to reduce duplicated
code across drivers.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Link: https://lore.kernel.org/r/20190914111010.24384-1-masneyb@onstation.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-03 15:02:40 +02:00
Linus Torvalds
3c2edc36a7 This is the bulk of pin control changes for the v5.4 kernel
cycle:
 
 Core changes:
 
 - Fix errors in example code in the documentation.
 
 New drivers:
 
 - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to
   the Ingenic driver.
 
 - Support Cirrus Logic Madera CS47L92 and CS47L15.
 
 - Support Allwinner Sunxi V3S.
 
 - Support Aspeed 2600 BMC.
 
 - Support Qualcomm SC7180.
 
 - Support Marvell MVEBU CS115.
 
 Driver improvements:
 
 - Clean up a few drivers to use the devm_platform_ioremap_resource()
   helper.
 
 - Pass the irqchip when registering the gpio_chip in some pin
   controllers that are also GPIO controllers.
 
 - Support suspend/resume in the Tegra driver.
 
 - Support pull-up on the Broadcom BCM2711.
 
 - The Intel driver can now request locked pads.
 
 - Fix the UFS reset pin in the Qualcomm SDM845 driver.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl2D6y0ACgkQQRCzN7AZ
 XXNAfw//Zh0zkrwVSiDU7xgjIgLpngkmPeDoFZoPW5Uqh6G3KlabkE0y7CXZT2kd
 hZU0v8CW/947t2zxNev6nNUPumfaTJsj5btVAvF8+QE2lnnbs3Id2mPVPK/mMUs+
 bOVFkMMFvGzsY2TaKiJSgOiTe8LoUUl2tJ25mFRBwgtPWYJh2NLVwbzScv+KTBX2
 Yy1UhltfWaobyPGgJucZn2yDbkZQeDLyKaExsL9jKBO9rAf8iwSOwkxEz5hLGRri
 ejubLV2C5WDcAYIMO2WscFm/0Cxv8ooWBlGTG3+v3P1eaB7l7rYkGpVkoRJpS7gr
 Qzf0z1PjVudCcwomkf7ZXJFVHCEkWe86oT4plII9TiZ0b5YpwxYA3Rzakrpb3K7E
 gxCuMR1PQK9/2VcqtnXjV2N40KJNRhsAGx47YK3mZxFQun8ksLDTSwKCEPvQ5GT6
 3CSYtqVkqgpRaj1MIe+QrFE5Y2bNPjYqXF8kqh5hz/2FWZErbaRuPuKscYh7x0Z4
 wY157HEYTlSnSs3nHFtPO3qeXt0i2MNOKVpIlyKzUnafPoyxcnqaB/ZMt5Dp3ygX
 NJI3xqULdSzXRpjj/oChCKzuNd9CmxO6yWMIK32f4Gdc3T1wmpBlOTIrHKUA5aZf
 KN38L/8iGnzvOKC57552eFpTXaF4Plh2y7e0xQkq4eshhHpz8H8=
 =2nNz
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.4 kernel cycle:

  Core changes:

   - Fix errors in example code in the documentation.

  New drivers:

   - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
     Ingenic driver.

   - Support Cirrus Logic Madera CS47L92 and CS47L15.

   - Support Allwinner Sunxi V3S.

   - Support Aspeed 2600 BMC.

   - Support Qualcomm SC7180.

   - Support Marvell MVEBU CS115.

  Driver improvements:

   - Clean up a few drivers to use the devm_platform_ioremap_resource()
     helper.

   - Pass the irqchip when registering the gpio_chip in some pin
     controllers that are also GPIO controllers.

   - Support suspend/resume in the Tegra driver.

   - Support pull-up on the Broadcom BCM2711.

   - The Intel driver can now request locked pads.

   - Fix the UFS reset pin in the Qualcomm SDM845 driver"

* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
  pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
  pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
  pinctrl: bcm: remove redundant assignment to pointer log
  pinctrl: iproc: Add 'get_direction' support
  pinctrl: iproc-gpio: Handle interrupts for multiple instances
  pinctrl: iproc-gpio: Fix incorrect pinconf configurations
  pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
  pinctrl: qcom: sdm845: Fix UFS_RESET pin
  pinctrl: mvebu: add additional variant for standalone CP115
  pinctrl: mvebu: Add CP110 missing pin functionality
  dt-bindings: cp110: document the new CP115 pinctrl compatible
  pinctrl: bcm2835: Pass irqchip when adding gpiochip
  pinctrl: meson: meson: Add of_node_put() before return
  pinctrl/gpio: Take MUX usage into account
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
  pinctrl: amd: disable spurious-firing GPIO IRQs
  pinctrl: rza2: Include the appropriate headers
  pinctrl: rza2: Drop driver use of consumer flags
  ...
2019-09-19 14:19:33 -07:00
Stephen Boyd
1fdbc02ce1 pinctrl: qcom: sdm845: Fix UFS_RESET pin
The UFS_RESET pin is the magical pin #150 now, not 153 per the
sdm845_groups array declared in this file. Fix the order of pins so that
UFS_RESET is 150 and the SDC pins follow after.

Fixes: 53a5372ce3 ("pinctrl: qcom: sdm845: Expose ufs_reset as gpio")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20190830060227.12792-1-swboyd@chromium.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-04 15:23:22 +02:00
Vinod Koul
2dc889a884 dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
Add support for the PM8150l GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190814123512.6017-3-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:59:55 +02:00
Vinod Koul
9bdacadd16 dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
Add support for the PM8150b GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190814123512.6017-2-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:59:13 +02:00
Vinod Koul
d67070c372 dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
Add support for the PM8150 GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190814123512.6017-1-vkoul@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23 09:57:50 +02:00
Linus Walleij
eb1e8bd6e3 gpio: Use callback presence to determine need of valid_mask
After we switched the two drivers that have .need_valid_mask
set to use the callback for setting up the .valid_mask,
we can just use the presence of the .init_valid_mask()
callback (or the OF reserved ranges, nota bene) to determine
whether to allocate the mask or not and we can drop the
.need_valid_mask field altogether.

Cc: Benjamin Gaignard <benjamin.gaignard@st.com>
Cc: Amelie Delaunay <amelie.delaunay@st.com>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819093058.10863-1-linus.walleij@linaro.org
2019-08-20 10:42:07 +02:00
Linus Walleij
c9fc5aff21 gpio: Pass mask and size with the init_valid_mask()
It is more helpful for drivers to have the affected fields
directly available when we use the callback to set up the
valid mask. Change this and switch over the only user
(MSM) to use the passed parameters. If we do this we can
also move the mask out of publicly visible struct fields.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190819084904.30027-1-linus.walleij@linaro.or
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-20 10:42:07 +02:00
Brian Masney
821c76c4c3 qcom: spmi-gpio: convert to hierarchical IRQ helpers in gpio core
Now that the GPIO core has support for hierarchical IRQ chips, convert
Qualcomm's spmi-gpio over to use these new helpers to reduce duplicated
code across drivers.

This change was tested on a LG Nexus 5 (hammerhead) phone.

Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20190808123242.5359-3-linus.walleij@linaro.org
2019-08-15 09:44:19 +02:00
Jitendra Sharma
f2ae04c45b pinctrl: qcom: Add SC7180 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7180

Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
[rnayak: modify to use upstream tile support
	 sort and squash some functions]
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190806060536.18094-2-rnayak@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-07 14:43:51 +02:00
Stephen Boyd
64c4dcbfcc pinctrl: Remove dev_err() usage after platform_get_irq()
We don't need dev_err() messages when platform_get_irq() fails now that
platform_get_irq() prints an error message itself when something goes
wrong. Let's remove these prints with a simple semantic patch.

// <smpl>
@@
expression ret;
struct platform_device *E;
@@

ret =
(
platform_get_irq(E, ...)
|
platform_get_irq_byname(E, ...)
);

if ( \( ret < 0 \| ret <= 0 \) )
{
(
-if (ret != -EPROBE_DEFER)
-{ ...
-dev_err(...);
-... }
|
...
-dev_err(...);
)
...
}
// </smpl>

While we're here, remove braces on if statements that only have one
statement (manually).

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20190730181557.90391-34-swboyd@chromium.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 13:24:06 +02:00
Anders Roxell
6161dc0358 pinctrl: qcom: spmi-gpio: Mark expected switch fall-through
When fall-through warnings was enabled by default the following warnings
was starting to show up:

../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c: In function ‘pmic_gpio_populate’:
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:815:20: warning: this statement may fall
 through [-Wimplicit-fallthrough=]
   pad->have_buffer = true;
   ~~~~~~~~~~~~~~~~~^~~~~~
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:816:2: note: here
  case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
  ^~~~
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:820:20: warning: this statement may fall
 through [-Wimplicit-fallthrough=]
   pad->have_buffer = true;
   ~~~~~~~~~~~~~~~~~^~~~~~
../drivers/pinctrl/qcom/pinctrl-spmi-gpio.c:821:2: note: here
  case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
  ^~~~

Rework so that the compiler doesn't warn about fall-through.

Fixes: d93512ef0f0e ("Makefile: Globally enable fall-through warning")
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
Link: https://lore.kernel.org/r/20190726112816.19723-1-anders.roxell@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:33:28 +02:00
Andy Shevchenko
db5b44f82a pinctrl: qdf2xxx: Switch to use device_property_count_uXX()
Use use device_property_count_uXX() directly, that makes code neater.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190723192738.68486-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 12:01:45 +02:00
Andy Shevchenko
720b8ec676 pinctrl: msm: Switch to use device_property_count_uXX()
Use use device_property_count_uXX() directly, that makes code neater.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20190723192738.68486-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-05 11:55:41 +02:00
Marc Gonzalez
fa21cbea92 pinctrl: msm8998: Squash TSIF pins together
TSIF is the Transport Stream Interface.
First, rename tsif1 to tsif0, and tsif2 to tsif1.
Then squash all 5 tsif0 pins into a single function.
Same for tsif1.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Link: https://lore.kernel.org/r/503b2ae8-ead6-70cd-7b21-ce5f5166a23a@free.fr
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 23:28:57 +02:00
Linus Walleij
0ce242ad2e pinctrl: qcom: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip.

For chained irqchips this is a pretty straight-forward
conversion.

Cc: Thierry Reding <treding@nvidia.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Co-developed-by: Lina Iyer <ilina@codeaurora.org>
Link: https://lore.kernel.org/r/20190724083828.7496-1-linus.walleij@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-29 00:43:25 +02:00
Linus Torvalds
43c95d3694 This is the bulk of pin control changes for the v5.3 kernel
cycle:
 
 Core changes:
 
 - Device links can optionally be added between a pin control
   producer and its consumers. This will affect how the system
   power management is handled: a pin controller will not suspend
   before all of its consumers have been suspended. This was
   necessary for the ST Microelectronics STMFX expander and
   need to be tested on other systems as well: it makes sense
   to make this default in the long run. Right now it is
   opt-in per driver.
 
 - Drive strength can be specified in microamps. With decreases
   in silicon technology, milliamps isn't granular enough, let's
   make it possible to select drive strengths in microamps. Right
   now the Meson (AMlogic) driver needs this.
 
 New drivers:
 
 - New subdriver for the Tegra 194 SoC.
 
 - New subdriver for the Qualcomm SDM845.
 
 - New subdriver for the Qualcomm SM8150.
 
 - New subdriver for the Freescale i.MX8MN (Freescale is now a
   product line of NXP).
 
 - New subdriver for Marvell MV98DX1135.
 
 Driver improvements:
 
 - The Bitmain BM1880 driver now supports pin config in
   addition to muxing.
 
 - The Qualcomm drivers can now reserve some GPIOs as taken
   aside and not usable for users. This is used in ACPI systems
   to take out some GPIO lines used by the BIOS so that
   noone else (neither kernel nor userspace) will play with them
   by mistake and crash the machine.
 
 - A slew of refurbishing around the Aspeed drivers (board
   management controllers for servers) in preparation for the
   new Aspeed AST2600 SoC.
 
 - A slew of improvements over the SH PFC drivers as usual.
 
 - Misc cleanups and fixes.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl0oTPcACgkQQRCzN7AZ
 XXNTsw//aNPfkJS8gRszv58G56lyuO8h6Cq4m5eDpzhlpjx5qjELgi9h2UNGINqD
 7CWxo35ufbKe0fDIcqpXmtuDMtSu6MuKT3SMepuw9uf9wxyndK4RIuyb0lpAJrx2
 +NMPxzS+ARlrMmcfvXPRyPWHqAkXsQk6zcCgiuNCPtROkOZgs1YZ3+pemZw2/FMq
 gSLTO/95p0TPWr6YAlpByqfsA1A/onEm9HOiU2INV7DrAfUj7mnkuC1nZ4IJDFcv
 Gn6qQVQPah+MBzkwt4WXy5kDRozCIbg7x+FQBw3KAO23TrLDTFuNsYIWGFcP2CN2
 eT8iSP3cWrXNUuEgcPD59aO07rhFooT+QBQFt2ih1dJCV1u/795wb57nxSh1YDcO
 M2tG+AW2EZky65FXwhLW2rq3LvmTM4kiEz3mA/DrcOAKvvQllK+6FKEhNy0StstP
 yvvlqoXdgH3sfOnWTAyHr35qA/pMuGEXSryWTJPqpflCvZ3wxNk+IV5nyPAtfaFz
 CK7U0Ya7NaEp/5ZlpE720apJ4uSqmRrLwk5Y1eKQvT46mGOk3rC9ZPIMXc8mB10/
 mJ9mTubi1t4uIPnBl/T1T7f8QhNtr9hOY6wjLf1LoMeJ1XVNBqA+2uydOlBJ1iop
 RQ7y/Jl1SZ/gBzKCmvjPHT2+0Oui9oXGd9bQi0xQKO5Lus/nAIg=
 =Wdw1
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.3 kernel cycle:

  Core changes:

   - Device links can optionally be added between a pin control producer
     and its consumers. This will affect how the system power management
     is handled: a pin controller will not suspend before all of its
     consumers have been suspended.

     This was necessary for the ST Microelectronics STMFX expander and
     need to be tested on other systems as well: it makes sense to make
     this default in the long run.

     Right now it is opt-in per driver.

   - Drive strength can be specified in microamps. With decreases in
     silicon technology, milliamps isn't granular enough, let's make it
     possible to select drive strengths in microamps.

     Right now the Meson (AMlogic) driver needs this.

  New drivers:

   - New subdriver for the Tegra 194 SoC.

   - New subdriver for the Qualcomm SDM845.

   - New subdriver for the Qualcomm SM8150.

   - New subdriver for the Freescale i.MX8MN (Freescale is now a product
     line of NXP).

   - New subdriver for Marvell MV98DX1135.

  Driver improvements:

   - The Bitmain BM1880 driver now supports pin config in addition to
     muxing.

   - The Qualcomm drivers can now reserve some GPIOs as taken aside and
     not usable for users. This is used in ACPI systems to take out some
     GPIO lines used by the BIOS so that noone else (neither kernel nor
     userspace) will play with them by mistake and crash the machine.

   - A slew of refurbishing around the Aspeed drivers (board management
     controllers for servers) in preparation for the new Aspeed AST2600
     SoC.

   - A slew of improvements over the SH PFC drivers as usual.

   - Misc cleanups and fixes"

* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
  pinctrl: aspeed: Strip moved macros and structs from private header
  pinctrl: aspeed: Fix missed include
  pinctrl: baytrail: Use GENMASK() consistently
  pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
  pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
  pinctrl: qcom: Add SM8150 pinctrl driver
  dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
  dt-bindings: pinctrl: qcom: Document missing gpio nodes
  pinctrl: aspeed: Add implementation-related documentation
  pinctrl: aspeed: Split out pinmux from general pinctrl
  pinctrl: aspeed: Clarify comment about strapping W1C
  pinctrl: aspeed: Correct comment that is no longer true
  MAINTAINERS: Add entry for ASPEED pinctrl drivers
  dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Split bindings document in two
  pinctrl: qcom: Add irq_enable callback for msm gpio
  pinctrl: madera: Fixup SPDX headers
  pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
  pinctrl: tegra: Add bitmask support for parked bits
  ...
2019-07-13 15:02:27 -07:00
Prasad Sodagudi
57218371d5 pinctrl: qcom: Add SM8150 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SM8150

Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: modify to use upstream tile support
	use upstream code style
	order the functions and squash functions]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-04 09:47:13 +02:00
Srinivas Ramana
4b7618fdc7 pinctrl: qcom: Add irq_enable callback for msm gpio
Introduce the irq_enable callback which will be same as irq_unmask
except that it will also clear the status bit before unmask.

This will help in clearing any erroneous interrupts that would
have got latched when the interrupt is not in use.

There may be devices like UART which can use the same gpio line
for data rx as well as a wakeup gpio when in suspend. The data that
was flowing on the line may latch the interrupt and when we enable
the interrupt before going to suspend, this would trigger the
unexpected interrupt. This change helps clearing the interrupt
so that these unexpected interrupts gets cleared.

Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-07-03 10:25:53 +02:00
Nathan Chancellor
3fe2f17c0e pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
Clang warns when CONFIG_ACPI is unset:

 drivers/pinctrl/qcom/pinctrl-sdm845.c:1320:5: warning: 'CONFIG_ACPI' is
 not defined, evaluates to 0 [-Wundef]
 #if CONFIG_ACPI
     ^
 1 warning generated.

Use ifdef instead of if to resolve this.

Fixes: a229105d7a ("pinctrl: qcom: sdm845: Provide ACPI support")
Link: https://github.com/ClangBuiltLinux/linux/issues/569
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-25 16:06:23 +02:00
Linus Walleij
c204436506 Merge branch 'ib-qcom-acpi' into devel 2019-06-12 09:19:31 +02:00
Lee Jones
a229105d7a pinctrl: qcom: sdm845: Provide ACPI support
This patch provides basic support for booting with ACPI instead
of the currently supported Device Tree.  When doing so there are a
couple of differences which we need to taken into consideration.

Firstly, the SDM850 ACPI tables omit information pertaining to the
4 reserved GPIOs on the platform.  If Linux attempts to touch/
initialise any of these lines, the firmware will restart the
platform.

Secondly, when booting with ACPI, it is expected that the firmware
will set-up things like; Regulators, Clocks, Pin Functions, etc in
their ideal configuration.  Thus, the possible Pin Functions
available to this platform are not advertised when providing the
higher GPIOD/Pinctrl APIs with pin information.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 09:14:00 +02:00
Lee Jones
4c0efbfb26 pinctrl: msm: Add ability for drivers to supply a reserved GPIO list
When booting MSM based platforms with Device Tree or some ACPI
implementations, it is possible to provide a list of reserved pins
via the 'gpio-reserved-ranges' and 'gpios' properties respectively.
However some ACPI tables are not populated with this information,
thus it has to come from a knowledgable device driver instead.

Here we provide the MSM common driver with additional support to
parse this informtion and correctly populate the widely used
'valid_mask'.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-06-12 09:12:49 +02:00