forked from Minki/linux
pinctrl: ssbi-gpio: convert to hierarchical IRQ helpers in gpio core
Now that the GPIO core has support for hierarchical IRQ chips, convert Qualcomm's ssbi-gpio over to use these new helpers to reduce duplicated code across drivers. Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lore.kernel.org/r/20190914111010.24384-1-masneyb@onstation.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Brian Masney
Linus Walleij
parent
be4c60b563
commit
ae436fe810
@ -152,6 +152,7 @@ config PINCTRL_QCOM_SSBI_PMIC
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select GPIOLIB_IRQCHIP
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select IRQ_DOMAIN_HIERARCHY
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help
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This is the pinctrl, pinmux, pinconf and gpiolib driver for the
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@ -56,7 +56,6 @@
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/**
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* struct pm8xxx_pin_data - dynamic configuration for a pin
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* @reg: address of the control register
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* @irq: IRQ from the PMIC interrupt controller
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* @power_source: logical selected voltage source, mapping in static data
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* is used translate to register values
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* @mode: operating mode for the pin (input/output)
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@ -72,7 +71,6 @@
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*/
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struct pm8xxx_pin_data {
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unsigned reg;
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int irq;
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u8 power_source;
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u8 mode;
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bool open_drain;
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@ -93,9 +91,6 @@ struct pm8xxx_gpio {
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struct pinctrl_desc desc;
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unsigned npins;
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struct fwnode_handle *fwnode;
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struct irq_domain *domain;
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};
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static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
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@ -491,13 +486,16 @@ static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
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struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
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int ret, irq;
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bool state;
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int ret;
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if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
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ret = pin->output_value;
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} else if (pin->irq >= 0) {
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ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
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if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT)
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return pin->output_value;
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irq = chip->to_irq(chip, offset);
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if (irq >= 0) {
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ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL,
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&state);
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if (!ret)
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ret = !!state;
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} else
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@ -535,37 +533,6 @@ static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
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}
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static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
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struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
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struct irq_fwspec fwspec;
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int ret;
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fwspec.fwnode = pctrl->fwnode;
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fwspec.param_count = 2;
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fwspec.param[0] = offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
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fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
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ret = irq_create_fwspec_mapping(&fwspec);
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/*
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* Cache the IRQ since pm8xxx_gpio_get() needs this to get determine the
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* line level.
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*/
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pin->irq = ret;
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return ret;
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}
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static void pm8xxx_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
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struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
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pin->irq = -1;
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}
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#ifdef CONFIG_DEBUG_FS
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#include <linux/seq_file.h>
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@ -624,13 +591,11 @@ static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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#endif
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static const struct gpio_chip pm8xxx_gpio_template = {
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.free = pm8xxx_gpio_free,
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.direction_input = pm8xxx_gpio_direction_input,
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.direction_output = pm8xxx_gpio_direction_output,
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.get = pm8xxx_gpio_get,
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.set = pm8xxx_gpio_set,
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.of_xlate = pm8xxx_gpio_of_xlate,
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.to_irq = pm8xxx_gpio_to_irq,
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.dbg_show = pm8xxx_gpio_dbg_show,
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.owner = THIS_MODULE,
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};
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@ -712,42 +677,23 @@ static int pm8xxx_domain_translate(struct irq_domain *domain,
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return 0;
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}
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static int pm8xxx_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *data)
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static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
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struct pm8xxx_gpio, chip);
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret, i;
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ret = pm8xxx_domain_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, hwirq + i,
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&pm8xxx_irq_chip, pctrl, handle_level_irq,
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NULL, NULL);
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parent_fwspec.fwnode = domain->parent->fwnode;
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parent_fwspec.param_count = 2;
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parent_fwspec.param[0] = hwirq + 0xc0;
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parent_fwspec.param[1] = fwspec->param[1];
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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return offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
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}
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static const struct irq_domain_ops pm8xxx_domain_ops = {
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.activate = gpiochip_irq_domain_activate,
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.alloc = pm8xxx_domain_alloc,
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.deactivate = gpiochip_irq_domain_deactivate,
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.free = irq_domain_free_irqs_common,
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.translate = pm8xxx_domain_translate,
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};
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static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip,
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unsigned int child_hwirq,
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unsigned int child_type,
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unsigned int *parent_hwirq,
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unsigned int *parent_type)
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{
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*parent_hwirq = child_hwirq + 0xc0;
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*parent_type = child_type;
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return 0;
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}
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static const struct of_device_id pm8xxx_gpio_of_match[] = {
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{ .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
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@ -765,6 +711,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
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struct irq_domain *parent_domain;
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struct device_node *parent_node;
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struct pinctrl_pin_desc *pins;
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struct gpio_irq_chip *girq;
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struct pm8xxx_gpio *pctrl;
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int ret, i;
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@ -800,7 +747,6 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
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for (i = 0; i < pctrl->desc.npins; i++) {
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pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
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pin_data[i].irq = -1;
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ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
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if (ret)
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@ -841,19 +787,21 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
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if (!parent_domain)
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return -ENXIO;
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pctrl->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
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pctrl->domain = irq_domain_create_hierarchy(parent_domain, 0,
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pctrl->chip.ngpio,
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pctrl->fwnode,
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&pm8xxx_domain_ops,
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&pctrl->chip);
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if (!pctrl->domain)
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return -ENODEV;
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girq = &pctrl->chip.irq;
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girq->chip = &pm8xxx_irq_chip;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
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girq->parent_domain = parent_domain;
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girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq;
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girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell;
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girq->child_offset_to_irq = pm8xxx_child_offset_to_irq;
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girq->child_irq_domain_ops.translate = pm8xxx_domain_translate;
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ret = gpiochip_add_data(&pctrl->chip, pctrl);
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if (ret) {
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dev_err(&pdev->dev, "failed register gpiochip\n");
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goto err_chip_add_data;
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return ret;
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}
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/*
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@ -883,8 +831,6 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev)
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unregister_gpiochip:
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gpiochip_remove(&pctrl->chip);
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err_chip_add_data:
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irq_domain_remove(pctrl->domain);
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return ret;
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}
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@ -894,7 +840,6 @@ static int pm8xxx_gpio_remove(struct platform_device *pdev)
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struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
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gpiochip_remove(&pctrl->chip);
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irq_domain_remove(pctrl->domain);
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return 0;
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}
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