- Some fixes for the DT schemas that were added during this release
- Wifi support for the H6
- LRADC suppport for the A64
- Some background work on A64 boards, to enable various devices such
as touchscreens, PMIC, audio, wifi, etc.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXQyQcQAKCRDj7w1vZxhR
xbybAP9uAJcwix86BmYLIA3I7n1fT1oLooS+WfPL4btmqYBykAD/fK7Nn1g3alWg
7c61AEJKDHZwObU1dNpxjvsjT+/u+Qc=
=B/U5
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-5.3-201906210808' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual bunch of arm64 DT changes, this time with:
- Some fixes for the DT schemas that were added during this release
- Wifi support for the H6
- LRADC suppport for the A64
- Some background work on A64 boards, to enable various devices such
as touchscreens, PMIC, audio, wifi, etc.
* tag 'sunxi-dt64-for-5.3-201906210808' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: dts: allwinner: h6: Add DMA node
arm64: dts: allwinner: a64: Add lradc node
dt-bindings: input: sun4i-lradc-keys: Add A64 compatible
arm64: dts: allwinner: h6: add r_watchog node
arm64: dts: allwinner: h6: add watchdog node
dt-bindings: watchdog: add Allwinner H6 watchdog
arm64: dts: allwinner: a64: Enable audio on Teres-I
arm64: dts: allwinner: a64: bananapi-m64: Enable PMIC USB power supply
arm64: dts: allwinner: axp803: add USB power supply node
arm64: dts: allwinner: a64: Add pinmux for RGB666 LCD
arm64: dts: allwinner: a64: orangepi-win: Add wifi and bluetooth nodes
arm64: dts: allwinner: h6: add PIO VCC bank supplies for Pine H64
arm64: dts: allwinner: a64-oceanic-5205-5inmfd: Enable GT911 CTP
arm64: dts: allwinner: a64-amarula-relic: Add GT5663 CTP node
arm64: dts: allwinner: a64: move I2C pinctrl to dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
- Some work on the BPi M2-Berry to support various devices
- Convert some bindings to a schema, and a lot of fixes reported by
the schemas we introduced.
- A few other fixes here and there
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXQyQTgAKCRDj7w1vZxhR
xYkmAQDT7s1MRH9OEFQpS80BcWCvQoj0drr1ghHdXwwEbfuBUgEAoIuLrfH1Vjyi
ZcEJwPGowLmSEZezVWSLqTL76iajJg4=
=PAul
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-5.3-201906210807' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
Our usual bunch of patches:
- Some work on the BPi M2-Berry to support various devices
- Convert some bindings to a schema, and a lot of fixes reported by
the schemas we introduced.
- A few other fixes here and there
* tag 'sunxi-dt-for-5.3-201906210807' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
dt-bindings: pwm: Convert Allwinner PWM to a schema
ARM: dts: sun8i: r40: Change the RTC compatible
ARM: dts: sun8i: v3s: Add external crystals accuracy
ARM: dts: sun8i: v3s: Fix the RTC node
ARM: dts: sun6i: Add external crystals accuracy
ARM: dts: sun6i: Fix RTC node
ARM: dts: sun8i: a83t: Add device node for CSI (Camera Sensor Interface)
ARM: dts: gr8-evb: Fix RTC vendor
ARM: dts: sun7i: icnova-swac: Fix the model vendor
ARM: dts: sun8i: a711: Change LRADC node names to avoid warnings
ARM: dts: sun7i: olimex-lime2: Enable ac and power supplies
ARM: dts: sun6i: Add default address and size cells for SPI
ARM: dts: sun8i-h3: Fix wifi in Beelink X2 DT
dt-bindings: bus: Convert Allwinner RSB to a schema
ARM: dts: sun8i: r40: bananapi-m2-ultra: Remove regulator-always-on
ARM: dts: sun8i: v40: bananapi-m2-berry: Add Bluetooth device node
ARM: dts: sun8i: v40: bananapi-m2-berry: Enable AHCI
ARM: dts: sun8i: v40: bananapi-m2-berry: Enable HDMI output
ARM: dts: sun8i: v40: bananapi-m2-berry: Enable GMAC ethernet controller
ARM: dts: sun8i: v40: bananapi-m2-berry: Add GPIO pin-bank regulator supplies
...
Signed-off-by: Olof Johansson <olof@lixom.net>
We have various device tree updates from the OpenBMC project to enable
bits and pieces in existing systems, notably updates to Google's Zaius.
There are some AST2500 machines under development:
* Lenovo Hr630
* IBM Swift
* Facebook YAMP
And some AST2400 machines that have been around but out of tree and have
now joined the party:
* YADRO VESNIN
* Microsoft Olympus
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE+nHMAt9PCBDH63wBa3ZZB4FHcJ4FAl0LMRUACgkQa3ZZB4FH
cJ65LBAAhtpaea/EsgjmRuEV22mrzY3YmDXL4uVahpoNftGdlrgPzBTSDXcxKbMI
QiTuY2aCJLKLWHod/qpM//2kB0Y8EGLDT94ji6aglOy35+41PCPzAQ12SyPZ/hUx
IofC8g0bqPkQiaUq9QRnQE9ns9jOr0nEArEBt/R0clgdOhgMl0NCrbI6rc7XBLfN
L1tMUxhVMfn71nyE4Q1nkMEMdLsxHIRl12sg2pboTVtoes+LBj+ZQ/7AEXkYjxaL
DSmLVwQwVES3+8rgcSxdtR/pB/H4SLZXst2tlf8I4AVafVUAHkZG7dsFUKnIC2qM
q2cn0IlAnVshwtbdYWZ6w1kWQSZEuasRdhQCUjCedMDkT52NQTOaeVclpe2wjPk4
F9WrPUFAkefxvD3MAog2WO8ORYs/cRyysIt+LxU+sv14qToTxcgrUwxLn/S6R7b9
qK+vmMxxu2B/VLfemcFHvlg19thU2GaDiHf427fXat1vqGDEADzTVyYNFaN5RbB+
hBg1OLm+vfki9uQ++bYuek4zYvgubSflxy+BwAtA0Xi34ayfPYCUiX/ntVHwHK1j
p/oewNu+23GxV5XohkTsVPIJnnhrktw2MzPoFQEL4Fqv5QeumdlQyBpvG9EYu88C
D5cUfCzTR5uX5/cz5R8Jaa5De9qbf5fLK9HGyLgkSjzpHruLX3o=
=Hwcm
-----END PGP SIGNATURE-----
Merge tag 'aspeed-5.3-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/dt
ASPEED device tree updates for 5.3
We have various device tree updates from the OpenBMC project to enable
bits and pieces in existing systems, notably updates to Google's Zaius.
There are some AST2500 machines under development:
* Lenovo Hr630
* IBM Swift
* Facebook YAMP
And some AST2400 machines that have been around but out of tree and have
now joined the party:
* YADRO VESNIN
* Microsoft Olympus
* tag 'aspeed-5.3-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
ARM: dts: aspeed: Enable video engine on romulus and wtherspoon
ARM: dts: aspeed: Add Inspur fp5280g2 BMC machine
ARM: dts: aspeed: Add YADRO VESNIN BMC
ARM: dts: aspeed: Add Microsoft Olympus BMC
ARM: dts: aspeed: Adding Lenovo Hr630 BMC
ARM: dts: aspeed: Add Facebook YAMP BMC
ARM: dts: aspeed: swift: Add pca9539 devices
ARM: dts: aspeed: Add Swift BMC machine
ARM: dts: aspeed: cmm: enable ehci host controllers
ARM: dts: aspeed: zaius: fixed I2C bus numbers for pcie slots
ARM: dts: aspeed: zaius: update 12V brick I2C address
ARM: dts: aspeed: zaius: add Infineon and Intersil regulators
ARM: dts: aspeed: quanta-q71: Enable p2a node
ARM: dts: aspeed: Add aspeed-p2a-ctrl node
ARM: dts: aspeed: Add Power9 and Power9 CFAM description
ARM: dts: aspeed: Rename flash-controller nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add display support to MSM8974
* Add display, backlight, and touchscreen support to MSM8974 Hammerhead
* Update coresight bindings for MSM8974 and APQ8064
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJdCeMbAAoJEFKiBbHx2RXV8ikQAKrkShMW6iBQ1v/dnyHsNvI5
rG0w2BKk6YVUjcP0DMgKMtVwvLCmk8sW1Hj9ZOO+eE/M0pNTmWzyeVlAqPW580WT
Bu9RWzRrQud2shx9uXMsQypcIA/t5zJ6TtbkG6VXFodYVUAMWQCnjWIH3TEPMwOp
HcZdz4bUVL7+mD20dXy4RTz6ZRaNEYf+IQUrc2WJehzv5IbIjS9UD1zzNeswEb/t
rBNa5quvSYC9sc5eKC6tt4qrnbU3urFZp5ugOCl9hgEkEpHrFeDf2QNUjKqHqdx/
xCPzFZpu61syRTivpykwvbwOkjqoYoT8+/RhcyPDYQiuMhcTr8XcTgRC1XVsm0Xd
OVU+XXOdaA9GqVWKc20rPbXWpMejM7LZQLpWwPr6Y/z2nTEUlNH+vCMcS4z4zvZS
7jIA/kRR1v0N0LO1644etthVGxmzTX0u+iLyjhAO7TItwdKsaCXygRjlR1GIjie7
fwUSXvZTwBpw38+mQj0QEe8N7HQBaRhRIMB8CYs/s+ktdT3flgw2VD1tqU5jXETA
syzKVcUjjoKkHo1ezErR+Zy8q/K43EqUbxbed0VWN0vvUAXxtnFzJPwhlRg5bpk5
bGwVvBxeA6cn+3HDtVWecBlztTfyV2w2hNQsJ7NU2X3j5KWE/ynX8IJ+Ibns4uE7
mON/7w9XG7d17CjY/vNE
=q1ev
-----END PGP SIGNATURE-----
Merge tag 'qcom-dts-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
Qualcomm Device Tree Changes for v5.3
* Add display support to MSM8974
* Add display, backlight, and touchscreen support to MSM8974 Hammerhead
* Update coresight bindings for MSM8974 and APQ8064
* tag 'qcom-dts-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: msm8974-hammerhead: add support for display
ARM: dts: msm8974: add display support
ARM: dts: qcom: msm8974-hammerhead: add support for backlight
ARM: dts: qcom: msm8974-hammerhead: add touchscreen support
ARM: dts: qcom-msm8974: Update coresight DT bindings
ARM: dts: qcom-apq8064: Update coresight DT bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
- Updated CoreSight funnel and replicator using new bindings to fix warning
for the hip04.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJdCloiAAoJEAvIV27ZiWZcnLQP/Az5KoBhY1q9ve5jF/2vRKHU
/vWlNp9fYpndza5XGOTFa53/59mI/D7BWUKPcLZ9V9weof8dVD+IDffAZrNozUTs
anfvn2S7ZlpGxnSnNnDLELk2mAe9jq8JwCi/wPlkHcO7dn55LTREBSRJSDQJj9mg
5YZmSN/1DM0aw85/PB2P69r1Ri5VNGOpNMEWv8mZGt8DhKfeW0/UMv4r7pzrgkr7
MEyWopNoe/Ca0u6GjJWz4aSCgmI12IkXkZETYVGEvYnWHMZxzIaPXCuEnyo9aqvW
L8zMPtVF7yIJcnv2JR8Dwv3VS1b6amThQiHBq4oKWJjZrJzlOA3XHbvLdkwYTOkl
b2Xls0R/kgetHRoD27imIMMYL81Ftv3gyL8FV0zRybrKWL43tk5rYKgB/NXbZv3U
02M9jK5BQlnzDVdhg56UWK/Ish3JhbHMbDbUPB/X72eA/2wEb3qJeBrxsVwr6cJx
UmMOOL4TkKcP6KRGe0SNd6NhX4Go9H+3zlPAGrfU8pEMQF5FqW8BnThb50+AsWTk
EpwjMudBtAv8eNHbBQonN0VnB3OeWQQUP2B5B5/RT1NNxFG8UFvQdM5pWSKi29tD
wBmON4jJuwUdPbLbo9LaqEFA4w2IcSOPmvELc6d2t2fv4cFNScic9tITVmWQCZRs
cdgbu5cMFjqTs25G1zqB
=vaAE
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm32-dt-for-5.3' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM: DT: Hisilicon ARM32 SoCs updates for v5.3
- Updated CoreSight funnel and replicator using new bindings to fix warning
for the hip04.
* tag 'hisi-arm32-dt-for-5.3' of git://github.com/hisilicon/linux-hisi:
ARM: dts: hip04: Update coresight DT bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
* Hi3660 SoC and related boards:
- Added CoreSight trace components
* Hi6220 SoC and related boards:
- Updated CoreSight funnel and replicator using new bindings to fix warning
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJdClO7AAoJEAvIV27ZiWZcHyUP/AiRfT+Z6HofsnA1G+hq+6tJ
AMHp6cYxuyZW0Bfx/sfRUNVZL6l4go4wX3XO4KW6D7UQjXwmyenHRlfei1SEeXtl
pTbq2WCprmElESj33ByruIPRxT8Rk3VTgjhE8rooociA+1t8+ATAwoj/zJLSXnPP
V9MZDWKAmSBAE9uhVWo2EGORZmUJOnIl5yRjGpCdadl5ZA6epQginIPfI1HMZCtL
LzMbt08bxTiLD9mbSeSJdTxvwMEUhCcXaC9zOyYcoLqsSwYatfK8XVFJxQjmetbt
HDDbKY78Ya0ZXmgCsUpn/I0gzxGPhAIHyA7wi1ogf6rkP4kHy1cUtjgugMp4ZqLP
9Jnc671o2x4OSc/2R7tZzFsCQE7ebJ9zaeQ6ZKwfyy6Tr1xaYXqmAa8m5g0AEu7+
iwiRv6Sl6/lSvN285RFS6uuMR+gH/oQjOATlgJqOVarRkbG/wEkM+We+QZiwK5fu
M60qsCeZfmFY7VxO9KvSxI53j6etGiAlITOF6/TV+QG8VdrlUyyfoLVcxSjTESlE
u82+GM6iGNLRYUcqllDQ70roUSy1N5LA4nOu4LsJxc96su/tm+jdqD7BqpiKOMIX
pfq+n3+ZYafrV2zKIS0Qf6j+4eW2NszdtSZty5LktaGNHl9zlq1+De+qjajCiMN5
f4rrCYsEdYp8PV5VTLTg
=GTKf
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi into arm/dt
ARM64: DT: Hisilicon SoCs DT updates for v5.3
* Hi3660 SoC and related boards:
- Added CoreSight trace components
* Hi6220 SoC and related boards:
- Updated CoreSight funnel and replicator using new bindings to fix warning
* tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hi3660: Add CoreSight support
arm64: dts: hi6220: Update coresight DT bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
for 5.3 please pull the following:
- Lukas enables DMA support for the BCM2835 (Raspberry Pi) SPI
controller
- Florian fixes a number of dtc W=1 warnings in the Broadcom DTS files
and provides a fix for devices failing to boot after the removal of
skelton.dtsi (that commit has been submitted as a separate fix)
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl0O5KUACgkQh9CWnEQH
BwRdAw//VtoEfHJkk90iBmQKmeBW/0hG9QocqGrPuP/PYMOID2rnqut08r0Bvpcy
7U0YKSVbdZbdSVG8MMNzmtX1SVthUBaQroC1wocXrJL0Onr8loD0RUorbL0gmsIY
wci3rUEUEn5Zi4R8ihjB+27CLnHnoD+A2ZNETNR8bE2VIbX6jW7qfZA0qMlYJu/S
7So2MKbQC7ei1XNcFufx4VF/ZfuaHcvkZtpcU5/leRgyOa/0MBux4CbDKmhjvywL
Ork8/F/TsC882ys5IRWVqC2rmnqqhSv+vFQw3bqSMY5bN5pqIufeP9BtLyWRb+mV
sIP8RxMGJCwvQU9rVqZz70V4ORaP5b2fkTFG84Hn4n5vjhoQADYuIdSREadO8rRk
nAc9uZkCS1GRSLPQZqo5WoBCStNtqqYFc9kYJJ27c2JzkafHq3GTuL0F6p/GT9TF
7hQUJRUsXwIJ0rLrtm4cesIUj9OY32Y0KN0M/jDJuAx8R5009x7u+TnddFRZbvG8
hulX8G9XCImJ04yyts2s0TwFOlI+8XjTeWfaJQY+I5j0PXxuM+eLYV3MetGY+OL2
1yKRBNE2mAs22VpQ2e70d5iMwwM/+ydu4aD3pRd0Q8sPMV7HfBLdNMxXaPovzjoA
0SdZTB73PNpXqBdM1fMD1G7TG+rtGgn1gKyfrShdMRMnRqhB/5Q=
=AQ6F
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-5.3/devicetree-v2' of https://github.com/Broadcom/stblinux into arm/dt
This pull request contain Broadcom ARM-based SoCs Device Tree changes
for 5.3 please pull the following:
- Lukas enables DMA support for the BCM2835 (Raspberry Pi) SPI
controller
- Florian fixes a number of dtc W=1 warnings in the Broadcom DTS files
and provides a fix for devices failing to boot after the removal of
skelton.dtsi (that commit has been submitted as a separate fix)
* tag 'arm-soc/for-5.3/devicetree-v2' of https://github.com/Broadcom/stblinux:
ARM: dts: BCM5301X: Fix most DTC W=1 warnings
ARM: dts: NSP: Fix the bulk of W=1 DTC warnings
ARM: dts: BCM63xx: Fix DTC W=1 warnings
ARM: dts: BCM53573: Fix DTC W=1 warnings
ARM: dts: bcm-mobile: Fix most DTC W=1 warnings
ARM: dts: Cygnus: Fix most DTC W=1 warnings
ARM: dts: Fix BCM7445 DTC warnings
ARM: bcm283x: Enable DMA support for SPI controller
ARM: dts: bcm: Add missing device_type = "memory" property
Signed-off-by: Olof Johansson <olof@lixom.net>
Fix the bulk of the unit_address_vs_reg warnings and unnecessary
\#address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Fix the bulk of the unit_address_vs_reg warnings and unnecessary
\#address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Fix the bulk of the unit_address_vs_reg warnings and unnecessary
\#address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Fix the the unit_address_vs_reg warnings and unnecessary
\#address-cells/#size-cells without "ranges" or child "reg" property
warnings.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Fix the bulk of the unit_address_vs_reg warnings and unnecessary
\#address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Fix the bulk of the unit_address_vs_reg warnings and unnecessary
\#address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Fixes a number of unit_address_vs_reg warnings:
DTC arch/arm/boot/dts/bcm7445-bcm97445svmb.dtb
arch/arm/boot/dts/bcm7445.dtsi:66.6-225.4: Warning (unit_address_vs_reg): /rdb: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/bcm7445.dtsi:227.21-298.4: Warning (unit_address_vs_reg): /memory_controllers: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/bcm7445-bcm97445svmb.dts:9.9-14.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
arch/arm/boot/dts/bcm7445.dtsi:255.10-275.5: Warning (simple_bus_reg): /memory_controllers/memc@1: simple-bus unit address format error, expected "80000"
arch/arm/boot/dts/bcm7445.dtsi:277.10-297.5: Warning (simple_bus_reg): /memory_controllers/memc@2: simple-bus unit address format error, expected "100000"
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Without this, the driver for the BCM2835 SPI controller uses interrupt
mode instead of DMA mode, incurring a significant performance penalty.
The Foundation's device tree has had these attributes for years, but for
some reason they were never upstreamed.
They were originally contributed by Noralf Trønnes and Martin Sperl:
https://github.com/raspberrypi/linux/commit/25f3e064afc8https://github.com/raspberrypi/linux/commit/e0edb52b47e6
The DREQ numbers 6 and 7 are documented in section 4.2.1.3 of:
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Cc: Martin Sperl <kernel@martin.sperl.org>
Cc: Noralf Trønnes <noralf@tronnes.org>
The Allwinner SoCs have a PWM controller supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.
Replace snps,reset-gpio from the ðmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.
snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.
Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- RTL8211F PHY on the Odroid-C1 and MXIII-Plus needs a 10ms assert
delay (the datasheet mentions: "For a complete PHY reset, this pin
must be asserted low for at least 10ms") and a 30ms deassert delay
(the datasheet mentions: "Wait for a further 30ms (for internal
circuits settling time) before accessing the PHY register"). The
old settings used 10ms for assert and 1000ms for deassert.
- IP101GR PHY on the EC-100 and MXQ needs a 10ms assert delay (the
datasheet mentions: "Trst | Reset period | 10ms") and a 10ms deassert
delay as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock
output ready after reset released | 10ms")). The old settings used
10ms for assert and 1000ms for deassert.
No functional changes intended.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the video engine and add it's optional reserved memory region.
Use 32MB for the reserved memory since the video engine could need up to
two 1920x1200@32bpp source buffers.
Source buffers: 2 * 1920 * 1200 * 4 = 18432000 bytes
In addition, the V4L2 subsystem will allocate any number of compression
buffers, each at most 1/8th the size of the source buffer.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The fp5280g2 is an OpenPower server platform with an ASPEED AST2500 BMC.
Signed-off-by: John Wang <wangzqbj@inspur.com>
Reviewed-by: Lei YU <mine260309@gmail.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
The invalid definition in the supply causes the Qualcomm's EVB-1000
and EVB-4000 not to boot.
Fix the boot issue by correctly defining the supply: vdd_s3 (namely
"vdd_apc") is actually connected to vph_pwr.
Reported-by: Niklas Cassel <niklas.cassel@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <agross@kernel.org>
- Use the new "altr,socfpga-stmmac-a10-s10" for the EMAC controllers on
Arria10/Stratix10
- Add the ltc2497 i2c entry on the Arria10 devkit
- Add the EMAC OCP reset property on the Arria10
-----BEGIN PGP SIGNATURE-----
iQJIBAABCgAyFiEEoHhMeiyk5VmwVMwNGZQEC4GjKPQFAlz+d5oUHGRpbmd1eWVu
QGtlcm5lbC5vcmcACgkQGZQEC4GjKPSl9g/8DvMqBsyvtoNJwqkEiZXjjBecjMBW
rN1O226DtbhHbaDA595vZE5U/va9fx+QVVEfxIT22r31BQ9b8c7RKWtly5DD3Il/
VIZ5JvUXmXvc/uDHDntRGbWmRbDmU8VEEjzzaGuGI5j4+dKhvy27jdRcqJLBKtdI
9cfdDv2Tqh047FuUDs2Q7PwrhBktPEJrvnAUmpBv+BBc/eRkzOz7QaAjTVgfO85E
WBBocEc1Zi/VjJzHGY4bGrmmf3CFriC+eO4lnuoBO+o1heNdBM97QB4cUHdfZ6/t
UCrNzrkvksMmFOyEuJbZahQ/rRhunBSK6LyfPtLWhEMxxkJXO7DxuUuMnsBsZuR8
64QrRKuXzrHqk18p805LQiqQupJn4WfkK3/r4qlNSD7mdFTshHOGynQ7HAJunbT9
pplYHF7bhMjskeeOW6FipWGPFUFn1MbYOgM8weZ7I+9+TKj5H3BxYKhpt90ae5Lu
cS1uk2bkDemSt9o6xzzb/xdBSRgzxGE5agYuUzuLwTK2SK6SlQZ/IZwwMu9GXEwh
rA4Wjg4LliEk/LEGEcwcosB6OalCuLCIa0ywnn9WOZMOHJCBPwoWtgJyeWEvPYiD
e1Oh/yBNOiOfnKi3bw3EvnwstTNzIaWqI12qO1BIJ1JEwSgC/rDy6P7eQQ8WMfBM
Im7ivw8tfEj/6Ik=
=22jl
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_updates_for_v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.3
- Use the new "altr,socfpga-stmmac-a10-s10" for the EMAC controllers on
Arria10/Stratix10
- Add the ltc2497 i2c entry on the Arria10 devkit
- Add the EMAC OCP reset property on the Arria10
* tag 'socfpga_dts_updates_for_v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: arria10: Add EMAC OCP reset property
ARM: dts: socfpga: add ltc2497 on arria10 devkit
arm64: dts: stratix10: use the "altr,socfpga-stmmac-a10-s10" binding
ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" binding
Signed-off-by: Olof Johansson <olof@lixom.net>
CoreSight DT bindings have been updated, thus the old compatible strings
are obsolete and the drivers will report warning if DTS uses these
obsolete strings.
This patch switches to the new bindings for CoreSight dynamic funnel and
static replicator, so can dismiss warning during initialisation.
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This patch adds DT bindings for the CoreSight trace components
on hi3660, which is used by 96boards Hikey960.
Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com>
Reviewed-and-tested-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
CoreSight DT bindings have been updated, thus the old compatible strings
are obsolete and the drivers will report warning if DTS uses these
obsolete strings.
This patch switches to the new bindings for CoreSight dynamic funnel and
static replicator, so can dismiss warning during initialisation.
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Samsung DTS ARM changes for v5.3
1. Fixes for minor warnings.
2. Enable ADC on Exynos5410 Odroid XU board.
* tag 'samsung-dt-5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Add ADC node to Exynos5410 and Odroid XU
ARM: dts: exynos: Raise maximum buck regulator voltages on Arndale Octa
ARM: dts: exynos: Move CPU OPP tables out of SoC node on Exynos5420
Signed-off-by: Olof Johansson <olof@lixom.net>
ARMv7 Vexpress updates for v5.3
1. Couple of updates switching to use new/updated bindings for CoreSight
dynamic funnel components and NOR flash partition type
2. Disable NOR flash on Vexpress TC2 platform as it conflicts with CPU
power management. This follows what we have on ARMv8 Juno platform
and is required after recent commit that enabled CFI NOR FLASH in
multi_v7 defconfig
* tag 'vexpress-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress: set the right partition type for NOR flash
arm: dts: vexpress-v2p-ca15_a7: disable NOR flash node by default
ARM: dts: vexpress-v2p-ca15_a7: update coresight DT bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
ARMv8 Juno updates for v5.3
Couple of updates switching to use new/updated bindings for CoreSight
dynamic funnel components and NOR flash partition type
* tag 'juno-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: set the right partition type for NOR flash
arm64: dts: juno: update coresight DT bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
ti-sysc dts changes for v5.3
We can now drop the custom dts property "ti,hwmods" for drivers that
have the ti-sysc interconnect target module configured in dts.
Let's start with a minimal changes to omap4 uart and mmc. We use
omap4 as the starting point as it has runtime PM implemented and all
the omap variants after that are based on it with similar clkctrl
clock for the modules. More devices will be updated later on as they
get tested.
Note that these changes are based on the related ti-sysc driver
changes.
* tag 'omap-for-v5.3/ti-sysc-dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: Drop legacy custom hwmods property for omap4 mmc
ARM: dts: Drop legacy custom hwmods property for omap4 uart
bus: ti-sysc: Detect uarts also on omap34xx
bus: ti-sysc: Do rstctrl reset handling in two phases
bus: ti-sysc: Add support for disabling module without legacy mode
bus: ti-sysc: Set ENAWAKEUP if available
bus: ti-sysc: Handle swsup idle mode quirks
bus: ti-sysc: Handle clockactivity for enable and disable
bus: ti-sysc: Enable interconnect target module autoidle bit on enable
bus: ti-sysc: Allow QUIRK_LEGACY_IDLE even if legacy_mode is not set
bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bits
bus: ti-sysc: Support 16-bit writes too
bus: ti-sysc: Add support for missing clockdomain handling
ARM: dts: dra71x: Disable usb4_tm target module
ARM: dts: dra71x: Disable rtc target module
ARM: dts: dra76x: Disable usb4_tm target module
ARM: dts: dra76x: Disable rtc target module
ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
ARM: dts: am57xx-idk: Remove support for voltage switching for SD card
bus: ti-sysc: Handle devices with no control registers
...
Signed-off-by: Olof Johansson <olof@lixom.net>
dts changes for omap variants for v5.3
This series of changes improves support for few boards:
- configure another lcd type for logicpd torpedo devkit
- a series of updates for am335x phytec boards
- configure mmc card detect pin for am335x-baltos
* tag 'omap-for-v5.3/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x-baltos: add support for MMC1 CD pin
ARM: dts: am335x-baltos: Fix PHY mode for ethernet
ARM: dts: Add support for phyBOARD-REGOR-AM335x
ARM: dts: am335x-pcm-953: Remove eth phy delay
ARM: dts: am335x-pcm-953: Update user led names
ARM: dts: am335x-phycore-som: Enable gpmc node in dts files
ARM: dts: am335x-phycore-som: Add emmc node
ARM: dts: am335x phytec boards: Remove regulator node
ARM: dts: Add LCD type 28 support to LogicPD Torpedo DM3730 devkit
Signed-off-by: Olof Johansson <olof@lixom.net>
This pull request contains Broadcom ARM64-based SoCs Device Tree changes
for 5.3, please pull the following:
- Pramod adds the Device Tree nodes for thermal support on Stingray
- Srinath adds the Device Tree nodes for both XHCI (host) and BDC
(device) modes
- Rayagonda adds the Device Tree node for slave I2C operation when
Stingray operates as a SmartNIC
* tag 'arm-soc/for-5.3/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: Stingray: Add NIC i2c device node
arm64: dts: Add USB DT nodes for Stingray SoC
arm64: dts: stingray: Add Stingray Thermal DT support.
Signed-off-by: Olof Johansson <olof@lixom.net>
and a fix for the yet unused isp-iommus.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlz/ZpUQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgTV7B/0XnPl7iXuZlASPd4isXVofOtVzRlASNupn
QsFg0KUb49p6s5rmc3QZNjJ+1CLk441UW009AkE/3pd+j10lv7AHdr/NGSI6Z7P0
4iNFFmI4SmZIkEvnmJD9HmX8Pg/cflWPEC26Mm5GlISy8kFQKqEJb6bXxjOSgAC/
GI+SnVBM4g2MK3RcGVPGIN2mPOQt6BseFXe4BEeIq7XpT+2kBkkBuphCmv4UECLB
az0fmRuW+fQHLqRdsvOByxQQQLYB6wiEEMQqsqUegfywACLOGgB+qE1qAt2SvQJz
Ek8uX4s1IKFx1DQ+GgGJ7rgBKv61AODoS6SDUmUYkorDwpQmni+k
=Nria
-----END PGP SIGNATURE-----
Merge tag 'v5.3-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
PCIe for rockpro64, wifi+bt for Rock-PI4, spi for Rock960 family
and a fix for the yet unused isp-iommus.
* tag 'v5.3-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: add WiFi+BT support on ROCK Pi4 board
arm64: dts: rockchip: fix isp iommu clocks and power domain
arm64: dts: rockchip: Enable SPI1 on Ficus
arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960
arm64: dts: rockchip: add PCIe nodes on rk3399-rockpro64
Signed-off-by: Olof Johansson <olof@lixom.net>
all over the place.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlz/ZecQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgYtuB/9uu5l+8ny2ea/5p11up58Vu97AYffchY4z
PuKTZvLlPGL/oe/7ZBCAZBrWiE2qDXrU+tDGnBGD9ZiF5aTHNNMFMH+GXlUNNQby
2gh3sVxjkesgg4fuMUhoipJVtIzZxh/t/+bKus2OSNTBfYAUY/LuB3MKO4NWSz+j
EnaKtzjV9WBn0K5NDxf6BiU6Inzhud+9xehKd55glwt6XWcvKCC+ejss9IYV+rC+
o/nA9Oz5K3vnJDZZCGKHcloowP5EWNXCXdVdMM1KpoIS0nTCKtO98vJ6Q7YXWIXD
L4Ia8NbqNKUfUhXYDA1MJN2y0dU9AhmptdOKbL/b/qhjenTUYQCT
=02qt
-----END PGP SIGNATURE-----
Merge tag 'v5.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
A lot more love for rk3288 in general and veyron specially with changes
all over the place.
* tag 'v5.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits)
ARM: dts: rockchip: Split GPIO keys for veyron into multiple devices
ARM: dts: rockchip: Add HDMI i2c unwedging for rk3288-veyron
ARM: dts: rockchip: Add unwedge pinctrl entries for dw_hdmi on rk3288
ARM: dts: rockchip: Switch to builtin HDMI DDC bus on rk3288-veyron
ARM: dts: rockchip: Add pin names for rk3288-veyron jaq, mickey, speedy
ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3
ARM: dts: rockchip: Configure the GPU thermal zone for mickey
ARM: dts: rockchip: Use the GPU to cool CPU thermal zone of veyron mickey
ARM: dts: rockchip: remove GPU 500 MHz OPP on rk3288
ARM: dts: rockchip: Use GPU as cooling device for the GPU thermal zone of the rk3288
ARM: dts: rockchip: Add #cooling-cells entry for rk3288 GPU
ARM: dts: rockchip: Mark that the rk3288 timer might stop in suspend
ARM: dts: rockchip: Add pin names for rk3288-veyron-jerry
ARM: dts: rockchip: Add pin names for rk3288-veyron-minnie
ARM: dts: raise GPU trip point temperature for speedy to 80 degC
ARM: dts: rockchip: raise GPU trip point temperatures for veyron
ARM: dts: rockchip: raise CPU trip point temperature for veyron to 100 degC
ARM: dts: rockchip: Make rk3288-veyron-minnie run at hs200
ARM: dts: rockchip: Make rk3288-veyron-mickey's emmc work again
ARM: dts: rockchip: Remove bogus 'i2s_clk_out' from rk3288-veyron-mickey
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds a reset-cells property to the gcc controller on the QCS404.
Without this in place, we get warnings like the following if nodes reference
a gcc reset:
arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property):
/soc@0/remoteproc@b00000: Missing property '#reset-cells' in node
/soc@0/clock-controller@1800000 or bad phandle (referred from resets[0])
also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3
DTC arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property):
/soc@0/remoteproc@b00000: Missing property '#reset-cells' in node
/soc@0/clock-controller@1800000 or bad phandle (referred from resets[0])
also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3
Signed-off-by: Andy Gross <agross@kernel.org>
Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add one Spreadtrum SD host controller to support eMMC card for Spreadtrum
SC9860 platform.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the on-chip SRAM present within the MCU domain as a mmio-sram node.
The K3 J721E SoCs have 1 MB of such memory. Any specific memory range
within this RAM needed by a driver/software module ought to be reserved
using an appropriate child node.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Wakeup domain in J721E SoC has an interrupt router connected to gpio
in wakeup domain. Add DT node for this interrupt router.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Main domain in J721E has the following interrupt controller instances:
- Main Domain GPIO Interrupt router connected to gpio in main domain.
- Under the Main Domain Navigator Subsystem(NAVSS)
- Main Navss Interrupt Router connected to main navss inta and mailboxes.
- Main Navss Interrupt Aggregator connected to main domain UDMASS
Add DT nodes for the interrupt controllers available in main domain.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the Interrupt controller node for the Interrupt Router present within
the Main NavSS module. This Interrupt Router can route 192 interrupts to
the GIC_SPI in 3 sets of 64 interrupts each. Note that the last set is
reserved for the host ID A72_3 for hypervisor usecases, so the node is
added only with 2 sets for the Linux kernel context (host id A72_2). This
is specified through the ti,sci-rm-range-girq property.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add Support for J721E Common Processor board support.
The EVM architecture is as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality. Add-n card
options add further functionality (such as additional Audio, Display,
networking options).
Note:
A) The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
B) Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
C) All daughter cards beyond the basic boards shall be maintained as
overlays.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
J721e uses a UART controller that is compatible with AM654 UART.
Introduce a specific compatible to help handle the differences if
necessary.
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
The J721E SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable lower system costs
of automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
This SoC is designed around reducing the system cost by eliminating
the need of an external system MCU and is targeted towards ASIL-B/C
certification/requirements in addition to allowing complex software
and system use-cases.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep
capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA),
C7x floating point Vector DSP, Two C66x floating point DSPs.
* 3D GPU PowerVR Rogue 8XE GE8430
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and
up to two DPI interfaces.
* Integrated Ethernet switch supporting up to a total of 8 external ports in
addition to legacy Ethernet switch of up to 2 ports.
* System MMU (SMMU) Version 3.0 and advanced virtualisation
capabilities.
* Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems,
16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI,
I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
* Configurable L3 Cache and IO-coherent architecture with high data throughput
capable distributed DMA architecture under NAVSS
* Centralized System Controller for Security, Power, and Resource
Management (DMSC)
See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
