PCIe for rockpro64, wifi+bt for Rock-PI4, spi for Rock960 family
and a fix for the yet unused isp-iommus. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlz/ZpUQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgTV7B/0XnPl7iXuZlASPd4isXVofOtVzRlASNupn QsFg0KUb49p6s5rmc3QZNjJ+1CLk441UW009AkE/3pd+j10lv7AHdr/NGSI6Z7P0 4iNFFmI4SmZIkEvnmJD9HmX8Pg/cflWPEC26Mm5GlISy8kFQKqEJb6bXxjOSgAC/ GI+SnVBM4g2MK3RcGVPGIN2mPOQt6BseFXe4BEeIq7XpT+2kBkkBuphCmv4UECLB az0fmRuW+fQHLqRdsvOByxQQQLYB6wiEEMQqsqUegfywACLOGgB+qE1qAt2SvQJz Ek8uX4s1IKFx1DQ+GgGJ7rgBKv61AODoS6SDUmUYkorDwpQmni+k =Nria -----END PGP SIGNATURE----- Merge tag 'v5.3-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt PCIe for rockpro64, wifi+bt for Rock-PI4, spi for Rock960 family and a fix for the yet unused isp-iommus. * tag 'v5.3-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: add WiFi+BT support on ROCK Pi4 board arm64: dts: rockchip: fix isp iommu clocks and power domain arm64: dts: rockchip: Enable SPI1 on Ficus arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960 arm64: dts: rockchip: add PCIe nodes on rk3399-rockpro64 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
3990c9918a
@ -146,6 +146,12 @@
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};
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};
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&spi1 {
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/* On both Low speed and High speed expansion */
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cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>;
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status = "okay";
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};
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&usbdrd_dwc3_0 {
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dr_mode = "host";
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};
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@ -25,6 +25,15 @@
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#clock-cells = <0>;
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&rk808 1>;
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clock-names = "ext_clock";
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_enable_h>;
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reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
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};
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vcc12v_dcin: dc-12v {
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compatible = "regulator-fixed";
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regulator-name = "vcc12v_dcin";
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@ -451,12 +460,46 @@
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};
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&pinctrl {
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bt {
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bt_enable_h: bt-enable-h {
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rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bt_host_wake_l: bt-host-wake-l {
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rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bt_wake_l: bt-wake-l {
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rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pcie {
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pcie_pwr_en: pcie-pwr-en {
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rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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sdio0 {
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sdio0_bus4: sdio0-bus4 {
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rockchip,pins =
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<2 20 RK_FUNC_1 &pcfg_pull_up_20ma>,
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<2 21 RK_FUNC_1 &pcfg_pull_up_20ma>,
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<2 22 RK_FUNC_1 &pcfg_pull_up_20ma>,
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<2 23 RK_FUNC_1 &pcfg_pull_up_20ma>;
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};
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sdio0_cmd: sdio0-cmd {
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rockchip,pins =
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<2 24 RK_FUNC_1 &pcfg_pull_up_20ma>;
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};
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sdio0_clk: sdio0-clk {
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rockchip,pins =
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<2 25 RK_FUNC_1 &pcfg_pull_none_20ma>;
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};
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};
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pmic {
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pmic_int_l: pmic-int-l {
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rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
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@ -482,6 +525,17 @@
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rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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wifi {
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wifi_enable_h: wifi-enable-h {
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rockchip,pins =
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<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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wifi_host_wake_l: wifi-host-wake-l {
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rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pwm2 {
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@ -494,6 +548,32 @@
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vref-supply = <&vcc_1v8>;
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};
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&sdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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bus-width = <4>;
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clock-frequency = <50000000>;
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cap-sdio-irq;
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cap-sd-highspeed;
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keep-power-in-suspend;
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mmc-pwrseq = <&sdio_pwrseq>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
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sd-uhs-sdr104;
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status = "okay";
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brcmf: wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
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interrupt-names = "host-wake";
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_host_wake_l>;
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};
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};
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&sdmmc {
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bus-width = <4>;
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cap-mmc-highspeed;
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@ -557,6 +637,23 @@
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "okay";
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bluetooth {
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compatible = "brcm,bcm43438-bt";
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clocks = <&rk808 1>;
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clock-names = "ext_clock";
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device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
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host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
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shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
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};
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};
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&uart2 {
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status = "okay";
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};
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@ -114,6 +114,16 @@
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};
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};
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&spi0 {
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/* On Low speed expansion (LS-SPI0) */
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status = "okay";
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};
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&spi4 {
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/* On High speed expansion (HS-SPI1) */
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status = "okay";
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};
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&usbdrd_dwc3_0 {
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dr_mode = "otg";
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};
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@ -513,6 +513,20 @@
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gpio1830-supply = <&vcc_3v0>;
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};
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&pcie0 {
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ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
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num-lanes = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_perst>;
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vpcie12v-supply = <&vcc12v_dcin>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pcie_phy {
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status = "okay";
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};
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&pmu_io_domains {
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pmu1830-supply = <&vcc_3v0>;
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status = "okay";
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@ -542,6 +556,10 @@
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};
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pcie {
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pcie_perst: pcie-perst {
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rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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pcie_pwr_en: pcie-pwr-en {
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rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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@ -1706,11 +1706,11 @@
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reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "isp0_mmu";
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clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
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clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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power-domains = <&power RK3399_PD_ISP0>;
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rockchip,disable-mmu-reset;
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status = "disabled";
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};
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isp1_mmu: iommu@ff924000 {
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@ -1718,11 +1718,11 @@
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reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "isp1_mmu";
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clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
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clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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power-domains = <&power RK3399_PD_ISP1>;
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rockchip,disable-mmu-reset;
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status = "disabled";
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};
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hdmi_sound: hdmi-sound {
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