linux

Author	SHA1	Message	Date
Stephen Boyd	28ecaf1c30	Merge branches 'clk-unisoc', 'clk-tegra', 'clk-qcom' and 'clk-imx' into clk-next - Add support for Unisoc SC9863A clks - GPU GX GDSC support on Qualcomm sc7180 - Qualcomm SM8250 RPMh and MSM8976 RPM clks - Qualcomm SM8250 Global Clock Controller (GCC) support - Qualcomm SC7180 Modem Clock Controller (MSS CC) support * clk-unisoc: clk: sprd: fix to get a correct ibias of pll clk: sprd: add clocks support for SC9863A clk: sprd: support to get regmap from parent node clk: sprd: Add macros for referencing parents without strings clk: sprd: Add dt-bindings include file for SC9863A dt-bindings: clk: sprd: add bindings for sc9863a clock controller dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific clk: sprd: add gate for pll clocks * clk-tegra: clk: tegra: Use NULL for pointer initialization clk: tegra: Remove audio clocks configuration from clock driver clk: tegra: Remove tegra_pmc_clk_init along with clk ids clk: tegra: Remove CLK_M_DIV fixed clocks clk: tegra: Fix Tegra PMC clock out parents clk: tegra: Add Tegra OSC to clock lookup clk: tegra: Add support for OSC_DIV fixed clocks dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: clock: tegra: Add IDs for OSC clocks * clk-qcom: (21 commits) clk: qcom: rpmh: Drop unnecessary semicolons clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 ipq806x: gcc: Added the enable regs and mask for PRNG clk: qcom: Add modem clock controller driver for SC7180 clk: qcom: gcc: Add support for modem clocks in GCC dt-bindings: clock: Add YAML schemas for the QCOM MSS clock bindings clk: qcom: clk-rpm: add missing rpm clk for ipq806x clk: qcom: gcc: Add global clock controller driver for SM8250 dt-bindings: clock: Add SM8250 GCC clock bindings clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs clk: qcom: clk-alpha-pll: Refactor trion PLL clk: qcom: clk-alpha-pll: Use common names for defines dt-bindings: clock: rpmcc: Document msm8976 compatible clk: qcom: smd: Add support for MSM8976 rpm clocks clk: qcom: clk-rpmh: Wait for completion when enabling clocks clk: qcom: rpmh: Add support for RPMH clocks on SM8250 dt-bindings: clock: Add RPMHCC bindings for SM8250 clk: qcom: alpha-pll: Make error prints more informative clk: qcom: gpucc: Add support for GX GDSC for SC7180 ... * clk-imx: (43 commits) dt-bindings: imx8mm-clock: Fix the file path dt-bindings: imx8mq-clock: Fix the file path clk: imx: clk-gate2: Pass the device to the register function clk: imx7d: Add PXP clock clk: imx8mq: A53 core clock no need to be critical clk: imx8mp: A53 core clock no need to be critical clk: imx8mm: A53 core clock no need to be critical clk: imx8mn: A53 core clock no need to be critical clk: imx: pllv4: use prepare/unprepare clk: imx: pfdv2: determine best parent rate clk: imx: pfdv2: switch to use determine_rate clk: imx: Fix division by zero warning on pfdv2 clk: imx: clk-sscg-pll: Drop unnecessary initialization clk: imx: pll14xx: Return error if pll type is invalid clk: imx: imx8mp: fix a53 cpu clock clk: imx: imx8mn: fix a53 cpu clock clk: imx: imx8mm: fix a53 cpu clock clk: imx: imx8mq: fix a53 cpu clock clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock clk: imx8mn: Remove unused includes ...	2020-04-03 15:10:19 -07:00
Stephen Boyd	53a2cc5cc3	Merge branches 'clk-ti', 'clk-ingenic', 'clk-typo', 'clk-at91', 'clk-mmp2' and 'clk-arm-icst' into clk-next - EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs - Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs - Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers * clk-ti: clk: keystone: Add new driver to handle syscon based clocks dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK * clk-ingenic: clk: ingenic/TCU: Fix round_rate returning error clk: ingenic/jz4770: Exit with error if CGU init failed clk: JZ4780: Add function for enable the second core. clk: Ingenic: Add support for TCU of X1000. * clk-typo: clk: Fix trivia typo in comment exlusive => exclusive * clk-at91: clk: at91: add at91rm9200 pmc driver clk: at91: add at91sam9n12 pmc driver clk: at91: add sama5d3 pmc driver clk: at91: add at91sam9g45 pmc driver clk: at91: usb: introduce num_parents in driver's structure clk: at91: usb: use proper usbs_mask clk: at91: sam9x60: fix usb clock parents clk: at91: usb: continue if clk_hw_round_rate() return zero clk: at91: sam9x60: Don't use audio PLL * clk-mmp2: clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks clk: mmp2: Add clock for fifth SD HCI on MMP3 dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 clk: mmp2: Add clocks for the thermal sensors dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors clk: mmp2: add the GPU clocks dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks clk: mmp2: Add PLLs that are available on MMP3 dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs clk: mmp2: Check for MMP3 dt-bindings: clock: Add MMP3 compatible string clk: mmp2: Stop pretending PLL outputs are constant clk: mmp2: Add support for PLL clock sources dt-bindings: clock: Convert marvell,mmp2-clock to json-schema clk: mmp2: Constify some strings clk: mmp2: Remove a unused prototype * clk-arm-icst: MAINTAINERS: dt: update reference for arm-integrator.txt clk: versatile: Add device tree probing for IM-PD1 clocks clk: versatile: Export icst_clk_setup() dt-bindings: clock: Create YAML schema for ICST clocks	2020-04-03 15:09:55 -07:00
Stephen Boyd	2d11e9a1fd	Merge branches 'clk-phase-errors', 'clk-amlogic', 'clk-renesas' and 'clk-allwinner' into clk-next - Don't show clk phase when it is invalid * clk-phase-errors: clk: rockchip: fix mmc get phase clk: Fix phase init check clk: Bail out when calculating phase fails during clk registration clk: Move rate and accuracy recalc to mostly consumer APIs clk: Use 'parent' to shorten lines in __clk_core_init() clk: Don't cache errors from clk_ops::get_phase() * clk-amlogic: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate * clk-renesas: dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema clk: renesas: rcar-usb2-clock-sel: Add reset_control clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties clk: renesas: Remove use of ARCH_R8A7795 clk: renesas: r8a77965: Add RPC clocks clk: renesas: r8a7796: Add RPC clocks clk: renesas: r8a7795: Add RPC clocks clk: renesas: rcar-gen3: Add CCREE clocks * clk-allwinner: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock	2020-04-03 15:09:32 -07:00
Stephen Boyd	ea0a1fb716	Merge branches 'clk-samsung', 'clk-formatting', 'clk-si5341' and 'clk-socfpga' into clk-next * clk-samsung: clk: samsung: Remove redundant check in samsung_cmu_register_one * clk-formatting: clk: Fix continuation of of_clk_detect_critical() * clk-si5341: clk, clk-si5341: Support multiple input ports * clk-socfpga: clk: socfpga: stratix10: simplify parameter passing clk: stratix10: use do_div() for 64-bit calculation	2020-04-03 15:09:22 -07:00
Chunyan Zhang	39d1c90665	clk: sprd: fix to get a correct ibias of pll The current driver is getting a wrong ibias index of pll clocks from number 1. This patch fix that issue, then getting ibias index from 0. Fixes: `3e37b00558` ("clk: sprd: add adjustable pll support") Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200330021640.14133-1-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-04-02 18:07:58 -07:00
Fabio Estevam	a8b4543093	dt-bindings: imx8mm-clock: Fix the file path Currently the following warning is seen with 'make dt_binding_check': Documentation/devicetree/bindings/clock/imx8mm-clock.yaml: $id: relative path/filename doesn't match actual path or filename Fix it by removing the "bindings" directory from the file path. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lkml.kernel.org/r/20200326171933.13394-2-festevam@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-26 23:09:43 -07:00
Fabio Estevam	1915253e35	dt-bindings: imx8mq-clock: Fix the file path Currently the following warning is seen with 'make dt_binding_check': Documentation/devicetree/bindings/clock/imx8mq-clock.yaml: $id: relative path/filename doesn't match actual path or filename Fix it by removing the "bindings" directory from the file path. Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lkml.kernel.org/r/20200326171933.13394-1-festevam@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-26 23:09:43 -07:00
Stephen Boyd	751d792343	clk: qcom: rpmh: Drop unnecessary semicolons Some functions end in }; which is just bad style. Remove the extra semicolon. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200309221232.145630-3-sboyd@kernel.org	2020-03-24 19:35:02 -07:00
Stephen Boyd	2cf7a4cbcb	clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd() This function has some duplication in unlocking a mutex and returns in a few different places. Let's use some if statements to consolidate code and make this a bit easier to read. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> CC: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200309221232.145630-2-sboyd@kernel.org	2020-03-24 19:35:00 -07:00
Stephen Boyd	17bbcd7d5f	i.MX clock drivers update for 5.7: - A series from Anson to convert i.MX8 clock bindings to json-schema. - Update pll14xx driver to include new frequency entries for pll1443x table, and return error for invalid PLL type. - Clean up header includes and unnecessary code on a few clock driver. - Add mssing of_node_put() call for a number of clock drivers. - Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already have the flag on its child cpu clock. - Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL via CORE_SEL slice, and source from A53 CCM clk root when we need to change ARM PLL frequency. Thus, we can support core running above 1GHz safely. - Update pfdv2 driver to check zero rate and use determine_rate for getting the best rate. - Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d. -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl5vHoUUHHNoYXduZ3Vv QGtlcm5lbC5vcmcACgkQUFdYWoewfM6lNgf/Qe1jojmzjLPD/QhC31sDrQMTZ+vQ K309EiXjcZdJ8QTIRTO9IIPHYzy82vjCNywzdy1azQEmPAqDj+MPAjRLu3KLFjr5 husU0wzSdGvkPQ7d4w+GI/4KfeP0evyXFioGyMKF//iFUKrurSc08ZbMBNtLsrQu a6iTia2+1UDzKbN5grKNu/JKYdAceoca1fRNCvkoysKUnqOm9be5eT0QfA7v+V8A I8qhGjKAzI8R2cfxuxRAG9Zw3/b2nbvzngkRMauId7nkD+gYTcP4q9la1ZibbR68 K6lZqjpi5BTN+5cDxkI3ezEstGshVJvd5jDeh2IIzcFCdeG5JF/pUsbZ+A== =h3BT -----END PGP SIGNATURE----- Merge tag 'clk-imx-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clk driver updates from Shawn Guo: - A series from Anson to convert i.MX8 clock bindings to json-schema - Update pll14xx driver to include new frequency entries for pll1443x table, and return error for invalid PLL type - Clean up header includes and unnecessary code on a few clock driver - Add mssing of_node_put() call for a number of clock drivers - Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already have the flag on its child cpu clock - Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL via CORE_SEL slice, and source from A53 CCM clk root when we need to change ARM PLL frequency. Thus, we can support core running above 1GHz safely - Update pfdv2 driver to check zero rate and use determine_rate for getting the best rate - Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for imx7d * tag 'clk-imx-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits) clk: imx: clk-gate2: Pass the device to the register function clk: imx7d: Add PXP clock clk: imx8mq: A53 core clock no need to be critical clk: imx8mp: A53 core clock no need to be critical clk: imx8mm: A53 core clock no need to be critical clk: imx8mn: A53 core clock no need to be critical clk: imx: pllv4: use prepare/unprepare clk: imx: pfdv2: determine best parent rate clk: imx: pfdv2: switch to use determine_rate clk: imx: Fix division by zero warning on pfdv2 clk: imx: clk-sscg-pll: Drop unnecessary initialization clk: imx: pll14xx: Return error if pll type is invalid clk: imx: imx8mp: fix a53 cpu clock clk: imx: imx8mn: fix a53 cpu clock clk: imx: imx8mm: fix a53 cpu clock clk: imx: imx8mq: fix a53 cpu clock clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock clk: imx8mn: Remove unused includes clk: imx8mm: Remove unused includes clk: imx8mp: Include slab.h instead of clkdev.h ...	2020-03-24 19:23:49 -07:00
Stephen Boyd	ba0eb9d57a	clk: tegra: Use NULL for pointer initialization This silences a sparse warning about using a plain integer instead of NULL for a pointer. Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:14:12 -07:00
Stephen Boyd	37a94882a3	clk: tegra: Changes for v5.7-rc1 These changes remove PMC clocks from the clock and reset controller driver because they are controlled by bits in the PMC controller. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl5rs/8THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoRuvD/45ZRenGVCVxxvFqEgs7p2Vwpv8373P UQx8atoK61wb6F9+crGdLhOUBiT/hBOsDkbeR6Pgi3zLNEtVLM02SQUPQmux1qNG 5GD9QrRkLWF6k91ovwGNDErfwmHtUmGZd3sCADTQs5361A3Yj7UGpkYb7Sx9anxo MLbwTNepOhrfqqyVKy11wyWYXiuU71qZosT/Hvgg/TuXxwePrKaCmgry631X98vf 88NNDsT/P82nnsdBqZFMagxBlolzhCZSxkfwEcboHxxadCXhxa+RQkTkFFzbQwtd Grs2sG2nrSEczAAuzyOYGPwq75ZqCg3roqdfXBEeGcGAiLqjibUizu8EYp5rkydI FtGIQK9bHGUoa+4/wtlLiMfzLTRvjB0WbpG0fK53lSasyfHgatqMlu0yD3PF5tgc zcVicb3wVPhRi+1mn3gY+yZD99GHgtwGodbOp2kaKNgXajdUDH76xgXq/RDISF7n qPe41CQtlACeo1MQ61O42BPRMOSgtsE7XaJZh8PdtqxrsGn0PSkyvWnFH4r3w6RM /jmJNax1ak9oNFODP6i02wwv8XY03sRzWEeOrHcVWWh0YJeI1x9gxVwvDhpW3odp 4Z38LVK29ZbKRxO6KbsehqUiaqtJEfHcPoj+CLO6OIAK4suB5hzHNAInPzUNVWHi ED1ebh57Yej9Rg== =iXOG -----END PGP SIGNATURE----- Merge tag 'for-5.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra Pull Nvidia Tegra clk driver updates from Thierry Reding: These changes remove PMC clocks from the clock and reset controller driver because they are controlled by bits in the PMC controller. * tag 'for-5.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Remove audio clocks configuration from clock driver clk: tegra: Remove tegra_pmc_clk_init along with clk ids clk: tegra: Remove CLK_M_DIV fixed clocks clk: tegra: Fix Tegra PMC clock out parents clk: tegra: Add Tegra OSC to clock lookup clk: tegra: Add support for OSC_DIV fixed clocks dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings dt-bindings: tegra: Convert Tegra PMC bindings to YAML dt-bindings: clock: tegra: Add IDs for OSC clocks	2020-03-24 19:06:38 -07:00
Chunyan Zhang	0e4b8a2349	clk: sprd: add clocks support for SC9863A Add the list of clocks for the Unisoc SC9863A, along with clock initialization. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-8-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:57 -07:00
Chunyan Zhang	f95e8c7923	clk: sprd: support to get regmap from parent node Some SC9863a clock nodes would be the child of a syscon node, clocks can use the regmap of syscon device directly for this kind of cases. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-7-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:57 -07:00
Chunyan Zhang	ea8ca3109d	clk: sprd: Add macros for referencing parents without strings With the new clk parenting code, clk_init_data was expanded to include .parent_hws and .parent_data, for clk drivers to specify parents without name strings of clocks. Also some macros were added for using these two items to reference clock parents. Based on that to expand macros for sprd clocks: - SPRD__DATA, take an array of struct clk_parent_data as its parents which should be a combination of .fw_name (devicetree clock-names), .hw (pointers to a local struct clk_hw). - SPRD__HW, take a local struct clk_hw pointer, instead of a string, as its parent. - SPRD__FW_NAME, take a string of clock-names decleared in the device tree as the clock parent. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-6-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:57 -07:00
Chunyan Zhang	be7ef655be	clk: sprd: Add dt-bindings include file for SC9863A This file defines all SC9863A clock indexes, it should be included in the device tree in which there's device using the clocks. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200304072730.9193-5-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:56 -07:00
Chunyan Zhang	eba8ba8ada	dt-bindings: clk: sprd: add bindings for sc9863a clock controller add a new bindings to describe sc9863a clock compatible string. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-4-zhang.lyra@gmail.com Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:56 -07:00
Chunyan Zhang	2112d1ddb9	dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific Only SC9860 clocks were described in sprd.txt, rename it with a SoC specific name, so that we can add more SoC support. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200304072730.9193-3-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:56 -07:00
Xiaolong Zhang	187e5cd2d1	clk: sprd: add gate for pll clocks Some sprd's gate clocks are used to the switch of pll, which need to wait a certain time for stable after being enabled. Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:03:56 -07:00
Mauro Carvalho Chehab	7928f4f6a2	MAINTAINERS: dt: update reference for arm-integrator.txt This file was renamed. Update references accordingly. Fixes: `78c7d8f96b` ("dt-bindings: clock: Create YAML schema for ICST clocks") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lkml.kernel.org/r/491d2928a47f59da3636bc63103a5f63fec72b1a.1584966325.git.mchehab+huawei@kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-24 19:02:26 -07:00
Lubomir Rintel	de17be999c	clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks They were reversed because I read the datasheet upside down. Actually there is no datasheet, but I ended up understanding the comments in Open Firmware driver wrong. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-18-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:41 -07:00
Lubomir Rintel	54198276ba	clk: mmp2: Add clock for fifth SD HCI on MMP3 There's one extra SDHCI on MMP3, used by the internal SD card on OLPC XO-4. Add a clock for it. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-17-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:40 -07:00
Lubomir Rintel	c2ca122a0a	dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3 There's one extra SDHCI on MMP3, used by the internal SD card on OLPC XO-4. Add a clock for it. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-16-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:40 -07:00
Lubomir Rintel	82d59c382c	clk: mmp2: Add clocks for the thermal sensors The register definitions gotten from OLPC Open Firmware. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-15-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:40 -07:00
Lubomir Rintel	41a8632049	dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors There seems to be a single thermal sensor block on MMP2 and a couple more on MMP3. Add definitions for their respective clocks. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-14-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:40 -07:00
Lubomir Rintel	bfa851b60c	clk: mmp2: add the GPU clocks MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300. On both platforms there's an AXI bus interface clock that's common for all GPUs and each GPU core has a separate clock. Meaning of the relevant APMU_GPU bits were gotten from James Cameron's message and [1], the OLPC OS kernel source [2] and Marvell's MMP3 tree. [1] http://lists.laptop.org/pipermail/devel/2019-April/039053.html [2] http://dev.laptop.org/git/olpc-kernel/commit/arch/arm/mach-mmp/mmp2.c?h=arm-3.0-wip&id=8ce9f6122 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-13-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:40 -07:00
Lubomir Rintel	e3142226fe	dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300. On both platforms there's an AXI bus interface clock that's common for all GPUs and each GPU core has a separate clock. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-12-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:40 -07:00
Lubomir Rintel	a70812b188	clk: mmp2: Add PLLs that are available on MMP3 There are more PLLs on MMP3 and are configured slightly differently. Tested on a MMP3-based Dell Wyse 3020 machine. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-10-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:32 -07:00
Lubomir Rintel	4d6da655d1	dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs MMP3 variant provides some more clocks. Add respective IDs. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200309194254.29009-9-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:32 -07:00
Lubomir Rintel	391bbbd2b2	clk: mmp2: Check for MMP3 The MMP3's are similar enough to MMP2, but there are differencies, such are more clocks available on the newer model. We want to tell which platform are we on. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-8-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:32 -07:00
Lubomir Rintel	b90e0eb304	dt-bindings: clock: Add MMP3 compatible string This binding describes the PMUs that are found on MMP3 as well. Add the compatible strings and adjust the description. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200309194254.29009-7-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:31 -07:00
Lubomir Rintel	ea56ad6026	clk: mmp2: Stop pretending PLL outputs are constant The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default, but also configurable. Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and set-pll2-988mhz Open Firmware words. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:31 -07:00
Lubomir Rintel	5d34d0b32d	clk: mmp2: Add support for PLL clock sources The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are constant, but in fact they are configurable. Add logic for obtaining the actual clock rates on MMP2 as well as MMP3. There is no documentation for either SoC, but the "systemsetting" drivers from Marvell GPL code dump provide some clue as far as MPMU registers on MMP2 [1] and MMP3 [2] go. [1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c [2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c A separate commit will adjust the clk-of-mmp2 driver. Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC XO-1.75 laptop. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-5-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:31 -07:00
Lubomir Rintel	7de0b8b8b0	dt-bindings: clock: Convert marvell,mmp2-clock to json-schema Convert the fixed-factor-clock binding to DT schema format using json-schema. While at that, fix a couple of small errors: make the file base name match the compatible string, add an example and document the reg-names property. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/20200309194254.29009-4-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:31 -07:00
Lubomir Rintel	cb8dbfe831	clk: mmp2: Constify some strings All the parent clock names for the muxes are constant. Add const. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-3-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:30 -07:00
Lubomir Rintel	b3296386c5	clk: mmp2: Remove a unused prototype There is no mmp_clk_register_pll2() routine. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-2-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:19:30 -07:00
Alexandre Belloni	02ff48e4d7	clk: at91: add at91rm9200 pmc driver Add a driver for the PMC clocks of the at91rm9200. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20200214145934.53648-1-alexandre.belloni@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 18:18:58 -07:00
Linus Walleij	84655b762a	clk: versatile: Add device tree probing for IM-PD1 clocks As we want to move these clocks over to probe from the device tree we add a device tree probing path. The old platform data path will be deleted once we have the device tree overall code in place. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lkml.kernel.org/r/20200219103326.81120-3-linus.walleij@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:55:31 -07:00
Linus Walleij	eb9d6428a7	clk: versatile: Export icst_clk_setup() Export this clock setup method so we can register the IM-PD1 clocks with common code in the next step. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lkml.kernel.org/r/20200219103326.81120-2-linus.walleij@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:55:31 -07:00
Linus Walleij	78c7d8f96b	dt-bindings: clock: Create YAML schema for ICST clocks The ICST clocks used in the ARM Integrator, Versatile and RealView platforms are updated to use YAML schema, and two new ICST clocks used by the Integrator IM-PD1 logical module are added in the process. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lkml.kernel.org/r/20200219103326.81120-1-linus.walleij@linaro.org [sboyd@kernel.org: Fix some typos] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:55:21 -07:00
Andy Shevchenko	a37a5a9d71	clk: Fix trivia typo in comment exlusive => exclusive Fix trivia typo in comment exlusive => exclusive. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lkml.kernel.org/r/20200310135507.87959-1-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:12:48 -07:00
Paul Cercueil	edcc42945d	clk: ingenic/TCU: Fix round_rate returning error When requesting a rate superior to the parent's rate, it would return -EINVAL instead of simply returning the parent's rate like it should. Fixes: `4f89e4b8f1` ("clk: ingenic: Add driver for the TCU clocks") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200213161952.37460-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:08:40 -07:00
Paul Cercueil	c067b46d73	clk: ingenic/jz4770: Exit with error if CGU init failed Exit jz4770_cgu_init() if the 'cgu' pointer we get is NULL, since the pointer is passed as argument to functions later on. Fixes: `7a01c19007` ("clk: Add Ingenic jz4770 CGU driver") Cc: stable@vger.kernel.org Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lkml.kernel.org/r/20200213161952.37460-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:08:40 -07:00
Vignesh Raghavendra	1aa0817e43	clk: keystone: Add new driver to handle syscon based clocks On TI's AM654/J721e SoCs, certain clocks can be gated/ungated by setting a single bit in SoC's System Control Module registers. Sometime more than one clock control can be in the same register. Add a driver to support such clocks using syscon framework. Driver currently supports controlling EHRPWM's TimeBase clock(TBCLK) for AM654 SoC. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lkml.kernel.org/r/20200227053529.16479-3-vigneshr@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:07:21 -07:00
Vignesh Raghavendra	cf891c6be1	dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK Add DT bindings for TI EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lkml.kernel.org/r/20200227053529.16479-2-vigneshr@ti.com Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:05:48 -07:00
周琰杰 (Zhou Yanjie)	6673db4f3f	clk: JZ4780: Add function for enable the second core. Add "jz4780_core1_enable()" for enable the second core of JZ4780, prepare for later commits. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:02:03 -07:00
周琰杰 (Zhou Yanjie)	dc6a81c338	clk: Ingenic: Add support for TCU of X1000. X1000 has a different TCU, since X1000 OST has been independent of TCU. This patch is add TCU support of X1000, and prepare for later OST driver. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lkml.kernel.org/r/1584457893-40418-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 17:01:38 -07:00
Wesley Cheng	8411aa5059	clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 This adds the USB3 PIPE clock and GDSC structures, so that the USB driver can vote for these resources to be enabled/disabled when required. Both are needed for SS and HS USB paths to operate properly. The GDSC will allow the USB system to be brought out of reset, while the PIPE clock is needed for data transactions between the PHY and controller. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lkml.kernel.org/r/1584478412-7798-2-git-send-email-wcheng@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 16:33:56 -07:00
Abhishek Sahu	1aec193ea4	ipq806x: gcc: Added the enable regs and mask for PRNG Kernel got hanged while reading from /dev/hwrng at the time of PRNG clock enable Fixes: `24d8fba44a` "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 16:29:02 -07:00
Taniya Das	8def929c40	clk: qcom: Add modem clock controller driver for SC7180 Add support for the modem clock controller found on SC7180 based devices. This would allow modem drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1584596131-22741-4-git-send-email-tdas@codeaurora.org Tested-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2020-03-20 16:28:05 -07:00

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