Merge branches 'clk-samsung', 'clk-formatting', 'clk-si5341' and 'clk-socfpga' into clk-next
* clk-samsung: clk: samsung: Remove redundant check in samsung_cmu_register_one * clk-formatting: clk: Fix continuation of of_clk_detect_critical() * clk-si5341: clk, clk-si5341: Support multiple input ports * clk-socfpga: clk: socfpga: stratix10: simplify parameter passing clk: stratix10: use do_div() for 64-bit calculation
This commit is contained in:
Stephen Boyd
commit
ea0a1fb716
@ -16,6 +16,8 @@
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#include <linux/slab.h>
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#include <asm/unaligned.h>
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#define SI5341_NUM_INPUTS 4
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#define SI5341_MAX_NUM_OUTPUTS 10
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#define SI5340_MAX_NUM_OUTPUTS 4
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@ -56,8 +58,8 @@ struct clk_si5341 {
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struct i2c_client *i2c_client;
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struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
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struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
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struct clk *pxtal;
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const char *pxtal_name;
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struct clk *input_clk[SI5341_NUM_INPUTS];
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const char *input_clk_name[SI5341_NUM_INPUTS];
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const u16 *reg_output_offset;
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const u16 *reg_rdiv_offset;
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u64 freq_vco; /* 13500–14256 MHz */
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@ -78,10 +80,25 @@ struct clk_si5341_output_config {
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#define SI5341_DEVICE_REV 0x0005
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#define SI5341_STATUS 0x000C
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#define SI5341_SOFT_RST 0x001C
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#define SI5341_IN_SEL 0x0021
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#define SI5341_XAXB_CFG 0x090E
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#define SI5341_IN_EN 0x0949
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#define SI5341_INX_TO_PFD_EN 0x094A
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/* Input selection */
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#define SI5341_IN_SEL_MASK 0x06
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#define SI5341_IN_SEL_SHIFT 1
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#define SI5341_IN_SEL_REGCTRL 0x01
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#define SI5341_INX_TO_PFD_SHIFT 4
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/* XTAL config bits */
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#define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
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#define SI5341_XAXB_CFG_PDNB BIT(1)
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/* Input dividers (48-bit) */
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#define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
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#define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
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#define SI5341_PX_UPD 0x0230
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/* PLL configuration */
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#define SI5341_PLL_M_NUM 0x0235
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@ -120,6 +137,10 @@ struct si5341_reg_default {
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u8 value;
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};
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static const char * const si5341_input_clock_names[] = {
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"in0", "in1", "in2", "xtal"
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};
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/* Output configuration registers 0..9 are not quite logically organized */
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static const u16 si5341_reg_output_offset[] = {
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0x0108,
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@ -390,7 +411,112 @@ static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
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return (unsigned long)res;
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}
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static int si5341_clk_get_selected_input(struct clk_si5341 *data)
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{
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int err;
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u32 val;
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err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
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if (err < 0)
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return err;
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return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
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}
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static u8 si5341_clk_get_parent(struct clk_hw *hw)
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{
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struct clk_si5341 *data = to_clk_si5341(hw);
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int res = si5341_clk_get_selected_input(data);
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if (res < 0)
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return 0; /* Apparently we cannot report errors */
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return res;
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}
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static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
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{
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int err;
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u8 val;
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val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
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/* Enable register-based input selection */
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val |= SI5341_IN_SEL_REGCTRL;
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err = regmap_update_bits(data->regmap,
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SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
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if (err < 0)
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return err;
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if (index < 3) {
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/* Enable input buffer for selected input */
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err = regmap_update_bits(data->regmap,
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SI5341_IN_EN, 0x07, BIT(index));
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if (err < 0)
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return err;
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/* Enables the input to phase detector */
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err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
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0x7 << SI5341_INX_TO_PFD_SHIFT,
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BIT(index + SI5341_INX_TO_PFD_SHIFT));
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if (err < 0)
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return err;
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/* Power down XTAL oscillator and buffer */
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err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
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SI5341_XAXB_CFG_PDNB, 0);
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if (err < 0)
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return err;
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/*
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* Set the P divider to "1". There's no explanation in the
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* datasheet of these registers, but the clockbuilder software
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* programs a "1" when the input is being used.
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*/
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err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
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if (err < 0)
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return err;
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err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
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if (err < 0)
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return err;
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/* Set update PDIV bit */
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err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
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if (err < 0)
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return err;
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} else {
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/* Disable all input buffers */
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err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
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if (err < 0)
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return err;
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/* Disable input to phase detector */
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err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
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0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
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if (err < 0)
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return err;
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/* Power up XTAL oscillator and buffer */
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err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
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SI5341_XAXB_CFG_PDNB, SI5341_XAXB_CFG_PDNB);
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if (err < 0)
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return err;
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}
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return 0;
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}
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static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_si5341 *data = to_clk_si5341(hw);
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return si5341_clk_reparent(data, index);
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}
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static const struct clk_ops si5341_clk_ops = {
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.set_parent = si5341_clk_set_parent,
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.get_parent = si5341_clk_get_parent,
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.recalc_rate = si5341_clk_recalc_rate,
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};
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@ -985,7 +1111,8 @@ static const struct regmap_range si5341_regmap_volatile_range[] = {
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regmap_reg_range(0x000C, 0x0012), /* Status */
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regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
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regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
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/* Update bits for synth config */
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/* Update bits for P divider and synth config */
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regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
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regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
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regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
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regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
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@ -1122,6 +1249,7 @@ static int si5341_initialize_pll(struct clk_si5341 *data)
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struct device_node *np = data->i2c_client->dev.of_node;
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u32 m_num = 0;
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u32 m_den = 0;
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int sel;
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if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
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dev_err(&data->i2c_client->dev,
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@ -1135,7 +1263,11 @@ static int si5341_initialize_pll(struct clk_si5341 *data)
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if (!m_num || !m_den) {
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dev_err(&data->i2c_client->dev,
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"PLL configuration invalid, assume 14GHz\n");
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m_den = clk_get_rate(data->pxtal) / 10;
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sel = si5341_clk_get_selected_input(data);
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if (sel < 0)
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return sel;
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m_den = clk_get_rate(data->input_clk[sel]) / 10;
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m_num = 1400000000;
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}
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@ -1143,11 +1275,52 @@ static int si5341_initialize_pll(struct clk_si5341 *data)
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SI5341_PLL_M_NUM, m_num, m_den);
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}
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static int si5341_clk_select_active_input(struct clk_si5341 *data)
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{
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int res;
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int err;
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int i;
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res = si5341_clk_get_selected_input(data);
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if (res < 0)
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return res;
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/* If the current register setting is invalid, pick the first input */
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if (!data->input_clk[res]) {
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dev_dbg(&data->i2c_client->dev,
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"Input %d not connected, rerouting\n", res);
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res = -ENODEV;
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for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
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if (data->input_clk[i]) {
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res = i;
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break;
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}
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}
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if (res < 0) {
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dev_err(&data->i2c_client->dev,
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"No clock input available\n");
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return res;
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}
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}
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/* Make sure the selected clock is also enabled and routed */
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err = si5341_clk_reparent(data, res);
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if (err < 0)
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return err;
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err = clk_prepare_enable(data->input_clk[res]);
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if (err < 0)
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return err;
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return res;
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}
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static int si5341_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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struct clk_si5341 *data;
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struct clk_init_data init;
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struct clk *input;
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const char *root_clock_name;
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const char *synth_clock_names[SI5341_NUM_SYNTH];
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int err;
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@ -1161,12 +1334,16 @@ static int si5341_probe(struct i2c_client *client,
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data->i2c_client = client;
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data->pxtal = devm_clk_get(&client->dev, "xtal");
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if (IS_ERR(data->pxtal)) {
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if (PTR_ERR(data->pxtal) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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dev_err(&client->dev, "Missing xtal clock input\n");
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for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
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input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
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if (IS_ERR(input)) {
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if (PTR_ERR(input) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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data->input_clk_name[i] = si5341_input_clock_names[i];
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} else {
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data->input_clk[i] = input;
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data->input_clk_name[i] = __clk_get_name(input);
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}
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}
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err = si5341_dt_parse_dt(client, config);
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@ -1188,9 +1365,6 @@ static int si5341_probe(struct i2c_client *client,
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if (err < 0)
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return err;
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/* "Activate" the xtal (usually a fixed clock) */
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clk_prepare_enable(data->pxtal);
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if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
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initialization_required = true;
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} else {
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@ -1223,7 +1397,14 @@ static int si5341_probe(struct i2c_client *client,
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ARRAY_SIZE(si5341_reg_defaults));
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if (err < 0)
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return err;
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}
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/* Input must be up and running at this point */
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err = si5341_clk_select_active_input(data);
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if (err < 0)
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return err;
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if (initialization_required) {
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/* PLL configuration is required */
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err = si5341_initialize_pll(data);
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if (err < 0)
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@ -1231,9 +1412,8 @@ static int si5341_probe(struct i2c_client *client,
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}
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/* Register the PLL */
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data->pxtal_name = __clk_get_name(data->pxtal);
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init.parent_names = &data->pxtal_name;
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init.num_parents = 1; /* For now, only XTAL input supported */
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init.parent_names = data->input_clk_name;
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init.num_parents = SI5341_NUM_INPUTS;
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init.ops = &si5341_clk_ops;
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init.flags = 0;
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data->hw.init = &init;
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@ -4865,8 +4865,8 @@ static int parent_ready(struct device_node *np)
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*
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* Return: error code or zero on success
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*/
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int of_clk_detect_critical(struct device_node *np,
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int index, unsigned long *flags)
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int of_clk_detect_critical(struct device_node *np, int index,
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unsigned long *flags)
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{
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struct property *prop;
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const __be32 *cur;
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@ -65,54 +65,49 @@ static const struct clk_ops dbgclk_ops = {
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.get_parent = socfpga_gate_get_parent,
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};
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struct clk *s10_register_gate(const char *name, const char *parent_name,
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const char * const *parent_names,
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u8 num_parents, unsigned long flags,
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void __iomem *regbase, unsigned long gate_reg,
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unsigned long gate_idx, unsigned long div_reg,
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unsigned long div_offset, u8 div_width,
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unsigned long bypass_reg, u8 bypass_shift,
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u8 fixed_div)
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struct clk *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase)
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{
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struct clk *clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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const char * const *parent_names = clks->parent_names;
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const char *parent_name = clks->parent_name;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (!socfpga_clk)
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return NULL;
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socfpga_clk->hw.reg = regbase + gate_reg;
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socfpga_clk->hw.bit_idx = gate_idx;
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socfpga_clk->hw.reg = regbase + clks->gate_reg;
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socfpga_clk->hw.bit_idx = clks->gate_idx;
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gateclk_ops.enable = clk_gate_ops.enable;
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gateclk_ops.disable = clk_gate_ops.disable;
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socfpga_clk->fixed_div = fixed_div;
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socfpga_clk->fixed_div = clks->fixed_div;
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if (div_reg)
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socfpga_clk->div_reg = regbase + div_reg;
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if (clks->div_reg)
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socfpga_clk->div_reg = regbase + clks->div_reg;
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else
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socfpga_clk->div_reg = NULL;
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socfpga_clk->width = div_width;
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socfpga_clk->shift = div_offset;
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socfpga_clk->width = clks->div_width;
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socfpga_clk->shift = clks->div_offset;
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if (bypass_reg)
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socfpga_clk->bypass_reg = regbase + bypass_reg;
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if (clks->bypass_reg)
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socfpga_clk->bypass_reg = regbase + clks->bypass_reg;
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else
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socfpga_clk->bypass_reg = NULL;
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socfpga_clk->bypass_shift = bypass_shift;
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socfpga_clk->bypass_shift = clks->bypass_shift;
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if (streq(name, "cs_pdbg_clk"))
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if (streq(clks->name, "cs_pdbg_clk"))
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init.ops = &dbgclk_ops;
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else
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init.ops = &gateclk_ops;
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init.name = name;
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init.flags = flags;
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init.name = clks->name;
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init.flags = clks->flags;
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init.num_parents = num_parents;
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init.num_parents = clks->num_parents;
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init.parent_names = parent_names ? parent_names : &parent_name;
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socfpga_clk->hw.hw.init = &init;
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@ -121,6 +116,5 @@ struct clk *s10_register_gate(const char *name, const char *parent_name,
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kfree(socfpga_clk);
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return NULL;
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}
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return clk;
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}
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@ -73,26 +73,27 @@ static const struct clk_ops peri_cnt_clk_ops = {
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.get_parent = clk_periclk_get_parent,
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};
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struct clk *s10_register_periph(const char *name, const char *parent_name,
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const char * const *parent_names,
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u8 num_parents, unsigned long flags,
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void __iomem *reg, unsigned long offset)
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struct clk *s10_register_periph(const struct stratix10_perip_c_clock *clks,
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void __iomem *reg)
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{
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struct clk *clk;
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struct socfpga_periph_clk *periph_clk;
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struct clk_init_data init;
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const char *name = clks->name;
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const char *parent_name = clks->parent_name;
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const char * const *parent_names = clks->parent_names;
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periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
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if (WARN_ON(!periph_clk))
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return NULL;
|
||||
|
||||
periph_clk->hw.reg = reg + offset;
|
||||
periph_clk->hw.reg = reg + clks->offset;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &peri_c_clk_ops;
|
||||
init.flags = flags;
|
||||
init.flags = clks->flags;
|
||||
|
||||
init.num_parents = num_parents;
|
||||
init.num_parents = clks->num_parents;
|
||||
init.parent_names = parent_names ? parent_names : &parent_name;
|
||||
|
||||
periph_clk->hw.hw.init = &init;
|
||||
@ -105,38 +106,37 @@ struct clk *s10_register_periph(const char *name, const char *parent_name,
|
||||
return clk;
|
||||
}
|
||||
|
||||
struct clk *s10_register_cnt_periph(const char *name, const char *parent_name,
|
||||
const char * const *parent_names,
|
||||
u8 num_parents, unsigned long flags,
|
||||
void __iomem *regbase, unsigned long offset,
|
||||
u8 fixed_divider, unsigned long bypass_reg,
|
||||
unsigned long bypass_shift)
|
||||
struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
|
||||
void __iomem *regbase)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct socfpga_periph_clk *periph_clk;
|
||||
struct clk_init_data init;
|
||||
const char *name = clks->name;
|
||||
const char *parent_name = clks->parent_name;
|
||||
const char * const *parent_names = clks->parent_names;
|
||||
|
||||
periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!periph_clk))
|
||||
return NULL;
|
||||
|
||||
if (offset)
|
||||
periph_clk->hw.reg = regbase + offset;
|
||||
if (clks->offset)
|
||||
periph_clk->hw.reg = regbase + clks->offset;
|
||||
else
|
||||
periph_clk->hw.reg = NULL;
|
||||
|
||||
if (bypass_reg)
|
||||
periph_clk->bypass_reg = regbase + bypass_reg;
|
||||
if (clks->bypass_reg)
|
||||
periph_clk->bypass_reg = regbase + clks->bypass_reg;
|
||||
else
|
||||
periph_clk->bypass_reg = NULL;
|
||||
periph_clk->bypass_shift = bypass_shift;
|
||||
periph_clk->fixed_div = fixed_divider;
|
||||
periph_clk->bypass_shift = clks->bypass_shift;
|
||||
periph_clk->fixed_div = clks->fixed_divider;
|
||||
|
||||
init.name = name;
|
||||
init.ops = &peri_cnt_clk_ops;
|
||||
init.flags = flags;
|
||||
init.flags = clks->flags;
|
||||
|
||||
init.num_parents = num_parents;
|
||||
init.num_parents = clks->num_parents;
|
||||
init.parent_names = parent_names ? parent_names : &parent_name;
|
||||
|
||||
periph_clk->hw.hw.init = &init;
|
||||
|
||||
@ -39,7 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
|
||||
/* read VCO1 reg for numerator and denominator */
|
||||
reg = readl(socfpgaclk->hw.reg);
|
||||
refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
|
||||
vco_freq = (unsigned long long)parent_rate / refdiv;
|
||||
|
||||
vco_freq = parent_rate;
|
||||
do_div(vco_freq, refdiv);
|
||||
|
||||
/* Read mdiv and fdiv from the fdbck register */
|
||||
reg = readl(socfpgaclk->hw.reg + 0x4);
|
||||
@ -108,19 +110,20 @@ static struct clk_ops clk_boot_ops = {
|
||||
.prepare = clk_pll_prepare,
|
||||
};
|
||||
|
||||
struct clk *s10_register_pll(const char *name, const char * const *parent_names,
|
||||
u8 num_parents, unsigned long flags,
|
||||
void __iomem *reg, unsigned long offset)
|
||||
struct clk *s10_register_pll(const struct stratix10_pll_clock *clks,
|
||||
void __iomem *reg)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct socfpga_pll *pll_clk;
|
||||
struct clk_init_data init;
|
||||
const char *name = clks->name;
|
||||
const char * const *parent_names = clks->parent_names;
|
||||
|
||||
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
|
||||
if (WARN_ON(!pll_clk))
|
||||
return NULL;
|
||||
|
||||
pll_clk->hw.reg = reg + offset;
|
||||
pll_clk->hw.reg = reg + clks->offset;
|
||||
|
||||
if (streq(name, SOCFPGA_BOOT_CLK))
|
||||
init.ops = &clk_boot_ops;
|
||||
@ -128,9 +131,9 @@ struct clk *s10_register_pll(const char *name, const char * const *parent_names,
|
||||
init.ops = &clk_pll_ops;
|
||||
|
||||
init.name = name;
|
||||
init.flags = flags;
|
||||
init.flags = clks->flags;
|
||||
|
||||
init.num_parents = num_parents;
|
||||
init.num_parents = clks->num_parents;
|
||||
init.parent_names = parent_names;
|
||||
pll_clk->hw.hw.init = &init;
|
||||
|
||||
|
||||
@ -177,9 +177,7 @@ static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_periph(clks[i].name, clks[i].parent_name,
|
||||
clks[i].parent_names, clks[i].num_parents,
|
||||
clks[i].flags, base, clks[i].offset);
|
||||
clk = s10_register_periph(&clks[i], base);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
@ -198,14 +196,7 @@ static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *cl
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name,
|
||||
clks[i].parent_names,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags, base,
|
||||
clks[i].offset,
|
||||
clks[i].fixed_divider,
|
||||
clks[i].bypass_reg,
|
||||
clks[i].bypass_shift);
|
||||
clk = s10_register_cnt_periph(&clks[i], base);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
@ -225,16 +216,7 @@ static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_gate(clks[i].name, clks[i].parent_name,
|
||||
clks[i].parent_names,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags, base,
|
||||
clks[i].gate_reg,
|
||||
clks[i].gate_idx, clks[i].div_reg,
|
||||
clks[i].div_offset, clks[i].div_width,
|
||||
clks[i].bypass_reg,
|
||||
clks[i].bypass_shift,
|
||||
clks[i].fixed_div);
|
||||
clk = s10_register_gate(&clks[i], base);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
@ -254,10 +236,7 @@ static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nums; i++) {
|
||||
clk = s10_register_pll(clks[i].name, clks[i].parent_names,
|
||||
clks[i].num_parents,
|
||||
clks[i].flags, base,
|
||||
clks[i].offset);
|
||||
clk = s10_register_pll(&clks[i], base);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: failed to register clock %s\n",
|
||||
__func__, clks[i].name);
|
||||
|
||||
@ -60,21 +60,12 @@ struct stratix10_gate_clock {
|
||||
u8 fixed_div;
|
||||
};
|
||||
|
||||
struct clk *s10_register_pll(const char *, const char *const *, u8,
|
||||
unsigned long, void __iomem *, unsigned long);
|
||||
|
||||
struct clk *s10_register_periph(const char *, const char *,
|
||||
const char * const *, u8, unsigned long,
|
||||
void __iomem *, unsigned long);
|
||||
struct clk *s10_register_cnt_periph(const char *, const char *,
|
||||
const char * const *, u8,
|
||||
unsigned long, void __iomem *,
|
||||
unsigned long, u8, unsigned long,
|
||||
unsigned long);
|
||||
struct clk *s10_register_gate(const char *, const char *,
|
||||
const char * const *, u8,
|
||||
unsigned long, void __iomem *,
|
||||
unsigned long, unsigned long,
|
||||
unsigned long, unsigned long, u8,
|
||||
unsigned long, u8, u8);
|
||||
struct clk *s10_register_pll(const struct stratix10_pll_clock *,
|
||||
void __iomem *);
|
||||
struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
|
||||
void __iomem *);
|
||||
struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
|
||||
void __iomem *);
|
||||
struct clk *s10_register_gate(const struct stratix10_gate_clock *,
|
||||
void __iomem *);
|
||||
#endif /* __STRATIX10_CLK_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user