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drm/amd/display: Disable mem low power for CM HW block on DCN3.1

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[WHY]
Currently causes visible flicker in some scenarios on OLED eDPs

Reviewed-by: Haonan Wang <haonan.wang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michael Strauss 2021-09-08 14:39:09 -04:00 committed by Alex Deucher
parent 253a55918c
commit 5d694266bd
1 changed files with 1 additions and 1 deletions

2
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
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@ -1013,7 +1013,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.i2c = true,
.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
.dscl = true,
.cm = true,
.cm = false, // visible flicker on OLED eDPs
.mpc = true,
.optc = true,
.vpg = true,