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drm/amd/display: Fix issue with dynamic bpp change for DCN3x

Browse Source 
Why:
Screen sometimes would have artifacts or blink once at the time when bpp
is dynamically changed.

How:
1. Changed to update PPS infopacket in frame mode instead of immediate mode
   since other updates for bpp change are double-buffered.
2. Changed double-buffering enablement programming for DCN30 as advised by
ASIC team

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Bing Guo <Bing.Guo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Guo, Bing 2021-08-24 12:08:22 -04:00 committed by Alex Deucher
parent 808643ea56
commit 253a55918c
11 changed files with 204 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -3554,7 +3554,7 @@ static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pi
/* Set DPS PPS SDP (AKA "info frames") */
if (pipe_ctx->stream->timing.flags.DSC) {
dp_set_dsc_pps_sdp(pipe_ctx, true);
dp_set_dsc_pps_sdp(pipe_ctx, true, true);
}
/* Allocate Payload */
@ -3803,7 +3803,7 @@ void core_link_enable_stream(
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
dc_is_virtual_signal(pipe_ctx->stream->signal)) {
dp_set_dsc_on_rx(pipe_ctx, true);
dp_set_dsc_pps_sdp(pipe_ctx, true);
dp_set_dsc_pps_sdp(pipe_ctx, true, true);
}
}

29
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
View File

@ -607,7 +607,8 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.hpo_dp_stream_enc,
false,
NULL);
NULL,
true);
else
#endif
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
@ -615,7 +616,7 @@ void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
pipe_ctx->stream_res.stream_enc,
OPTC_DSC_DISABLED, 0, 0);
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, false, NULL);
pipe_ctx->stream_res.stream_enc, false, NULL, true);
}
}
@ -650,7 +651,16 @@ out:
return result;
}
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
/*
* For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled;
* hence PPS info packet update need to use frame update instead of immediate update.
* Added parameter immediate_update for this purpose.
* The decision to use frame update is hard-coded in function dp_update_dsc_config(),
* which is the only place where a "false" would be passed in for param immediate_update.
*
* immediate_update is only applicable when DSC is enabled.
*/
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update)
{
struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
struct dc_stream_state *stream = pipe_ctx->stream;
@ -682,13 +692,15 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.hpo_dp_stream_enc,
true,
&dsc_packed_pps[0]);
&dsc_packed_pps[0],
immediate_update);
else
#endif
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc,
true,
&dsc_packed_pps[0]);
&dsc_packed_pps[0],
immediate_update);
}
} else {
/* disable DSC PPS in stream encoder */
@ -698,11 +710,12 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.hpo_dp_stream_enc,
false,
NULL);
NULL,
true);
else
#endif
pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
pipe_ctx->stream_res.stream_enc, false, NULL);
pipe_ctx->stream_res.stream_enc, false, NULL, true);
}
}
@ -720,7 +733,7 @@ bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
return false;
dp_set_dsc_on_stream(pipe_ctx, true);
dp_set_dsc_pps_sdp(pipe_ctx, true);
dp_set_dsc_pps_sdp(pipe_ctx, true, false);
return true;
}

3
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
View File

@ -292,7 +292,8 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
bool enable,
uint8_t *dsc_packed_pps)
uint8_t *dsc_packed_pps,
bool immediate_update)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);

18
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c
View File

@ -77,7 +77,8 @@ static void enc3_update_hdmi_info_packet(
enc1->base.vpg->funcs->update_generic_info_packet(
enc1->base.vpg,
packet_index,
info_packet);
info_packet,
true);
/* enable transmission of packet(s) -
* packet transmission begins on the next frame */
@ -335,7 +336,8 @@ static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
bool enable,
uint8_t *dsc_packed_pps)
uint8_t *dsc_packed_pps,
bool immediate_update)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
@ -365,7 +367,8 @@ static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
enc1->base.vpg->funcs->update_generic_info_packet(
enc1->base.vpg,
11 + i,
&pps_sdp);
&pps_sdp,
immediate_update);
}
/* SW should make sure VBID[6] update line number is bigger
@ -429,19 +432,22 @@ static void enc3_stream_encoder_update_dp_info_packets(
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
0, /* packetIndex */
&info_frame->vsc);
&info_frame->vsc,
true);
}
if (info_frame->spd.valid) {
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
2, /* packetIndex */
&info_frame->spd);
&info_frame->spd,
true);
}
if (info_frame->hdrsmd.valid) {
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
3, /* packetIndex */
&info_frame->hdrsmd);
&info_frame->hdrsmd,
true);
}
/* packetIndex 4 is used for send immediate sdp message, and please
* use other packetIndex (such as 5,6) for other info packet

17
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
View File

@ -73,16 +73,23 @@ void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
OTG_H_BLANK_END, &h_blank_end);
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start,
MASTER_UPDATE_LOCK_DB_END_Y, v_blank_end);
MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start - 1,
MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start);
REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
DIG_UPDATE_POSITION_X, 20,
DIG_UPDATE_POSITION_Y, v_blank_start);
DIG_UPDATE_POSITION_X, h_blank_start - 180 - 1,
DIG_UPDATE_POSITION_Y, v_blank_start - 1);
// there is a DIG_UPDATE_VCOUNT_MODE and it is 0.
REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
MASTER_UPDATE_LOCK_DB_END_X, h_blank_end,
MASTER_UPDATE_LOCK_DB_END_X, h_blank_start - 180,
MASTER_UPDATE_LOCK_DB_EN, 1);
REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
}
void optc3_lock_doublebuffer_disable(struct timing_generator *optc)

198
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.c
View File

@ -46,7 +46,8 @@
void vpg3_update_generic_info_packet(
struct vpg *vpg,
uint32_t packet_index,
const struct dc_info_packet *info_packet)
const struct dc_info_packet *info_packet,
bool immediate_update)
{
struct dcn30_vpg *vpg3 = DCN30_VPG_FROM_VPG(vpg);
uint32_t i;
@ -106,69 +107,138 @@ void vpg3_update_generic_info_packet(
/* atomically update double-buffered GENERIC0 registers in immediate mode
* (update at next block_update when block_update_lock == 0).
*/
switch (packet_index) {
case 0:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC0_IMMEDIATE_UPDATE, 1);
break;
case 1:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC1_IMMEDIATE_UPDATE, 1);
break;
case 2:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC2_IMMEDIATE_UPDATE, 1);
break;
case 3:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC3_IMMEDIATE_UPDATE, 1);
break;
case 4:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC4_IMMEDIATE_UPDATE, 1);
break;
case 5:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC5_IMMEDIATE_UPDATE, 1);
break;
case 6:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC6_IMMEDIATE_UPDATE, 1);
break;
case 7:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC7_IMMEDIATE_UPDATE, 1);
break;
case 8:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC8_IMMEDIATE_UPDATE, 1);
break;
case 9:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC9_IMMEDIATE_UPDATE, 1);
break;
case 10:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC10_IMMEDIATE_UPDATE, 1);
break;
case 11:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC11_IMMEDIATE_UPDATE, 1);
break;
case 12:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC12_IMMEDIATE_UPDATE, 1);
break;
case 13:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC13_IMMEDIATE_UPDATE, 1);
break;
case 14:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC14_IMMEDIATE_UPDATE, 1);
break;
default:
break;
if (immediate_update) {
switch (packet_index) {
case 0:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC0_IMMEDIATE_UPDATE, 1);
break;
case 1:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC1_IMMEDIATE_UPDATE, 1);
break;
case 2:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC2_IMMEDIATE_UPDATE, 1);
break;
case 3:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC3_IMMEDIATE_UPDATE, 1);
break;
case 4:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC4_IMMEDIATE_UPDATE, 1);
break;
case 5:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC5_IMMEDIATE_UPDATE, 1);
break;
case 6:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC6_IMMEDIATE_UPDATE, 1);
break;
case 7:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC7_IMMEDIATE_UPDATE, 1);
break;
case 8:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC8_IMMEDIATE_UPDATE, 1);
break;
case 9:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC9_IMMEDIATE_UPDATE, 1);
break;
case 10:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC10_IMMEDIATE_UPDATE, 1);
break;
case 11:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC11_IMMEDIATE_UPDATE, 1);
break;
case 12:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC12_IMMEDIATE_UPDATE, 1);
break;
case 13:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC13_IMMEDIATE_UPDATE, 1);
break;
case 14:
REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL,
VPG_GENERIC14_IMMEDIATE_UPDATE, 1);
break;
default:
break;
}
} else {
switch (packet_index) {
case 0:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC0_FRAME_UPDATE, 1);
break;
case 1:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC1_FRAME_UPDATE, 1);
break;
case 2:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC2_FRAME_UPDATE, 1);
break;
case 3:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC3_FRAME_UPDATE, 1);
break;
case 4:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC4_FRAME_UPDATE, 1);
break;
case 5:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC5_FRAME_UPDATE, 1);
break;
case 6:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC6_FRAME_UPDATE, 1);
break;
case 7:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC7_FRAME_UPDATE, 1);
break;
case 8:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC8_FRAME_UPDATE, 1);
break;
case 9:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC9_FRAME_UPDATE, 1);
break;
case 10:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC10_FRAME_UPDATE, 1);
break;
case 11:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC11_FRAME_UPDATE, 1);
break;
case 12:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC12_FRAME_UPDATE, 1);
break;
case 13:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC13_FRAME_UPDATE, 1);
break;
case 14:
REG_UPDATE(VPG_GSP_FRAME_UPDATE_CTRL,
VPG_GENERIC14_FRAME_UPDATE, 1);
break;
default:
break;
}
}
}

6
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_vpg.h
View File

@ -138,7 +138,8 @@ struct vpg_funcs {
void (*update_generic_info_packet)(
struct vpg *vpg,
uint32_t packet_index,
const struct dc_info_packet *info_packet);
const struct dc_info_packet *info_packet,
bool immediate_update);
void (*vpg_poweron)(
struct vpg *vpg);
@ -163,7 +164,8 @@ struct dcn30_vpg {
void vpg3_update_generic_info_packet(
struct vpg *vpg,
uint32_t packet_index,
const struct dc_info_packet *info_packet);
const struct dc_info_packet *info_packet,
bool immediate_update);
void vpg3_construct(struct dcn30_vpg *vpg3,
struct dc_context *ctx,

15
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c
View File

@ -442,21 +442,24 @@ static void dcn31_hpo_dp_stream_enc_update_dp_info_packets(
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
0, /* packetIndex */
&info_frame->vsc);
&info_frame->vsc,
true);
sdp_stream_enable = true;
}
if (info_frame->spd.valid) {
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
2, /* packetIndex */
&info_frame->spd);
&info_frame->spd,
true);
sdp_stream_enable = true;
}
if (info_frame->hdrsmd.valid) {
enc->vpg->funcs->update_generic_info_packet(
enc->vpg,
3, /* packetIndex */
&info_frame->hdrsmd);
&info_frame->hdrsmd,
true);
sdp_stream_enable = true;
}
/* enable/disable transmission of packet(s).
@ -520,7 +523,8 @@ static uint32_t hpo_dp_is_gsp_enabled(
static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet(
struct hpo_dp_stream_encoder *enc,
bool enable,
uint8_t *dsc_packed_pps)
uint8_t *dsc_packed_pps,
bool immediate_update)
{
struct dcn31_hpo_dp_stream_encoder *enc3 = DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(enc);
@ -544,7 +548,8 @@ static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet(
enc3->base.vpg->funcs->update_generic_info_packet(
enc3->base.vpg,
11 + i,
&pps_sdp);
&pps_sdp,
immediate_update);
}
/* SW should make sure VBID[6] update line number is bigger

2
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
View File

@ -166,7 +166,7 @@ uint8_t dc_dp_initialize_scrambling_data_symbols(
enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready);
void dp_set_fec_enable(struct dc_link *link, bool enable);
bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update);
void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);

6
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
View File

@ -229,7 +229,8 @@ struct stream_encoder_funcs {
void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc,
bool enable,
uint8_t *dsc_packed_pps);
uint8_t *dsc_packed_pps,
bool immediate_update);
void (*set_dynamic_metadata)(struct stream_encoder *enc,
bool enable,
@ -298,7 +299,8 @@ struct hpo_dp_stream_encoder_funcs {
void (*dp_set_dsc_pps_info_packet)(
struct hpo_dp_stream_encoder *enc,
bool enable,
uint8_t *dsc_packed_pps);
uint8_t *dsc_packed_pps,
bool immediate_update);
void (*map_stream_to_link)(
struct hpo_dp_stream_encoder *enc,

3
drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
View File

@ -104,7 +104,8 @@ static void virtual_setup_stereo_sync(
static void virtual_stream_encoder_set_dsc_pps_info_packet(
struct stream_encoder *enc,
bool enable,
uint8_t *dsc_packed_pps)
uint8_t *dsc_packed_pps,
bool immediate_update)
{}
static const struct stream_encoder_funcs virtual_str_enc_funcs = {