From 5d694266bd14d5a0ac359ef6aef88dbc93efda70 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Wed, 8 Sep 2021 14:39:09 -0400 Subject: [PATCH] drm/amd/display: Disable mem low power for CM HW block on DCN3.1 [WHY] Currently causes visible flicker in some scenarios on OLED eDPs Reviewed-by: Haonan Wang Acked-by: Rodrigo Siqueira Signed-off-by: Michael Strauss Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c index a823a64d02a5..0b60ac676423 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c @@ -1013,7 +1013,7 @@ static const struct dc_debug_options debug_defaults_drv = { .i2c = true, .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled .dscl = true, - .cm = true, + .cm = false, // visible flicker on OLED eDPs .mpc = true, .optc = true, .vpg = true,