2012-04-17 01:20:34 +00:00
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eugeni Dodonov <eugeni.dodonov@intel.com>
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*
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*/
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2012-04-18 18:29:23 +00:00
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#include <linux/cpufreq.h>
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2016-05-16 22:52:00 +00:00
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#include <drm/drm_plane_helper.h>
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2012-04-17 01:20:34 +00:00
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#include "i915_drv.h"
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#include "intel_drv.h"
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2012-04-26 21:28:12 +00:00
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#include "../../../platform/x86/intel_ips.h"
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#include <linux/module.h>
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2016-10-26 13:41:29 +00:00
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#include <drm/drm_atomic_helper.h>
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2012-04-17 01:20:34 +00:00
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2013-10-18 19:32:07 +00:00
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/**
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2016-01-18 07:19:48 +00:00
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* DOC: RC6
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*
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2013-10-18 19:32:07 +00:00
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* RC6 is a special power stage which allows the GPU to enter an very
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* low-voltage mode when idle, using down to 0V while at this stage. This
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* stage is entered automatically when the GPU is idle when RC6 support is
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* enabled, and as soon as new workload arises GPU wakes up automatically as well.
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*
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* There are different RC6 modes available in Intel GPU, which differentiate
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* among each other with the latency required to enter and leave RC6 and
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* voltage consumed by the GPU in different states.
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*
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* The combination of the following flags define which states GPU is allowed
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* to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
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* RC6pp is deepest RC6. Their support by hardware varies according to the
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* GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
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* which brings the most power savings; deeper states save more power, but
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* require higher latency to switch to and wake up.
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*/
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#define INTEL_RC6_ENABLE (1<<0)
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#define INTEL_RC6p_ENABLE (1<<1)
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#define INTEL_RC6pp_ENABLE (1<<2)
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2016-10-31 20:37:22 +00:00
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static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
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2015-03-27 12:00:04 +00:00
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{
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2016-06-07 14:19:04 +00:00
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/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
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2016-05-19 07:14:20 +00:00
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I915_WRITE(CHICKEN_PAR1_1,
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I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
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2016-06-07 14:19:04 +00:00
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I915_WRITE(GEN8_CONFIG0,
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I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
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2016-06-07 14:19:13 +00:00
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2017-01-26 09:16:58 +00:00
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/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
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2016-06-07 14:19:13 +00:00
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I915_WRITE(GEN8_CHICKEN_DCPR_1,
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I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
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2016-06-07 14:19:16 +00:00
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/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
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2017-01-26 09:16:58 +00:00
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/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
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2016-06-07 14:19:17 +00:00
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I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
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DISP_FBC_WM_DIS |
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DISP_FBC_MEMORY_WAKE);
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2016-06-07 14:19:19 +00:00
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/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
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I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
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ILK_DPFC_DISABLE_DUMMY0);
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2016-06-07 14:19:04 +00:00
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}
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2016-10-31 20:37:22 +00:00
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static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
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2016-06-07 14:19:04 +00:00
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{
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2016-10-31 20:37:22 +00:00
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gen9_init_clock_gating(dev_priv);
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2016-06-07 14:19:04 +00:00
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2015-06-29 13:07:32 +00:00
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/* WaDisableSDEUnitClockGating:bxt */
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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2015-03-11 09:10:27 +00:00
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/*
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* FIXME:
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2015-03-11 08:49:32 +00:00
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* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
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2015-03-11 09:10:27 +00:00
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*/
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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2015-03-11 08:49:32 +00:00
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GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
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2015-12-01 08:23:52 +00:00
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/*
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* Wa: Backlight PWM may stop in the asserted state, causing backlight
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* to stay fully on.
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*/
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if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
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I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
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PWM1_GATING_DIS | PWM2_GATING_DIS);
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2015-03-27 12:00:04 +00:00
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}
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2017-01-26 09:16:58 +00:00
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static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
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{
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gen9_init_clock_gating(dev_priv);
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/*
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* WaDisablePWMClockGating:glk
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* Backlight PWM may stop in the asserted state, causing backlight
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* to stay fully on.
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*/
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I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
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PWM1_GATING_DIS | PWM2_GATING_DIS);
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}
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2016-10-31 20:37:16 +00:00
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static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
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2012-04-26 21:28:17 +00:00
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{
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u32 tmp;
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tmp = I915_READ(CLKCFG);
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switch (tmp & CLKCFG_FSB_MASK) {
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case CLKCFG_FSB_533:
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dev_priv->fsb_freq = 533; /* 133*4 */
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break;
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case CLKCFG_FSB_800:
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dev_priv->fsb_freq = 800; /* 200*4 */
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break;
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case CLKCFG_FSB_667:
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dev_priv->fsb_freq = 667; /* 167*4 */
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break;
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case CLKCFG_FSB_400:
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dev_priv->fsb_freq = 400; /* 100*4 */
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break;
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}
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switch (tmp & CLKCFG_MEM_MASK) {
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case CLKCFG_MEM_533:
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dev_priv->mem_freq = 533;
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break;
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case CLKCFG_MEM_667:
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dev_priv->mem_freq = 667;
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break;
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case CLKCFG_MEM_800:
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dev_priv->mem_freq = 800;
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break;
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}
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/* detect pineview DDR3 setting */
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tmp = I915_READ(CSHRDDR3CTL);
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dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
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}
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2016-10-31 20:37:16 +00:00
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static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
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2012-04-26 21:28:17 +00:00
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{
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u16 ddrpll, csipll;
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ddrpll = I915_READ16(DDRMPLL1);
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csipll = I915_READ16(CSIPLL0);
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switch (ddrpll & 0xff) {
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case 0xc:
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dev_priv->mem_freq = 800;
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break;
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case 0x10:
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dev_priv->mem_freq = 1066;
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break;
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case 0x14:
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dev_priv->mem_freq = 1333;
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break;
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case 0x18:
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dev_priv->mem_freq = 1600;
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break;
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default:
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DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
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ddrpll & 0xff);
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dev_priv->mem_freq = 0;
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break;
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}
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2012-08-08 21:35:39 +00:00
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dev_priv->ips.r_t = dev_priv->mem_freq;
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2012-04-26 21:28:17 +00:00
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switch (csipll & 0x3ff) {
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case 0x00c:
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dev_priv->fsb_freq = 3200;
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break;
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case 0x00e:
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dev_priv->fsb_freq = 3733;
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break;
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case 0x010:
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dev_priv->fsb_freq = 4266;
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break;
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case 0x012:
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dev_priv->fsb_freq = 4800;
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break;
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case 0x014:
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dev_priv->fsb_freq = 5333;
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break;
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case 0x016:
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dev_priv->fsb_freq = 5866;
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break;
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case 0x018:
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dev_priv->fsb_freq = 6400;
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break;
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default:
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DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
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csipll & 0x3ff);
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dev_priv->fsb_freq = 0;
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break;
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}
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if (dev_priv->fsb_freq == 3200) {
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2012-08-08 21:35:39 +00:00
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dev_priv->ips.c_m = 0;
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2012-04-26 21:28:17 +00:00
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} else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
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2012-08-08 21:35:39 +00:00
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dev_priv->ips.c_m = 1;
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2012-04-26 21:28:17 +00:00
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} else {
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2012-08-08 21:35:39 +00:00
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dev_priv->ips.c_m = 2;
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2012-04-26 21:28:17 +00:00
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}
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}
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2012-04-17 01:20:35 +00:00
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static const struct cxsr_latency cxsr_latency_table[] = {
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{1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
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{1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
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{1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
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{1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
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{1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
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{1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
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{1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
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{1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
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{1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
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{1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
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{1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
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{1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
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{1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
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{1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
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{1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
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{0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
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{0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
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{0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
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{0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
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{0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
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{0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
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{0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
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{0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
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{0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
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{0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
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{0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
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{0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
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{0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
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{0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
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{0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
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};
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|
|
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|
2016-10-13 10:09:23 +00:00
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|
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static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
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bool is_ddr3,
|
2012-04-17 01:20:35 +00:00
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int fsb,
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int mem)
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{
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const struct cxsr_latency *latency;
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int i;
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if (fsb == 0 || mem == 0)
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return NULL;
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for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
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latency = &cxsr_latency_table[i];
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|
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if (is_desktop == latency->is_desktop &&
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is_ddr3 == latency->is_ddr3 &&
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fsb == latency->fsb_freq && mem == latency->mem_freq)
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return latency;
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}
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|
|
DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
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return NULL;
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}
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|
|
|
|
2015-03-05 19:19:52 +00:00
|
|
|
static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
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|
|
|
{
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|
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u32 val;
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|
|
mutex_lock(&dev_priv->rps.hw_lock);
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val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
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|
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if (enable)
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|
|
val &= ~FORCE_DDR_HIGH_FREQ;
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else
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|
|
val |= FORCE_DDR_HIGH_FREQ;
|
|
|
|
val &= ~FORCE_DDR_LOW_FREQ;
|
|
|
|
val |= FORCE_DDR_FREQ_REQ_ACK;
|
|
|
|
vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
|
|
|
|
|
|
|
|
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
|
|
|
|
FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
|
|
|
|
DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
}
|
|
|
|
|
2015-03-05 19:19:51 +00:00
|
|
|
static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
|
|
|
|
if (enable)
|
|
|
|
val |= DSP_MAXFIFO_PM5_ENABLE;
|
|
|
|
else
|
|
|
|
val &= ~DSP_MAXFIFO_PM5_ENABLE;
|
|
|
|
vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
}
|
|
|
|
|
2015-03-10 15:02:21 +00:00
|
|
|
#define FW_WM(value, plane) \
|
|
|
|
(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
|
|
|
|
|
2016-11-28 17:37:12 +00:00
|
|
|
static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-11-28 17:37:12 +00:00
|
|
|
bool was_enabled;
|
2014-07-01 09:36:17 +00:00
|
|
|
u32 val;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-10-14 09:13:44 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
2016-11-28 17:37:12 +00:00
|
|
|
was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
|
2014-07-01 09:36:17 +00:00
|
|
|
I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
|
2015-06-24 19:00:01 +00:00
|
|
|
POSTING_READ(FW_BLC_SELF_VLV);
|
2016-12-07 10:13:04 +00:00
|
|
|
} else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
|
2016-11-28 17:37:12 +00:00
|
|
|
was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
|
2014-07-01 09:36:17 +00:00
|
|
|
I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
|
2015-06-24 19:00:01 +00:00
|
|
|
POSTING_READ(FW_BLC_SELF);
|
2016-10-31 20:37:15 +00:00
|
|
|
} else if (IS_PINEVIEW(dev_priv)) {
|
2016-11-28 17:37:12 +00:00
|
|
|
val = I915_READ(DSPFW3);
|
|
|
|
was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
|
|
|
|
if (enable)
|
|
|
|
val |= PINEVIEW_SELF_REFRESH_EN;
|
|
|
|
else
|
|
|
|
val &= ~PINEVIEW_SELF_REFRESH_EN;
|
2014-07-01 09:36:17 +00:00
|
|
|
I915_WRITE(DSPFW3, val);
|
2015-06-24 19:00:01 +00:00
|
|
|
POSTING_READ(DSPFW3);
|
2016-10-13 10:02:58 +00:00
|
|
|
} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
|
2016-11-28 17:37:12 +00:00
|
|
|
was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
|
2014-07-01 09:36:17 +00:00
|
|
|
val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
|
|
|
|
_MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
|
|
|
|
I915_WRITE(FW_BLC_SELF, val);
|
2015-06-24 19:00:01 +00:00
|
|
|
POSTING_READ(FW_BLC_SELF);
|
2016-10-13 10:02:58 +00:00
|
|
|
} else if (IS_I915GM(dev_priv)) {
|
2016-07-29 14:57:02 +00:00
|
|
|
/*
|
|
|
|
* FIXME can't find a bit like this for 915G, and
|
|
|
|
* and yet it does have the related watermark in
|
|
|
|
* FW_BLC_SELF. What's going on?
|
|
|
|
*/
|
2016-11-28 17:37:12 +00:00
|
|
|
was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
|
2014-07-01 09:36:17 +00:00
|
|
|
val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
|
|
|
|
_MASKED_BIT_DISABLE(INSTPM_SELF_EN);
|
|
|
|
I915_WRITE(INSTPM, val);
|
2015-06-24 19:00:01 +00:00
|
|
|
POSTING_READ(INSTPM);
|
2014-07-01 09:36:17 +00:00
|
|
|
} else {
|
2016-11-28 17:37:12 +00:00
|
|
|
return false;
|
2014-07-01 09:36:17 +00:00
|
|
|
}
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-11-28 17:37:12 +00:00
|
|
|
DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
|
|
|
|
enableddisabled(enable),
|
|
|
|
enableddisabled(was_enabled));
|
|
|
|
|
|
|
|
return was_enabled;
|
2012-04-17 01:20:35 +00:00
|
|
|
}
|
|
|
|
|
2016-11-28 17:37:12 +00:00
|
|
|
bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
|
2016-11-28 17:37:11 +00:00
|
|
|
{
|
2016-11-28 17:37:12 +00:00
|
|
|
bool ret;
|
|
|
|
|
2016-11-28 17:37:11 +00:00
|
|
|
mutex_lock(&dev_priv->wm.wm_mutex);
|
2016-11-28 17:37:12 +00:00
|
|
|
ret = _intel_set_memory_cxsr(dev_priv, enable);
|
2016-11-28 17:37:11 +00:00
|
|
|
dev_priv->wm.vlv.cxsr = enable;
|
|
|
|
mutex_unlock(&dev_priv->wm.wm_mutex);
|
2016-11-28 17:37:12 +00:00
|
|
|
|
|
|
|
return ret;
|
2016-11-28 17:37:11 +00:00
|
|
|
}
|
2015-03-05 19:19:52 +00:00
|
|
|
|
2012-04-17 01:20:35 +00:00
|
|
|
/*
|
|
|
|
* Latency for FIFO fetches is dependent on several factors:
|
|
|
|
* - memory configuration (speed, channels)
|
|
|
|
* - chipset
|
|
|
|
* - current MCH state
|
|
|
|
* It can be fairly high in some situations, so here we assume a fairly
|
|
|
|
* pessimal value. It's a tradeoff between extra memory fetches (if we
|
|
|
|
* set this value too high, the FIFO will fetch frequently to stay full)
|
|
|
|
* and power consumption (set it too low to save power and we might see
|
|
|
|
* FIFO underruns and display "flicker").
|
|
|
|
*
|
|
|
|
* A value of 5us seems to be a good balance; safe for very low end
|
|
|
|
* platforms but not overly aggressive on lower latency configs.
|
|
|
|
*/
|
2014-09-03 10:56:07 +00:00
|
|
|
static const int pessimal_latency_ns = 5000;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2015-03-05 19:19:47 +00:00
|
|
|
#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
|
|
|
|
((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
|
|
|
|
|
2016-11-22 16:02:01 +00:00
|
|
|
static int vlv_get_fifo_size(struct intel_plane *plane)
|
2015-03-05 19:19:47 +00:00
|
|
|
{
|
2016-11-22 16:02:01 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
2015-03-05 19:19:47 +00:00
|
|
|
int sprite0_start, sprite1_start, size;
|
|
|
|
|
2016-11-22 16:02:01 +00:00
|
|
|
if (plane->id == PLANE_CURSOR)
|
|
|
|
return 63;
|
|
|
|
|
|
|
|
switch (plane->pipe) {
|
2015-03-05 19:19:47 +00:00
|
|
|
uint32_t dsparb, dsparb2, dsparb3;
|
|
|
|
case PIPE_A:
|
|
|
|
dsparb = I915_READ(DSPARB);
|
|
|
|
dsparb2 = I915_READ(DSPARB2);
|
|
|
|
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
|
|
|
|
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
|
|
|
|
break;
|
|
|
|
case PIPE_B:
|
|
|
|
dsparb = I915_READ(DSPARB);
|
|
|
|
dsparb2 = I915_READ(DSPARB2);
|
|
|
|
sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
|
|
|
|
sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
|
|
|
|
break;
|
|
|
|
case PIPE_C:
|
|
|
|
dsparb2 = I915_READ(DSPARB2);
|
|
|
|
dsparb3 = I915_READ(DSPARB3);
|
|
|
|
sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
|
|
|
|
sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-22 16:02:01 +00:00
|
|
|
switch (plane->id) {
|
|
|
|
case PLANE_PRIMARY:
|
2015-03-05 19:19:47 +00:00
|
|
|
size = sprite0_start;
|
|
|
|
break;
|
2016-11-22 16:02:01 +00:00
|
|
|
case PLANE_SPRITE0:
|
2015-03-05 19:19:47 +00:00
|
|
|
size = sprite1_start - sprite0_start;
|
|
|
|
break;
|
2016-11-22 16:02:01 +00:00
|
|
|
case PLANE_SPRITE1:
|
2015-03-05 19:19:47 +00:00
|
|
|
size = 512 - 1 - sprite1_start;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-22 16:02:01 +00:00
|
|
|
DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
|
2015-03-05 19:19:47 +00:00
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:17 +00:00
|
|
|
static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
|
|
|
uint32_t dsparb = I915_READ(DSPARB);
|
|
|
|
int size;
|
|
|
|
|
|
|
|
size = dsparb & 0x7f;
|
|
|
|
if (plane)
|
|
|
|
size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
|
|
|
|
plane ? "B" : "A", size);
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:17 +00:00
|
|
|
static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
|
|
|
uint32_t dsparb = I915_READ(DSPARB);
|
|
|
|
int size;
|
|
|
|
|
|
|
|
size = dsparb & 0x1ff;
|
|
|
|
if (plane)
|
|
|
|
size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
|
|
|
|
size >>= 1; /* Convert to cachelines */
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
|
|
|
|
plane ? "B" : "A", size);
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:17 +00:00
|
|
|
static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
|
|
|
uint32_t dsparb = I915_READ(DSPARB);
|
|
|
|
int size;
|
|
|
|
|
|
|
|
size = dsparb & 0x7f;
|
|
|
|
size >>= 2; /* Convert to cachelines */
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
|
|
|
|
plane ? "B" : "A",
|
|
|
|
size);
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Pineview has different values for various configs */
|
|
|
|
static const struct intel_watermark_params pineview_display_wm = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = PINEVIEW_DISPLAY_FIFO,
|
|
|
|
.max_wm = PINEVIEW_MAX_WM,
|
|
|
|
.default_wm = PINEVIEW_DFT_WM,
|
|
|
|
.guard_size = PINEVIEW_GUARD_WM,
|
|
|
|
.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params pineview_display_hplloff_wm = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = PINEVIEW_DISPLAY_FIFO,
|
|
|
|
.max_wm = PINEVIEW_MAX_WM,
|
|
|
|
.default_wm = PINEVIEW_DFT_HPLLOFF_WM,
|
|
|
|
.guard_size = PINEVIEW_GUARD_WM,
|
|
|
|
.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params pineview_cursor_wm = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = PINEVIEW_CURSOR_FIFO,
|
|
|
|
.max_wm = PINEVIEW_CURSOR_MAX_WM,
|
|
|
|
.default_wm = PINEVIEW_CURSOR_DFT_WM,
|
|
|
|
.guard_size = PINEVIEW_CURSOR_GUARD_WM,
|
|
|
|
.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = PINEVIEW_CURSOR_FIFO,
|
|
|
|
.max_wm = PINEVIEW_CURSOR_MAX_WM,
|
|
|
|
.default_wm = PINEVIEW_CURSOR_DFT_WM,
|
|
|
|
.guard_size = PINEVIEW_CURSOR_GUARD_WM,
|
|
|
|
.cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params g4x_wm_info = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = G4X_FIFO_SIZE,
|
|
|
|
.max_wm = G4X_MAX_WM,
|
|
|
|
.default_wm = G4X_MAX_WM,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = G4X_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params g4x_cursor_wm_info = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = I965_CURSOR_FIFO,
|
|
|
|
.max_wm = I965_CURSOR_MAX_WM,
|
|
|
|
.default_wm = I965_CURSOR_DFT_WM,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = G4X_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params i965_cursor_wm_info = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = I965_CURSOR_FIFO,
|
|
|
|
.max_wm = I965_CURSOR_MAX_WM,
|
|
|
|
.default_wm = I965_CURSOR_DFT_WM,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = I915_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params i945_wm_info = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = I945_FIFO_SIZE,
|
|
|
|
.max_wm = I915_MAX_WM,
|
|
|
|
.default_wm = 1,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = I915_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
static const struct intel_watermark_params i915_wm_info = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = I915_FIFO_SIZE,
|
|
|
|
.max_wm = I915_MAX_WM,
|
|
|
|
.default_wm = 1,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = I915_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
2014-08-14 22:21:53 +00:00
|
|
|
static const struct intel_watermark_params i830_a_wm_info = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = I855GM_FIFO_SIZE,
|
|
|
|
.max_wm = I915_MAX_WM,
|
|
|
|
.default_wm = 1,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = I830_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
2014-08-14 22:21:53 +00:00
|
|
|
static const struct intel_watermark_params i830_bc_wm_info = {
|
|
|
|
.fifo_size = I855GM_FIFO_SIZE,
|
|
|
|
.max_wm = I915_MAX_WM/2,
|
|
|
|
.default_wm = 1,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = I830_FIFO_LINE_SIZE,
|
|
|
|
};
|
2013-12-14 22:38:30 +00:00
|
|
|
static const struct intel_watermark_params i845_wm_info = {
|
2014-06-05 16:15:50 +00:00
|
|
|
.fifo_size = I830_FIFO_SIZE,
|
|
|
|
.max_wm = I915_MAX_WM,
|
|
|
|
.default_wm = 1,
|
|
|
|
.guard_size = 2,
|
|
|
|
.cacheline_size = I830_FIFO_LINE_SIZE,
|
2012-04-17 01:20:35 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_calculate_wm - calculate watermark level
|
|
|
|
* @clock_in_khz: pixel clock
|
|
|
|
* @wm: chip FIFO params
|
2016-01-20 19:05:26 +00:00
|
|
|
* @cpp: bytes per pixel
|
2012-04-17 01:20:35 +00:00
|
|
|
* @latency_ns: memory latency for the platform
|
|
|
|
*
|
|
|
|
* Calculate the watermark level (the level at which the display plane will
|
|
|
|
* start fetching from memory again). Each chip has a different display
|
|
|
|
* FIFO size and allocation, so the caller needs to figure that out and pass
|
|
|
|
* in the correct intel_watermark_params structure.
|
|
|
|
*
|
|
|
|
* As the pixel clock runs, the FIFO will be drained at a rate that depends
|
|
|
|
* on the pixel size. When it reaches the watermark level, it'll start
|
|
|
|
* fetching FIFO line sized based chunks from memory until the FIFO fills
|
|
|
|
* past the watermark point. If the FIFO drains completely, a FIFO underrun
|
|
|
|
* will occur, and a display engine hang could result.
|
|
|
|
*/
|
|
|
|
static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
|
|
|
|
const struct intel_watermark_params *wm,
|
2016-01-20 19:05:26 +00:00
|
|
|
int fifo_size, int cpp,
|
2012-04-17 01:20:35 +00:00
|
|
|
unsigned long latency_ns)
|
|
|
|
{
|
|
|
|
long entries_required, wm_size;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note: we need to make sure we don't overflow for various clock &
|
|
|
|
* latency values.
|
|
|
|
* clocks go from a few thousand to several hundred thousand.
|
|
|
|
* latency is usually a few thousand
|
|
|
|
*/
|
2016-01-20 19:05:26 +00:00
|
|
|
entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
|
2012-04-17 01:20:35 +00:00
|
|
|
1000;
|
|
|
|
entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
|
|
|
|
|
|
|
|
wm_size = fifo_size - (entries_required + wm->guard_size);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
|
|
|
|
|
|
|
|
/* Don't promote wm_size to unsigned... */
|
|
|
|
if (wm_size > (long)wm->max_wm)
|
|
|
|
wm_size = wm->max_wm;
|
|
|
|
if (wm_size <= 0)
|
|
|
|
wm_size = wm->default_wm;
|
2014-09-05 18:54:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Bspec seems to indicate that the value shouldn't be lower than
|
|
|
|
* 'burst size + 1'. Certainly 830 is quite unhappy with low values.
|
|
|
|
* Lets go for 8 which is the burst size since certain platforms
|
|
|
|
* already use a hardcoded 8 (which is what the spec says should be
|
|
|
|
* done).
|
|
|
|
*/
|
|
|
|
if (wm_size <= 8)
|
|
|
|
wm_size = 8;
|
|
|
|
|
2012-04-17 01:20:35 +00:00
|
|
|
return wm_size;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:21 +00:00
|
|
|
static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-10-31 20:37:04 +00:00
|
|
|
struct intel_crtc *crtc, *enabled = NULL;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-10-31 20:37:21 +00:00
|
|
|
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
2016-10-31 20:37:04 +00:00
|
|
|
if (intel_crtc_active(crtc)) {
|
2012-04-17 01:20:35 +00:00
|
|
|
if (enabled)
|
|
|
|
return NULL;
|
|
|
|
enabled = crtc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return enabled;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
static void pineview_update_wm(struct intel_crtc *unused_crtc)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-10-31 20:37:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
|
2016-10-31 20:37:04 +00:00
|
|
|
struct intel_crtc *crtc;
|
2012-04-17 01:20:35 +00:00
|
|
|
const struct cxsr_latency *latency;
|
|
|
|
u32 reg;
|
|
|
|
unsigned long wm;
|
|
|
|
|
2016-10-13 10:02:58 +00:00
|
|
|
latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
|
|
|
|
dev_priv->is_ddr3,
|
|
|
|
dev_priv->fsb_freq,
|
|
|
|
dev_priv->mem_freq);
|
2012-04-17 01:20:35 +00:00
|
|
|
if (!latency) {
|
|
|
|
DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
|
2014-07-01 09:36:17 +00:00
|
|
|
intel_set_memory_cxsr(dev_priv, false);
|
2012-04-17 01:20:35 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:21 +00:00
|
|
|
crtc = single_enabled_crtc(dev_priv);
|
2012-04-17 01:20:35 +00:00
|
|
|
if (crtc) {
|
2016-10-31 20:37:04 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc->config->base.adjusted_mode;
|
|
|
|
const struct drm_framebuffer *fb =
|
|
|
|
crtc->base.primary->state->fb;
|
2016-12-14 21:30:57 +00:00
|
|
|
int cpp = fb->format->cpp[0];
|
2015-09-08 10:40:49 +00:00
|
|
|
int clock = adjusted_mode->crtc_clock;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
/* Display SR */
|
|
|
|
wm = intel_calculate_wm(clock, &pineview_display_wm,
|
|
|
|
pineview_display_wm.fifo_size,
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp, latency->display_sr);
|
2012-04-17 01:20:35 +00:00
|
|
|
reg = I915_READ(DSPFW1);
|
|
|
|
reg &= ~DSPFW_SR_MASK;
|
2015-03-10 15:02:21 +00:00
|
|
|
reg |= FW_WM(wm, SR);
|
2012-04-17 01:20:35 +00:00
|
|
|
I915_WRITE(DSPFW1, reg);
|
|
|
|
DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
|
|
|
|
|
|
|
|
/* cursor SR */
|
|
|
|
wm = intel_calculate_wm(clock, &pineview_cursor_wm,
|
|
|
|
pineview_display_wm.fifo_size,
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp, latency->cursor_sr);
|
2012-04-17 01:20:35 +00:00
|
|
|
reg = I915_READ(DSPFW3);
|
|
|
|
reg &= ~DSPFW_CURSOR_SR_MASK;
|
2015-03-10 15:02:21 +00:00
|
|
|
reg |= FW_WM(wm, CURSOR_SR);
|
2012-04-17 01:20:35 +00:00
|
|
|
I915_WRITE(DSPFW3, reg);
|
|
|
|
|
|
|
|
/* Display HPLL off SR */
|
|
|
|
wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
|
|
|
|
pineview_display_hplloff_wm.fifo_size,
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp, latency->display_hpll_disable);
|
2012-04-17 01:20:35 +00:00
|
|
|
reg = I915_READ(DSPFW3);
|
|
|
|
reg &= ~DSPFW_HPLL_SR_MASK;
|
2015-03-10 15:02:21 +00:00
|
|
|
reg |= FW_WM(wm, HPLL_SR);
|
2012-04-17 01:20:35 +00:00
|
|
|
I915_WRITE(DSPFW3, reg);
|
|
|
|
|
|
|
|
/* cursor HPLL off SR */
|
|
|
|
wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
|
|
|
|
pineview_display_hplloff_wm.fifo_size,
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp, latency->cursor_hpll_disable);
|
2012-04-17 01:20:35 +00:00
|
|
|
reg = I915_READ(DSPFW3);
|
|
|
|
reg &= ~DSPFW_HPLL_CURSOR_MASK;
|
2015-03-10 15:02:21 +00:00
|
|
|
reg |= FW_WM(wm, HPLL_CURSOR);
|
2012-04-17 01:20:35 +00:00
|
|
|
I915_WRITE(DSPFW3, reg);
|
|
|
|
DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
|
|
|
|
|
2014-07-01 09:36:17 +00:00
|
|
|
intel_set_memory_cxsr(dev_priv, true);
|
2012-04-17 01:20:35 +00:00
|
|
|
} else {
|
2014-07-01 09:36:17 +00:00
|
|
|
intel_set_memory_cxsr(dev_priv, false);
|
2012-04-17 01:20:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:08 +00:00
|
|
|
static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
|
2012-04-17 01:20:35 +00:00
|
|
|
int plane,
|
|
|
|
const struct intel_watermark_params *display,
|
|
|
|
int display_latency_ns,
|
|
|
|
const struct intel_watermark_params *cursor,
|
|
|
|
int cursor_latency_ns,
|
|
|
|
int *plane_wm,
|
|
|
|
int *cursor_wm)
|
|
|
|
{
|
2016-10-31 20:37:04 +00:00
|
|
|
struct intel_crtc *crtc;
|
2013-09-04 15:25:22 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode;
|
2016-10-31 20:37:04 +00:00
|
|
|
const struct drm_framebuffer *fb;
|
2016-01-20 19:05:26 +00:00
|
|
|
int htotal, hdisplay, clock, cpp;
|
2012-04-17 01:20:35 +00:00
|
|
|
int line_time_us, line_count;
|
|
|
|
int entries, tlb_miss;
|
|
|
|
|
2016-10-31 20:37:09 +00:00
|
|
|
crtc = intel_get_crtc_for_plane(dev_priv, plane);
|
2016-10-31 20:37:04 +00:00
|
|
|
if (!intel_crtc_active(crtc)) {
|
2012-04-17 01:20:35 +00:00
|
|
|
*cursor_wm = cursor->guard_size;
|
|
|
|
*plane_wm = display->guard_size;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:04 +00:00
|
|
|
adjusted_mode = &crtc->config->base.adjusted_mode;
|
|
|
|
fb = crtc->base.primary->state->fb;
|
2013-09-25 15:45:37 +00:00
|
|
|
clock = adjusted_mode->crtc_clock;
|
2013-11-27 19:10:26 +00:00
|
|
|
htotal = adjusted_mode->crtc_htotal;
|
2016-10-31 20:37:04 +00:00
|
|
|
hdisplay = crtc->config->pipe_src_w;
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = fb->format->cpp[0];
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
/* Use the small buffer method to calculate plane watermark */
|
2016-01-20 19:05:26 +00:00
|
|
|
entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
|
2012-04-17 01:20:35 +00:00
|
|
|
tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
|
|
|
|
if (tlb_miss > 0)
|
|
|
|
entries += tlb_miss;
|
|
|
|
entries = DIV_ROUND_UP(entries, display->cacheline_size);
|
|
|
|
*plane_wm = entries + display->guard_size;
|
|
|
|
if (*plane_wm > (int)display->max_wm)
|
|
|
|
*plane_wm = display->max_wm;
|
|
|
|
|
|
|
|
/* Use the large buffer method to calculate cursor watermark */
|
2014-02-14 12:18:57 +00:00
|
|
|
line_time_us = max(htotal * 1000 / clock, 1);
|
2012-04-17 01:20:35 +00:00
|
|
|
line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
|
2016-10-31 20:37:04 +00:00
|
|
|
entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
|
2012-04-17 01:20:35 +00:00
|
|
|
tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
|
|
|
|
if (tlb_miss > 0)
|
|
|
|
entries += tlb_miss;
|
|
|
|
entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
|
|
|
|
*cursor_wm = entries + cursor->guard_size;
|
|
|
|
if (*cursor_wm > (int)cursor->max_wm)
|
|
|
|
*cursor_wm = (int)cursor->max_wm;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check the wm result.
|
|
|
|
*
|
|
|
|
* If any calculated watermark values is larger than the maximum value that
|
|
|
|
* can be programmed into the associated watermark register, that watermark
|
|
|
|
* must be disabled.
|
|
|
|
*/
|
2016-10-31 20:37:08 +00:00
|
|
|
static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
|
2012-04-17 01:20:35 +00:00
|
|
|
int display_wm, int cursor_wm,
|
|
|
|
const struct intel_watermark_params *display,
|
|
|
|
const struct intel_watermark_params *cursor)
|
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
|
|
|
|
display_wm, cursor_wm);
|
|
|
|
|
|
|
|
if (display_wm > display->max_wm) {
|
2016-10-13 10:09:25 +00:00
|
|
|
DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
|
2012-04-17 01:20:35 +00:00
|
|
|
display_wm, display->max_wm);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cursor_wm > cursor->max_wm) {
|
2016-10-13 10:09:25 +00:00
|
|
|
DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
|
2012-04-17 01:20:35 +00:00
|
|
|
cursor_wm, cursor->max_wm);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(display_wm || cursor_wm)) {
|
|
|
|
DRM_DEBUG_KMS("SR latency is 0, disabling\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:08 +00:00
|
|
|
static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
|
2012-04-17 01:20:35 +00:00
|
|
|
int plane,
|
|
|
|
int latency_ns,
|
|
|
|
const struct intel_watermark_params *display,
|
|
|
|
const struct intel_watermark_params *cursor,
|
|
|
|
int *display_wm, int *cursor_wm)
|
|
|
|
{
|
2016-10-31 20:37:04 +00:00
|
|
|
struct intel_crtc *crtc;
|
2013-09-04 15:25:22 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode;
|
2016-10-31 20:37:04 +00:00
|
|
|
const struct drm_framebuffer *fb;
|
2016-01-20 19:05:26 +00:00
|
|
|
int hdisplay, htotal, cpp, clock;
|
2012-04-17 01:20:35 +00:00
|
|
|
unsigned long line_time_us;
|
|
|
|
int line_count, line_size;
|
|
|
|
int small, large;
|
|
|
|
int entries;
|
|
|
|
|
|
|
|
if (!latency_ns) {
|
|
|
|
*display_wm = *cursor_wm = 0;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:09 +00:00
|
|
|
crtc = intel_get_crtc_for_plane(dev_priv, plane);
|
2016-10-31 20:37:04 +00:00
|
|
|
adjusted_mode = &crtc->config->base.adjusted_mode;
|
|
|
|
fb = crtc->base.primary->state->fb;
|
2013-09-25 15:45:37 +00:00
|
|
|
clock = adjusted_mode->crtc_clock;
|
2013-11-27 19:10:26 +00:00
|
|
|
htotal = adjusted_mode->crtc_htotal;
|
2016-10-31 20:37:04 +00:00
|
|
|
hdisplay = crtc->config->pipe_src_w;
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = fb->format->cpp[0];
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2014-02-14 12:18:57 +00:00
|
|
|
line_time_us = max(htotal * 1000 / clock, 1);
|
2012-04-17 01:20:35 +00:00
|
|
|
line_count = (latency_ns / line_time_us + 1000) / 1000;
|
2016-01-20 19:05:26 +00:00
|
|
|
line_size = hdisplay * cpp;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
/* Use the minimum of the small and large buffer method for primary */
|
2016-01-20 19:05:26 +00:00
|
|
|
small = ((clock * cpp / 1000) * latency_ns) / 1000;
|
2012-04-17 01:20:35 +00:00
|
|
|
large = line_count * line_size;
|
|
|
|
|
|
|
|
entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
|
|
|
|
*display_wm = entries + display->guard_size;
|
|
|
|
|
|
|
|
/* calculate the self-refresh watermark for display cursor */
|
2016-10-31 20:37:04 +00:00
|
|
|
entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
|
2012-04-17 01:20:35 +00:00
|
|
|
entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
|
|
|
|
*cursor_wm = entries + cursor->guard_size;
|
|
|
|
|
2016-10-31 20:37:08 +00:00
|
|
|
return g4x_check_srwm(dev_priv,
|
2012-04-17 01:20:35 +00:00
|
|
|
*display_wm, *cursor_wm,
|
|
|
|
display, cursor);
|
|
|
|
}
|
|
|
|
|
2015-03-10 14:16:28 +00:00
|
|
|
#define FW_WM_VLV(value, plane) \
|
|
|
|
(((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
|
|
|
|
|
2016-11-28 17:37:15 +00:00
|
|
|
static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
|
2015-03-05 19:19:45 +00:00
|
|
|
const struct vlv_wm_values *wm)
|
|
|
|
{
|
2016-11-28 17:37:15 +00:00
|
|
|
enum pipe pipe;
|
|
|
|
|
|
|
|
for_each_pipe(dev_priv, pipe) {
|
|
|
|
I915_WRITE(VLV_DDL(pipe),
|
|
|
|
(wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
|
|
|
|
(wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
|
|
|
|
(wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
|
|
|
|
(wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
|
|
|
|
}
|
2015-03-05 19:19:45 +00:00
|
|
|
|
2016-11-28 17:37:14 +00:00
|
|
|
/*
|
|
|
|
* Zero the (unused) WM1 watermarks, and also clear all the
|
|
|
|
* high order bits so that there are no out of bounds values
|
|
|
|
* present in the registers during the reprogramming.
|
|
|
|
*/
|
|
|
|
I915_WRITE(DSPHOWM, 0);
|
|
|
|
I915_WRITE(DSPHOWM1, 0);
|
|
|
|
I915_WRITE(DSPFW4, 0);
|
|
|
|
I915_WRITE(DSPFW5, 0);
|
|
|
|
I915_WRITE(DSPFW6, 0);
|
|
|
|
|
2015-03-05 19:19:49 +00:00
|
|
|
I915_WRITE(DSPFW1,
|
2015-03-10 14:16:28 +00:00
|
|
|
FW_WM(wm->sr.plane, SR) |
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
|
|
|
|
FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
|
|
|
|
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
|
2015-03-05 19:19:49 +00:00
|
|
|
I915_WRITE(DSPFW2,
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
|
|
|
|
FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
|
|
|
|
FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
|
2015-03-05 19:19:49 +00:00
|
|
|
I915_WRITE(DSPFW3,
|
2015-03-10 14:16:28 +00:00
|
|
|
FW_WM(wm->sr.cursor, CURSOR_SR));
|
2015-03-05 19:19:49 +00:00
|
|
|
|
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
|
|
I915_WRITE(DSPFW7_CHV,
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
|
|
|
|
FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
|
2015-03-05 19:19:49 +00:00
|
|
|
I915_WRITE(DSPFW8_CHV,
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
|
|
|
|
FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
|
2015-03-05 19:19:49 +00:00
|
|
|
I915_WRITE(DSPFW9_CHV,
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
|
|
|
|
FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
|
2015-03-05 19:19:49 +00:00
|
|
|
I915_WRITE(DSPHOWM,
|
2015-03-10 14:16:28 +00:00
|
|
|
FW_WM(wm->sr.plane >> 9, SR_HI) |
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
|
2015-03-05 19:19:49 +00:00
|
|
|
} else {
|
|
|
|
I915_WRITE(DSPFW7,
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
|
|
|
|
FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
|
2015-03-05 19:19:49 +00:00
|
|
|
I915_WRITE(DSPHOWM,
|
2015-03-10 14:16:28 +00:00
|
|
|
FW_WM(wm->sr.plane >> 9, SR_HI) |
|
2016-11-28 17:37:08 +00:00
|
|
|
FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
|
|
|
|
FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
|
2015-03-05 19:19:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
POSTING_READ(DSPFW1);
|
2015-03-05 19:19:45 +00:00
|
|
|
}
|
|
|
|
|
2015-03-10 14:16:28 +00:00
|
|
|
#undef FW_WM_VLV
|
|
|
|
|
2015-06-24 19:00:03 +00:00
|
|
|
enum vlv_wm_level {
|
|
|
|
VLV_WM_LEVEL_PM2,
|
|
|
|
VLV_WM_LEVEL_PM5,
|
|
|
|
VLV_WM_LEVEL_DDR_DVFS,
|
|
|
|
};
|
|
|
|
|
2015-06-24 19:00:04 +00:00
|
|
|
/* latency must be in 0.1us units. */
|
|
|
|
static unsigned int vlv_wm_method2(unsigned int pixel_rate,
|
|
|
|
unsigned int pipe_htotal,
|
|
|
|
unsigned int horiz_pixels,
|
2016-01-20 19:05:26 +00:00
|
|
|
unsigned int cpp,
|
2015-06-24 19:00:04 +00:00
|
|
|
unsigned int latency)
|
|
|
|
{
|
|
|
|
unsigned int ret;
|
|
|
|
|
|
|
|
ret = (latency * pixel_rate) / (pipe_htotal * 10000);
|
2016-01-20 19:05:26 +00:00
|
|
|
ret = (ret + 1) * horiz_pixels * cpp;
|
2015-06-24 19:00:04 +00:00
|
|
|
ret = DIV_ROUND_UP(ret, 64);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:24 +00:00
|
|
|
static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
|
2015-06-24 19:00:04 +00:00
|
|
|
{
|
|
|
|
/* all latencies in usec */
|
|
|
|
dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
|
|
|
|
|
2015-09-08 18:05:12 +00:00
|
|
|
dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
|
|
|
|
|
2015-06-24 19:00:04 +00:00
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
|
|
dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
|
|
|
|
dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
|
2015-09-08 18:05:12 +00:00
|
|
|
|
|
|
|
dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
|
2015-06-24 19:00:04 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-28 17:37:17 +00:00
|
|
|
static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
|
|
|
|
const struct intel_plane_state *plane_state,
|
2015-06-24 19:00:04 +00:00
|
|
|
int level)
|
|
|
|
{
|
2016-11-28 17:37:17 +00:00
|
|
|
struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
|
2015-06-24 19:00:04 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
2016-11-28 17:37:17 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc_state->base.adjusted_mode;
|
2016-01-20 19:05:26 +00:00
|
|
|
int clock, htotal, cpp, width, wm;
|
2015-06-24 19:00:04 +00:00
|
|
|
|
|
|
|
if (dev_priv->wm.pri_latency[level] == 0)
|
|
|
|
return USHRT_MAX;
|
|
|
|
|
2016-11-28 17:37:17 +00:00
|
|
|
if (!plane_state->base.visible)
|
2015-06-24 19:00:04 +00:00
|
|
|
return 0;
|
|
|
|
|
2017-01-04 10:41:10 +00:00
|
|
|
cpp = plane_state->base.fb->format->cpp[0];
|
2016-11-28 17:37:17 +00:00
|
|
|
clock = adjusted_mode->crtc_clock;
|
|
|
|
htotal = adjusted_mode->crtc_htotal;
|
|
|
|
width = crtc_state->pipe_src_w;
|
2015-06-24 19:00:04 +00:00
|
|
|
if (WARN_ON(htotal == 0))
|
|
|
|
htotal = 1;
|
|
|
|
|
|
|
|
if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
|
|
|
|
/*
|
|
|
|
* FIXME the formula gives values that are
|
|
|
|
* too big for the cursor FIFO, and hence we
|
|
|
|
* would never be able to use cursors. For
|
|
|
|
* now just hardcode the watermark.
|
|
|
|
*/
|
|
|
|
wm = 63;
|
|
|
|
} else {
|
2016-01-20 19:05:26 +00:00
|
|
|
wm = vlv_wm_method2(clock, htotal, width, cpp,
|
2015-06-24 19:00:04 +00:00
|
|
|
dev_priv->wm.pri_latency[level] * 10);
|
|
|
|
}
|
|
|
|
|
|
|
|
return min_t(int, wm, USHRT_MAX);
|
|
|
|
}
|
|
|
|
|
2015-06-24 19:00:05 +00:00
|
|
|
static void vlv_compute_fifo(struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
|
struct vlv_wm_state *wm_state = &crtc->wm_state;
|
|
|
|
struct intel_plane *plane;
|
|
|
|
unsigned int total_rate = 0;
|
|
|
|
const int fifo_size = 512 - 1;
|
|
|
|
int fifo_extra, fifo_left = fifo_size;
|
|
|
|
|
|
|
|
for_each_intel_plane_on_crtc(dev, crtc, plane) {
|
|
|
|
struct intel_plane_state *state =
|
|
|
|
to_intel_plane_state(plane->base.state);
|
|
|
|
|
|
|
|
if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
|
|
|
|
continue;
|
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (state->base.visible) {
|
2015-06-24 19:00:05 +00:00
|
|
|
wm_state->num_active_planes++;
|
2016-12-14 21:30:57 +00:00
|
|
|
total_rate += state->base.fb->format->cpp[0];
|
2015-06-24 19:00:05 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_intel_plane_on_crtc(dev, crtc, plane) {
|
|
|
|
struct intel_plane_state *state =
|
|
|
|
to_intel_plane_state(plane->base.state);
|
|
|
|
unsigned int rate;
|
|
|
|
|
|
|
|
if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
|
|
|
|
plane->wm.fifo_size = 63;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (!state->base.visible) {
|
2015-06-24 19:00:05 +00:00
|
|
|
plane->wm.fifo_size = 0;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2016-12-14 21:30:57 +00:00
|
|
|
rate = state->base.fb->format->cpp[0];
|
2015-06-24 19:00:05 +00:00
|
|
|
plane->wm.fifo_size = fifo_size * rate / total_rate;
|
|
|
|
fifo_left -= plane->wm.fifo_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
|
|
|
|
|
|
|
|
/* spread the remainder evenly */
|
|
|
|
for_each_intel_plane_on_crtc(dev, crtc, plane) {
|
|
|
|
int plane_extra;
|
|
|
|
|
|
|
|
if (fifo_left == 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* give it all to the first plane if none are active */
|
|
|
|
if (plane->wm.fifo_size == 0 &&
|
|
|
|
wm_state->num_active_planes)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
plane_extra = min(fifo_extra, fifo_left);
|
|
|
|
plane->wm.fifo_size += plane_extra;
|
|
|
|
fifo_left -= plane_extra;
|
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(fifo_left != 0);
|
|
|
|
}
|
|
|
|
|
2016-11-28 17:37:09 +00:00
|
|
|
static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
|
|
|
|
{
|
|
|
|
if (wm > fifo_size)
|
|
|
|
return USHRT_MAX;
|
|
|
|
else
|
|
|
|
return fifo_size - wm;
|
|
|
|
}
|
|
|
|
|
2015-06-24 19:00:04 +00:00
|
|
|
static void vlv_invert_wms(struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct vlv_wm_state *wm_state = &crtc->wm_state;
|
|
|
|
int level;
|
|
|
|
|
|
|
|
for (level = 0; level < wm_state->num_levels; level++) {
|
2016-11-28 17:37:10 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2016-11-09 11:30:45 +00:00
|
|
|
const int sr_fifo_size =
|
2016-11-28 17:37:10 +00:00
|
|
|
INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
|
2015-06-24 19:00:04 +00:00
|
|
|
struct intel_plane *plane;
|
|
|
|
|
2016-11-28 17:37:09 +00:00
|
|
|
wm_state->sr[level].plane =
|
|
|
|
vlv_invert_wm_value(wm_state->sr[level].plane,
|
|
|
|
sr_fifo_size);
|
|
|
|
wm_state->sr[level].cursor =
|
|
|
|
vlv_invert_wm_value(wm_state->sr[level].cursor,
|
|
|
|
63);
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2016-11-28 17:37:10 +00:00
|
|
|
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
|
2016-11-28 17:37:09 +00:00
|
|
|
wm_state->wm[level].plane[plane->id] =
|
|
|
|
vlv_invert_wm_value(wm_state->wm[level].plane[plane->id],
|
|
|
|
plane->wm.fifo_size);
|
2015-06-24 19:00:04 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-06-24 19:00:06 +00:00
|
|
|
static void vlv_compute_wm(struct intel_crtc *crtc)
|
2015-06-24 19:00:04 +00:00
|
|
|
{
|
2016-11-28 17:37:10 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2015-06-24 19:00:04 +00:00
|
|
|
struct vlv_wm_state *wm_state = &crtc->wm_state;
|
|
|
|
struct intel_plane *plane;
|
|
|
|
int level;
|
|
|
|
|
|
|
|
memset(wm_state, 0, sizeof(*wm_state));
|
|
|
|
|
2015-06-24 19:00:07 +00:00
|
|
|
wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
|
2016-11-09 11:30:45 +00:00
|
|
|
wm_state->num_levels = dev_priv->wm.max_level + 1;
|
2015-06-24 19:00:04 +00:00
|
|
|
|
|
|
|
wm_state->num_active_planes = 0;
|
|
|
|
|
2015-06-24 19:00:05 +00:00
|
|
|
vlv_compute_fifo(crtc);
|
2015-06-24 19:00:04 +00:00
|
|
|
|
|
|
|
if (wm_state->num_active_planes != 1)
|
|
|
|
wm_state->cxsr = false;
|
|
|
|
|
2016-11-28 17:37:10 +00:00
|
|
|
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
|
2015-06-24 19:00:04 +00:00
|
|
|
struct intel_plane_state *state =
|
|
|
|
to_intel_plane_state(plane->base.state);
|
2016-11-28 17:37:08 +00:00
|
|
|
int level;
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (!state->base.visible)
|
2015-06-24 19:00:04 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* normal watermarks */
|
|
|
|
for (level = 0; level < wm_state->num_levels; level++) {
|
2016-11-28 17:37:17 +00:00
|
|
|
int wm = vlv_compute_wm_level(crtc->config, state, level);
|
2016-11-28 17:37:05 +00:00
|
|
|
int max_wm = plane->wm.fifo_size;
|
2015-06-24 19:00:04 +00:00
|
|
|
|
|
|
|
/* hack */
|
|
|
|
if (WARN_ON(level == 0 && wm > max_wm))
|
|
|
|
wm = max_wm;
|
|
|
|
|
2016-11-28 17:37:05 +00:00
|
|
|
if (wm > max_wm)
|
2015-06-24 19:00:04 +00:00
|
|
|
break;
|
|
|
|
|
2016-11-28 17:37:08 +00:00
|
|
|
wm_state->wm[level].plane[plane->id] = wm;
|
2015-06-24 19:00:04 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
wm_state->num_levels = level;
|
|
|
|
|
|
|
|
if (!wm_state->cxsr)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* maxfifo watermarks */
|
2016-11-28 17:37:08 +00:00
|
|
|
if (plane->id == PLANE_CURSOR) {
|
2015-06-24 19:00:04 +00:00
|
|
|
for (level = 0; level < wm_state->num_levels; level++)
|
|
|
|
wm_state->sr[level].cursor =
|
2016-11-28 17:37:08 +00:00
|
|
|
wm_state->wm[level].plane[PLANE_CURSOR];
|
|
|
|
} else {
|
2015-06-24 19:00:04 +00:00
|
|
|
for (level = 0; level < wm_state->num_levels; level++)
|
|
|
|
wm_state->sr[level].plane =
|
2016-11-28 17:37:06 +00:00
|
|
|
max(wm_state->sr[level].plane,
|
2016-11-28 17:37:08 +00:00
|
|
|
wm_state->wm[level].plane[plane->id]);
|
2015-06-24 19:00:04 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear any (partially) filled invalid levels */
|
2016-11-09 11:30:45 +00:00
|
|
|
for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
|
2015-06-24 19:00:04 +00:00
|
|
|
memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
|
|
|
|
memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
|
|
|
|
}
|
|
|
|
|
|
|
|
vlv_invert_wms(crtc);
|
|
|
|
}
|
|
|
|
|
2015-06-24 19:00:05 +00:00
|
|
|
#define VLV_FIFO(plane, value) \
|
|
|
|
(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
|
|
|
|
|
|
|
|
static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct intel_plane *plane;
|
|
|
|
int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
|
|
|
|
|
|
|
|
for_each_intel_plane_on_crtc(dev, crtc, plane) {
|
2016-11-22 16:02:01 +00:00
|
|
|
switch (plane->id) {
|
|
|
|
case PLANE_PRIMARY:
|
2015-06-24 19:00:05 +00:00
|
|
|
sprite0_start = plane->wm.fifo_size;
|
2016-11-22 16:02:01 +00:00
|
|
|
break;
|
|
|
|
case PLANE_SPRITE0:
|
2015-06-24 19:00:05 +00:00
|
|
|
sprite1_start = sprite0_start + plane->wm.fifo_size;
|
2016-11-22 16:02:01 +00:00
|
|
|
break;
|
|
|
|
case PLANE_SPRITE1:
|
2015-06-24 19:00:05 +00:00
|
|
|
fifo_size = sprite1_start + plane->wm.fifo_size;
|
2016-11-22 16:02:01 +00:00
|
|
|
break;
|
|
|
|
case PLANE_CURSOR:
|
|
|
|
WARN_ON(plane->wm.fifo_size != 63);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(plane->id);
|
|
|
|
break;
|
|
|
|
}
|
2015-06-24 19:00:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(fifo_size != 512 - 1);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
|
|
|
|
pipe_name(crtc->pipe), sprite0_start,
|
|
|
|
sprite1_start, fifo_size);
|
|
|
|
|
2016-12-05 14:13:28 +00:00
|
|
|
spin_lock(&dev_priv->wm.dsparb_lock);
|
|
|
|
|
2015-06-24 19:00:05 +00:00
|
|
|
switch (crtc->pipe) {
|
|
|
|
uint32_t dsparb, dsparb2, dsparb3;
|
|
|
|
case PIPE_A:
|
|
|
|
dsparb = I915_READ(DSPARB);
|
|
|
|
dsparb2 = I915_READ(DSPARB2);
|
|
|
|
|
|
|
|
dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
|
|
|
|
VLV_FIFO(SPRITEB, 0xff));
|
|
|
|
dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
|
|
|
|
VLV_FIFO(SPRITEB, sprite1_start));
|
|
|
|
|
|
|
|
dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
|
|
|
|
VLV_FIFO(SPRITEB_HI, 0x1));
|
|
|
|
dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
|
|
|
|
VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
|
|
|
|
|
|
|
|
I915_WRITE(DSPARB, dsparb);
|
|
|
|
I915_WRITE(DSPARB2, dsparb2);
|
|
|
|
break;
|
|
|
|
case PIPE_B:
|
|
|
|
dsparb = I915_READ(DSPARB);
|
|
|
|
dsparb2 = I915_READ(DSPARB2);
|
|
|
|
|
|
|
|
dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
|
|
|
|
VLV_FIFO(SPRITED, 0xff));
|
|
|
|
dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
|
|
|
|
VLV_FIFO(SPRITED, sprite1_start));
|
|
|
|
|
|
|
|
dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
|
|
|
|
VLV_FIFO(SPRITED_HI, 0xff));
|
|
|
|
dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
|
|
|
|
VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
|
|
|
|
|
|
|
|
I915_WRITE(DSPARB, dsparb);
|
|
|
|
I915_WRITE(DSPARB2, dsparb2);
|
|
|
|
break;
|
|
|
|
case PIPE_C:
|
|
|
|
dsparb3 = I915_READ(DSPARB3);
|
|
|
|
dsparb2 = I915_READ(DSPARB2);
|
|
|
|
|
|
|
|
dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
|
|
|
|
VLV_FIFO(SPRITEF, 0xff));
|
|
|
|
dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
|
|
|
|
VLV_FIFO(SPRITEF, sprite1_start));
|
|
|
|
|
|
|
|
dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
|
|
|
|
VLV_FIFO(SPRITEF_HI, 0xff));
|
|
|
|
dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
|
|
|
|
VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
|
|
|
|
|
|
|
|
I915_WRITE(DSPARB3, dsparb3);
|
|
|
|
I915_WRITE(DSPARB2, dsparb2);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2016-12-05 14:13:28 +00:00
|
|
|
|
|
|
|
POSTING_READ(DSPARB);
|
|
|
|
|
|
|
|
spin_unlock(&dev_priv->wm.dsparb_lock);
|
2015-06-24 19:00:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#undef VLV_FIFO
|
|
|
|
|
2016-11-28 17:37:10 +00:00
|
|
|
static void vlv_merge_wm(struct drm_i915_private *dev_priv,
|
2015-06-24 19:00:04 +00:00
|
|
|
struct vlv_wm_values *wm)
|
|
|
|
{
|
|
|
|
struct intel_crtc *crtc;
|
|
|
|
int num_active_crtcs = 0;
|
|
|
|
|
2016-11-28 17:37:10 +00:00
|
|
|
wm->level = dev_priv->wm.max_level;
|
2015-06-24 19:00:04 +00:00
|
|
|
wm->cxsr = true;
|
|
|
|
|
2016-11-28 17:37:10 +00:00
|
|
|
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
2015-06-24 19:00:04 +00:00
|
|
|
const struct vlv_wm_state *wm_state = &crtc->wm_state;
|
|
|
|
|
|
|
|
if (!crtc->active)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!wm_state->cxsr)
|
|
|
|
wm->cxsr = false;
|
|
|
|
|
|
|
|
num_active_crtcs++;
|
|
|
|
wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (num_active_crtcs != 1)
|
|
|
|
wm->cxsr = false;
|
|
|
|
|
2015-06-24 19:00:08 +00:00
|
|
|
if (num_active_crtcs > 1)
|
|
|
|
wm->level = VLV_WM_LEVEL_PM2;
|
|
|
|
|
2016-11-28 17:37:10 +00:00
|
|
|
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
2015-06-24 19:00:04 +00:00
|
|
|
struct vlv_wm_state *wm_state = &crtc->wm_state;
|
|
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
|
|
|
|
if (!crtc->active)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
wm->pipe[pipe] = wm_state->wm[wm->level];
|
|
|
|
if (wm->cxsr)
|
|
|
|
wm->sr = wm_state->sr[wm->level];
|
|
|
|
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
|
|
|
|
wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
|
|
|
|
wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
|
|
|
|
wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
|
2015-06-24 19:00:04 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
static bool is_disabling(int old, int new, int threshold)
|
|
|
|
{
|
|
|
|
return old >= threshold && new < threshold;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool is_enabling(int old, int new, int threshold)
|
|
|
|
{
|
|
|
|
return old < threshold && new >= threshold;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
static void vlv_update_wm(struct intel_crtc *crtc)
|
2015-06-24 19:00:04 +00:00
|
|
|
{
|
2016-11-28 17:37:10 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2016-10-31 20:37:03 +00:00
|
|
|
enum pipe pipe = crtc->pipe;
|
2016-11-28 17:37:16 +00:00
|
|
|
struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
|
|
|
|
struct vlv_wm_values new_wm = {};
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
vlv_compute_wm(crtc);
|
2016-11-28 17:37:16 +00:00
|
|
|
vlv_merge_wm(dev_priv, &new_wm);
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
|
2015-06-24 19:00:05 +00:00
|
|
|
/* FIXME should be part of crtc atomic commit */
|
2016-10-31 20:37:03 +00:00
|
|
|
vlv_pipe_set_fifo_size(crtc);
|
2016-11-28 17:37:16 +00:00
|
|
|
|
2015-06-24 19:00:04 +00:00
|
|
|
return;
|
2015-06-24 19:00:05 +00:00
|
|
|
}
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
|
2015-06-24 19:00:04 +00:00
|
|
|
chv_set_memory_dvfs(dev_priv, false);
|
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
|
2015-06-24 19:00:04 +00:00
|
|
|
chv_set_memory_pm5(dev_priv, false);
|
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
|
2016-11-28 17:37:11 +00:00
|
|
|
_intel_set_memory_cxsr(dev_priv, false);
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2015-06-24 19:00:05 +00:00
|
|
|
/* FIXME should be part of crtc atomic commit */
|
2016-10-31 20:37:03 +00:00
|
|
|
vlv_pipe_set_fifo_size(crtc);
|
2015-06-24 19:00:05 +00:00
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
vlv_write_wm_values(dev_priv, &new_wm);
|
2015-06-24 19:00:04 +00:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
|
|
|
|
"sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
|
2016-11-28 17:37:16 +00:00
|
|
|
pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
|
|
|
|
new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
|
|
|
|
new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
|
2016-11-28 17:37:11 +00:00
|
|
|
_intel_set_memory_cxsr(dev_priv, true);
|
2015-06-24 19:00:04 +00:00
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
|
2015-06-24 19:00:04 +00:00
|
|
|
chv_set_memory_pm5(dev_priv, true);
|
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
|
2015-06-24 19:00:04 +00:00
|
|
|
chv_set_memory_dvfs(dev_priv, true);
|
|
|
|
|
2016-11-28 17:37:16 +00:00
|
|
|
*old_wm = new_wm;
|
2014-06-26 14:03:06 +00:00
|
|
|
}
|
|
|
|
|
2015-03-05 19:19:49 +00:00
|
|
|
#define single_plane_enabled(mask) is_power_of_2(mask)
|
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
static void g4x_update_wm(struct intel_crtc *crtc)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-10-31 20:37:09 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2012-04-17 01:20:35 +00:00
|
|
|
static const int sr_latency_ns = 12000;
|
|
|
|
int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
|
|
|
|
int plane_sr, cursor_sr;
|
|
|
|
unsigned int enabled = 0;
|
2014-06-13 11:54:20 +00:00
|
|
|
bool cxsr_enabled;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-10-31 20:37:08 +00:00
|
|
|
if (g4x_compute_wm0(dev_priv, PIPE_A,
|
2014-09-03 10:56:07 +00:00
|
|
|
&g4x_wm_info, pessimal_latency_ns,
|
|
|
|
&g4x_cursor_wm_info, pessimal_latency_ns,
|
2012-04-17 01:20:35 +00:00
|
|
|
&planea_wm, &cursora_wm))
|
2013-03-21 11:10:44 +00:00
|
|
|
enabled |= 1 << PIPE_A;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-10-31 20:37:08 +00:00
|
|
|
if (g4x_compute_wm0(dev_priv, PIPE_B,
|
2014-09-03 10:56:07 +00:00
|
|
|
&g4x_wm_info, pessimal_latency_ns,
|
|
|
|
&g4x_cursor_wm_info, pessimal_latency_ns,
|
2012-04-17 01:20:35 +00:00
|
|
|
&planeb_wm, &cursorb_wm))
|
2013-03-21 11:10:44 +00:00
|
|
|
enabled |= 1 << PIPE_B;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
if (single_plane_enabled(enabled) &&
|
2016-10-31 20:37:08 +00:00
|
|
|
g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
|
2012-04-17 01:20:35 +00:00
|
|
|
sr_latency_ns,
|
|
|
|
&g4x_wm_info,
|
|
|
|
&g4x_cursor_wm_info,
|
2012-12-07 10:43:24 +00:00
|
|
|
&plane_sr, &cursor_sr)) {
|
2014-06-13 11:54:20 +00:00
|
|
|
cxsr_enabled = true;
|
2012-12-07 10:43:24 +00:00
|
|
|
} else {
|
2014-06-13 11:54:20 +00:00
|
|
|
cxsr_enabled = false;
|
2014-07-01 09:36:17 +00:00
|
|
|
intel_set_memory_cxsr(dev_priv, false);
|
2012-12-07 10:43:24 +00:00
|
|
|
plane_sr = cursor_sr = 0;
|
|
|
|
}
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2014-06-27 23:04:18 +00:00
|
|
|
DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
|
|
|
|
"B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
|
2012-04-17 01:20:35 +00:00
|
|
|
planea_wm, cursora_wm,
|
|
|
|
planeb_wm, cursorb_wm,
|
|
|
|
plane_sr, cursor_sr);
|
|
|
|
|
|
|
|
I915_WRITE(DSPFW1,
|
2015-03-10 15:02:21 +00:00
|
|
|
FW_WM(plane_sr, SR) |
|
|
|
|
FW_WM(cursorb_wm, CURSORB) |
|
|
|
|
FW_WM(planeb_wm, PLANEB) |
|
|
|
|
FW_WM(planea_wm, PLANEA));
|
2012-04-17 01:20:35 +00:00
|
|
|
I915_WRITE(DSPFW2,
|
2012-12-04 16:33:19 +00:00
|
|
|
(I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
|
2015-03-10 15:02:21 +00:00
|
|
|
FW_WM(cursora_wm, CURSORA));
|
2012-04-17 01:20:35 +00:00
|
|
|
/* HPLL off in SR has some issues on G4x... disable it */
|
|
|
|
I915_WRITE(DSPFW3,
|
2012-12-04 16:33:19 +00:00
|
|
|
(I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
|
2015-03-10 15:02:21 +00:00
|
|
|
FW_WM(cursor_sr, CURSOR_SR));
|
2014-06-13 11:54:20 +00:00
|
|
|
|
|
|
|
if (cxsr_enabled)
|
|
|
|
intel_set_memory_cxsr(dev_priv, true);
|
2012-04-17 01:20:35 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
static void i965_update_wm(struct intel_crtc *unused_crtc)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-10-31 20:37:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
|
2016-10-31 20:37:04 +00:00
|
|
|
struct intel_crtc *crtc;
|
2012-04-17 01:20:35 +00:00
|
|
|
int srwm = 1;
|
|
|
|
int cursor_sr = 16;
|
2014-06-13 11:54:20 +00:00
|
|
|
bool cxsr_enabled;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
/* Calc sr entries for one plane configs */
|
2016-10-31 20:37:21 +00:00
|
|
|
crtc = single_enabled_crtc(dev_priv);
|
2012-04-17 01:20:35 +00:00
|
|
|
if (crtc) {
|
|
|
|
/* self-refresh has much higher latency */
|
|
|
|
static const int sr_latency_ns = 12000;
|
2016-10-31 20:37:04 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc->config->base.adjusted_mode;
|
|
|
|
const struct drm_framebuffer *fb =
|
|
|
|
crtc->base.primary->state->fb;
|
2013-09-25 15:45:37 +00:00
|
|
|
int clock = adjusted_mode->crtc_clock;
|
2013-11-27 19:10:26 +00:00
|
|
|
int htotal = adjusted_mode->crtc_htotal;
|
2016-10-31 20:37:04 +00:00
|
|
|
int hdisplay = crtc->config->pipe_src_w;
|
2016-12-14 21:30:57 +00:00
|
|
|
int cpp = fb->format->cpp[0];
|
2012-04-17 01:20:35 +00:00
|
|
|
unsigned long line_time_us;
|
|
|
|
int entries;
|
|
|
|
|
2014-02-14 12:18:57 +00:00
|
|
|
line_time_us = max(htotal * 1000 / clock, 1);
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
/* Use ns/us then divide to preserve precision */
|
|
|
|
entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp * hdisplay;
|
2012-04-17 01:20:35 +00:00
|
|
|
entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
|
|
|
|
srwm = I965_FIFO_SIZE - entries;
|
|
|
|
if (srwm < 0)
|
|
|
|
srwm = 1;
|
|
|
|
srwm &= 0x1ff;
|
|
|
|
DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
|
|
|
|
entries, srwm);
|
|
|
|
|
|
|
|
entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
|
2016-10-31 20:37:04 +00:00
|
|
|
cpp * crtc->base.cursor->state->crtc_w;
|
2012-04-17 01:20:35 +00:00
|
|
|
entries = DIV_ROUND_UP(entries,
|
|
|
|
i965_cursor_wm_info.cacheline_size);
|
|
|
|
cursor_sr = i965_cursor_wm_info.fifo_size -
|
|
|
|
(entries + i965_cursor_wm_info.guard_size);
|
|
|
|
|
|
|
|
if (cursor_sr > i965_cursor_wm_info.max_wm)
|
|
|
|
cursor_sr = i965_cursor_wm_info.max_wm;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
|
|
|
|
"cursor %d\n", srwm, cursor_sr);
|
|
|
|
|
2014-06-13 11:54:20 +00:00
|
|
|
cxsr_enabled = true;
|
2012-04-17 01:20:35 +00:00
|
|
|
} else {
|
2014-06-13 11:54:20 +00:00
|
|
|
cxsr_enabled = false;
|
2012-04-17 01:20:35 +00:00
|
|
|
/* Turn off self refresh if both pipes are enabled */
|
2014-07-01 09:36:17 +00:00
|
|
|
intel_set_memory_cxsr(dev_priv, false);
|
2012-04-17 01:20:35 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
|
|
|
|
srwm);
|
|
|
|
|
|
|
|
/* 965 has limitations... */
|
2015-03-10 15:02:21 +00:00
|
|
|
I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
|
|
|
|
FW_WM(8, CURSORB) |
|
|
|
|
FW_WM(8, PLANEB) |
|
|
|
|
FW_WM(8, PLANEA));
|
|
|
|
I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
|
|
|
|
FW_WM(8, PLANEC_OLD));
|
2012-04-17 01:20:35 +00:00
|
|
|
/* update cursor SR watermark */
|
2015-03-10 15:02:21 +00:00
|
|
|
I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
|
2014-06-13 11:54:20 +00:00
|
|
|
|
|
|
|
if (cxsr_enabled)
|
|
|
|
intel_set_memory_cxsr(dev_priv, true);
|
2012-04-17 01:20:35 +00:00
|
|
|
}
|
|
|
|
|
2015-03-10 15:02:21 +00:00
|
|
|
#undef FW_WM
|
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
static void i9xx_update_wm(struct intel_crtc *unused_crtc)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-10-31 20:37:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
|
2012-04-17 01:20:35 +00:00
|
|
|
const struct intel_watermark_params *wm_info;
|
|
|
|
uint32_t fwater_lo;
|
|
|
|
uint32_t fwater_hi;
|
|
|
|
int cwm, srwm = 1;
|
|
|
|
int fifo_size;
|
|
|
|
int planea_wm, planeb_wm;
|
2016-10-31 20:37:04 +00:00
|
|
|
struct intel_crtc *crtc, *enabled = NULL;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-10-31 20:37:20 +00:00
|
|
|
if (IS_I945GM(dev_priv))
|
2012-04-17 01:20:35 +00:00
|
|
|
wm_info = &i945_wm_info;
|
2016-10-13 10:03:10 +00:00
|
|
|
else if (!IS_GEN2(dev_priv))
|
2012-04-17 01:20:35 +00:00
|
|
|
wm_info = &i915_wm_info;
|
|
|
|
else
|
2014-08-14 22:21:53 +00:00
|
|
|
wm_info = &i830_a_wm_info;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-10-31 20:37:17 +00:00
|
|
|
fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
|
2016-10-31 20:37:09 +00:00
|
|
|
crtc = intel_get_crtc_for_plane(dev_priv, 0);
|
2016-10-31 20:37:04 +00:00
|
|
|
if (intel_crtc_active(crtc)) {
|
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc->config->base.adjusted_mode;
|
|
|
|
const struct drm_framebuffer *fb =
|
|
|
|
crtc->base.primary->state->fb;
|
|
|
|
int cpp;
|
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN2(dev_priv))
|
2012-10-22 11:32:15 +00:00
|
|
|
cpp = 4;
|
2016-10-31 20:37:04 +00:00
|
|
|
else
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = fb->format->cpp[0];
|
2012-10-22 11:32:15 +00:00
|
|
|
|
2013-09-25 15:45:37 +00:00
|
|
|
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
2012-10-22 11:32:15 +00:00
|
|
|
wm_info, fifo_size, cpp,
|
2014-09-03 10:56:07 +00:00
|
|
|
pessimal_latency_ns);
|
2012-04-17 01:20:35 +00:00
|
|
|
enabled = crtc;
|
2014-08-14 22:21:53 +00:00
|
|
|
} else {
|
2012-04-17 01:20:35 +00:00
|
|
|
planea_wm = fifo_size - wm_info->guard_size;
|
2014-08-14 22:21:53 +00:00
|
|
|
if (planea_wm > (long)wm_info->max_wm)
|
|
|
|
planea_wm = wm_info->max_wm;
|
|
|
|
}
|
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN2(dev_priv))
|
2014-08-14 22:21:53 +00:00
|
|
|
wm_info = &i830_bc_wm_info;
|
2012-04-17 01:20:35 +00:00
|
|
|
|
2016-10-31 20:37:17 +00:00
|
|
|
fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
|
2016-10-31 20:37:09 +00:00
|
|
|
crtc = intel_get_crtc_for_plane(dev_priv, 1);
|
2016-10-31 20:37:04 +00:00
|
|
|
if (intel_crtc_active(crtc)) {
|
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&crtc->config->base.adjusted_mode;
|
|
|
|
const struct drm_framebuffer *fb =
|
|
|
|
crtc->base.primary->state->fb;
|
|
|
|
int cpp;
|
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN2(dev_priv))
|
2012-10-22 11:32:15 +00:00
|
|
|
cpp = 4;
|
2016-10-31 20:37:04 +00:00
|
|
|
else
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = fb->format->cpp[0];
|
2012-10-22 11:32:15 +00:00
|
|
|
|
2013-09-25 15:45:37 +00:00
|
|
|
planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
2012-10-22 11:32:15 +00:00
|
|
|
wm_info, fifo_size, cpp,
|
2014-09-03 10:56:07 +00:00
|
|
|
pessimal_latency_ns);
|
2012-04-17 01:20:35 +00:00
|
|
|
if (enabled == NULL)
|
|
|
|
enabled = crtc;
|
|
|
|
else
|
|
|
|
enabled = NULL;
|
2014-08-14 22:21:53 +00:00
|
|
|
} else {
|
2012-04-17 01:20:35 +00:00
|
|
|
planeb_wm = fifo_size - wm_info->guard_size;
|
2014-08-14 22:21:53 +00:00
|
|
|
if (planeb_wm > (long)wm_info->max_wm)
|
|
|
|
planeb_wm = wm_info->max_wm;
|
|
|
|
}
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
|
|
|
|
|
2016-10-13 10:02:58 +00:00
|
|
|
if (IS_I915GM(dev_priv) && enabled) {
|
2014-07-08 14:50:07 +00:00
|
|
|
struct drm_i915_gem_object *obj;
|
2014-04-07 06:54:21 +00:00
|
|
|
|
2016-10-31 20:37:04 +00:00
|
|
|
obj = intel_fb_obj(enabled->base.primary->state->fb);
|
2014-04-07 06:54:21 +00:00
|
|
|
|
|
|
|
/* self-refresh seems busted with untiled */
|
2016-08-05 09:14:23 +00:00
|
|
|
if (!i915_gem_object_is_tiled(obj))
|
2014-04-07 06:54:21 +00:00
|
|
|
enabled = NULL;
|
|
|
|
}
|
|
|
|
|
2012-04-17 01:20:35 +00:00
|
|
|
/*
|
|
|
|
* Overlay gets an aggressive default since video jitter is bad.
|
|
|
|
*/
|
|
|
|
cwm = 2;
|
|
|
|
|
|
|
|
/* Play safe and disable self-refresh before adjusting watermarks. */
|
2014-07-01 09:36:17 +00:00
|
|
|
intel_set_memory_cxsr(dev_priv, false);
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
/* Calc sr entries for one plane configs */
|
2016-10-31 20:37:18 +00:00
|
|
|
if (HAS_FW_BLC(dev_priv) && enabled) {
|
2012-04-17 01:20:35 +00:00
|
|
|
/* self-refresh has much higher latency */
|
|
|
|
static const int sr_latency_ns = 6000;
|
2016-10-31 20:37:04 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&enabled->config->base.adjusted_mode;
|
|
|
|
const struct drm_framebuffer *fb =
|
|
|
|
enabled->base.primary->state->fb;
|
2013-09-25 15:45:37 +00:00
|
|
|
int clock = adjusted_mode->crtc_clock;
|
2013-11-27 19:10:26 +00:00
|
|
|
int htotal = adjusted_mode->crtc_htotal;
|
2016-10-31 20:37:04 +00:00
|
|
|
int hdisplay = enabled->config->pipe_src_w;
|
|
|
|
int cpp;
|
2012-04-17 01:20:35 +00:00
|
|
|
unsigned long line_time_us;
|
|
|
|
int entries;
|
|
|
|
|
2016-10-13 10:02:58 +00:00
|
|
|
if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
|
2016-07-29 14:57:01 +00:00
|
|
|
cpp = 4;
|
2016-10-31 20:37:04 +00:00
|
|
|
else
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = fb->format->cpp[0];
|
2016-07-29 14:57:01 +00:00
|
|
|
|
2014-02-14 12:18:57 +00:00
|
|
|
line_time_us = max(htotal * 1000 / clock, 1);
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
/* Use ns/us then divide to preserve precision */
|
|
|
|
entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp * hdisplay;
|
2012-04-17 01:20:35 +00:00
|
|
|
entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
|
|
|
|
DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
|
|
|
|
srwm = wm_info->fifo_size - entries;
|
|
|
|
if (srwm < 0)
|
|
|
|
srwm = 1;
|
|
|
|
|
2016-10-13 10:02:58 +00:00
|
|
|
if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
|
2012-04-17 01:20:35 +00:00
|
|
|
I915_WRITE(FW_BLC_SELF,
|
|
|
|
FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
|
2016-07-29 14:57:02 +00:00
|
|
|
else
|
2012-04-17 01:20:35 +00:00
|
|
|
I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
|
|
|
|
planea_wm, planeb_wm, cwm, srwm);
|
|
|
|
|
|
|
|
fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
|
|
|
|
fwater_hi = (cwm & 0x1f);
|
|
|
|
|
|
|
|
/* Set request length to 8 cachelines per fetch */
|
|
|
|
fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
|
|
|
|
fwater_hi = fwater_hi | (1 << 8);
|
|
|
|
|
|
|
|
I915_WRITE(FW_BLC, fwater_lo);
|
|
|
|
I915_WRITE(FW_BLC2, fwater_hi);
|
|
|
|
|
2014-07-01 09:36:17 +00:00
|
|
|
if (enabled)
|
|
|
|
intel_set_memory_cxsr(dev_priv, true);
|
2012-04-17 01:20:35 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
static void i845_update_wm(struct intel_crtc *unused_crtc)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-10-31 20:37:21 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
|
2016-10-31 20:37:04 +00:00
|
|
|
struct intel_crtc *crtc;
|
2013-09-25 15:45:37 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode;
|
2012-04-17 01:20:35 +00:00
|
|
|
uint32_t fwater_lo;
|
|
|
|
int planea_wm;
|
|
|
|
|
2016-10-31 20:37:21 +00:00
|
|
|
crtc = single_enabled_crtc(dev_priv);
|
2012-04-17 01:20:35 +00:00
|
|
|
if (crtc == NULL)
|
|
|
|
return;
|
|
|
|
|
2016-10-31 20:37:04 +00:00
|
|
|
adjusted_mode = &crtc->config->base.adjusted_mode;
|
2013-09-25 15:45:37 +00:00
|
|
|
planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
|
2013-12-14 22:38:30 +00:00
|
|
|
&i845_wm_info,
|
2016-10-31 20:37:17 +00:00
|
|
|
dev_priv->display.get_fifo_size(dev_priv, 0),
|
2014-09-03 10:56:07 +00:00
|
|
|
4, pessimal_latency_ns);
|
2012-04-17 01:20:35 +00:00
|
|
|
fwater_lo = I915_READ(FW_BLC) & ~0xfff;
|
|
|
|
fwater_lo |= (3<<8) | planea_wm;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
|
|
|
|
|
|
|
|
I915_WRITE(FW_BLC, fwater_lo);
|
|
|
|
}
|
|
|
|
|
2015-06-03 12:45:11 +00:00
|
|
|
uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
|
2013-05-31 13:08:35 +00:00
|
|
|
{
|
2013-08-27 16:04:17 +00:00
|
|
|
uint32_t pixel_rate;
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2015-06-03 12:45:11 +00:00
|
|
|
pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
|
2013-05-31 13:08:35 +00:00
|
|
|
|
|
|
|
/* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
|
|
|
|
* adjust the pixel_rate here. */
|
|
|
|
|
2015-06-03 12:45:11 +00:00
|
|
|
if (pipe_config->pch_pfit.enabled) {
|
2013-05-31 13:08:35 +00:00
|
|
|
uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
|
2015-06-03 12:45:11 +00:00
|
|
|
uint32_t pfit_size = pipe_config->pch_pfit.size;
|
|
|
|
|
|
|
|
pipe_w = pipe_config->pipe_src_w;
|
|
|
|
pipe_h = pipe_config->pipe_src_h;
|
2013-05-31 13:08:35 +00:00
|
|
|
|
|
|
|
pfit_w = (pfit_size >> 16) & 0xFFFF;
|
|
|
|
pfit_h = pfit_size & 0xFFFF;
|
|
|
|
if (pipe_w < pfit_w)
|
|
|
|
pipe_w = pfit_w;
|
|
|
|
if (pipe_h < pfit_h)
|
|
|
|
pipe_h = pfit_h;
|
|
|
|
|
2015-12-03 19:37:40 +00:00
|
|
|
if (WARN_ON(!pfit_w || !pfit_h))
|
|
|
|
return pixel_rate;
|
|
|
|
|
2013-05-31 13:08:35 +00:00
|
|
|
pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
|
|
|
|
pfit_w * pfit_h);
|
|
|
|
}
|
|
|
|
|
|
|
|
return pixel_rate;
|
|
|
|
}
|
|
|
|
|
2013-08-01 13:18:55 +00:00
|
|
|
/* latency must be in 0.1us units. */
|
2016-01-20 19:05:26 +00:00
|
|
|
static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
|
2013-05-31 13:08:35 +00:00
|
|
|
{
|
|
|
|
uint64_t ret;
|
|
|
|
|
2013-08-01 13:18:53 +00:00
|
|
|
if (WARN(latency == 0, "Latency value missing\n"))
|
|
|
|
return UINT_MAX;
|
|
|
|
|
2016-01-20 19:05:26 +00:00
|
|
|
ret = (uint64_t) pixel_rate * cpp * latency;
|
2013-05-31 13:08:35 +00:00
|
|
|
ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-08-01 13:18:55 +00:00
|
|
|
/* latency must be in 0.1us units. */
|
2013-07-05 08:57:17 +00:00
|
|
|
static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
|
2016-01-20 19:05:26 +00:00
|
|
|
uint32_t horiz_pixels, uint8_t cpp,
|
2013-05-31 13:08:35 +00:00
|
|
|
uint32_t latency)
|
|
|
|
{
|
|
|
|
uint32_t ret;
|
|
|
|
|
2013-08-01 13:18:53 +00:00
|
|
|
if (WARN(latency == 0, "Latency value missing\n"))
|
|
|
|
return UINT_MAX;
|
2015-12-03 19:37:40 +00:00
|
|
|
if (WARN_ON(!pipe_htotal))
|
|
|
|
return UINT_MAX;
|
2013-08-01 13:18:53 +00:00
|
|
|
|
2013-05-31 13:08:35 +00:00
|
|
|
ret = (latency * pixel_rate) / (pipe_htotal * 10000);
|
2016-01-20 19:05:26 +00:00
|
|
|
ret = (ret + 1) * horiz_pixels * cpp;
|
2013-05-31 13:08:35 +00:00
|
|
|
ret = DIV_ROUND_UP(ret, 64) + 2;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-07-05 08:57:17 +00:00
|
|
|
static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
|
2016-01-20 19:05:26 +00:00
|
|
|
uint8_t cpp)
|
2013-05-31 14:45:06 +00:00
|
|
|
{
|
2015-12-03 19:37:40 +00:00
|
|
|
/*
|
|
|
|
* Neither of these should be possible since this function shouldn't be
|
|
|
|
* called if the CRTC is off or the plane is invisible. But let's be
|
|
|
|
* extra paranoid to avoid a potential divide-by-zero if we screw up
|
|
|
|
* elsewhere in the driver.
|
|
|
|
*/
|
2016-01-20 19:05:26 +00:00
|
|
|
if (WARN_ON(!cpp))
|
2015-12-03 19:37:40 +00:00
|
|
|
return 0;
|
|
|
|
if (WARN_ON(!horiz_pixels))
|
|
|
|
return 0;
|
|
|
|
|
2016-01-20 19:05:26 +00:00
|
|
|
return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
|
2013-05-31 14:45:06 +00:00
|
|
|
}
|
|
|
|
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_maximums {
|
2013-05-31 14:45:06 +00:00
|
|
|
uint16_t pri;
|
|
|
|
uint16_t spr;
|
|
|
|
uint16_t cur;
|
|
|
|
uint16_t fbc;
|
|
|
|
};
|
|
|
|
|
2013-08-01 13:18:55 +00:00
|
|
|
/*
|
|
|
|
* For both WM_PIPE and WM_LP.
|
|
|
|
* mem_value must be in 0.1us units.
|
|
|
|
*/
|
2015-09-24 22:53:08 +00:00
|
|
|
static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
|
2015-09-24 22:53:07 +00:00
|
|
|
const struct intel_plane_state *pstate,
|
2013-05-31 14:45:06 +00:00
|
|
|
uint32_t mem_value,
|
|
|
|
bool is_lp)
|
2013-05-31 13:08:35 +00:00
|
|
|
{
|
2013-05-31 14:45:06 +00:00
|
|
|
uint32_t method1, method2;
|
2016-11-18 19:53:00 +00:00
|
|
|
int cpp;
|
2013-05-31 14:45:06 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (!cstate->base.active || !pstate->base.visible)
|
2013-05-31 13:08:35 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = pstate->base.fb->format->cpp[0];
|
2016-11-18 19:53:00 +00:00
|
|
|
|
2016-01-20 19:05:26 +00:00
|
|
|
method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
|
2013-05-31 14:45:06 +00:00
|
|
|
|
|
|
|
if (!is_lp)
|
|
|
|
return method1;
|
|
|
|
|
2015-09-24 22:53:08 +00:00
|
|
|
method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
|
|
|
|
cstate->base.adjusted_mode.crtc_htotal,
|
2016-07-26 16:06:59 +00:00
|
|
|
drm_rect_width(&pstate->base.dst),
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp, mem_value);
|
2013-05-31 14:45:06 +00:00
|
|
|
|
|
|
|
return min(method1, method2);
|
2013-05-31 13:08:35 +00:00
|
|
|
}
|
|
|
|
|
2013-08-01 13:18:55 +00:00
|
|
|
/*
|
|
|
|
* For both WM_PIPE and WM_LP.
|
|
|
|
* mem_value must be in 0.1us units.
|
|
|
|
*/
|
2015-09-24 22:53:08 +00:00
|
|
|
static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
|
2015-09-24 22:53:07 +00:00
|
|
|
const struct intel_plane_state *pstate,
|
2013-05-31 13:08:35 +00:00
|
|
|
uint32_t mem_value)
|
|
|
|
{
|
|
|
|
uint32_t method1, method2;
|
2016-11-18 19:53:00 +00:00
|
|
|
int cpp;
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (!cstate->base.active || !pstate->base.visible)
|
2013-05-31 13:08:35 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = pstate->base.fb->format->cpp[0];
|
2016-11-18 19:53:00 +00:00
|
|
|
|
2016-01-20 19:05:26 +00:00
|
|
|
method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
|
2015-09-24 22:53:08 +00:00
|
|
|
method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
|
|
|
|
cstate->base.adjusted_mode.crtc_htotal,
|
2016-07-26 16:06:59 +00:00
|
|
|
drm_rect_width(&pstate->base.dst),
|
2016-01-20 19:05:26 +00:00
|
|
|
cpp, mem_value);
|
2013-05-31 13:08:35 +00:00
|
|
|
return min(method1, method2);
|
|
|
|
}
|
|
|
|
|
2013-08-01 13:18:55 +00:00
|
|
|
/*
|
|
|
|
* For both WM_PIPE and WM_LP.
|
|
|
|
* mem_value must be in 0.1us units.
|
|
|
|
*/
|
2015-09-24 22:53:08 +00:00
|
|
|
static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
|
2015-09-24 22:53:07 +00:00
|
|
|
const struct intel_plane_state *pstate,
|
2013-05-31 13:08:35 +00:00
|
|
|
uint32_t mem_value)
|
|
|
|
{
|
2016-02-03 06:06:51 +00:00
|
|
|
/*
|
|
|
|
* We treat the cursor plane as always-on for the purposes of watermark
|
|
|
|
* calculation. Until we have two-stage watermark programming merged,
|
|
|
|
* this is necessary to avoid flickering.
|
|
|
|
*/
|
|
|
|
int cpp = 4;
|
2016-07-26 16:06:59 +00:00
|
|
|
int width = pstate->base.visible ? pstate->base.crtc_w : 64;
|
2015-09-24 22:53:07 +00:00
|
|
|
|
2016-02-03 06:06:51 +00:00
|
|
|
if (!cstate->base.active)
|
2013-05-31 13:08:35 +00:00
|
|
|
return 0;
|
|
|
|
|
2015-09-24 22:53:08 +00:00
|
|
|
return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
|
|
|
|
cstate->base.adjusted_mode.crtc_htotal,
|
2016-02-03 06:06:51 +00:00
|
|
|
width, cpp, mem_value);
|
2013-05-31 13:08:35 +00:00
|
|
|
}
|
|
|
|
|
2013-05-31 14:45:06 +00:00
|
|
|
/* Only for WM_LP. */
|
2015-09-24 22:53:08 +00:00
|
|
|
static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
|
2015-09-24 22:53:07 +00:00
|
|
|
const struct intel_plane_state *pstate,
|
2013-07-05 08:57:19 +00:00
|
|
|
uint32_t pri_val)
|
2013-05-31 14:45:06 +00:00
|
|
|
{
|
2016-11-18 19:53:00 +00:00
|
|
|
int cpp;
|
2015-09-24 22:53:07 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (!cstate->base.active || !pstate->base.visible)
|
2013-05-31 14:45:06 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = pstate->base.fb->format->cpp[0];
|
2016-11-18 19:53:00 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
|
2013-05-31 14:45:06 +00:00
|
|
|
}
|
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
static unsigned int
|
|
|
|
ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
|
2013-08-07 10:28:19 +00:00
|
|
|
{
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
2013-11-03 04:07:46 +00:00
|
|
|
return 3072;
|
2016-11-16 08:55:42 +00:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 7)
|
2013-08-07 10:28:19 +00:00
|
|
|
return 768;
|
|
|
|
else
|
|
|
|
return 512;
|
|
|
|
}
|
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
static unsigned int
|
|
|
|
ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
|
|
|
|
int level, bool is_sprite)
|
2014-03-07 16:32:11 +00:00
|
|
|
{
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
2014-03-07 16:32:11 +00:00
|
|
|
/* BDW primary/sprite plane watermarks */
|
|
|
|
return level == 0 ? 255 : 2047;
|
2016-11-16 08:55:42 +00:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 7)
|
2014-03-07 16:32:11 +00:00
|
|
|
/* IVB/HSW primary/sprite plane watermarks */
|
|
|
|
return level == 0 ? 127 : 1023;
|
|
|
|
else if (!is_sprite)
|
|
|
|
/* ILK/SNB primary plane watermarks */
|
|
|
|
return level == 0 ? 127 : 511;
|
|
|
|
else
|
|
|
|
/* ILK/SNB sprite plane watermarks */
|
|
|
|
return level == 0 ? 63 : 255;
|
|
|
|
}
|
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
static unsigned int
|
|
|
|
ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
|
2014-03-07 16:32:11 +00:00
|
|
|
{
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 7)
|
2014-03-07 16:32:11 +00:00
|
|
|
return level == 0 ? 63 : 255;
|
|
|
|
else
|
|
|
|
return level == 0 ? 31 : 63;
|
|
|
|
}
|
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
|
2014-03-07 16:32:11 +00:00
|
|
|
{
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
2014-03-07 16:32:11 +00:00
|
|
|
return 31;
|
|
|
|
else
|
|
|
|
return 15;
|
|
|
|
}
|
|
|
|
|
2013-08-07 10:28:19 +00:00
|
|
|
/* Calculate the maximum primary/sprite plane watermark */
|
|
|
|
static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
|
|
|
|
int level,
|
2013-08-07 10:29:12 +00:00
|
|
|
const struct intel_wm_config *config,
|
2013-08-07 10:28:19 +00:00
|
|
|
enum intel_ddb_partitioning ddb_partitioning,
|
|
|
|
bool is_sprite)
|
|
|
|
{
|
2016-11-16 08:55:42 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
|
2013-08-07 10:28:19 +00:00
|
|
|
|
|
|
|
/* if sprites aren't enabled, sprites get nothing */
|
2013-08-07 10:29:12 +00:00
|
|
|
if (is_sprite && !config->sprites_enabled)
|
2013-08-07 10:28:19 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* HSW allows LP1+ watermarks even with multiple pipes */
|
2013-08-07 10:29:12 +00:00
|
|
|
if (level == 0 || config->num_pipes_active > 1) {
|
2016-11-16 08:55:42 +00:00
|
|
|
fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
|
2013-08-07 10:28:19 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For some reason the non self refresh
|
|
|
|
* FIFO size is only half of the self
|
|
|
|
* refresh FIFO size on ILK/SNB.
|
|
|
|
*/
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) <= 6)
|
2013-08-07 10:28:19 +00:00
|
|
|
fifo_size /= 2;
|
|
|
|
}
|
|
|
|
|
2013-08-07 10:29:12 +00:00
|
|
|
if (config->sprites_enabled) {
|
2013-08-07 10:28:19 +00:00
|
|
|
/* level 0 is always calculated with 1:1 split */
|
|
|
|
if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
|
|
|
|
if (is_sprite)
|
|
|
|
fifo_size *= 5;
|
|
|
|
fifo_size /= 6;
|
|
|
|
} else {
|
|
|
|
fifo_size /= 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clamp to max that the registers can hold */
|
2016-11-16 08:55:42 +00:00
|
|
|
return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
|
2013-08-07 10:28:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Calculate the maximum cursor plane watermark */
|
|
|
|
static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
|
2013-08-07 10:29:12 +00:00
|
|
|
int level,
|
|
|
|
const struct intel_wm_config *config)
|
2013-08-07 10:28:19 +00:00
|
|
|
{
|
|
|
|
/* HSW LP1+ watermarks w/ multiple pipes */
|
2013-08-07 10:29:12 +00:00
|
|
|
if (level > 0 && config->num_pipes_active > 1)
|
2013-08-07 10:28:19 +00:00
|
|
|
return 64;
|
|
|
|
|
|
|
|
/* otherwise just report max that registers can hold */
|
2016-11-16 08:55:42 +00:00
|
|
|
return ilk_cursor_wm_reg_max(to_i915(dev), level);
|
2013-08-07 10:28:19 +00:00
|
|
|
}
|
|
|
|
|
2014-01-06 19:17:23 +00:00
|
|
|
static void ilk_compute_wm_maximums(const struct drm_device *dev,
|
2013-10-09 16:18:09 +00:00
|
|
|
int level,
|
|
|
|
const struct intel_wm_config *config,
|
|
|
|
enum intel_ddb_partitioning ddb_partitioning,
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_maximums *max)
|
2013-08-07 10:28:19 +00:00
|
|
|
{
|
2013-08-07 10:29:12 +00:00
|
|
|
max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
|
|
|
|
max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
|
|
|
|
max->cur = ilk_cursor_wm_max(dev, level, config);
|
2016-11-16 08:55:42 +00:00
|
|
|
max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
|
2013-08-07 10:28:19 +00:00
|
|
|
}
|
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
|
2014-04-28 12:44:56 +00:00
|
|
|
int level,
|
|
|
|
struct ilk_wm_maximums *max)
|
|
|
|
{
|
2016-11-16 08:55:42 +00:00
|
|
|
max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
|
|
|
|
max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
|
|
|
|
max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
|
|
|
|
max->fbc = ilk_fbc_wm_reg_max(dev_priv);
|
2014-04-28 12:44:56 +00:00
|
|
|
}
|
|
|
|
|
2013-10-09 16:18:10 +00:00
|
|
|
static bool ilk_validate_wm_level(int level,
|
2013-12-17 12:46:36 +00:00
|
|
|
const struct ilk_wm_maximums *max,
|
2013-10-09 16:18:10 +00:00
|
|
|
struct intel_wm_level *result)
|
2013-08-07 10:24:47 +00:00
|
|
|
{
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
/* already determined to be invalid? */
|
|
|
|
if (!result->enable)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
result->enable = result->pri_val <= max->pri &&
|
|
|
|
result->spr_val <= max->spr &&
|
|
|
|
result->cur_val <= max->cur;
|
|
|
|
|
|
|
|
ret = result->enable;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* HACK until we can pre-compute everything,
|
|
|
|
* and thus fail gracefully if LP0 watermarks
|
|
|
|
* are exceeded...
|
|
|
|
*/
|
|
|
|
if (level == 0 && !result->enable) {
|
|
|
|
if (result->pri_val > max->pri)
|
|
|
|
DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
|
|
|
|
level, result->pri_val, max->pri);
|
|
|
|
if (result->spr_val > max->spr)
|
|
|
|
DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
|
|
|
|
level, result->spr_val, max->spr);
|
|
|
|
if (result->cur_val > max->cur)
|
|
|
|
DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
|
|
|
|
level, result->cur_val, max->cur);
|
|
|
|
|
|
|
|
result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
|
|
|
|
result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
|
|
|
|
result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
|
|
|
|
result->enable = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-01-06 19:17:23 +00:00
|
|
|
static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
|
2015-09-24 22:53:07 +00:00
|
|
|
const struct intel_crtc *intel_crtc,
|
2013-08-06 19:24:02 +00:00
|
|
|
int level,
|
2015-09-24 22:53:08 +00:00
|
|
|
struct intel_crtc_state *cstate,
|
2015-09-24 22:53:16 +00:00
|
|
|
struct intel_plane_state *pristate,
|
|
|
|
struct intel_plane_state *sprstate,
|
|
|
|
struct intel_plane_state *curstate,
|
2013-08-06 19:24:05 +00:00
|
|
|
struct intel_wm_level *result)
|
2013-08-06 19:24:02 +00:00
|
|
|
{
|
|
|
|
uint16_t pri_latency = dev_priv->wm.pri_latency[level];
|
|
|
|
uint16_t spr_latency = dev_priv->wm.spr_latency[level];
|
|
|
|
uint16_t cur_latency = dev_priv->wm.cur_latency[level];
|
|
|
|
|
|
|
|
/* WM1+ latency values stored in 0.5us units */
|
|
|
|
if (level > 0) {
|
|
|
|
pri_latency *= 5;
|
|
|
|
spr_latency *= 5;
|
|
|
|
cur_latency *= 5;
|
|
|
|
}
|
|
|
|
|
2016-03-01 10:07:22 +00:00
|
|
|
if (pristate) {
|
|
|
|
result->pri_val = ilk_compute_pri_wm(cstate, pristate,
|
|
|
|
pri_latency, level);
|
|
|
|
result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sprstate)
|
|
|
|
result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
|
|
|
|
|
|
|
|
if (curstate)
|
|
|
|
result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
|
|
|
|
|
2013-08-06 19:24:02 +00:00
|
|
|
result->enable = true;
|
|
|
|
}
|
|
|
|
|
2013-05-31 13:08:35 +00:00
|
|
|
static uint32_t
|
2016-04-29 14:31:17 +00:00
|
|
|
hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
|
2012-05-09 18:37:24 +00:00
|
|
|
{
|
2016-04-29 14:31:17 +00:00
|
|
|
const struct intel_atomic_state *intel_state =
|
|
|
|
to_intel_atomic_state(cstate->base.state);
|
2015-12-03 19:37:39 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode =
|
|
|
|
&cstate->base.adjusted_mode;
|
2013-05-03 20:23:43 +00:00
|
|
|
u32 linetime, ips_linetime;
|
2012-05-09 18:37:24 +00:00
|
|
|
|
2015-12-03 19:37:39 +00:00
|
|
|
if (!cstate->base.active)
|
|
|
|
return 0;
|
|
|
|
if (WARN_ON(adjusted_mode->crtc_clock == 0))
|
|
|
|
return 0;
|
2016-04-29 14:31:17 +00:00
|
|
|
if (WARN_ON(intel_state->cdclk == 0))
|
2013-05-31 13:08:35 +00:00
|
|
|
return 0;
|
2013-05-09 19:55:50 +00:00
|
|
|
|
2012-05-09 18:37:24 +00:00
|
|
|
/* The WM are computed with base on how long it takes to fill a single
|
|
|
|
* row at the given clock rate, multiplied by 8.
|
|
|
|
* */
|
2015-09-08 10:40:45 +00:00
|
|
|
linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
|
|
|
|
adjusted_mode->crtc_clock);
|
|
|
|
ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
|
2016-04-29 14:31:17 +00:00
|
|
|
intel_state->cdclk);
|
2012-05-09 18:37:24 +00:00
|
|
|
|
2013-05-31 13:08:35 +00:00
|
|
|
return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
|
|
|
|
PIPE_WM_LINETIME_TIME(linetime);
|
2012-05-09 18:37:24 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:24 +00:00
|
|
|
static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
|
|
|
|
uint16_t wm[8])
|
2013-07-05 08:57:21 +00:00
|
|
|
{
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN9(dev_priv)) {
|
2014-11-04 17:06:38 +00:00
|
|
|
uint32_t val;
|
2014-11-04 17:06:47 +00:00
|
|
|
int ret, i;
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
2014-11-04 17:06:38 +00:00
|
|
|
|
|
|
|
/* read the first set of memory latencies[0:3] */
|
|
|
|
val = 0; /* data0 to be programmed to 0 for first set */
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
ret = sandybridge_pcode_read(dev_priv,
|
|
|
|
GEN9_PCODE_READ_MEM_LATENCY,
|
|
|
|
&val);
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("SKL Mailbox read error = %d\n", ret);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
|
|
|
|
GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
|
|
|
|
GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
|
|
|
|
GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
|
|
|
|
/* read the second set of memory latencies[4:7] */
|
|
|
|
val = 1; /* data0 to be programmed to 1 for second set */
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
ret = sandybridge_pcode_read(dev_priv,
|
|
|
|
GEN9_PCODE_READ_MEM_LATENCY,
|
|
|
|
&val);
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
if (ret) {
|
|
|
|
DRM_ERROR("SKL Mailbox read error = %d\n", ret);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
|
|
|
|
GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
|
|
|
|
GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
|
|
|
|
GEN9_MEM_LATENCY_LEVEL_MASK;
|
|
|
|
|
2016-09-22 21:00:30 +00:00
|
|
|
/*
|
|
|
|
* If a level n (n > 1) has a 0us latency, all levels m (m >= n)
|
|
|
|
* need to be disabled. We make sure to sanitize the values out
|
|
|
|
* of the punit to satisfy this requirement.
|
|
|
|
*/
|
|
|
|
for (level = 1; level <= max_level; level++) {
|
|
|
|
if (wm[level] == 0) {
|
|
|
|
for (i = level + 1; i <= max_level; i++)
|
|
|
|
wm[i] = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:46 +00:00
|
|
|
/*
|
2017-01-26 09:16:58 +00:00
|
|
|
* WaWmMemoryReadLatency:skl,glk
|
2015-02-09 19:33:07 +00:00
|
|
|
*
|
2014-11-04 17:06:46 +00:00
|
|
|
* punit doesn't take into account the read latency so we need
|
2016-09-22 21:00:30 +00:00
|
|
|
* to add 2us to the various latency levels we retrieve from the
|
|
|
|
* punit when level 0 response data us 0us.
|
2014-11-04 17:06:46 +00:00
|
|
|
*/
|
2016-09-22 21:00:30 +00:00
|
|
|
if (wm[0] == 0) {
|
|
|
|
wm[0] += 2;
|
|
|
|
for (level = 1; level <= max_level; level++) {
|
|
|
|
if (wm[level] == 0)
|
|
|
|
break;
|
2014-11-04 17:06:46 +00:00
|
|
|
wm[level] += 2;
|
2014-11-04 17:06:47 +00:00
|
|
|
}
|
2016-09-22 21:00:30 +00:00
|
|
|
}
|
|
|
|
|
2016-10-13 10:03:00 +00:00
|
|
|
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
|
2013-07-05 08:57:21 +00:00
|
|
|
uint64_t sskpd = I915_READ64(MCH_SSKPD);
|
|
|
|
|
|
|
|
wm[0] = (sskpd >> 56) & 0xFF;
|
|
|
|
if (wm[0] == 0)
|
|
|
|
wm[0] = sskpd & 0xF;
|
2013-07-05 08:57:22 +00:00
|
|
|
wm[1] = (sskpd >> 4) & 0xFF;
|
|
|
|
wm[2] = (sskpd >> 12) & 0xFF;
|
|
|
|
wm[3] = (sskpd >> 20) & 0x1FF;
|
|
|
|
wm[4] = (sskpd >> 32) & 0x1FF;
|
2016-10-31 20:37:24 +00:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
2013-07-05 08:57:23 +00:00
|
|
|
uint32_t sskpd = I915_READ(MCH_SSKPD);
|
|
|
|
|
|
|
|
wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
|
|
|
|
wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
|
|
|
|
wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
|
|
|
|
wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
|
2016-10-31 20:37:24 +00:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 5) {
|
2013-08-01 13:18:49 +00:00
|
|
|
uint32_t mltr = I915_READ(MLTR_ILK);
|
|
|
|
|
|
|
|
/* ILK primary LP0 latency is 700 ns */
|
|
|
|
wm[0] = 7;
|
|
|
|
wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
|
|
|
|
wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
|
2013-07-05 08:57:21 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
|
|
|
|
uint16_t wm[5])
|
2013-08-01 13:18:50 +00:00
|
|
|
{
|
|
|
|
/* ILK sprite LP0 latency is 1300 ns */
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN5(dev_priv))
|
2013-08-01 13:18:50 +00:00
|
|
|
wm[0] = 13;
|
|
|
|
}
|
|
|
|
|
2016-10-14 09:13:06 +00:00
|
|
|
static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
|
|
|
|
uint16_t wm[5])
|
2013-08-01 13:18:50 +00:00
|
|
|
{
|
|
|
|
/* ILK cursor LP0 latency is 1300 ns */
|
2016-10-14 09:13:06 +00:00
|
|
|
if (IS_GEN5(dev_priv))
|
2013-08-01 13:18:50 +00:00
|
|
|
wm[0] = 13;
|
|
|
|
|
|
|
|
/* WaDoubleCursorLP3Latency:ivb */
|
2016-10-14 09:13:06 +00:00
|
|
|
if (IS_IVYBRIDGE(dev_priv))
|
2013-08-01 13:18:50 +00:00
|
|
|
wm[3] *= 2;
|
|
|
|
}
|
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
|
2013-08-01 13:18:52 +00:00
|
|
|
{
|
|
|
|
/* how many WM levels are we expecting */
|
2016-10-13 10:03:00 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 9)
|
2014-11-04 17:06:38 +00:00
|
|
|
return 7;
|
2016-10-13 10:03:00 +00:00
|
|
|
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
2013-08-30 11:30:25 +00:00
|
|
|
return 4;
|
2016-10-13 10:03:00 +00:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 6)
|
2013-08-30 11:30:25 +00:00
|
|
|
return 3;
|
2013-08-01 13:18:52 +00:00
|
|
|
else
|
2013-08-30 11:30:25 +00:00
|
|
|
return 2;
|
|
|
|
}
|
2014-09-29 13:07:19 +00:00
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
|
2013-08-30 11:30:25 +00:00
|
|
|
const char *name,
|
2014-11-04 17:06:38 +00:00
|
|
|
const uint16_t wm[8])
|
2013-08-30 11:30:25 +00:00
|
|
|
{
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
2013-08-01 13:18:52 +00:00
|
|
|
|
|
|
|
for (level = 0; level <= max_level; level++) {
|
|
|
|
unsigned int latency = wm[level];
|
|
|
|
|
|
|
|
if (latency == 0) {
|
|
|
|
DRM_ERROR("%s WM%d latency not provided\n",
|
|
|
|
name, level);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:38 +00:00
|
|
|
/*
|
|
|
|
* - latencies are in us on gen9.
|
|
|
|
* - before then, WM1+ latency values are in 0.5us units
|
|
|
|
*/
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN9(dev_priv))
|
2014-11-04 17:06:38 +00:00
|
|
|
latency *= 10;
|
|
|
|
else if (level > 0)
|
2013-08-01 13:18:52 +00:00
|
|
|
latency *= 5;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
|
|
|
|
name, level, wm[level],
|
|
|
|
latency / 10, latency % 10);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-08 12:09:19 +00:00
|
|
|
static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
|
|
|
|
uint16_t wm[5], uint16_t min)
|
|
|
|
{
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
2014-05-08 12:09:19 +00:00
|
|
|
|
|
|
|
if (wm[0] >= min)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
wm[0] = max(wm[0], min);
|
|
|
|
for (level = 1; level <= max_level; level++)
|
|
|
|
wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:24 +00:00
|
|
|
static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
|
2014-05-08 12:09:19 +00:00
|
|
|
{
|
|
|
|
bool changed;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The BIOS provided WM memory latency values are often
|
|
|
|
* inadequate for high resolution displays. Adjust them.
|
|
|
|
*/
|
|
|
|
changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
|
|
|
|
ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
|
|
|
|
ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
|
|
|
|
|
|
|
|
if (!changed)
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
|
2016-10-13 10:03:10 +00:00
|
|
|
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
|
|
|
|
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
|
|
|
|
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
|
2014-05-08 12:09:19 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:24 +00:00
|
|
|
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
|
2013-08-01 13:18:50 +00:00
|
|
|
{
|
2016-10-31 20:37:24 +00:00
|
|
|
intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
|
2013-08-01 13:18:50 +00:00
|
|
|
|
|
|
|
memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
|
|
|
|
sizeof(dev_priv->wm.pri_latency));
|
|
|
|
memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
|
|
|
|
sizeof(dev_priv->wm.pri_latency));
|
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
|
2016-10-14 09:13:06 +00:00
|
|
|
intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
|
2013-08-01 13:18:52 +00:00
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
|
|
|
|
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
|
|
|
|
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
|
2014-05-08 12:09:19 +00:00
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN6(dev_priv))
|
2016-10-31 20:37:24 +00:00
|
|
|
snb_wm_latency_quirk(dev_priv);
|
2013-08-01 13:18:50 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:24 +00:00
|
|
|
static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
|
2014-11-04 17:06:38 +00:00
|
|
|
{
|
2016-10-31 20:37:24 +00:00
|
|
|
intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
|
2016-10-13 10:03:10 +00:00
|
|
|
intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
|
2014-11-04 17:06:38 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
static bool ilk_validate_pipe_wm(struct drm_device *dev,
|
|
|
|
struct intel_pipe_wm *pipe_wm)
|
|
|
|
{
|
|
|
|
/* LP0 watermark maximums depend on this pipe alone */
|
|
|
|
const struct intel_wm_config config = {
|
|
|
|
.num_pipes_active = 1,
|
|
|
|
.sprites_enabled = pipe_wm->sprites_enabled,
|
|
|
|
.sprites_scaled = pipe_wm->sprites_scaled,
|
|
|
|
};
|
|
|
|
struct ilk_wm_maximums max;
|
|
|
|
|
|
|
|
/* LP0 watermarks always use 1/2 DDB partitioning */
|
|
|
|
ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
|
|
|
|
|
|
|
|
/* At least LP0 must be valid */
|
|
|
|
if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
|
|
|
|
DRM_DEBUG_KMS("LP0 watermark invalid\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-10-09 16:17:55 +00:00
|
|
|
/* Compute new watermarks for the pipe */
|
2016-03-01 10:07:22 +00:00
|
|
|
static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
|
2013-10-09 16:17:55 +00:00
|
|
|
{
|
2016-03-01 10:07:22 +00:00
|
|
|
struct drm_atomic_state *state = cstate->base.state;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
|
2015-09-24 22:53:16 +00:00
|
|
|
struct intel_pipe_wm *pipe_wm;
|
2016-03-01 10:07:22 +00:00
|
|
|
struct drm_device *dev = state->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
const struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-09-24 22:53:07 +00:00
|
|
|
struct intel_plane *intel_plane;
|
2015-09-24 22:53:16 +00:00
|
|
|
struct intel_plane_state *pristate = NULL;
|
2015-09-24 22:53:07 +00:00
|
|
|
struct intel_plane_state *sprstate = NULL;
|
2015-09-24 22:53:16 +00:00
|
|
|
struct intel_plane_state *curstate = NULL;
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_maximums max;
|
2013-10-09 16:17:55 +00:00
|
|
|
|
2016-05-12 14:05:55 +00:00
|
|
|
pipe_wm = &cstate->wm.ilk.optimal;
|
2015-09-24 22:53:16 +00:00
|
|
|
|
2015-09-24 22:53:07 +00:00
|
|
|
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
|
2016-03-01 10:07:22 +00:00
|
|
|
struct intel_plane_state *ps;
|
|
|
|
|
|
|
|
ps = intel_atomic_get_existing_plane_state(state,
|
|
|
|
intel_plane);
|
|
|
|
if (!ps)
|
|
|
|
continue;
|
2015-09-24 22:53:16 +00:00
|
|
|
|
|
|
|
if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
|
2016-03-01 10:07:22 +00:00
|
|
|
pristate = ps;
|
2015-09-24 22:53:16 +00:00
|
|
|
else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
|
2016-03-01 10:07:22 +00:00
|
|
|
sprstate = ps;
|
2015-09-24 22:53:16 +00:00
|
|
|
else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
|
2016-03-01 10:07:22 +00:00
|
|
|
curstate = ps;
|
2015-09-24 22:53:07 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
pipe_wm->pipe_enabled = cstate->base.active;
|
2016-03-01 10:07:22 +00:00
|
|
|
if (sprstate) {
|
2016-07-26 16:06:59 +00:00
|
|
|
pipe_wm->sprites_enabled = sprstate->base.visible;
|
|
|
|
pipe_wm->sprites_scaled = sprstate->base.visible &&
|
|
|
|
(drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
|
|
|
|
drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
|
2016-03-01 10:07:22 +00:00
|
|
|
}
|
|
|
|
|
2016-03-02 11:38:06 +00:00
|
|
|
usable_level = max_level;
|
|
|
|
|
2013-12-05 13:51:30 +00:00
|
|
|
/* ILK/SNB: LP2+ watermarks only w/o sprites */
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
|
2016-03-02 11:38:06 +00:00
|
|
|
usable_level = 1;
|
2013-12-05 13:51:30 +00:00
|
|
|
|
|
|
|
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
if (pipe_wm->sprites_scaled)
|
2016-03-02 11:38:06 +00:00
|
|
|
usable_level = 0;
|
2013-12-05 13:51:30 +00:00
|
|
|
|
2015-09-24 22:53:16 +00:00
|
|
|
ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
|
2016-03-08 09:57:16 +00:00
|
|
|
pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
|
|
|
|
|
|
|
|
memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
|
|
|
|
pipe_wm->wm[0] = pipe_wm->raw_wm[0];
|
2013-10-09 16:17:55 +00:00
|
|
|
|
2016-10-13 10:03:00 +00:00
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
2016-04-29 14:31:17 +00:00
|
|
|
pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
|
2013-10-09 16:17:55 +00:00
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
if (!ilk_validate_pipe_wm(dev, pipe_wm))
|
2016-03-02 11:36:03 +00:00
|
|
|
return -EINVAL;
|
2014-04-28 12:44:56 +00:00
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
|
2014-04-28 12:44:56 +00:00
|
|
|
|
|
|
|
for (level = 1; level <= max_level; level++) {
|
2016-03-08 09:57:16 +00:00
|
|
|
struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
|
2014-04-28 12:44:56 +00:00
|
|
|
|
2015-09-24 22:53:16 +00:00
|
|
|
ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
|
2016-03-02 11:38:06 +00:00
|
|
|
pristate, sprstate, curstate, wm);
|
2014-04-28 12:44:56 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable any watermark level that exceeds the
|
|
|
|
* register maximums since such watermarks are
|
|
|
|
* always invalid.
|
|
|
|
*/
|
2016-03-08 09:57:16 +00:00
|
|
|
if (level > usable_level)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (ilk_validate_wm_level(level, &max, wm))
|
|
|
|
pipe_wm->wm[level] = *wm;
|
|
|
|
else
|
2016-03-02 11:38:06 +00:00
|
|
|
usable_level = level;
|
2014-04-28 12:44:56 +00:00
|
|
|
}
|
|
|
|
|
2015-09-24 22:53:16 +00:00
|
|
|
return 0;
|
2013-10-09 16:17:55 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
/*
|
|
|
|
* Build a set of 'intermediate' watermark values that satisfy both the old
|
|
|
|
* state and the new state. These can be programmed to the hardware
|
|
|
|
* immediately.
|
|
|
|
*/
|
|
|
|
static int ilk_compute_intermediate_wm(struct drm_device *dev,
|
|
|
|
struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *newstate)
|
|
|
|
{
|
2016-05-12 14:05:55 +00:00
|
|
|
struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(to_i915(dev));
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Start with the final, target watermarks, then combine with the
|
|
|
|
* currently active watermarks to get values that are safe both before
|
|
|
|
* and after the vblank.
|
|
|
|
*/
|
2016-05-12 14:05:55 +00:00
|
|
|
*a = newstate->wm.ilk.optimal;
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
a->pipe_enabled |= b->pipe_enabled;
|
|
|
|
a->sprites_enabled |= b->sprites_enabled;
|
|
|
|
a->sprites_scaled |= b->sprites_scaled;
|
|
|
|
|
|
|
|
for (level = 0; level <= max_level; level++) {
|
|
|
|
struct intel_wm_level *a_wm = &a->wm[level];
|
|
|
|
const struct intel_wm_level *b_wm = &b->wm[level];
|
|
|
|
|
|
|
|
a_wm->enable &= b_wm->enable;
|
|
|
|
a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
|
|
|
|
a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
|
|
|
|
a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
|
|
|
|
a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to make sure that these merged watermark values are
|
|
|
|
* actually a valid configuration themselves. If they're not,
|
|
|
|
* there's no safe way to transition from the old state to
|
|
|
|
* the new state, so we need to fail the atomic transaction.
|
|
|
|
*/
|
|
|
|
if (!ilk_validate_pipe_wm(dev, a))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If our intermediate WM are identical to the final WM, then we can
|
|
|
|
* omit the post-vblank programming; only update if it's different.
|
|
|
|
*/
|
2016-05-12 14:05:55 +00:00
|
|
|
if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
newstate->wm.need_postvbl_update = false;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-09 16:17:55 +00:00
|
|
|
/*
|
|
|
|
* Merge the watermarks from all active pipes for a specific level.
|
|
|
|
*/
|
|
|
|
static void ilk_merge_wm_level(struct drm_device *dev,
|
|
|
|
int level,
|
|
|
|
struct intel_wm_level *ret_wm)
|
|
|
|
{
|
|
|
|
const struct intel_crtc *intel_crtc;
|
|
|
|
|
2014-04-28 12:44:57 +00:00
|
|
|
ret_wm->enable = true;
|
|
|
|
|
2014-05-13 22:32:22 +00:00
|
|
|
for_each_intel_crtc(dev, intel_crtc) {
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
|
2014-03-07 16:32:10 +00:00
|
|
|
const struct intel_wm_level *wm = &active->wm[level];
|
|
|
|
|
|
|
|
if (!active->pipe_enabled)
|
|
|
|
continue;
|
2013-10-09 16:17:55 +00:00
|
|
|
|
2014-04-28 12:44:57 +00:00
|
|
|
/*
|
|
|
|
* The watermark values may have been used in the past,
|
|
|
|
* so we must maintain them in the registers for some
|
|
|
|
* time even if the level is now disabled.
|
|
|
|
*/
|
2013-10-09 16:17:55 +00:00
|
|
|
if (!wm->enable)
|
2014-04-28 12:44:57 +00:00
|
|
|
ret_wm->enable = false;
|
2013-10-09 16:17:55 +00:00
|
|
|
|
|
|
|
ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
|
|
|
|
ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
|
|
|
|
ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
|
|
|
|
ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Merge all low power watermarks for all active pipes.
|
|
|
|
*/
|
|
|
|
static void ilk_wm_merge(struct drm_device *dev,
|
2013-12-05 13:51:34 +00:00
|
|
|
const struct intel_wm_config *config,
|
2013-12-17 12:46:36 +00:00
|
|
|
const struct ilk_wm_maximums *max,
|
2013-10-09 16:17:55 +00:00
|
|
|
struct intel_pipe_wm *merged)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
2014-04-28 12:44:57 +00:00
|
|
|
int last_enabled_level = max_level;
|
2013-10-09 16:17:55 +00:00
|
|
|
|
2013-12-05 13:51:34 +00:00
|
|
|
/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
|
2016-10-14 09:13:06 +00:00
|
|
|
if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
|
2013-12-05 13:51:34 +00:00
|
|
|
config->num_pipes_active > 1)
|
2016-04-01 18:53:18 +00:00
|
|
|
last_enabled_level = 0;
|
2013-12-05 13:51:34 +00:00
|
|
|
|
2013-12-05 13:51:35 +00:00
|
|
|
/* ILK: FBC WM must be disabled always */
|
2016-11-16 08:55:42 +00:00
|
|
|
merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
|
2013-10-09 16:17:55 +00:00
|
|
|
|
|
|
|
/* merge each WM1+ level */
|
|
|
|
for (level = 1; level <= max_level; level++) {
|
|
|
|
struct intel_wm_level *wm = &merged->wm[level];
|
|
|
|
|
|
|
|
ilk_merge_wm_level(dev, level, wm);
|
|
|
|
|
2014-04-28 12:44:57 +00:00
|
|
|
if (level > last_enabled_level)
|
|
|
|
wm->enable = false;
|
|
|
|
else if (!ilk_validate_wm_level(level, max, wm))
|
|
|
|
/* make sure all following levels get disabled */
|
|
|
|
last_enabled_level = level - 1;
|
2013-10-09 16:17:55 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The spec says it is preferred to disable
|
|
|
|
* FBC WMs instead of disabling a WM level.
|
|
|
|
*/
|
|
|
|
if (wm->fbc_val > max->fbc) {
|
2014-04-28 12:44:57 +00:00
|
|
|
if (wm->enable)
|
|
|
|
merged->fbc_wm_enabled = false;
|
2013-10-09 16:17:55 +00:00
|
|
|
wm->fbc_val = 0;
|
|
|
|
}
|
|
|
|
}
|
2013-12-05 13:51:35 +00:00
|
|
|
|
|
|
|
/* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
|
|
|
|
/*
|
|
|
|
* FIXME this is racy. FBC might get enabled later.
|
|
|
|
* What we should check here is whether FBC can be
|
|
|
|
* enabled sometime later.
|
|
|
|
*/
|
2016-10-13 10:03:10 +00:00
|
|
|
if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
|
2015-10-14 20:45:36 +00:00
|
|
|
intel_fbc_is_active(dev_priv)) {
|
2013-12-05 13:51:35 +00:00
|
|
|
for (level = 2; level <= max_level; level++) {
|
|
|
|
struct intel_wm_level *wm = &merged->wm[level];
|
|
|
|
|
|
|
|
wm->enable = false;
|
|
|
|
}
|
|
|
|
}
|
2013-10-09 16:17:55 +00:00
|
|
|
}
|
|
|
|
|
2013-10-09 16:18:01 +00:00
|
|
|
static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
|
|
|
|
{
|
|
|
|
/* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
|
|
|
|
return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
|
|
|
|
}
|
|
|
|
|
2013-12-05 13:51:29 +00:00
|
|
|
/* The value we need to program into the WM_LPx latency field */
|
|
|
|
static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2013-12-05 13:51:29 +00:00
|
|
|
|
2016-10-13 10:03:00 +00:00
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
2013-12-05 13:51:29 +00:00
|
|
|
return 2 * level;
|
|
|
|
else
|
|
|
|
return dev_priv->wm.pri_latency[level];
|
|
|
|
}
|
|
|
|
|
2013-12-17 12:46:36 +00:00
|
|
|
static void ilk_compute_wm_results(struct drm_device *dev,
|
2013-10-09 16:17:57 +00:00
|
|
|
const struct intel_pipe_wm *merged,
|
2013-10-09 16:18:03 +00:00
|
|
|
enum intel_ddb_partitioning partitioning,
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_values *results)
|
2013-05-31 13:08:35 +00:00
|
|
|
{
|
2016-11-16 08:55:42 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2013-10-09 16:17:55 +00:00
|
|
|
struct intel_crtc *intel_crtc;
|
|
|
|
int level, wm_lp;
|
2013-05-31 14:45:06 +00:00
|
|
|
|
2013-10-09 16:17:57 +00:00
|
|
|
results->enable_fbc_wm = merged->fbc_wm_enabled;
|
2013-10-09 16:18:03 +00:00
|
|
|
results->partitioning = partitioning;
|
2013-05-31 14:45:06 +00:00
|
|
|
|
2013-10-09 16:17:55 +00:00
|
|
|
/* LP1+ register values */
|
2013-05-31 14:45:06 +00:00
|
|
|
for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
|
2013-08-06 19:24:05 +00:00
|
|
|
const struct intel_wm_level *r;
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2013-10-09 16:18:01 +00:00
|
|
|
level = ilk_wm_lp_to_level(wm_lp, merged);
|
2013-10-09 16:17:55 +00:00
|
|
|
|
2013-10-09 16:17:57 +00:00
|
|
|
r = &merged->wm[level];
|
2013-05-31 14:45:06 +00:00
|
|
|
|
2014-04-28 12:44:57 +00:00
|
|
|
/*
|
|
|
|
* Maintain the watermark values even if the level is
|
|
|
|
* disabled. Doing otherwise could cause underruns.
|
|
|
|
*/
|
|
|
|
results->wm_lp[wm_lp - 1] =
|
2013-12-05 13:51:29 +00:00
|
|
|
(ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
|
2013-11-03 04:07:46 +00:00
|
|
|
(r->pri_val << WM1_LP_SR_SHIFT) |
|
|
|
|
r->cur_val;
|
|
|
|
|
2014-04-28 12:44:57 +00:00
|
|
|
if (r->enable)
|
|
|
|
results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
|
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
2013-11-03 04:07:46 +00:00
|
|
|
results->wm_lp[wm_lp - 1] |=
|
|
|
|
r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
|
|
|
|
else
|
|
|
|
results->wm_lp[wm_lp - 1] |=
|
|
|
|
r->fbc_val << WM1_LP_FBC_SHIFT;
|
|
|
|
|
2014-04-28 12:44:57 +00:00
|
|
|
/*
|
|
|
|
* Always set WM1S_LP_EN when spr_val != 0, even if the
|
|
|
|
* level is disabled. Doing otherwise could cause underruns.
|
|
|
|
*/
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
|
2013-12-05 13:51:32 +00:00
|
|
|
WARN_ON(wm_lp != 1);
|
|
|
|
results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
|
|
|
|
} else
|
|
|
|
results->wm_lp_spr[wm_lp - 1] = r->spr_val;
|
2013-05-31 14:45:06 +00:00
|
|
|
}
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2013-10-09 16:17:55 +00:00
|
|
|
/* LP0 register values */
|
2014-05-13 22:32:22 +00:00
|
|
|
for_each_intel_crtc(dev, intel_crtc) {
|
2013-10-09 16:17:55 +00:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
const struct intel_wm_level *r =
|
|
|
|
&intel_crtc->wm.active.ilk.wm[0];
|
2013-10-09 16:17:55 +00:00
|
|
|
|
|
|
|
if (WARN_ON(!r->enable))
|
|
|
|
continue;
|
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
|
2013-05-09 19:55:50 +00:00
|
|
|
|
2013-10-09 16:17:55 +00:00
|
|
|
results->wm_pipe[pipe] =
|
|
|
|
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
|
|
|
|
(r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
|
|
|
|
r->cur_val;
|
2013-05-31 13:08:35 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-05-31 13:19:21 +00:00
|
|
|
/* Find the result with the highest level enabled. Check for enable_fbc_wm in
|
|
|
|
* case both are at the same level. Prefer r1 in case they're the same. */
|
2013-12-17 12:46:36 +00:00
|
|
|
static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
|
2013-10-09 16:17:58 +00:00
|
|
|
struct intel_pipe_wm *r1,
|
|
|
|
struct intel_pipe_wm *r2)
|
2013-05-31 13:19:21 +00:00
|
|
|
{
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(to_i915(dev));
|
2013-10-09 16:17:58 +00:00
|
|
|
int level1 = 0, level2 = 0;
|
2013-05-31 13:19:21 +00:00
|
|
|
|
2013-10-09 16:17:58 +00:00
|
|
|
for (level = 1; level <= max_level; level++) {
|
|
|
|
if (r1->wm[level].enable)
|
|
|
|
level1 = level;
|
|
|
|
if (r2->wm[level].enable)
|
|
|
|
level2 = level;
|
2013-05-31 13:19:21 +00:00
|
|
|
}
|
|
|
|
|
2013-10-09 16:17:58 +00:00
|
|
|
if (level1 == level2) {
|
|
|
|
if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
|
2013-05-31 13:19:21 +00:00
|
|
|
return r2;
|
|
|
|
else
|
|
|
|
return r1;
|
2013-10-09 16:17:58 +00:00
|
|
|
} else if (level1 > level2) {
|
2013-05-31 13:19:21 +00:00
|
|
|
return r1;
|
|
|
|
} else {
|
|
|
|
return r2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-10-11 16:39:52 +00:00
|
|
|
/* dirty bits used to track which watermarks need changes */
|
|
|
|
#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
|
|
|
|
#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
|
|
|
|
#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
|
|
|
|
#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
|
|
|
|
#define WM_DIRTY_FBC (1 << 24)
|
|
|
|
#define WM_DIRTY_DDB (1 << 25)
|
|
|
|
|
2014-08-18 12:49:10 +00:00
|
|
|
static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
|
2013-12-17 12:46:36 +00:00
|
|
|
const struct ilk_wm_values *old,
|
|
|
|
const struct ilk_wm_values *new)
|
2013-10-11 16:39:52 +00:00
|
|
|
{
|
|
|
|
unsigned int dirty = 0;
|
|
|
|
enum pipe pipe;
|
|
|
|
int wm_lp;
|
|
|
|
|
2014-08-18 12:49:10 +00:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2013-10-11 16:39:52 +00:00
|
|
|
if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
|
|
|
|
dirty |= WM_DIRTY_LINETIME(pipe);
|
|
|
|
/* Must disable LP1+ watermarks too */
|
|
|
|
dirty |= WM_DIRTY_LP_ALL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
|
|
|
|
dirty |= WM_DIRTY_PIPE(pipe);
|
|
|
|
/* Must disable LP1+ watermarks too */
|
|
|
|
dirty |= WM_DIRTY_LP_ALL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (old->enable_fbc_wm != new->enable_fbc_wm) {
|
|
|
|
dirty |= WM_DIRTY_FBC;
|
|
|
|
/* Must disable LP1+ watermarks too */
|
|
|
|
dirty |= WM_DIRTY_LP_ALL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (old->partitioning != new->partitioning) {
|
|
|
|
dirty |= WM_DIRTY_DDB;
|
|
|
|
/* Must disable LP1+ watermarks too */
|
|
|
|
dirty |= WM_DIRTY_LP_ALL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* LP1+ watermarks already deemed dirty, no need to continue */
|
|
|
|
if (dirty & WM_DIRTY_LP_ALL)
|
|
|
|
return dirty;
|
|
|
|
|
|
|
|
/* Find the lowest numbered LP1+ watermark in need of an update... */
|
|
|
|
for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
|
|
|
|
if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
|
|
|
|
old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ...and mark it and all higher numbered LP1+ watermarks as dirty */
|
|
|
|
for (; wm_lp <= 3; wm_lp++)
|
|
|
|
dirty |= WM_DIRTY_LP(wm_lp);
|
|
|
|
|
|
|
|
return dirty;
|
|
|
|
}
|
|
|
|
|
2013-12-05 13:51:39 +00:00
|
|
|
static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int dirty)
|
2013-05-31 13:08:35 +00:00
|
|
|
{
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_values *previous = &dev_priv->wm.hw;
|
2013-12-05 13:51:39 +00:00
|
|
|
bool changed = false;
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2013-12-05 13:51:33 +00:00
|
|
|
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
|
|
|
|
previous->wm_lp[2] &= ~WM1_LP_SR_EN;
|
|
|
|
I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
|
2013-12-05 13:51:39 +00:00
|
|
|
changed = true;
|
2013-12-05 13:51:33 +00:00
|
|
|
}
|
|
|
|
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
|
|
|
|
previous->wm_lp[1] &= ~WM1_LP_SR_EN;
|
|
|
|
I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
|
2013-12-05 13:51:39 +00:00
|
|
|
changed = true;
|
2013-12-05 13:51:33 +00:00
|
|
|
}
|
|
|
|
if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
|
|
|
|
previous->wm_lp[0] &= ~WM1_LP_SR_EN;
|
|
|
|
I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
|
2013-12-05 13:51:39 +00:00
|
|
|
changed = true;
|
2013-12-05 13:51:33 +00:00
|
|
|
}
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2013-12-05 13:51:33 +00:00
|
|
|
/*
|
|
|
|
* Don't touch WM1S_LP_EN here.
|
|
|
|
* Doing so could cause underruns.
|
|
|
|
*/
|
2013-12-05 13:51:32 +00:00
|
|
|
|
2013-12-05 13:51:39 +00:00
|
|
|
return changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The spec says we shouldn't write when we don't need, because every write
|
|
|
|
* causes WMs to be re-evaluated, expending some power.
|
|
|
|
*/
|
2013-12-17 12:46:36 +00:00
|
|
|
static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
|
|
|
|
struct ilk_wm_values *results)
|
2013-12-05 13:51:39 +00:00
|
|
|
{
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_values *previous = &dev_priv->wm.hw;
|
2013-12-05 13:51:39 +00:00
|
|
|
unsigned int dirty;
|
|
|
|
uint32_t val;
|
|
|
|
|
2014-08-18 12:49:10 +00:00
|
|
|
dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
|
2013-12-05 13:51:39 +00:00
|
|
|
if (!dirty)
|
|
|
|
return;
|
|
|
|
|
|
|
|
_ilk_disable_lp_wm(dev_priv, dirty);
|
|
|
|
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_PIPE(PIPE_A))
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_PIPE(PIPE_B))
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_PIPE(PIPE_C))
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
|
|
|
|
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_LINETIME(PIPE_A))
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_LINETIME(PIPE_B))
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_LINETIME(PIPE_C))
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
|
|
|
|
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_DDB) {
|
2016-10-13 10:03:00 +00:00
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
|
2013-12-05 13:51:28 +00:00
|
|
|
val = I915_READ(WM_MISC);
|
|
|
|
if (results->partitioning == INTEL_DDB_PART_1_2)
|
|
|
|
val &= ~WM_MISC_DATA_PARTITION_5_6;
|
|
|
|
else
|
|
|
|
val |= WM_MISC_DATA_PARTITION_5_6;
|
|
|
|
I915_WRITE(WM_MISC, val);
|
|
|
|
} else {
|
|
|
|
val = I915_READ(DISP_ARB_CTL2);
|
|
|
|
if (results->partitioning == INTEL_DDB_PART_1_2)
|
|
|
|
val &= ~DISP_DATA_PARTITION_5_6;
|
|
|
|
else
|
|
|
|
val |= DISP_DATA_PARTITION_5_6;
|
|
|
|
I915_WRITE(DISP_ARB_CTL2, val);
|
|
|
|
}
|
2013-05-09 19:55:50 +00:00
|
|
|
}
|
|
|
|
|
2013-10-11 16:39:52 +00:00
|
|
|
if (dirty & WM_DIRTY_FBC) {
|
2013-05-31 14:45:06 +00:00
|
|
|
val = I915_READ(DISP_ARB_CTL);
|
|
|
|
if (results->enable_fbc_wm)
|
|
|
|
val &= ~DISP_FBC_WM_DIS;
|
|
|
|
else
|
|
|
|
val |= DISP_FBC_WM_DIS;
|
|
|
|
I915_WRITE(DISP_ARB_CTL, val);
|
|
|
|
}
|
|
|
|
|
2013-12-17 12:46:34 +00:00
|
|
|
if (dirty & WM_DIRTY_LP(1) &&
|
|
|
|
previous->wm_lp_spr[0] != results->wm_lp_spr[0])
|
|
|
|
I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
|
|
|
|
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 7) {
|
2013-12-05 13:51:32 +00:00
|
|
|
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
|
|
|
|
I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
|
|
|
|
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
|
|
|
|
I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
|
|
|
|
}
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2013-12-05 13:51:33 +00:00
|
|
|
if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
|
2013-12-05 13:51:33 +00:00
|
|
|
if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
|
2013-12-05 13:51:33 +00:00
|
|
|
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
|
2013-05-31 13:08:35 +00:00
|
|
|
I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
|
2013-10-09 16:18:03 +00:00
|
|
|
|
|
|
|
dev_priv->wm.hw = *results;
|
2013-05-31 13:08:35 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
bool ilk_disable_lp_wm(struct drm_device *dev)
|
2013-12-05 13:51:39 +00:00
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2013-12-05 13:51:39 +00:00
|
|
|
|
|
|
|
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
|
|
|
|
}
|
|
|
|
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
#define SKL_SAGV_BLOCK_TIME 30 /* µs */
|
2014-11-04 17:06:43 +00:00
|
|
|
|
2016-10-11 18:25:38 +00:00
|
|
|
/*
|
|
|
|
* FIXME: We still don't have the proper code detect if we need to apply the WA,
|
|
|
|
* so assume we'll always need it in order to avoid underruns.
|
|
|
|
*/
|
|
|
|
static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
|
|
|
|
2017-01-23 18:32:37 +00:00
|
|
|
if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
|
2016-10-11 18:25:38 +00:00
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-09-22 21:00:28 +00:00
|
|
|
static bool
|
|
|
|
intel_has_sagv(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2016-09-22 21:00:29 +00:00
|
|
|
if (IS_KABYLAKE(dev_priv))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (IS_SKYLAKE(dev_priv) &&
|
|
|
|
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
2016-09-22 21:00:28 +00:00
|
|
|
}
|
|
|
|
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
/*
|
|
|
|
* SAGV dynamically adjusts the system agent voltage and clock frequencies
|
|
|
|
* depending on power and performance requirements. The display engine access
|
|
|
|
* to system memory is blocked during the adjustment time. Because of the
|
|
|
|
* blocking time, having this enabled can cause full system hangs and/or pipe
|
|
|
|
* underruns if we don't meet all of the following requirements:
|
|
|
|
*
|
|
|
|
* - <= 1 pipe enabled
|
|
|
|
* - All planes can enable watermarks for latencies >= SAGV engine block time
|
|
|
|
* - We're not using an interlaced display configuration
|
|
|
|
*/
|
|
|
|
int
|
2016-09-22 21:00:27 +00:00
|
|
|
intel_enable_sagv(struct drm_i915_private *dev_priv)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2016-09-22 21:00:28 +00:00
|
|
|
if (!intel_has_sagv(dev_priv))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (dev_priv->sagv_status == I915_SAGV_ENABLED)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Enabling the SAGV\n");
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
|
|
|
|
GEN9_SAGV_ENABLE);
|
|
|
|
|
|
|
|
/* We don't need to wait for the SAGV when enabling */
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Some skl systems, pre-release machines in particular,
|
|
|
|
* don't actually have an SAGV.
|
|
|
|
*/
|
2016-09-22 21:00:29 +00:00
|
|
|
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
|
2016-09-22 21:00:27 +00:00
|
|
|
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return 0;
|
|
|
|
} else if (ret < 0) {
|
|
|
|
DRM_ERROR("Failed to enable the SAGV\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-09-22 21:00:27 +00:00
|
|
|
dev_priv->sagv_status = I915_SAGV_ENABLED;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
2016-09-22 21:00:27 +00:00
|
|
|
intel_disable_sagv(struct drm_i915_private *dev_priv)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
{
|
2016-12-05 16:27:38 +00:00
|
|
|
int ret;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
|
2016-09-22 21:00:28 +00:00
|
|
|
if (!intel_has_sagv(dev_priv))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (dev_priv->sagv_status == I915_SAGV_DISABLED)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Disabling the SAGV\n");
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
/* bspec says to keep retrying for at least 1 ms */
|
2016-12-05 16:27:38 +00:00
|
|
|
ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
|
|
|
|
GEN9_SAGV_DISABLE,
|
|
|
|
GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
|
|
|
|
1);
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Some skl systems, pre-release machines in particular,
|
|
|
|
* don't actually have an SAGV.
|
|
|
|
*/
|
2016-12-05 16:27:38 +00:00
|
|
|
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
|
2016-09-22 21:00:27 +00:00
|
|
|
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return 0;
|
2016-12-05 16:27:38 +00:00
|
|
|
} else if (ret < 0) {
|
|
|
|
DRM_ERROR("Failed to disable the SAGV (%d)\n", ret);
|
|
|
|
return ret;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
}
|
|
|
|
|
2016-09-22 21:00:27 +00:00
|
|
|
dev_priv->sagv_status = I915_SAGV_DISABLED;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-09-22 21:00:27 +00:00
|
|
|
bool intel_can_enable_sagv(struct drm_atomic_state *state)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = state->dev;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
2016-10-11 18:25:38 +00:00
|
|
|
struct intel_crtc *crtc;
|
|
|
|
struct intel_plane *plane;
|
2016-10-18 18:09:49 +00:00
|
|
|
struct intel_crtc_state *cstate;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
enum pipe pipe;
|
2016-10-18 18:09:49 +00:00
|
|
|
int level, latency;
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
|
2016-09-22 21:00:28 +00:00
|
|
|
if (!intel_has_sagv(dev_priv))
|
|
|
|
return false;
|
|
|
|
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
/*
|
|
|
|
* SKL workaround: bspec recommends we disable the SAGV when we have
|
|
|
|
* more then one pipe enabled
|
|
|
|
*
|
|
|
|
* If there are no active CRTCs, no additional checks need be performed
|
|
|
|
*/
|
|
|
|
if (hweight32(intel_state->active_crtcs) == 0)
|
|
|
|
return true;
|
|
|
|
else if (hweight32(intel_state->active_crtcs) > 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* Since we're now guaranteed to only have one active CRTC... */
|
|
|
|
pipe = ffs(intel_state->active_crtcs) - 1;
|
2016-10-31 20:37:10 +00:00
|
|
|
crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
|
2016-10-18 18:09:49 +00:00
|
|
|
cstate = to_intel_crtc_state(crtc->base.state);
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
|
2016-10-10 20:30:59 +00:00
|
|
|
if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return false;
|
|
|
|
|
2016-10-11 18:25:38 +00:00
|
|
|
for_each_intel_plane_on_crtc(dev, crtc, plane) {
|
2016-11-22 16:01:58 +00:00
|
|
|
struct skl_plane_wm *wm =
|
|
|
|
&cstate->wm.skl.optimal.planes[plane->id];
|
2016-10-11 18:25:38 +00:00
|
|
|
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
/* Skip this plane if it's not enabled */
|
2016-10-18 18:09:49 +00:00
|
|
|
if (!wm->wm[0].plane_en)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Find the highest enabled wm level for this plane */
|
2016-10-13 10:03:10 +00:00
|
|
|
for (level = ilk_wm_max_level(dev_priv);
|
2016-10-18 18:09:49 +00:00
|
|
|
!wm->wm[level].plane_en; --level)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
{ }
|
|
|
|
|
2016-10-11 18:25:38 +00:00
|
|
|
latency = dev_priv->wm.skl_latency[level];
|
|
|
|
|
|
|
|
if (skl_needs_memory_bw_wa(intel_state) &&
|
2016-11-16 11:33:16 +00:00
|
|
|
plane->base.state->fb->modifier ==
|
2016-10-11 18:25:38 +00:00
|
|
|
I915_FORMAT_MOD_X_TILED)
|
|
|
|
latency += 15;
|
|
|
|
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
/*
|
|
|
|
* If any of the planes on this pipe don't enable wm levels
|
|
|
|
* that incur memory latencies higher then 30µs we can't enable
|
|
|
|
* the SAGV
|
|
|
|
*/
|
2016-10-11 18:25:38 +00:00
|
|
|
if (latency < SKL_SAGV_BLOCK_TIME)
|
drm/i915/skl: Add support for the SAGV, fix underrun hangs
Since the watermark calculations for Skylake are still broken, we're apt
to hitting underruns very easily under multi-monitor configurations.
While it would be lovely if this was fixed, it's not. Another problem
that's been coming from this however, is the mysterious issue of
underruns causing full system hangs. An easy way to reproduce this with
a skylake system:
- Get a laptop with a skylake GPU, and hook up two external monitors to
it
- Move the cursor from the built-in LCD to one of the external displays
as quickly as you can
- You'll get a few pipe underruns, and eventually the entire system will
just freeze.
After doing a lot of investigation and reading through the bspec, I
found the existence of the SAGV, which is responsible for adjusting the
system agent voltage and clock frequencies depending on how much power
we need. According to the bspec:
"The display engine access to system memory is blocked during the
adjustment time. SAGV defaults to enabled. Software must use the
GT-driver pcode mailbox to disable SAGV when the display engine is not
able to tolerate the blocking time."
The rest of the bspec goes on to explain that software can simply leave
the SAGV enabled, and disable it when we use interlaced pipes/have more
then one pipe active.
Sure enough, with this patchset the system hangs resulting from pipe
underruns on Skylake have completely vanished on my T460s. Additionally,
the bspec mentions turning off the SAGV with more then one pipe enabled
as a workaround for display underruns. While this patch doesn't entirely
fix that, it looks like it does improve the situation a little bit so
it's likely this is going to be required to make watermarks on Skylake
fully functional.
This will still need additional work in the future: we shouldn't be
enabling the SAGV if any of the currently enabled planes can't enable WM
levels that introduce latencies >= 30 µs.
Changes since v11:
- Add skl_can_enable_sagv()
- Make sure we don't enable SAGV when not all planes can enable
watermarks >= the SAGV engine block time. I was originally going to
save this for later, but I recently managed to run into a machine
that was having problems with a single pipe configuration + SAGV.
- Make comparisons to I915_SKL_SAGV_NOT_CONTROLLED explicit
- Change I915_SAGV_DYNAMIC_FREQ to I915_SAGV_ENABLE
- Move printks outside of mutexes
- Don't print error messages twice
Changes since v10:
- Apparently sandybridge_pcode_read actually writes values and reads
them back, despite it's misleading function name. This means we've
been doing this mostly wrong and have been writing garbage to the
SAGV control. Because of this, we no longer attempt to read the SAGV
status during initialization (since there are no helpers for this).
- mlankhorst noticed that this patch was breaking on some very early
pre-release Skylake machines, which apparently don't allow you to
disable the SAGV. To prevent machines from failing tests due to SAGV
errors, if the first time we try to control the SAGV results in the
mailbox indicating an invalid command, we just disable future attempts
to control the SAGV state by setting dev_priv->skl_sagv_status to
I915_SKL_SAGV_NOT_CONTROLLED and make a note of it in dmesg.
- Move mutex_unlock() a little higher in skl_enable_sagv(). This
doesn't actually fix anything, but lets us release the lock a little
sooner since we're finished with it.
Changes since v9:
- Only enable/disable sagv on Skylake
Changes since v8:
- Add intel_state->modeset guard to the conditional for
skl_enable_sagv()
Changes since v7:
- Remove GEN9_SAGV_LOW_FREQ, replace with GEN9_SAGV_IS_ENABLED (that's
all we use it for anyway)
- Use GEN9_SAGV_IS_ENABLED instead of 0x1 for clarification
- Fix a styling error that snuck past me
Changes since v6:
- Protect skl_enable_sagv() with intel_state->modeset conditional in
intel_atomic_commit_tail()
Changes since v5:
- Don't use is_power_of_2. Makes things confusing
- Don't use the old state to figure out whether or not to
enable/disable the sagv, use the new one
- Split the loop in skl_disable_sagv into it's own function
- Move skl_sagv_enable/disable() calls into intel_atomic_commit_tail()
Changes since v4:
- Use is_power_of_2 against active_crtcs to check whether we have > 1
pipe enabled
- Fix skl_sagv_get_hw_state(): (temp & 0x1) indicates disabled, 0x0
enabled
- Call skl_sagv_enable/disable() from pre/post-plane updates
Changes since v3:
- Use time_before() to compare timeout to jiffies
Changes since v2:
- Really apply minor style nitpicks to patch this time
Changes since v1:
- Added comments about this probably being one of the requirements to
fixing Skylake's watermark issues
- Minor style nitpicks from Matt Roper
- Disable these functions on Broxton, since it doesn't have an SAGV
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471463761-26796-3-git-send-email-cpaul@redhat.com
[mlankhorst: ENOSYS -> ENXIO, whitespace fixes]
2016-08-17 19:55:54 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:43 +00:00
|
|
|
static void
|
|
|
|
skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
|
2015-09-24 22:53:11 +00:00
|
|
|
const struct intel_crtc_state *cstate,
|
2016-05-12 14:06:01 +00:00
|
|
|
struct skl_ddb_entry *alloc, /* out */
|
|
|
|
int *num_active /* out */)
|
2014-11-04 17:06:43 +00:00
|
|
|
{
|
2016-05-12 14:06:01 +00:00
|
|
|
struct drm_atomic_state *state = cstate->base.state;
|
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2015-09-24 22:53:11 +00:00
|
|
|
struct drm_crtc *for_crtc = cstate->base.crtc;
|
2014-11-04 17:06:43 +00:00
|
|
|
unsigned int pipe_size, ddb_size;
|
|
|
|
int nth_active_pipe;
|
2016-05-12 14:06:01 +00:00
|
|
|
|
2016-05-12 14:06:04 +00:00
|
|
|
if (WARN_ON(!state) || !cstate->base.active) {
|
2014-11-04 17:06:43 +00:00
|
|
|
alloc->start = 0;
|
|
|
|
alloc->end = 0;
|
2016-05-12 14:06:04 +00:00
|
|
|
*num_active = hweight32(dev_priv->active_crtcs);
|
2014-11-04 17:06:43 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:04 +00:00
|
|
|
if (intel_state->active_pipe_changes)
|
|
|
|
*num_active = hweight32(intel_state->active_crtcs);
|
|
|
|
else
|
|
|
|
*num_active = hweight32(dev_priv->active_crtcs);
|
|
|
|
|
2016-09-15 09:31:10 +00:00
|
|
|
ddb_size = INTEL_INFO(dev_priv)->ddb_size;
|
|
|
|
WARN_ON(ddb_size == 0);
|
2014-11-04 17:06:43 +00:00
|
|
|
|
|
|
|
ddb_size -= 4; /* 4 blocks for bypass path allocation */
|
|
|
|
|
2016-05-12 14:06:01 +00:00
|
|
|
/*
|
2016-05-12 14:06:04 +00:00
|
|
|
* If the state doesn't change the active CRTC's, then there's
|
|
|
|
* no need to recalculate; the existing pipe allocation limits
|
|
|
|
* should remain unchanged. Note that we're safe from racing
|
|
|
|
* commits since any racing commit that changes the active CRTC
|
|
|
|
* list would need to grab _all_ crtc locks, including the one
|
|
|
|
* we currently hold.
|
2016-05-12 14:06:01 +00:00
|
|
|
*/
|
2016-05-12 14:06:04 +00:00
|
|
|
if (!intel_state->active_pipe_changes) {
|
2016-11-08 12:55:34 +00:00
|
|
|
/*
|
|
|
|
* alloc may be cleared by clear_intel_crtc_state,
|
|
|
|
* copy from old state to be sure
|
|
|
|
*/
|
|
|
|
*alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
|
2016-05-12 14:06:04 +00:00
|
|
|
return;
|
2016-05-12 14:06:01 +00:00
|
|
|
}
|
2016-05-12 14:06:04 +00:00
|
|
|
|
|
|
|
nth_active_pipe = hweight32(intel_state->active_crtcs &
|
|
|
|
(drm_crtc_mask(for_crtc) - 1));
|
|
|
|
pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
|
|
|
|
alloc->start = nth_active_pipe * ddb_size / *num_active;
|
|
|
|
alloc->end = alloc->start + pipe_size;
|
2014-11-04 17:06:43 +00:00
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:01 +00:00
|
|
|
static unsigned int skl_cursor_allocation(int num_active)
|
2014-11-04 17:06:43 +00:00
|
|
|
{
|
2016-05-12 14:06:01 +00:00
|
|
|
if (num_active == 1)
|
2014-11-04 17:06:43 +00:00
|
|
|
return 32;
|
|
|
|
|
|
|
|
return 8;
|
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:49 +00:00
|
|
|
static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
|
|
|
|
{
|
|
|
|
entry->start = reg & 0x3ff;
|
|
|
|
entry->end = (reg >> 16) & 0x3ff;
|
2014-11-04 17:06:53 +00:00
|
|
|
if (entry->end)
|
|
|
|
entry->end += 1;
|
2014-11-04 17:06:49 +00:00
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:52 +00:00
|
|
|
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct skl_ddb_allocation *ddb /* out */)
|
2014-11-04 17:06:49 +00:00
|
|
|
{
|
2016-11-22 16:01:58 +00:00
|
|
|
struct intel_crtc *crtc;
|
2014-11-04 17:06:49 +00:00
|
|
|
|
2015-10-22 11:56:34 +00:00
|
|
|
memset(ddb, 0, sizeof(*ddb));
|
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
for_each_intel_crtc(&dev_priv->drm, crtc) {
|
2016-02-17 14:31:29 +00:00
|
|
|
enum intel_display_power_domain power_domain;
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id;
|
|
|
|
enum pipe pipe = crtc->pipe;
|
2016-02-17 14:31:29 +00:00
|
|
|
|
|
|
|
power_domain = POWER_DOMAIN_PIPE(pipe);
|
|
|
|
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
2015-10-22 11:56:34 +00:00
|
|
|
continue;
|
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
for_each_plane_id_on_crtc(crtc, plane_id) {
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (plane_id != PLANE_CURSOR)
|
|
|
|
val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
|
|
|
|
else
|
|
|
|
val = I915_READ(CUR_BUF_CFG(pipe));
|
2014-11-04 17:06:49 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
|
|
|
|
}
|
2016-02-17 14:31:29 +00:00
|
|
|
|
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
2014-11-04 17:06:49 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-16 22:52:00 +00:00
|
|
|
/*
|
|
|
|
* Determines the downscale amount of a plane for the purposes of watermark calculations.
|
|
|
|
* The bspec defines downscale amount as:
|
|
|
|
*
|
|
|
|
* """
|
|
|
|
* Horizontal down scale amount = maximum[1, Horizontal source size /
|
|
|
|
* Horizontal destination size]
|
|
|
|
* Vertical down scale amount = maximum[1, Vertical source size /
|
|
|
|
* Vertical destination size]
|
|
|
|
* Total down scale amount = Horizontal down scale amount *
|
|
|
|
* Vertical down scale amount
|
|
|
|
* """
|
|
|
|
*
|
|
|
|
* Return value is provided in 16.16 fixed point form to retain fractional part.
|
|
|
|
* Caller should take care of dividing & rounding off the value.
|
|
|
|
*/
|
|
|
|
static uint32_t
|
|
|
|
skl_plane_downscale_amount(const struct intel_plane_state *pstate)
|
|
|
|
{
|
|
|
|
uint32_t downscale_h, downscale_w;
|
|
|
|
uint32_t src_w, src_h, dst_w, dst_h;
|
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (WARN_ON(!pstate->base.visible))
|
2016-05-16 22:52:00 +00:00
|
|
|
return DRM_PLANE_HELPER_NO_SCALING;
|
|
|
|
|
|
|
|
/* n.b., src is 16.16 fixed point, dst is whole integer */
|
2016-07-26 16:06:59 +00:00
|
|
|
src_w = drm_rect_width(&pstate->base.src);
|
|
|
|
src_h = drm_rect_height(&pstate->base.src);
|
|
|
|
dst_w = drm_rect_width(&pstate->base.dst);
|
|
|
|
dst_h = drm_rect_height(&pstate->base.dst);
|
2016-09-26 16:30:46 +00:00
|
|
|
if (drm_rotation_90_or_270(pstate->base.rotation))
|
2016-05-16 22:52:00 +00:00
|
|
|
swap(dst_w, dst_h);
|
|
|
|
|
|
|
|
downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
|
|
|
|
downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
|
|
|
|
|
|
|
|
/* Provide result in 16.16 fixed point */
|
|
|
|
return (uint64_t)downscale_w * downscale_h >> 16;
|
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:43 +00:00
|
|
|
static unsigned int
|
2015-09-24 22:53:11 +00:00
|
|
|
skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
|
|
|
|
const struct drm_plane_state *pstate,
|
|
|
|
int y)
|
2014-11-04 17:06:43 +00:00
|
|
|
{
|
2016-04-06 15:26:39 +00:00
|
|
|
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
|
2016-05-19 22:03:01 +00:00
|
|
|
uint32_t down_scale_amount, data_rate;
|
2016-04-06 15:26:39 +00:00
|
|
|
uint32_t width = 0, height = 0;
|
2016-11-18 19:53:00 +00:00
|
|
|
struct drm_framebuffer *fb;
|
|
|
|
u32 format;
|
2016-05-12 14:05:57 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (!intel_pstate->base.visible)
|
2016-05-12 14:05:57 +00:00
|
|
|
return 0;
|
2016-11-18 19:53:00 +00:00
|
|
|
|
|
|
|
fb = pstate->fb;
|
2016-12-14 21:32:55 +00:00
|
|
|
format = fb->format->format;
|
2016-11-18 19:53:00 +00:00
|
|
|
|
2016-05-12 14:05:57 +00:00
|
|
|
if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
|
|
|
|
return 0;
|
|
|
|
if (y && format != DRM_FORMAT_NV12)
|
|
|
|
return 0;
|
2016-04-06 15:26:39 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
width = drm_rect_width(&intel_pstate->base.src) >> 16;
|
|
|
|
height = drm_rect_height(&intel_pstate->base.src) >> 16;
|
2016-04-06 15:26:39 +00:00
|
|
|
|
2016-09-26 16:30:46 +00:00
|
|
|
if (drm_rotation_90_or_270(pstate->rotation))
|
2016-04-06 15:26:39 +00:00
|
|
|
swap(width, height);
|
2015-04-27 22:47:37 +00:00
|
|
|
|
|
|
|
/* for planar format */
|
2016-05-12 14:05:57 +00:00
|
|
|
if (format == DRM_FORMAT_NV12) {
|
2015-04-27 22:47:37 +00:00
|
|
|
if (y) /* y-plane data rate */
|
2016-05-19 22:03:01 +00:00
|
|
|
data_rate = width * height *
|
2016-12-14 21:30:57 +00:00
|
|
|
fb->format->cpp[0];
|
2015-04-27 22:47:37 +00:00
|
|
|
else /* uv-plane data rate */
|
2016-05-19 22:03:01 +00:00
|
|
|
data_rate = (width / 2) * (height / 2) *
|
2016-12-14 21:30:57 +00:00
|
|
|
fb->format->cpp[1];
|
2016-05-19 22:03:01 +00:00
|
|
|
} else {
|
|
|
|
/* for packed formats */
|
2016-12-14 21:30:57 +00:00
|
|
|
data_rate = width * height * fb->format->cpp[0];
|
2015-04-27 22:47:37 +00:00
|
|
|
}
|
|
|
|
|
2016-05-19 22:03:01 +00:00
|
|
|
down_scale_amount = skl_plane_downscale_amount(intel_pstate);
|
|
|
|
|
|
|
|
return (uint64_t)data_rate * down_scale_amount >> 16;
|
2014-11-04 17:06:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
|
|
|
|
* a 8192x4096@32bpp framebuffer:
|
|
|
|
* 3 * 4096 * 8192 * 4 < 2^32
|
|
|
|
*/
|
|
|
|
static unsigned int
|
2016-10-26 13:41:32 +00:00
|
|
|
skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
|
|
|
|
unsigned *plane_data_rate,
|
|
|
|
unsigned *plane_y_data_rate)
|
2014-11-04 17:06:43 +00:00
|
|
|
{
|
2016-05-12 14:05:58 +00:00
|
|
|
struct drm_crtc_state *cstate = &intel_cstate->base;
|
|
|
|
struct drm_atomic_state *state = cstate->state;
|
2016-10-26 13:41:29 +00:00
|
|
|
struct drm_plane *plane;
|
|
|
|
const struct drm_plane_state *pstate;
|
2016-11-22 16:01:58 +00:00
|
|
|
unsigned int total_data_rate = 0;
|
2016-05-12 14:06:04 +00:00
|
|
|
|
|
|
|
if (WARN_ON(!state))
|
|
|
|
return 0;
|
2014-11-04 17:06:43 +00:00
|
|
|
|
2016-05-12 14:05:57 +00:00
|
|
|
/* Calculate and cache data rate for each plane */
|
2016-10-26 13:41:29 +00:00
|
|
|
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id = to_intel_plane(plane)->id;
|
|
|
|
unsigned int rate;
|
2016-05-12 14:06:04 +00:00
|
|
|
|
|
|
|
/* packed/uv */
|
|
|
|
rate = skl_plane_relative_data_rate(intel_cstate,
|
|
|
|
pstate, 0);
|
2016-11-22 16:01:58 +00:00
|
|
|
plane_data_rate[plane_id] = rate;
|
2016-10-26 13:41:32 +00:00
|
|
|
|
|
|
|
total_data_rate += rate;
|
2016-05-12 14:06:04 +00:00
|
|
|
|
|
|
|
/* y-plane */
|
|
|
|
rate = skl_plane_relative_data_rate(intel_cstate,
|
|
|
|
pstate, 1);
|
2016-11-22 16:01:58 +00:00
|
|
|
plane_y_data_rate[plane_id] = rate;
|
2015-09-24 22:53:11 +00:00
|
|
|
|
2016-10-26 13:41:32 +00:00
|
|
|
total_data_rate += rate;
|
2014-11-04 17:06:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return total_data_rate;
|
|
|
|
}
|
|
|
|
|
2016-05-31 16:58:59 +00:00
|
|
|
static uint16_t
|
|
|
|
skl_ddb_min_alloc(const struct drm_plane_state *pstate,
|
|
|
|
const int y)
|
|
|
|
{
|
|
|
|
struct drm_framebuffer *fb = pstate->fb;
|
|
|
|
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
|
|
|
|
uint32_t src_w, src_h;
|
|
|
|
uint32_t min_scanlines = 8;
|
|
|
|
uint8_t plane_bpp;
|
|
|
|
|
|
|
|
if (WARN_ON(!fb))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* For packed formats, no y-plane, return 0 */
|
2016-12-14 21:32:55 +00:00
|
|
|
if (y && fb->format->format != DRM_FORMAT_NV12)
|
2016-05-31 16:58:59 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* For Non Y-tile return 8-blocks */
|
2016-11-16 11:33:16 +00:00
|
|
|
if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
|
|
|
|
fb->modifier != I915_FORMAT_MOD_Yf_TILED)
|
2016-05-31 16:58:59 +00:00
|
|
|
return 8;
|
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
|
|
|
|
src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
|
2016-05-31 16:58:59 +00:00
|
|
|
|
2016-09-26 16:30:46 +00:00
|
|
|
if (drm_rotation_90_or_270(pstate->rotation))
|
2016-05-31 16:58:59 +00:00
|
|
|
swap(src_w, src_h);
|
|
|
|
|
|
|
|
/* Halve UV plane width and height for NV12 */
|
2016-12-14 21:32:55 +00:00
|
|
|
if (fb->format->format == DRM_FORMAT_NV12 && !y) {
|
2016-05-31 16:58:59 +00:00
|
|
|
src_w /= 2;
|
|
|
|
src_h /= 2;
|
|
|
|
}
|
|
|
|
|
2016-12-14 21:32:55 +00:00
|
|
|
if (fb->format->format == DRM_FORMAT_NV12 && !y)
|
2016-12-14 21:30:57 +00:00
|
|
|
plane_bpp = fb->format->cpp[1];
|
2016-05-31 16:58:59 +00:00
|
|
|
else
|
2016-12-14 21:30:57 +00:00
|
|
|
plane_bpp = fb->format->cpp[0];
|
2016-05-31 16:58:59 +00:00
|
|
|
|
2016-09-26 16:30:46 +00:00
|
|
|
if (drm_rotation_90_or_270(pstate->rotation)) {
|
2016-05-31 16:58:59 +00:00
|
|
|
switch (plane_bpp) {
|
|
|
|
case 1:
|
|
|
|
min_scanlines = 32;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
min_scanlines = 16;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
min_scanlines = 8;
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
min_scanlines = 4;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "Unsupported pixel depth %u for rotation",
|
|
|
|
plane_bpp);
|
|
|
|
min_scanlines = 32;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
|
|
|
|
}
|
|
|
|
|
2016-10-26 13:41:34 +00:00
|
|
|
static void
|
|
|
|
skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
|
|
|
|
uint16_t *minimum, uint16_t *y_minimum)
|
|
|
|
{
|
|
|
|
const struct drm_plane_state *pstate;
|
|
|
|
struct drm_plane *plane;
|
|
|
|
|
|
|
|
drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id = to_intel_plane(plane)->id;
|
2016-10-26 13:41:34 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
if (plane_id == PLANE_CURSOR)
|
2016-10-26 13:41:34 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!pstate->visible)
|
|
|
|
continue;
|
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
|
|
|
|
y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
|
2016-10-26 13:41:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
|
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:01 +00:00
|
|
|
static int
|
2015-09-24 22:53:11 +00:00
|
|
|
skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
|
2014-11-04 17:06:43 +00:00
|
|
|
struct skl_ddb_allocation *ddb /* out */)
|
|
|
|
{
|
2016-05-12 14:06:01 +00:00
|
|
|
struct drm_atomic_state *state = cstate->base.state;
|
2015-09-24 22:53:11 +00:00
|
|
|
struct drm_crtc *crtc = cstate->base.crtc;
|
2014-11-04 17:06:43 +00:00
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
2016-09-15 14:46:35 +00:00
|
|
|
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
|
2016-10-26 13:41:34 +00:00
|
|
|
uint16_t alloc_size, start;
|
2016-10-26 13:41:33 +00:00
|
|
|
uint16_t minimum[I915_MAX_PLANES] = {};
|
|
|
|
uint16_t y_minimum[I915_MAX_PLANES] = {};
|
2014-11-04 17:06:43 +00:00
|
|
|
unsigned int total_data_rate;
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id;
|
2016-05-12 14:06:01 +00:00
|
|
|
int num_active;
|
2016-10-26 13:41:32 +00:00
|
|
|
unsigned plane_data_rate[I915_MAX_PLANES] = {};
|
|
|
|
unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
|
2014-11-04 17:06:43 +00:00
|
|
|
|
2016-10-04 17:37:32 +00:00
|
|
|
/* Clear the partitioning for disabled planes. */
|
|
|
|
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
|
|
|
|
memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
|
|
|
|
|
2016-05-12 14:06:04 +00:00
|
|
|
if (WARN_ON(!state))
|
|
|
|
return 0;
|
|
|
|
|
2016-05-12 14:06:01 +00:00
|
|
|
if (!cstate->base.active) {
|
2016-09-15 14:46:35 +00:00
|
|
|
alloc->start = alloc->end = 0;
|
2016-05-12 14:06:01 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:04 +00:00
|
|
|
skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
|
2014-11-04 17:07:01 +00:00
|
|
|
alloc_size = skl_ddb_entry_size(alloc);
|
2014-11-04 17:06:43 +00:00
|
|
|
if (alloc_size == 0) {
|
|
|
|
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
|
2016-05-12 14:06:01 +00:00
|
|
|
return 0;
|
2014-11-04 17:06:43 +00:00
|
|
|
}
|
|
|
|
|
2016-10-26 13:41:34 +00:00
|
|
|
skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
|
2016-05-12 14:06:04 +00:00
|
|
|
|
2016-10-26 13:41:34 +00:00
|
|
|
/*
|
|
|
|
* 1. Allocate the mininum required blocks for each active plane
|
|
|
|
* and allocate the cursor, it doesn't require extra allocation
|
|
|
|
* proportional to the data rate.
|
|
|
|
*/
|
2015-02-09 13:35:10 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
|
|
|
|
alloc_size -= minimum[plane_id];
|
|
|
|
alloc_size -= y_minimum[plane_id];
|
2015-02-09 13:35:10 +00:00
|
|
|
}
|
|
|
|
|
2016-10-26 13:41:34 +00:00
|
|
|
ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
|
|
|
|
ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
|
|
|
|
|
2014-11-04 17:06:43 +00:00
|
|
|
/*
|
2015-02-09 13:35:10 +00:00
|
|
|
* 2. Distribute the remaining space in proportion to the amount of
|
|
|
|
* data each plane needs to fetch from memory.
|
2014-11-04 17:06:43 +00:00
|
|
|
*
|
|
|
|
* FIXME: we may not allocate every single block here.
|
|
|
|
*/
|
2016-10-26 13:41:32 +00:00
|
|
|
total_data_rate = skl_get_total_relative_data_rate(cstate,
|
|
|
|
plane_data_rate,
|
|
|
|
plane_y_data_rate);
|
2016-05-12 14:05:57 +00:00
|
|
|
if (total_data_rate == 0)
|
2016-05-12 14:06:01 +00:00
|
|
|
return 0;
|
2014-11-04 17:06:43 +00:00
|
|
|
|
2014-11-04 17:07:01 +00:00
|
|
|
start = alloc->start;
|
2016-11-22 16:01:58 +00:00
|
|
|
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
|
2015-04-27 22:47:37 +00:00
|
|
|
unsigned int data_rate, y_data_rate;
|
|
|
|
uint16_t plane_blocks, y_plane_blocks = 0;
|
2014-11-04 17:06:43 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
if (plane_id == PLANE_CURSOR)
|
2016-10-26 13:41:34 +00:00
|
|
|
continue;
|
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
data_rate = plane_data_rate[plane_id];
|
2014-11-04 17:06:43 +00:00
|
|
|
|
|
|
|
/*
|
2015-04-27 22:47:37 +00:00
|
|
|
* allocation for (packed formats) or (uv-plane part of planar format):
|
2014-11-04 17:06:43 +00:00
|
|
|
* promote the expression to 64 bits to avoid overflowing, the
|
|
|
|
* result is < available as data_rate / total_data_rate < 1
|
|
|
|
*/
|
2016-11-22 16:01:58 +00:00
|
|
|
plane_blocks = minimum[plane_id];
|
2015-02-09 13:35:10 +00:00
|
|
|
plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
|
|
|
|
total_data_rate);
|
2014-11-04 17:06:43 +00:00
|
|
|
|
2016-05-12 14:06:01 +00:00
|
|
|
/* Leave disabled planes at (0,0) */
|
|
|
|
if (data_rate) {
|
2016-11-22 16:01:58 +00:00
|
|
|
ddb->plane[pipe][plane_id].start = start;
|
|
|
|
ddb->plane[pipe][plane_id].end = start + plane_blocks;
|
2016-05-12 14:06:01 +00:00
|
|
|
}
|
2014-11-04 17:06:43 +00:00
|
|
|
|
|
|
|
start += plane_blocks;
|
2015-04-27 22:47:37 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* allocation for y_plane part of planar format:
|
|
|
|
*/
|
2016-11-22 16:01:58 +00:00
|
|
|
y_data_rate = plane_y_data_rate[plane_id];
|
2016-05-12 14:05:57 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
y_plane_blocks = y_minimum[plane_id];
|
2016-05-12 14:05:57 +00:00
|
|
|
y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
|
|
|
|
total_data_rate);
|
2015-04-27 22:47:37 +00:00
|
|
|
|
2016-05-12 14:06:01 +00:00
|
|
|
if (y_data_rate) {
|
2016-11-22 16:01:58 +00:00
|
|
|
ddb->y_plane[pipe][plane_id].start = start;
|
|
|
|
ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
|
2016-05-12 14:06:01 +00:00
|
|
|
}
|
2016-05-12 14:05:57 +00:00
|
|
|
|
|
|
|
start += y_plane_blocks;
|
2014-11-04 17:06:43 +00:00
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:01 +00:00
|
|
|
return 0;
|
2014-11-04 17:06:43 +00:00
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:42 +00:00
|
|
|
/*
|
|
|
|
* The max latency should be 257 (max the punit can code is 255 and we add 2us
|
2016-01-20 19:05:26 +00:00
|
|
|
* for the read latency) and cpp should always be <= 8, so that
|
2014-11-04 17:06:42 +00:00
|
|
|
* should allow pixel_rate up to ~2 GHz which seems sufficient since max
|
|
|
|
* 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
|
|
|
|
*/
|
2016-12-01 15:49:37 +00:00
|
|
|
static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
|
|
|
|
uint32_t latency)
|
2014-11-04 17:06:42 +00:00
|
|
|
{
|
2016-12-01 15:49:37 +00:00
|
|
|
uint32_t wm_intermediate_val;
|
|
|
|
uint_fixed_16_16_t ret;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
|
|
|
if (latency == 0)
|
2016-12-01 15:49:37 +00:00
|
|
|
return FP_16_16_MAX;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-12-01 15:49:37 +00:00
|
|
|
wm_intermediate_val = latency * pixel_rate * cpp;
|
|
|
|
ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512);
|
2014-11-04 17:06:42 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-12-01 15:49:37 +00:00
|
|
|
static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
|
|
|
|
uint32_t pipe_htotal,
|
|
|
|
uint32_t latency,
|
|
|
|
uint_fixed_16_16_t plane_blocks_per_line)
|
2014-11-04 17:06:42 +00:00
|
|
|
{
|
2015-02-27 11:15:22 +00:00
|
|
|
uint32_t wm_intermediate_val;
|
2016-12-01 15:49:37 +00:00
|
|
|
uint_fixed_16_16_t ret;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
|
|
|
if (latency == 0)
|
2016-12-01 15:49:37 +00:00
|
|
|
return FP_16_16_MAX;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
|
|
|
wm_intermediate_val = latency * pixel_rate;
|
2016-12-01 15:49:37 +00:00
|
|
|
wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
|
|
|
|
pipe_htotal * 1000);
|
|
|
|
ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line);
|
2014-11-04 17:06:42 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-05-16 22:52:00 +00:00
|
|
|
static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
|
|
|
|
struct intel_plane_state *pstate)
|
|
|
|
{
|
|
|
|
uint64_t adjusted_pixel_rate;
|
|
|
|
uint64_t downscale_amount;
|
|
|
|
uint64_t pixel_rate;
|
|
|
|
|
|
|
|
/* Shouldn't reach here on disabled planes... */
|
2016-07-26 16:06:59 +00:00
|
|
|
if (WARN_ON(!pstate->base.visible))
|
2016-05-16 22:52:00 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Adjusted plane pixel rate is just the pipe's adjusted pixel rate
|
|
|
|
* with additional adjustments for plane-specific scaling.
|
|
|
|
*/
|
2016-10-07 20:28:57 +00:00
|
|
|
adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
|
2016-05-16 22:52:00 +00:00
|
|
|
downscale_amount = skl_plane_downscale_amount(pstate);
|
|
|
|
|
|
|
|
pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
|
|
|
|
WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
|
|
|
|
|
|
|
|
return pixel_rate;
|
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_crtc_state *cstate,
|
|
|
|
struct intel_plane_state *intel_pstate,
|
|
|
|
uint16_t ddb_allocation,
|
|
|
|
int level,
|
|
|
|
uint16_t *out_blocks, /* out */
|
|
|
|
uint8_t *out_lines, /* out */
|
|
|
|
bool *enabled /* out */)
|
2014-11-04 17:06:42 +00:00
|
|
|
{
|
2016-05-12 14:06:05 +00:00
|
|
|
struct drm_plane_state *pstate = &intel_pstate->base;
|
|
|
|
struct drm_framebuffer *fb = pstate->fb;
|
2015-02-27 11:15:22 +00:00
|
|
|
uint32_t latency = dev_priv->wm.skl_latency[level];
|
2016-12-01 15:49:37 +00:00
|
|
|
uint_fixed_16_16_t method1, method2;
|
|
|
|
uint_fixed_16_16_t plane_blocks_per_line;
|
|
|
|
uint_fixed_16_16_t selected_result;
|
|
|
|
uint32_t interm_pbpl;
|
|
|
|
uint32_t plane_bytes_per_line;
|
2015-02-27 11:15:22 +00:00
|
|
|
uint32_t res_blocks, res_lines;
|
2016-01-20 19:05:26 +00:00
|
|
|
uint8_t cpp;
|
2016-04-06 15:26:39 +00:00
|
|
|
uint32_t width = 0, height = 0;
|
2016-05-16 22:52:00 +00:00
|
|
|
uint32_t plane_pixel_rate;
|
2016-12-01 15:49:37 +00:00
|
|
|
uint_fixed_16_16_t y_tile_minimum;
|
|
|
|
uint32_t y_min_scanlines;
|
2016-10-11 18:25:38 +00:00
|
|
|
struct intel_atomic_state *state =
|
|
|
|
to_intel_atomic_state(cstate->base.state);
|
|
|
|
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
|
2016-12-01 15:49:33 +00:00
|
|
|
bool y_tiled, x_tiled;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
|
2016-05-12 14:06:08 +00:00
|
|
|
*enabled = false;
|
|
|
|
return 0;
|
|
|
|
}
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-12-01 15:49:33 +00:00
|
|
|
y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
|
|
|
|
fb->modifier == I915_FORMAT_MOD_Yf_TILED;
|
|
|
|
x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
|
|
|
|
|
2016-12-01 15:49:35 +00:00
|
|
|
/* Display WA #1141: kbl. */
|
|
|
|
if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
|
|
|
|
latency += 4;
|
|
|
|
|
2016-12-01 15:49:33 +00:00
|
|
|
if (apply_memory_bw_wa && x_tiled)
|
2016-10-11 18:25:38 +00:00
|
|
|
latency += 15;
|
|
|
|
|
2016-07-26 16:06:59 +00:00
|
|
|
width = drm_rect_width(&intel_pstate->base.src) >> 16;
|
|
|
|
height = drm_rect_height(&intel_pstate->base.src) >> 16;
|
2016-04-06 15:26:39 +00:00
|
|
|
|
2016-09-26 16:30:46 +00:00
|
|
|
if (drm_rotation_90_or_270(pstate->rotation))
|
2016-04-06 15:26:39 +00:00
|
|
|
swap(width, height);
|
|
|
|
|
2016-12-14 21:30:57 +00:00
|
|
|
cpp = fb->format->cpp[0];
|
2016-05-16 22:52:00 +00:00
|
|
|
plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
|
|
|
|
|
2016-10-25 06:35:20 +00:00
|
|
|
if (drm_rotation_90_or_270(pstate->rotation)) {
|
2016-12-14 21:32:55 +00:00
|
|
|
int cpp = (fb->format->format == DRM_FORMAT_NV12) ?
|
2016-12-14 21:30:57 +00:00
|
|
|
fb->format->cpp[1] :
|
|
|
|
fb->format->cpp[0];
|
2016-09-22 21:00:31 +00:00
|
|
|
|
|
|
|
switch (cpp) {
|
|
|
|
case 1:
|
|
|
|
y_min_scanlines = 16;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
y_min_scanlines = 8;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
y_min_scanlines = 4;
|
|
|
|
break;
|
2016-09-22 21:00:35 +00:00
|
|
|
default:
|
|
|
|
MISSING_CASE(cpp);
|
|
|
|
return -EINVAL;
|
2016-09-22 21:00:31 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
y_min_scanlines = 4;
|
|
|
|
}
|
|
|
|
|
2016-11-08 20:22:11 +00:00
|
|
|
if (apply_memory_bw_wa)
|
|
|
|
y_min_scanlines *= 2;
|
|
|
|
|
2016-09-22 21:00:32 +00:00
|
|
|
plane_bytes_per_line = width * cpp;
|
2016-12-01 15:49:33 +00:00
|
|
|
if (y_tiled) {
|
2016-12-01 15:49:37 +00:00
|
|
|
interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line *
|
|
|
|
y_min_scanlines, 512);
|
2016-09-22 21:00:32 +00:00
|
|
|
plane_blocks_per_line =
|
2016-12-01 15:49:37 +00:00
|
|
|
fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines);
|
2016-12-01 15:49:33 +00:00
|
|
|
} else if (x_tiled) {
|
2016-12-01 15:49:37 +00:00
|
|
|
interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512);
|
|
|
|
plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
|
2016-12-01 15:49:33 +00:00
|
|
|
} else {
|
2016-12-01 15:49:37 +00:00
|
|
|
interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
|
|
|
|
plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl);
|
2016-09-22 21:00:32 +00:00
|
|
|
}
|
|
|
|
|
2016-05-16 22:52:00 +00:00
|
|
|
method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
|
|
|
|
method2 = skl_wm_method2(plane_pixel_rate,
|
2015-09-24 22:53:11 +00:00
|
|
|
cstate->base.adjusted_mode.crtc_htotal,
|
2016-09-22 21:00:31 +00:00
|
|
|
latency,
|
2016-09-22 21:00:32 +00:00
|
|
|
plane_blocks_per_line);
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-12-01 15:49:37 +00:00
|
|
|
y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines,
|
|
|
|
plane_blocks_per_line);
|
2016-09-22 21:00:33 +00:00
|
|
|
|
2016-12-01 15:49:33 +00:00
|
|
|
if (y_tiled) {
|
2016-12-01 15:49:37 +00:00
|
|
|
selected_result = max_fixed_16_16(method2, y_tile_minimum);
|
2015-02-27 15:12:35 +00:00
|
|
|
} else {
|
2016-09-22 21:00:34 +00:00
|
|
|
if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
|
|
|
|
(plane_bytes_per_line / 512 < 1))
|
|
|
|
selected_result = method2;
|
2016-12-01 15:49:37 +00:00
|
|
|
else if ((ddb_allocation /
|
|
|
|
fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
|
|
|
|
selected_result = min_fixed_16_16(method1, method2);
|
2015-02-27 15:12:35 +00:00
|
|
|
else
|
|
|
|
selected_result = method1;
|
|
|
|
}
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-12-01 15:49:37 +00:00
|
|
|
res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1;
|
|
|
|
res_lines = DIV_ROUND_UP(selected_result.val,
|
|
|
|
plane_blocks_per_line.val);
|
2014-11-04 17:06:55 +00:00
|
|
|
|
2015-02-27 15:12:35 +00:00
|
|
|
if (level >= 1 && level <= 7) {
|
2016-12-01 15:49:33 +00:00
|
|
|
if (y_tiled) {
|
2016-12-01 15:49:37 +00:00
|
|
|
res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
|
2016-09-22 21:00:31 +00:00
|
|
|
res_lines += y_min_scanlines;
|
2016-09-22 21:00:33 +00:00
|
|
|
} else {
|
2015-02-27 15:12:35 +00:00
|
|
|
res_blocks++;
|
2016-09-22 21:00:33 +00:00
|
|
|
}
|
2015-02-27 15:12:35 +00:00
|
|
|
}
|
2014-11-04 17:06:55 +00:00
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
if (res_blocks >= ddb_allocation || res_lines > 31) {
|
|
|
|
*enabled = false;
|
2016-05-12 14:06:10 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If there are no valid level 0 watermarks, then we can't
|
|
|
|
* support this display configuration.
|
|
|
|
*/
|
|
|
|
if (level) {
|
|
|
|
return 0;
|
|
|
|
} else {
|
2016-11-22 16:01:58 +00:00
|
|
|
struct drm_plane *plane = pstate->plane;
|
|
|
|
|
2016-05-12 14:06:10 +00:00
|
|
|
DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
|
2016-11-22 16:01:58 +00:00
|
|
|
DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
|
|
|
|
plane->base.id, plane->name,
|
2016-05-12 14:06:10 +00:00
|
|
|
res_blocks, ddb_allocation, res_lines);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2016-05-12 14:06:08 +00:00
|
|
|
}
|
2014-11-04 17:06:55 +00:00
|
|
|
|
|
|
|
*out_blocks = res_blocks;
|
|
|
|
*out_lines = res_lines;
|
2016-05-12 14:06:08 +00:00
|
|
|
*enabled = true;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
return 0;
|
2014-11-04 17:06:42 +00:00
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:06 +00:00
|
|
|
static int
|
|
|
|
skl_compute_wm_level(const struct drm_i915_private *dev_priv,
|
|
|
|
struct skl_ddb_allocation *ddb,
|
|
|
|
struct intel_crtc_state *cstate,
|
2016-10-04 18:28:20 +00:00
|
|
|
struct intel_plane *intel_plane,
|
2016-05-12 14:06:06 +00:00
|
|
|
int level,
|
|
|
|
struct skl_wm_level *result)
|
2014-11-04 17:06:42 +00:00
|
|
|
{
|
2016-05-12 14:06:06 +00:00
|
|
|
struct drm_atomic_state *state = cstate->base.state;
|
2015-09-24 22:53:11 +00:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
|
2016-10-04 18:28:20 +00:00
|
|
|
struct drm_plane *plane = &intel_plane->base;
|
|
|
|
struct intel_plane_state *intel_pstate = NULL;
|
2014-11-04 17:06:42 +00:00
|
|
|
uint16_t ddb_blocks;
|
2015-09-24 22:53:11 +00:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
2016-05-12 14:06:08 +00:00
|
|
|
int ret;
|
2016-10-04 18:28:20 +00:00
|
|
|
|
|
|
|
if (state)
|
|
|
|
intel_pstate =
|
|
|
|
intel_atomic_get_existing_plane_state(state,
|
|
|
|
intel_plane);
|
2015-09-24 22:53:11 +00:00
|
|
|
|
2016-05-12 14:06:06 +00:00
|
|
|
/*
|
2016-10-04 18:28:20 +00:00
|
|
|
* Note: If we start supporting multiple pending atomic commits against
|
|
|
|
* the same planes/CRTC's in the future, plane->state will no longer be
|
|
|
|
* the correct pre-state to use for the calculations here and we'll
|
|
|
|
* need to change where we get the 'unchanged' plane data from.
|
|
|
|
*
|
|
|
|
* For now this is fine because we only allow one queued commit against
|
|
|
|
* a CRTC. Even if the plane isn't modified by this transaction and we
|
|
|
|
* don't have a plane lock, we still have the CRTC's lock, so we know
|
|
|
|
* that no other transactions are racing with us to update it.
|
2016-05-12 14:06:06 +00:00
|
|
|
*/
|
2016-10-04 18:28:20 +00:00
|
|
|
if (!intel_pstate)
|
|
|
|
intel_pstate = to_intel_plane_state(plane->state);
|
2016-05-12 14:06:06 +00:00
|
|
|
|
2016-10-04 18:28:20 +00:00
|
|
|
WARN_ON(!intel_pstate->base.fb);
|
2016-05-12 14:06:06 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-10-04 18:28:20 +00:00
|
|
|
ret = skl_compute_plane_wm(dev_priv,
|
|
|
|
cstate,
|
|
|
|
intel_pstate,
|
|
|
|
ddb_blocks,
|
|
|
|
level,
|
|
|
|
&result->plane_res_b,
|
|
|
|
&result->plane_res_l,
|
|
|
|
&result->plane_en);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-05-12 14:06:06 +00:00
|
|
|
|
|
|
|
return 0;
|
2014-11-04 17:06:42 +00:00
|
|
|
}
|
|
|
|
|
2014-11-04 17:06:57 +00:00
|
|
|
static uint32_t
|
2015-09-24 22:53:11 +00:00
|
|
|
skl_compute_linetime_wm(struct intel_crtc_state *cstate)
|
2014-11-04 17:06:57 +00:00
|
|
|
{
|
2016-12-01 15:49:34 +00:00
|
|
|
struct drm_atomic_state *state = cstate->base.state;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(state->dev);
|
2016-10-07 20:28:58 +00:00
|
|
|
uint32_t pixel_rate;
|
2016-12-01 15:49:34 +00:00
|
|
|
uint32_t linetime_wm;
|
2016-10-07 20:28:58 +00:00
|
|
|
|
2015-09-24 22:53:11 +00:00
|
|
|
if (!cstate->base.active)
|
2014-11-04 17:06:57 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-10-07 20:28:58 +00:00
|
|
|
pixel_rate = ilk_pipe_pixel_rate(cstate);
|
|
|
|
|
|
|
|
if (WARN_ON(pixel_rate == 0))
|
2015-07-16 16:36:51 +00:00
|
|
|
return 0;
|
2014-11-04 17:06:57 +00:00
|
|
|
|
2016-12-01 15:49:34 +00:00
|
|
|
linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
|
|
|
|
1000, pixel_rate);
|
|
|
|
|
|
|
|
/* Display WA #1135: bxt. */
|
|
|
|
if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
|
|
|
|
linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
|
|
|
|
|
|
|
|
return linetime_wm;
|
2014-11-04 17:06:57 +00:00
|
|
|
}
|
|
|
|
|
2015-09-24 22:53:11 +00:00
|
|
|
static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
|
2014-11-04 17:06:58 +00:00
|
|
|
struct skl_wm_level *trans_wm /* out */)
|
2014-11-04 17:06:57 +00:00
|
|
|
{
|
2015-09-24 22:53:11 +00:00
|
|
|
if (!cstate->base.active)
|
2014-11-04 17:06:57 +00:00
|
|
|
return;
|
2014-11-04 17:06:58 +00:00
|
|
|
|
|
|
|
/* Until we know more, just disable transition WMs */
|
2016-10-04 18:28:20 +00:00
|
|
|
trans_wm->plane_en = false;
|
2014-11-04 17:06:57 +00:00
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
|
|
|
|
struct skl_ddb_allocation *ddb,
|
|
|
|
struct skl_pipe_wm *pipe_wm)
|
2014-11-04 17:06:42 +00:00
|
|
|
{
|
2015-09-24 22:53:11 +00:00
|
|
|
struct drm_device *dev = cstate->base.crtc->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
const struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-10-04 18:28:20 +00:00
|
|
|
struct intel_plane *intel_plane;
|
|
|
|
struct skl_plane_wm *wm;
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
2016-05-12 14:06:08 +00:00
|
|
|
int ret;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-10-04 18:28:20 +00:00
|
|
|
/*
|
|
|
|
* We'll only calculate watermarks for planes that are actually
|
|
|
|
* enabled, so make sure all other planes are set as disabled.
|
|
|
|
*/
|
|
|
|
memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
|
|
|
|
|
|
|
|
for_each_intel_plane_mask(&dev_priv->drm,
|
|
|
|
intel_plane,
|
|
|
|
cstate->base.plane_mask) {
|
2016-11-22 16:01:58 +00:00
|
|
|
wm = &pipe_wm->planes[intel_plane->id];
|
2016-10-04 18:28:20 +00:00
|
|
|
|
|
|
|
for (level = 0; level <= max_level; level++) {
|
|
|
|
ret = skl_compute_wm_level(dev_priv, ddb, cstate,
|
|
|
|
intel_plane, level,
|
|
|
|
&wm->wm[level]);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
skl_compute_transition_wm(cstate, &wm->trans_wm);
|
2014-11-04 17:06:42 +00:00
|
|
|
}
|
2015-09-24 22:53:11 +00:00
|
|
|
pipe_wm->linetime = skl_compute_linetime_wm(cstate);
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
return 0;
|
2014-11-04 17:06:42 +00:00
|
|
|
}
|
|
|
|
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg,
|
2014-11-04 17:06:53 +00:00
|
|
|
const struct skl_ddb_entry *entry)
|
|
|
|
{
|
|
|
|
if (entry->end)
|
|
|
|
I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
|
|
|
|
else
|
|
|
|
I915_WRITE(reg, 0);
|
|
|
|
}
|
|
|
|
|
2016-10-18 18:09:49 +00:00
|
|
|
static void skl_write_wm_level(struct drm_i915_private *dev_priv,
|
|
|
|
i915_reg_t reg,
|
|
|
|
const struct skl_wm_level *level)
|
|
|
|
{
|
|
|
|
uint32_t val = 0;
|
|
|
|
|
|
|
|
if (level->plane_en) {
|
|
|
|
val |= PLANE_WM_EN;
|
|
|
|
val |= level->plane_res_b;
|
|
|
|
val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
|
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
}
|
|
|
|
|
2016-11-22 20:21:53 +00:00
|
|
|
static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
|
|
|
|
const struct skl_plane_wm *wm,
|
|
|
|
const struct skl_ddb_allocation *ddb,
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id)
|
drm/i915/skl: Update plane watermarks atomically during plane updates
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"armed", which is done by writing to the PLANE_SURF (or in the case of
cursor planes, the CURBASE register) register.
With this in mind, up until now we've been updating watermarks on skl
like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
or
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
Now we update watermarks atomically like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks() (wm values aren't written yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks() (actual wm values aren't written
yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
So this patch moves all of the watermark writes into the right place;
inside of the vblank evasion where we update all of the registers for
each plane. While this patch doesn't fix everything, it does allow us to
update the watermark values in the way the hardware expects us to.
Changes since original patch series:
- Remove mutex_lock/mutex_unlock since they don't do anything and we're
not touching global state
- Move skl_write_cursor_wm/skl_write_plane_wm functions into
intel_pm.c, make externally visible
- Add skl_write_plane_wm calls to skl_update_plane
- Fix conditional for for loop in skl_write_plane_wm (level < max_level
should be level <= max_level)
- Make diagram in commit more accurate to what's actually happening
- Add Fixes:
Changes since v1:
- Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
then just Skylake
- Update description to make it clear this patch doesn't fix everything
- Check if pipes were actually changed before writing watermarks
Changes since v2:
- Write PIPE_WM_LINETIME during vblank evasion
Changes since v3:
- Rebase against new SAGV patch changes
Changes since v4:
- Add a parameter to choose what skl_wm_values struct to use when
writing new plane watermarks
Changes since v5:
- Remove cursor ddb entry write in skl_write_cursor_wm(), defer until
patch 6
- Write WM_LINETIME in intel_begin_crtc_commit()
Changes since v6:
- Remove redundant dirty_pipes check in skl_write_plane_wm (we check
this in all places where we call this function, and it was supposed
to have been removed earlier anyway)
- In i9xx_update_cursor(), use dev_priv->info.gen >= 9 instead of
IS_GEN9(dev_priv). We do this everywhere else and I'd imagine this
needs to be done for gen10 as well
Changes since v7:
- Fix rebase fail (unused variable obj)
- Make struct skl_wm_values *wm const
- Fix indenting
- Use INTEL_GEN() instead of dev_priv->info.gen
Changes since v8:
- Don't forget calls to skl_write_plane_wm() when disabling planes
- Use INTEL_GEN(), not INTEL_INFO()->gen in intel_begin_crtc_commit()
Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
Signed-off-by: Lyude <cpaul@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
2016-08-22 16:50:08 +00:00
|
|
|
{
|
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
drm/i915/skl: Update plane watermarks atomically during plane updates
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"armed", which is done by writing to the PLANE_SURF (or in the case of
cursor planes, the CURBASE register) register.
With this in mind, up until now we've been updating watermarks on skl
like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
or
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
Now we update watermarks atomically like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks() (wm values aren't written yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks() (actual wm values aren't written
yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
So this patch moves all of the watermark writes into the right place;
inside of the vblank evasion where we update all of the registers for
each plane. While this patch doesn't fix everything, it does allow us to
update the watermark values in the way the hardware expects us to.
Changes since original patch series:
- Remove mutex_lock/mutex_unlock since they don't do anything and we're
not touching global state
- Move skl_write_cursor_wm/skl_write_plane_wm functions into
intel_pm.c, make externally visible
- Add skl_write_plane_wm calls to skl_update_plane
- Fix conditional for for loop in skl_write_plane_wm (level < max_level
should be level <= max_level)
- Make diagram in commit more accurate to what's actually happening
- Add Fixes:
Changes since v1:
- Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
then just Skylake
- Update description to make it clear this patch doesn't fix everything
- Check if pipes were actually changed before writing watermarks
Changes since v2:
- Write PIPE_WM_LINETIME during vblank evasion
Changes since v3:
- Rebase against new SAGV patch changes
Changes since v4:
- Add a parameter to choose what skl_wm_values struct to use when
writing new plane watermarks
Changes since v5:
- Remove cursor ddb entry write in skl_write_cursor_wm(), defer until
patch 6
- Write WM_LINETIME in intel_begin_crtc_commit()
Changes since v6:
- Remove redundant dirty_pipes check in skl_write_plane_wm (we check
this in all places where we call this function, and it was supposed
to have been removed earlier anyway)
- In i9xx_update_cursor(), use dev_priv->info.gen >= 9 instead of
IS_GEN9(dev_priv). We do this everywhere else and I'd imagine this
needs to be done for gen10 as well
Changes since v7:
- Fix rebase fail (unused variable obj)
- Make struct skl_wm_values *wm const
- Fix indenting
- Use INTEL_GEN() instead of dev_priv->info.gen
Changes since v8:
- Don't forget calls to skl_write_plane_wm() when disabling planes
- Use INTEL_GEN(), not INTEL_INFO()->gen in intel_begin_crtc_commit()
Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
Signed-off-by: Lyude <cpaul@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
2016-08-22 16:50:08 +00:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
|
|
|
|
for (level = 0; level <= max_level; level++) {
|
2016-11-22 16:01:58 +00:00
|
|
|
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
|
2016-10-18 18:09:49 +00:00
|
|
|
&wm->wm[level]);
|
drm/i915/skl: Update plane watermarks atomically during plane updates
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"armed", which is done by writing to the PLANE_SURF (or in the case of
cursor planes, the CURBASE register) register.
With this in mind, up until now we've been updating watermarks on skl
like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
or
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
Now we update watermarks atomically like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks() (wm values aren't written yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks() (actual wm values aren't written
yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
So this patch moves all of the watermark writes into the right place;
inside of the vblank evasion where we update all of the registers for
each plane. While this patch doesn't fix everything, it does allow us to
update the watermark values in the way the hardware expects us to.
Changes since original patch series:
- Remove mutex_lock/mutex_unlock since they don't do anything and we're
not touching global state
- Move skl_write_cursor_wm/skl_write_plane_wm functions into
intel_pm.c, make externally visible
- Add skl_write_plane_wm calls to skl_update_plane
- Fix conditional for for loop in skl_write_plane_wm (level < max_level
should be level <= max_level)
- Make diagram in commit more accurate to what's actually happening
- Add Fixes:
Changes since v1:
- Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
then just Skylake
- Update description to make it clear this patch doesn't fix everything
- Check if pipes were actually changed before writing watermarks
Changes since v2:
- Write PIPE_WM_LINETIME during vblank evasion
Changes since v3:
- Rebase against new SAGV patch changes
Changes since v4:
- Add a parameter to choose what skl_wm_values struct to use when
writing new plane watermarks
Changes since v5:
- Remove cursor ddb entry write in skl_write_cursor_wm(), defer until
patch 6
- Write WM_LINETIME in intel_begin_crtc_commit()
Changes since v6:
- Remove redundant dirty_pipes check in skl_write_plane_wm (we check
this in all places where we call this function, and it was supposed
to have been removed earlier anyway)
- In i9xx_update_cursor(), use dev_priv->info.gen >= 9 instead of
IS_GEN9(dev_priv). We do this everywhere else and I'd imagine this
needs to be done for gen10 as well
Changes since v7:
- Fix rebase fail (unused variable obj)
- Make struct skl_wm_values *wm const
- Fix indenting
- Use INTEL_GEN() instead of dev_priv->info.gen
Changes since v8:
- Don't forget calls to skl_write_plane_wm() when disabling planes
- Use INTEL_GEN(), not INTEL_INFO()->gen in intel_begin_crtc_commit()
Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
Signed-off-by: Lyude <cpaul@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
2016-08-22 16:50:08 +00:00
|
|
|
}
|
2016-11-22 16:01:58 +00:00
|
|
|
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
|
2016-10-18 18:09:49 +00:00
|
|
|
&wm->trans_wm);
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
|
|
|
|
&ddb->plane[pipe][plane_id]);
|
|
|
|
skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
|
|
|
|
&ddb->y_plane[pipe][plane_id]);
|
drm/i915/skl: Update plane watermarks atomically during plane updates
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"armed", which is done by writing to the PLANE_SURF (or in the case of
cursor planes, the CURBASE register) register.
With this in mind, up until now we've been updating watermarks on skl
like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
or
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
Now we update watermarks atomically like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks() (wm values aren't written yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks() (actual wm values aren't written
yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
So this patch moves all of the watermark writes into the right place;
inside of the vblank evasion where we update all of the registers for
each plane. While this patch doesn't fix everything, it does allow us to
update the watermark values in the way the hardware expects us to.
Changes since original patch series:
- Remove mutex_lock/mutex_unlock since they don't do anything and we're
not touching global state
- Move skl_write_cursor_wm/skl_write_plane_wm functions into
intel_pm.c, make externally visible
- Add skl_write_plane_wm calls to skl_update_plane
- Fix conditional for for loop in skl_write_plane_wm (level < max_level
should be level <= max_level)
- Make diagram in commit more accurate to what's actually happening
- Add Fixes:
Changes since v1:
- Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
then just Skylake
- Update description to make it clear this patch doesn't fix everything
- Check if pipes were actually changed before writing watermarks
Changes since v2:
- Write PIPE_WM_LINETIME during vblank evasion
Changes since v3:
- Rebase against new SAGV patch changes
Changes since v4:
- Add a parameter to choose what skl_wm_values struct to use when
writing new plane watermarks
Changes since v5:
- Remove cursor ddb entry write in skl_write_cursor_wm(), defer until
patch 6
- Write WM_LINETIME in intel_begin_crtc_commit()
Changes since v6:
- Remove redundant dirty_pipes check in skl_write_plane_wm (we check
this in all places where we call this function, and it was supposed
to have been removed earlier anyway)
- In i9xx_update_cursor(), use dev_priv->info.gen >= 9 instead of
IS_GEN9(dev_priv). We do this everywhere else and I'd imagine this
needs to be done for gen10 as well
Changes since v7:
- Fix rebase fail (unused variable obj)
- Make struct skl_wm_values *wm const
- Fix indenting
- Use INTEL_GEN() instead of dev_priv->info.gen
Changes since v8:
- Don't forget calls to skl_write_plane_wm() when disabling planes
- Use INTEL_GEN(), not INTEL_INFO()->gen in intel_begin_crtc_commit()
Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
Signed-off-by: Lyude <cpaul@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
2016-08-22 16:50:08 +00:00
|
|
|
}
|
|
|
|
|
2016-11-22 20:21:53 +00:00
|
|
|
static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
|
|
|
|
const struct skl_plane_wm *wm,
|
|
|
|
const struct skl_ddb_allocation *ddb)
|
drm/i915/skl: Update plane watermarks atomically during plane updates
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"armed", which is done by writing to the PLANE_SURF (or in the case of
cursor planes, the CURBASE register) register.
With this in mind, up until now we've been updating watermarks on skl
like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
or
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
Now we update watermarks atomically like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks() (wm values aren't written yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks() (actual wm values aren't written
yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
So this patch moves all of the watermark writes into the right place;
inside of the vblank evasion where we update all of the registers for
each plane. While this patch doesn't fix everything, it does allow us to
update the watermark values in the way the hardware expects us to.
Changes since original patch series:
- Remove mutex_lock/mutex_unlock since they don't do anything and we're
not touching global state
- Move skl_write_cursor_wm/skl_write_plane_wm functions into
intel_pm.c, make externally visible
- Add skl_write_plane_wm calls to skl_update_plane
- Fix conditional for for loop in skl_write_plane_wm (level < max_level
should be level <= max_level)
- Make diagram in commit more accurate to what's actually happening
- Add Fixes:
Changes since v1:
- Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
then just Skylake
- Update description to make it clear this patch doesn't fix everything
- Check if pipes were actually changed before writing watermarks
Changes since v2:
- Write PIPE_WM_LINETIME during vblank evasion
Changes since v3:
- Rebase against new SAGV patch changes
Changes since v4:
- Add a parameter to choose what skl_wm_values struct to use when
writing new plane watermarks
Changes since v5:
- Remove cursor ddb entry write in skl_write_cursor_wm(), defer until
patch 6
- Write WM_LINETIME in intel_begin_crtc_commit()
Changes since v6:
- Remove redundant dirty_pipes check in skl_write_plane_wm (we check
this in all places where we call this function, and it was supposed
to have been removed earlier anyway)
- In i9xx_update_cursor(), use dev_priv->info.gen >= 9 instead of
IS_GEN9(dev_priv). We do this everywhere else and I'd imagine this
needs to be done for gen10 as well
Changes since v7:
- Fix rebase fail (unused variable obj)
- Make struct skl_wm_values *wm const
- Fix indenting
- Use INTEL_GEN() instead of dev_priv->info.gen
Changes since v8:
- Don't forget calls to skl_write_plane_wm() when disabling planes
- Use INTEL_GEN(), not INTEL_INFO()->gen in intel_begin_crtc_commit()
Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
Signed-off-by: Lyude <cpaul@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
2016-08-22 16:50:08 +00:00
|
|
|
{
|
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
drm/i915/skl: Update plane watermarks atomically during plane updates
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"armed", which is done by writing to the PLANE_SURF (or in the case of
cursor planes, the CURBASE register) register.
With this in mind, up until now we've been updating watermarks on skl
like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
or
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
Now we update watermarks atomically like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks() (wm values aren't written yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks() (actual wm values aren't written
yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
So this patch moves all of the watermark writes into the right place;
inside of the vblank evasion where we update all of the registers for
each plane. While this patch doesn't fix everything, it does allow us to
update the watermark values in the way the hardware expects us to.
Changes since original patch series:
- Remove mutex_lock/mutex_unlock since they don't do anything and we're
not touching global state
- Move skl_write_cursor_wm/skl_write_plane_wm functions into
intel_pm.c, make externally visible
- Add skl_write_plane_wm calls to skl_update_plane
- Fix conditional for for loop in skl_write_plane_wm (level < max_level
should be level <= max_level)
- Make diagram in commit more accurate to what's actually happening
- Add Fixes:
Changes since v1:
- Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
then just Skylake
- Update description to make it clear this patch doesn't fix everything
- Check if pipes were actually changed before writing watermarks
Changes since v2:
- Write PIPE_WM_LINETIME during vblank evasion
Changes since v3:
- Rebase against new SAGV patch changes
Changes since v4:
- Add a parameter to choose what skl_wm_values struct to use when
writing new plane watermarks
Changes since v5:
- Remove cursor ddb entry write in skl_write_cursor_wm(), defer until
patch 6
- Write WM_LINETIME in intel_begin_crtc_commit()
Changes since v6:
- Remove redundant dirty_pipes check in skl_write_plane_wm (we check
this in all places where we call this function, and it was supposed
to have been removed earlier anyway)
- In i9xx_update_cursor(), use dev_priv->info.gen >= 9 instead of
IS_GEN9(dev_priv). We do this everywhere else and I'd imagine this
needs to be done for gen10 as well
Changes since v7:
- Fix rebase fail (unused variable obj)
- Make struct skl_wm_values *wm const
- Fix indenting
- Use INTEL_GEN() instead of dev_priv->info.gen
Changes since v8:
- Don't forget calls to skl_write_plane_wm() when disabling planes
- Use INTEL_GEN(), not INTEL_INFO()->gen in intel_begin_crtc_commit()
Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
Signed-off-by: Lyude <cpaul@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
2016-08-22 16:50:08 +00:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
|
|
|
|
for (level = 0; level <= max_level; level++) {
|
2016-10-18 18:09:49 +00:00
|
|
|
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
|
|
|
|
&wm->wm[level]);
|
drm/i915/skl: Update plane watermarks atomically during plane updates
Thanks to Ville for suggesting this as a potential solution to pipe
underruns on Skylake.
On Skylake all of the registers for configuring planes, including the
registers for configuring their watermarks, are double buffered. New
values written to them won't take effect until said registers are
"armed", which is done by writing to the PLANE_SURF (or in the case of
cursor planes, the CURBASE register) register.
With this in mind, up until now we've been updating watermarks on skl
like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
or
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks()
- {vblank happens; new watermarks + old plane values => underrun }
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- end vblank evasion
}
Now we update watermarks atomically like this:
non-modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- intel_pre_plane_update:
- intel_update_watermarks() (wm values aren't written yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
modeset {
- calculate (during atomic check phase)
- finish_atomic_commit:
- crtc_enable:
- intel_update_watermarks() (actual wm values aren't written
yet)
- drm_atomic_helper_commit_planes_on_crtc:
- start vblank evasion
- write new plane registers
- write new wm values
- end vblank evasion
}
So this patch moves all of the watermark writes into the right place;
inside of the vblank evasion where we update all of the registers for
each plane. While this patch doesn't fix everything, it does allow us to
update the watermark values in the way the hardware expects us to.
Changes since original patch series:
- Remove mutex_lock/mutex_unlock since they don't do anything and we're
not touching global state
- Move skl_write_cursor_wm/skl_write_plane_wm functions into
intel_pm.c, make externally visible
- Add skl_write_plane_wm calls to skl_update_plane
- Fix conditional for for loop in skl_write_plane_wm (level < max_level
should be level <= max_level)
- Make diagram in commit more accurate to what's actually happening
- Add Fixes:
Changes since v1:
- Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more
then just Skylake
- Update description to make it clear this patch doesn't fix everything
- Check if pipes were actually changed before writing watermarks
Changes since v2:
- Write PIPE_WM_LINETIME during vblank evasion
Changes since v3:
- Rebase against new SAGV patch changes
Changes since v4:
- Add a parameter to choose what skl_wm_values struct to use when
writing new plane watermarks
Changes since v5:
- Remove cursor ddb entry write in skl_write_cursor_wm(), defer until
patch 6
- Write WM_LINETIME in intel_begin_crtc_commit()
Changes since v6:
- Remove redundant dirty_pipes check in skl_write_plane_wm (we check
this in all places where we call this function, and it was supposed
to have been removed earlier anyway)
- In i9xx_update_cursor(), use dev_priv->info.gen >= 9 instead of
IS_GEN9(dev_priv). We do this everywhere else and I'd imagine this
needs to be done for gen10 as well
Changes since v7:
- Fix rebase fail (unused variable obj)
- Make struct skl_wm_values *wm const
- Fix indenting
- Use INTEL_GEN() instead of dev_priv->info.gen
Changes since v8:
- Don't forget calls to skl_write_plane_wm() when disabling planes
- Use INTEL_GEN(), not INTEL_INFO()->gen in intel_begin_crtc_commit()
Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
Signed-off-by: Lyude <cpaul@redhat.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
Link: http://patchwork.freedesktop.org/patch/msgid/1471884608-10671-1-git-send-email-cpaul@redhat.com
2016-08-22 16:50:08 +00:00
|
|
|
}
|
2016-10-18 18:09:49 +00:00
|
|
|
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
|
2014-11-04 17:07:00 +00:00
|
|
|
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
|
2016-10-18 18:09:49 +00:00
|
|
|
&ddb->plane[pipe][PLANE_CURSOR]);
|
2014-11-04 17:06:42 +00:00
|
|
|
}
|
|
|
|
|
2016-10-14 21:31:56 +00:00
|
|
|
bool skl_wm_level_equals(const struct skl_wm_level *l1,
|
|
|
|
const struct skl_wm_level *l2)
|
|
|
|
{
|
|
|
|
if (l1->plane_en != l2->plane_en)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/* If both planes aren't enabled, the rest shouldn't matter */
|
|
|
|
if (!l1->plane_en)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return (l1->plane_res_l == l2->plane_res_l &&
|
|
|
|
l1->plane_res_b == l2->plane_res_b);
|
|
|
|
}
|
|
|
|
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
|
|
|
|
const struct skl_ddb_entry *b)
|
2014-11-04 17:07:02 +00:00
|
|
|
{
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
return a->start < b->end && b->start < a->end;
|
2014-11-04 17:07:02 +00:00
|
|
|
}
|
|
|
|
|
2016-11-08 12:55:35 +00:00
|
|
|
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
|
|
|
|
const struct skl_ddb_entry *ddb,
|
|
|
|
int ignore)
|
2014-11-04 17:07:02 +00:00
|
|
|
{
|
2016-09-15 14:46:35 +00:00
|
|
|
int i;
|
2014-11-04 17:07:02 +00:00
|
|
|
|
2016-11-08 12:55:35 +00:00
|
|
|
for (i = 0; i < I915_MAX_PIPES; i++)
|
|
|
|
if (i != ignore && entries[i] &&
|
|
|
|
skl_ddb_entries_overlap(ddb, entries[i]))
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
return true;
|
2014-11-04 17:07:02 +00:00
|
|
|
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
return false;
|
2014-11-04 17:07:02 +00:00
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
|
2016-10-26 13:41:36 +00:00
|
|
|
const struct skl_pipe_wm *old_pipe_wm,
|
2016-05-12 14:06:08 +00:00
|
|
|
struct skl_pipe_wm *pipe_wm, /* out */
|
2016-10-26 13:41:36 +00:00
|
|
|
struct skl_ddb_allocation *ddb, /* out */
|
2016-05-12 14:06:08 +00:00
|
|
|
bool *changed /* out */)
|
2014-11-04 17:06:42 +00:00
|
|
|
{
|
2016-05-12 14:06:06 +00:00
|
|
|
struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
|
2016-05-12 14:06:08 +00:00
|
|
|
int ret;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-10-26 13:41:36 +00:00
|
|
|
if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
|
2016-05-12 14:06:08 +00:00
|
|
|
*changed = false;
|
|
|
|
else
|
|
|
|
*changed = true;
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-05-12 14:06:08 +00:00
|
|
|
return 0;
|
2014-11-04 17:06:42 +00:00
|
|
|
}
|
|
|
|
|
2016-06-27 23:42:44 +00:00
|
|
|
static uint32_t
|
|
|
|
pipes_modified(struct drm_atomic_state *state)
|
|
|
|
{
|
|
|
|
struct drm_crtc *crtc;
|
|
|
|
struct drm_crtc_state *cstate;
|
|
|
|
uint32_t i, ret = 0;
|
|
|
|
|
|
|
|
for_each_crtc_in_state(state, crtc, cstate, i)
|
|
|
|
ret |= drm_crtc_mask(crtc);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-10-04 09:29:17 +00:00
|
|
|
static int
|
2016-09-29 19:36:48 +00:00
|
|
|
skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
|
|
|
|
{
|
|
|
|
struct drm_atomic_state *state = cstate->base.state;
|
|
|
|
struct drm_device *dev = state->dev;
|
|
|
|
struct drm_crtc *crtc = cstate->base.crtc;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
|
struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
|
|
|
|
struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
|
|
|
|
struct drm_plane_state *plane_state;
|
|
|
|
struct drm_plane *plane;
|
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
|
|
|
|
WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
|
|
|
|
|
2016-10-26 13:41:30 +00:00
|
|
|
drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id = to_intel_plane(plane)->id;
|
2016-09-29 19:36:48 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
|
|
|
|
&new_ddb->plane[pipe][plane_id]) &&
|
|
|
|
skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
|
|
|
|
&new_ddb->y_plane[pipe][plane_id]))
|
2016-09-29 19:36:48 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
plane_state = drm_atomic_get_plane_state(state, plane);
|
|
|
|
if (IS_ERR(plane_state))
|
|
|
|
return PTR_ERR(plane_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:03 +00:00
|
|
|
static int
|
|
|
|
skl_compute_ddb(struct drm_atomic_state *state)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = state->dev;
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
|
struct intel_crtc *intel_crtc;
|
2016-05-12 22:11:40 +00:00
|
|
|
struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
|
2016-06-27 23:42:44 +00:00
|
|
|
uint32_t realloc_pipes = pipes_modified(state);
|
2016-05-12 14:06:03 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If this is our first atomic update following hardware readout,
|
|
|
|
* we can't trust the DDB that the BIOS programmed for us. Let's
|
|
|
|
* pretend that all pipes switched active status so that we'll
|
|
|
|
* ensure a full DDB recompute.
|
|
|
|
*/
|
2016-06-17 20:42:18 +00:00
|
|
|
if (dev_priv->wm.distrust_bios_wm) {
|
|
|
|
ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
|
|
|
|
state->acquire_ctx);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-05-12 14:06:03 +00:00
|
|
|
intel_state->active_pipe_changes = ~0;
|
|
|
|
|
2016-06-17 20:42:18 +00:00
|
|
|
/*
|
|
|
|
* We usually only initialize intel_state->active_crtcs if we
|
|
|
|
* we're doing a modeset; make sure this field is always
|
|
|
|
* initialized during the sanitization process that happens
|
|
|
|
* on the first commit too.
|
|
|
|
*/
|
|
|
|
if (!intel_state->modeset)
|
|
|
|
intel_state->active_crtcs = dev_priv->active_crtcs;
|
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:03 +00:00
|
|
|
/*
|
|
|
|
* If the modeset changes which CRTC's are active, we need to
|
|
|
|
* recompute the DDB allocation for *all* active pipes, even
|
|
|
|
* those that weren't otherwise being modified in any way by this
|
|
|
|
* atomic commit. Due to the shrinking of the per-pipe allocations
|
|
|
|
* when new active CRTC's are added, it's possible for a pipe that
|
|
|
|
* we were already using and aren't changing at all here to suddenly
|
|
|
|
* become invalid if its DDB needs exceeds its new allocation.
|
|
|
|
*
|
|
|
|
* Note that if we wind up doing a full DDB recompute, we can't let
|
|
|
|
* any other display updates race with this transaction, so we need
|
|
|
|
* to grab the lock on *all* CRTC's.
|
|
|
|
*/
|
2016-05-12 22:11:40 +00:00
|
|
|
if (intel_state->active_pipe_changes) {
|
2016-05-12 14:06:03 +00:00
|
|
|
realloc_pipes = ~0;
|
2016-05-12 22:11:40 +00:00
|
|
|
intel_state->wm_results.dirty_pipes = ~0;
|
|
|
|
}
|
2016-05-12 14:06:03 +00:00
|
|
|
|
2016-10-04 17:37:32 +00:00
|
|
|
/*
|
|
|
|
* We're not recomputing for the pipes not included in the commit, so
|
|
|
|
* make sure we start with the current state.
|
|
|
|
*/
|
|
|
|
memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
|
|
|
|
|
2016-05-12 14:06:03 +00:00
|
|
|
for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
|
|
|
|
struct intel_crtc_state *cstate;
|
|
|
|
|
|
|
|
cstate = intel_atomic_get_crtc_state(state, intel_crtc);
|
|
|
|
if (IS_ERR(cstate))
|
|
|
|
return PTR_ERR(cstate);
|
|
|
|
|
2016-05-12 22:11:40 +00:00
|
|
|
ret = skl_allocate_pipe_ddb(cstate, ddb);
|
2016-05-12 14:06:03 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-08-17 19:55:57 +00:00
|
|
|
|
2016-09-29 19:36:48 +00:00
|
|
|
ret = skl_ddb_add_affected_planes(cstate);
|
2016-08-17 19:55:57 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2016-05-12 14:06:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-08-17 19:55:55 +00:00
|
|
|
static void
|
|
|
|
skl_copy_wm_for_pipe(struct skl_wm_values *dst,
|
|
|
|
struct skl_wm_values *src,
|
|
|
|
enum pipe pipe)
|
|
|
|
{
|
|
|
|
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
|
|
|
|
sizeof(dst->ddb.y_plane[pipe]));
|
|
|
|
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
|
|
|
|
sizeof(dst->ddb.plane[pipe]));
|
|
|
|
}
|
|
|
|
|
2016-10-14 21:31:54 +00:00
|
|
|
static void
|
|
|
|
skl_print_wm_changes(const struct drm_atomic_state *state)
|
|
|
|
{
|
|
|
|
const struct drm_device *dev = state->dev;
|
|
|
|
const struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
const struct intel_atomic_state *intel_state =
|
|
|
|
to_intel_atomic_state(state);
|
|
|
|
const struct drm_crtc *crtc;
|
|
|
|
const struct drm_crtc_state *cstate;
|
|
|
|
const struct intel_plane *intel_plane;
|
|
|
|
const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
|
|
|
|
const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
|
2016-11-01 11:04:10 +00:00
|
|
|
int i;
|
2016-10-14 21:31:54 +00:00
|
|
|
|
|
|
|
for_each_crtc_in_state(state, crtc, cstate, i) {
|
2016-11-01 11:04:10 +00:00
|
|
|
const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
2016-10-14 21:31:54 +00:00
|
|
|
|
2016-11-01 11:04:10 +00:00
|
|
|
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id = intel_plane->id;
|
2016-10-14 21:31:54 +00:00
|
|
|
const struct skl_ddb_entry *old, *new;
|
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
old = &old_ddb->plane[pipe][plane_id];
|
|
|
|
new = &new_ddb->plane[pipe][plane_id];
|
2016-10-14 21:31:54 +00:00
|
|
|
|
|
|
|
if (skl_ddb_entry_equal(old, new))
|
|
|
|
continue;
|
|
|
|
|
2016-11-01 11:04:10 +00:00
|
|
|
DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
|
|
|
|
intel_plane->base.base.id,
|
|
|
|
intel_plane->base.name,
|
|
|
|
old->start, old->end,
|
|
|
|
new->start, new->end);
|
2016-10-14 21:31:54 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-12 14:06:03 +00:00
|
|
|
static int
|
|
|
|
skl_compute_wm(struct drm_atomic_state *state)
|
|
|
|
{
|
|
|
|
struct drm_crtc *crtc;
|
|
|
|
struct drm_crtc_state *cstate;
|
2016-05-12 22:11:40 +00:00
|
|
|
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
|
|
|
struct skl_wm_values *results = &intel_state->wm_results;
|
|
|
|
struct skl_pipe_wm *pipe_wm;
|
2016-05-12 14:06:03 +00:00
|
|
|
bool changed = false;
|
2016-05-12 22:11:40 +00:00
|
|
|
int ret, i;
|
2016-05-12 14:06:03 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If this transaction isn't actually touching any CRTC's, don't
|
|
|
|
* bother with watermark calculation. Note that if we pass this
|
|
|
|
* test, we're guaranteed to hold at least one CRTC state mutex,
|
|
|
|
* which means we can safely use values like dev_priv->active_crtcs
|
|
|
|
* since any racing commits that want to update them would need to
|
|
|
|
* hold _all_ CRTC state mutexes.
|
|
|
|
*/
|
|
|
|
for_each_crtc_in_state(state, crtc, cstate, i)
|
|
|
|
changed = true;
|
|
|
|
if (!changed)
|
|
|
|
return 0;
|
|
|
|
|
2016-05-12 22:11:40 +00:00
|
|
|
/* Clear all dirty flags */
|
|
|
|
results->dirty_pipes = 0;
|
|
|
|
|
2016-05-12 14:06:03 +00:00
|
|
|
ret = skl_compute_ddb(state);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-05-12 22:11:40 +00:00
|
|
|
/*
|
|
|
|
* Calculate WM's for all pipes that are part of this transaction.
|
|
|
|
* Note that the DDB allocation above may have added more CRTC's that
|
|
|
|
* weren't otherwise being modified (and set bits in dirty_pipes) if
|
|
|
|
* pipe allocations had to change.
|
|
|
|
*
|
|
|
|
* FIXME: Now that we're doing this in the atomic check phase, we
|
|
|
|
* should allow skl_update_pipe_wm() to return failure in cases where
|
|
|
|
* no suitable watermark values can be found.
|
|
|
|
*/
|
|
|
|
for_each_crtc_in_state(state, crtc, cstate, i) {
|
|
|
|
struct intel_crtc_state *intel_cstate =
|
|
|
|
to_intel_crtc_state(cstate);
|
2016-10-26 13:41:36 +00:00
|
|
|
const struct skl_pipe_wm *old_pipe_wm =
|
|
|
|
&to_intel_crtc_state(crtc->state)->wm.skl.optimal;
|
2016-05-12 22:11:40 +00:00
|
|
|
|
|
|
|
pipe_wm = &intel_cstate->wm.skl.optimal;
|
2016-10-26 13:41:36 +00:00
|
|
|
ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
|
|
|
|
&results->ddb, &changed);
|
2016-05-12 22:11:40 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (changed)
|
|
|
|
results->dirty_pipes |= drm_crtc_mask(crtc);
|
|
|
|
|
|
|
|
if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
|
|
|
|
/* This pipe's WM's did not change */
|
|
|
|
continue;
|
|
|
|
|
|
|
|
intel_cstate->update_wm_pre = true;
|
|
|
|
}
|
|
|
|
|
2016-10-14 21:31:54 +00:00
|
|
|
skl_print_wm_changes(state);
|
|
|
|
|
2016-05-12 14:06:03 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-08 12:55:32 +00:00
|
|
|
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc_state *cstate)
|
|
|
|
{
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
|
|
|
struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
|
2016-11-08 12:55:33 +00:00
|
|
|
const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
|
2016-11-08 12:55:32 +00:00
|
|
|
enum pipe pipe = crtc->pipe;
|
2016-11-22 16:01:58 +00:00
|
|
|
enum plane_id plane_id;
|
2016-11-08 12:55:33 +00:00
|
|
|
|
|
|
|
if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
|
|
|
|
return;
|
2016-11-08 12:55:32 +00:00
|
|
|
|
|
|
|
I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
|
2016-11-08 12:55:33 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
for_each_plane_id_on_crtc(crtc, plane_id) {
|
|
|
|
if (plane_id != PLANE_CURSOR)
|
|
|
|
skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
|
|
|
|
ddb, plane_id);
|
|
|
|
else
|
|
|
|
skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
|
|
|
|
ddb);
|
|
|
|
}
|
2016-11-08 12:55:32 +00:00
|
|
|
}
|
|
|
|
|
2016-11-08 12:55:33 +00:00
|
|
|
static void skl_initial_wm(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc_state *cstate)
|
2014-11-04 17:06:42 +00:00
|
|
|
{
|
2016-11-08 12:55:33 +00:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
|
2016-10-31 20:37:03 +00:00
|
|
|
struct drm_device *dev = intel_crtc->base.dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-11-08 12:55:33 +00:00
|
|
|
struct skl_wm_values *results = &state->wm_results;
|
2016-08-17 19:55:55 +00:00
|
|
|
struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
2015-07-21 17:42:53 +00:00
|
|
|
|
2016-10-31 20:37:03 +00:00
|
|
|
if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
|
2014-11-04 17:06:42 +00:00
|
|
|
return;
|
|
|
|
|
2016-05-12 22:11:40 +00:00
|
|
|
mutex_lock(&dev_priv->wm.wm_mutex);
|
2014-11-04 17:06:42 +00:00
|
|
|
|
2016-11-08 12:55:33 +00:00
|
|
|
if (cstate->base.active_changed)
|
|
|
|
skl_atomic_update_crtc_wm(state, cstate);
|
drm/i915/skl: Update DDB values atomically with wms/plane attrs
Now that we can hook into update_crtcs and control the order in which we
update CRTCs at each modeset, we can finish the final step of fixing
Skylake's watermark handling by performing DDB updates at the same time
as plane updates and watermark updates.
The first major change in this patch is skl_update_crtcs(), which
handles ensuring that we order each CRTC update in our atomic commits
properly so that they honor the DDB flush order.
The second major change in this patch is the order in which we flush the
pipes. While the previous order may have worked, it can't be used in
this approach since it no longer will do the right thing. For example,
using the old ddb flush order:
We have pipes A, B, and C enabled, and we're disabling C. Initial ddb
allocation looks like this:
| A | B |xxxxxxx|
Since we're performing the ddb updates after performing any CRTC
disablements in intel_atomic_commit_tail(), the space to the right of
pipe B is unallocated.
1. Flush pipes with new allocation contained into old space. None
apply, so we skip this
2. Flush pipes having their allocation reduced, but overlapping with a
previous allocation. None apply, so we also skip this
3. Flush pipes that got more space allocated. This applies to A and B,
giving us the following update order: A, B
This is wrong, since updating pipe A first will cause it to overlap with
B and potentially burst into flames. Our new order (see the code
comments for details) would update the pipes in the proper order: B, A.
As well, we calculate the order for each DDB update during the check
phase, and reference it later in the commit phase when we hit
skl_update_crtcs().
This long overdue patch fixes the rest of the underruns on Skylake.
Changes since v1:
- Add skl_ddb_entry_write() for cursor into skl_write_cursor_wm()
Changes since v2:
- Use the method for updating CRTCs that Ville suggested
- In skl_update_wm(), only copy the watermarks for the crtc that was
passed to us
Changes since v3:
- Small comment fix in skl_ddb_allocation_overlaps()
Changes since v4:
- Remove the second loop in intel_update_crtcs() and use Ville's
suggestion for updating the ddb allocations in the right order
- Get rid of the second loop and just use the ddb state as it updates
to determine what order to update everything in (thanks for the
suggestion Ville)
- Simplify skl_ddb_allocation_overlaps()
- Split actual overlap checking into it's own helper
Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
[omitting CC for stable, since this patch will need to be changed for
such backports first]
Testcase: kms_cursor_legacy
Testcase: plane-all-modeset-transition
Signed-off-by: Lyude <cpaul@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1471961565-28540-2-git-send-email-cpaul@redhat.com
2016-08-24 05:48:10 +00:00
|
|
|
|
|
|
|
skl_copy_wm_for_pipe(hw_vals, results, pipe);
|
2016-05-12 22:11:40 +00:00
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->wm.wm_mutex);
|
2014-11-04 17:06:42 +00:00
|
|
|
}
|
|
|
|
|
2016-01-14 12:53:35 +00:00
|
|
|
static void ilk_compute_wm_config(struct drm_device *dev,
|
|
|
|
struct intel_wm_config *config)
|
|
|
|
{
|
|
|
|
struct intel_crtc *crtc;
|
|
|
|
|
|
|
|
/* Compute the currently _active_ config */
|
|
|
|
for_each_intel_crtc(dev, crtc) {
|
|
|
|
const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
|
|
|
|
|
|
|
|
if (!wm->pipe_enabled)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
config->sprites_enabled |= wm->sprites_enabled;
|
|
|
|
config->sprites_scaled |= wm->sprites_scaled;
|
|
|
|
config->num_pipes_active++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
|
2013-05-31 13:08:35 +00:00
|
|
|
{
|
2016-07-05 09:40:23 +00:00
|
|
|
struct drm_device *dev = &dev_priv->drm;
|
2015-09-24 22:53:14 +00:00
|
|
|
struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_maximums max;
|
2016-01-14 12:53:35 +00:00
|
|
|
struct intel_wm_config config = {};
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_values results = {};
|
2013-08-06 19:24:04 +00:00
|
|
|
enum intel_ddb_partitioning partitioning;
|
2015-10-08 22:28:25 +00:00
|
|
|
|
2016-01-14 12:53:35 +00:00
|
|
|
ilk_compute_wm_config(dev, &config);
|
|
|
|
|
|
|
|
ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
|
|
|
|
ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
|
2013-10-09 16:17:59 +00:00
|
|
|
|
|
|
|
/* 5/6 split only in single pipe config on IVB+ */
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 7 &&
|
2016-01-14 12:53:35 +00:00
|
|
|
config.num_pipes_active == 1 && config.sprites_enabled) {
|
|
|
|
ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
|
|
|
|
ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
|
2013-10-09 16:17:57 +00:00
|
|
|
|
2013-12-17 12:46:36 +00:00
|
|
|
best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
|
2013-05-31 13:19:21 +00:00
|
|
|
} else {
|
2013-10-09 16:17:58 +00:00
|
|
|
best_lp_wm = &lp_wm_1_2;
|
2013-05-31 13:19:21 +00:00
|
|
|
}
|
|
|
|
|
2013-10-09 16:17:58 +00:00
|
|
|
partitioning = (best_lp_wm == &lp_wm_1_2) ?
|
2013-08-06 19:24:04 +00:00
|
|
|
INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
|
2013-05-31 13:08:35 +00:00
|
|
|
|
2013-12-17 12:46:36 +00:00
|
|
|
ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
|
2013-10-09 16:18:03 +00:00
|
|
|
|
2013-12-17 12:46:36 +00:00
|
|
|
ilk_write_wm_values(dev_priv, &results);
|
2013-05-09 19:55:50 +00:00
|
|
|
}
|
|
|
|
|
2016-11-08 12:55:32 +00:00
|
|
|
static void ilk_initial_watermarks(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc_state *cstate)
|
2015-09-24 22:53:14 +00:00
|
|
|
{
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
|
2015-09-24 22:53:14 +00:00
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
mutex_lock(&dev_priv->wm.wm_mutex);
|
2016-05-12 14:05:55 +00:00
|
|
|
intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
ilk_program_watermarks(dev_priv);
|
|
|
|
mutex_unlock(&dev_priv->wm.wm_mutex);
|
|
|
|
}
|
2016-01-19 19:43:04 +00:00
|
|
|
|
2016-11-08 12:55:32 +00:00
|
|
|
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
|
|
|
|
struct intel_crtc_state *cstate)
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
|
2016-01-19 19:43:04 +00:00
|
|
|
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
mutex_lock(&dev_priv->wm.wm_mutex);
|
|
|
|
if (cstate->wm.need_postvbl_update) {
|
2016-05-12 14:05:55 +00:00
|
|
|
intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
ilk_program_watermarks(dev_priv);
|
|
|
|
}
|
|
|
|
mutex_unlock(&dev_priv->wm.wm_mutex);
|
2015-09-24 22:53:14 +00:00
|
|
|
}
|
|
|
|
|
2016-10-18 18:09:49 +00:00
|
|
|
static inline void skl_wm_level_from_reg_val(uint32_t val,
|
|
|
|
struct skl_wm_level *level)
|
2014-11-04 17:06:45 +00:00
|
|
|
{
|
2016-10-18 18:09:49 +00:00
|
|
|
level->plane_en = val & PLANE_WM_EN;
|
|
|
|
level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
|
|
|
|
level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
|
|
|
|
PLANE_WM_LINES_MASK;
|
2014-11-04 17:06:45 +00:00
|
|
|
}
|
|
|
|
|
2016-10-14 21:31:55 +00:00
|
|
|
void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
|
|
|
|
struct skl_pipe_wm *out)
|
2014-11-04 17:06:45 +00:00
|
|
|
{
|
2016-11-22 16:01:58 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
2014-11-04 17:06:45 +00:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
2016-11-22 16:01:58 +00:00
|
|
|
int level, max_level;
|
|
|
|
enum plane_id plane_id;
|
2016-10-18 18:09:49 +00:00
|
|
|
uint32_t val;
|
2014-11-04 17:06:45 +00:00
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
max_level = ilk_wm_max_level(dev_priv);
|
2014-11-04 17:06:45 +00:00
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
|
|
|
|
struct skl_plane_wm *wm = &out->planes[plane_id];
|
2014-11-04 17:06:45 +00:00
|
|
|
|
2016-10-18 18:09:49 +00:00
|
|
|
for (level = 0; level <= max_level; level++) {
|
2016-11-22 16:01:58 +00:00
|
|
|
if (plane_id != PLANE_CURSOR)
|
|
|
|
val = I915_READ(PLANE_WM(pipe, plane_id, level));
|
2016-10-18 18:09:49 +00:00
|
|
|
else
|
|
|
|
val = I915_READ(CUR_WM(pipe, level));
|
2014-11-04 17:06:45 +00:00
|
|
|
|
2016-10-18 18:09:49 +00:00
|
|
|
skl_wm_level_from_reg_val(val, &wm->wm[level]);
|
2014-11-04 17:06:45 +00:00
|
|
|
}
|
|
|
|
|
2016-11-22 16:01:58 +00:00
|
|
|
if (plane_id != PLANE_CURSOR)
|
|
|
|
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
|
2016-10-18 18:09:49 +00:00
|
|
|
else
|
|
|
|
val = I915_READ(CUR_WM_TRANS(pipe));
|
|
|
|
|
|
|
|
skl_wm_level_from_reg_val(val, &wm->trans_wm);
|
2014-11-04 17:06:45 +00:00
|
|
|
}
|
|
|
|
|
2016-10-18 18:09:49 +00:00
|
|
|
if (!intel_crtc->active)
|
|
|
|
return;
|
2015-09-24 22:53:15 +00:00
|
|
|
|
2016-10-14 21:31:55 +00:00
|
|
|
out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
|
2014-11-04 17:06:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void skl_wm_get_hw_state(struct drm_device *dev)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2016-10-14 21:31:55 +00:00
|
|
|
struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
|
2014-11-04 17:06:49 +00:00
|
|
|
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
|
2014-11-04 17:06:45 +00:00
|
|
|
struct drm_crtc *crtc;
|
2016-10-14 21:31:55 +00:00
|
|
|
struct intel_crtc *intel_crtc;
|
|
|
|
struct intel_crtc_state *cstate;
|
2014-11-04 17:06:45 +00:00
|
|
|
|
2014-11-04 17:06:49 +00:00
|
|
|
skl_ddb_get_hw_state(dev_priv, ddb);
|
2016-10-14 21:31:55 +00:00
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
|
|
|
intel_crtc = to_intel_crtc(crtc);
|
|
|
|
cstate = to_intel_crtc_state(crtc->state);
|
|
|
|
|
|
|
|
skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
|
|
|
|
|
2016-10-26 13:41:36 +00:00
|
|
|
if (intel_crtc->active)
|
2016-10-14 21:31:55 +00:00
|
|
|
hw->dirty_pipes |= drm_crtc_mask(crtc);
|
|
|
|
}
|
2016-05-12 14:05:57 +00:00
|
|
|
|
2016-05-12 14:06:02 +00:00
|
|
|
if (dev_priv->active_crtcs) {
|
|
|
|
/* Fully recompute DDB on first atomic commit */
|
|
|
|
dev_priv->wm.distrust_bios_wm = true;
|
|
|
|
} else {
|
|
|
|
/* Easy/common case; just sanitize DDB now if everything off */
|
|
|
|
memset(ddb, 0, sizeof(*ddb));
|
|
|
|
}
|
2014-11-04 17:06:45 +00:00
|
|
|
}
|
|
|
|
|
2013-10-14 11:55:24 +00:00
|
|
|
static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_values *hw = &dev_priv->wm.hw;
|
2013-10-14 11:55:24 +00:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2015-09-24 22:53:15 +00:00
|
|
|
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
|
2016-05-12 14:05:55 +00:00
|
|
|
struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
|
2013-10-14 11:55:24 +00:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 13:33:26 +00:00
|
|
|
static const i915_reg_t wm0_pipe_reg[] = {
|
2013-10-14 11:55:24 +00:00
|
|
|
[PIPE_A] = WM0_PIPEA_ILK,
|
|
|
|
[PIPE_B] = WM0_PIPEB_ILK,
|
|
|
|
[PIPE_C] = WM0_PIPEC_IVB,
|
|
|
|
};
|
|
|
|
|
|
|
|
hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
|
2016-10-13 10:03:00 +00:00
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
2013-12-05 13:51:36 +00:00
|
|
|
hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
|
2013-10-14 11:55:24 +00:00
|
|
|
|
2016-05-13 14:55:17 +00:00
|
|
|
memset(active, 0, sizeof(*active));
|
|
|
|
|
2015-03-09 17:19:24 +00:00
|
|
|
active->pipe_enabled = intel_crtc->active;
|
2014-03-07 16:32:09 +00:00
|
|
|
|
|
|
|
if (active->pipe_enabled) {
|
2013-10-14 11:55:24 +00:00
|
|
|
u32 tmp = hw->wm_pipe[pipe];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For active pipes LP0 watermark is marked as
|
|
|
|
* enabled, and LP1+ watermaks as disabled since
|
|
|
|
* we can't really reverse compute them in case
|
|
|
|
* multiple pipes are active.
|
|
|
|
*/
|
|
|
|
active->wm[0].enable = true;
|
|
|
|
active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
|
|
|
|
active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
|
|
|
|
active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
|
|
|
|
active->linetime = hw->wm_linetime[pipe];
|
|
|
|
} else {
|
2016-10-13 10:03:10 +00:00
|
|
|
int level, max_level = ilk_wm_max_level(dev_priv);
|
2013-10-14 11:55:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For inactive pipes, all watermark levels
|
|
|
|
* should be marked as enabled but zeroed,
|
|
|
|
* which is what we'd compute them to.
|
|
|
|
*/
|
|
|
|
for (level = 0; level <= max_level; level++)
|
|
|
|
active->wm[level].enable = true;
|
|
|
|
}
|
2015-09-24 22:53:15 +00:00
|
|
|
|
|
|
|
intel_crtc->wm.active.ilk = *active;
|
2013-10-14 11:55:24 +00:00
|
|
|
}
|
|
|
|
|
2015-06-24 19:00:03 +00:00
|
|
|
#define _FW_WM(value, plane) \
|
|
|
|
(((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
|
|
|
|
#define _FW_WM_VLV(value, plane) \
|
|
|
|
(((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
|
|
|
|
|
|
|
|
static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
|
|
|
|
struct vlv_wm_values *wm)
|
|
|
|
{
|
|
|
|
enum pipe pipe;
|
|
|
|
uint32_t tmp;
|
|
|
|
|
|
|
|
for_each_pipe(dev_priv, pipe) {
|
|
|
|
tmp = I915_READ(VLV_DDL(pipe));
|
|
|
|
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->ddl[pipe].plane[PLANE_PRIMARY] =
|
2015-06-24 19:00:03 +00:00
|
|
|
(tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->ddl[pipe].plane[PLANE_CURSOR] =
|
2015-06-24 19:00:03 +00:00
|
|
|
(tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->ddl[pipe].plane[PLANE_SPRITE0] =
|
2015-06-24 19:00:03 +00:00
|
|
|
(tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->ddl[pipe].plane[PLANE_SPRITE1] =
|
2015-06-24 19:00:03 +00:00
|
|
|
(tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp = I915_READ(DSPFW1);
|
|
|
|
wm->sr.plane = _FW_WM(tmp, SR);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
tmp = I915_READ(DSPFW2);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
tmp = I915_READ(DSPFW3);
|
|
|
|
wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
|
|
|
|
|
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
|
|
tmp = I915_READ(DSPFW7_CHV);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
tmp = I915_READ(DSPFW8_CHV);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
|
|
|
|
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
tmp = I915_READ(DSPFW9_CHV);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
|
|
|
|
wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
tmp = I915_READ(DSPHOWM);
|
|
|
|
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
|
|
|
|
wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
|
|
|
|
wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
|
2015-06-24 19:00:03 +00:00
|
|
|
} else {
|
|
|
|
tmp = I915_READ(DSPFW7);
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
tmp = I915_READ(DSPHOWM);
|
|
|
|
wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
|
2016-11-28 17:37:08 +00:00
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
|
|
|
|
wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
|
|
|
|
wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
|
2015-06-24 19:00:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#undef _FW_WM
|
|
|
|
#undef _FW_WM_VLV
|
|
|
|
|
|
|
|
void vlv_wm_get_hw_state(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
|
struct vlv_wm_values *wm = &dev_priv->wm.vlv;
|
|
|
|
struct intel_plane *plane;
|
|
|
|
enum pipe pipe;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
vlv_read_wm_values(dev_priv, wm);
|
|
|
|
|
2016-11-22 16:02:01 +00:00
|
|
|
for_each_intel_plane(dev, plane)
|
|
|
|
plane->wm.fifo_size = vlv_get_fifo_size(plane);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
|
|
|
|
wm->level = VLV_WM_LEVEL_PM2;
|
|
|
|
|
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
|
|
|
|
if (val & DSP_MAXFIFO_PM5_ENABLE)
|
|
|
|
wm->level = VLV_WM_LEVEL_PM5;
|
|
|
|
|
2015-09-08 18:05:12 +00:00
|
|
|
/*
|
|
|
|
* If DDR DVFS is disabled in the BIOS, Punit
|
|
|
|
* will never ack the request. So if that happens
|
|
|
|
* assume we don't have to enable/disable DDR DVFS
|
|
|
|
* dynamically. To test that just set the REQ_ACK
|
|
|
|
* bit to poke the Punit, but don't change the
|
|
|
|
* HIGH/LOW bits so that we don't actually change
|
|
|
|
* the current state.
|
|
|
|
*/
|
2015-06-24 19:00:03 +00:00
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
|
2015-09-08 18:05:12 +00:00
|
|
|
val |= FORCE_DDR_FREQ_REQ_ACK;
|
|
|
|
vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
|
|
|
|
|
|
|
|
if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
|
|
|
|
FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
|
|
|
|
DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
|
|
|
|
"assuming DDR DVFS is disabled\n");
|
|
|
|
dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
|
|
|
|
} else {
|
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
|
|
|
|
if ((val & FORCE_DDR_HIGH_FREQ) == 0)
|
|
|
|
wm->level = VLV_WM_LEVEL_DDR_DVFS;
|
|
|
|
}
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
|
|
DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
|
2016-11-28 17:37:08 +00:00
|
|
|
pipe_name(pipe),
|
|
|
|
wm->pipe[pipe].plane[PLANE_PRIMARY],
|
|
|
|
wm->pipe[pipe].plane[PLANE_CURSOR],
|
|
|
|
wm->pipe[pipe].plane[PLANE_SPRITE0],
|
|
|
|
wm->pipe[pipe].plane[PLANE_SPRITE1]);
|
2015-06-24 19:00:03 +00:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
|
|
|
|
wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
|
|
|
|
}
|
|
|
|
|
2013-10-14 11:55:24 +00:00
|
|
|
void ilk_wm_get_hw_state(struct drm_device *dev)
|
|
|
|
{
|
2016-07-04 10:34:36 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2013-12-17 12:46:36 +00:00
|
|
|
struct ilk_wm_values *hw = &dev_priv->wm.hw;
|
2013-10-14 11:55:24 +00:00
|
|
|
struct drm_crtc *crtc;
|
|
|
|
|
2014-05-13 22:32:24 +00:00
|
|
|
for_each_crtc(dev, crtc)
|
2013-10-14 11:55:24 +00:00
|
|
|
ilk_pipe_wm_get_hw_state(crtc);
|
|
|
|
|
|
|
|
hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
|
|
|
|
hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
|
|
|
|
hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
|
|
|
|
|
|
|
|
hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
|
2016-11-16 08:55:42 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 7) {
|
2014-03-07 16:32:08 +00:00
|
|
|
hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
|
|
|
|
hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
|
|
|
|
}
|
2013-10-14 11:55:24 +00:00
|
|
|
|
2016-10-13 10:03:00 +00:00
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
2013-12-05 13:51:28 +00:00
|
|
|
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
|
|
|
|
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
|
2016-10-14 09:13:06 +00:00
|
|
|
else if (IS_IVYBRIDGE(dev_priv))
|
2013-12-05 13:51:28 +00:00
|
|
|
hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
|
|
|
|
INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
|
2013-10-14 11:55:24 +00:00
|
|
|
|
|
|
|
hw->enable_fbc_wm =
|
|
|
|
!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
|
|
|
|
}
|
|
|
|
|
2012-04-17 01:20:35 +00:00
|
|
|
/**
|
|
|
|
* intel_update_watermarks - update FIFO watermark values based on current modes
|
|
|
|
*
|
|
|
|
* Calculate watermark values for the various WM regs based on current mode
|
|
|
|
* and plane configuration.
|
|
|
|
*
|
|
|
|
* There are several cases to deal with here:
|
|
|
|
* - normal (i.e. non-self-refresh)
|
|
|
|
* - self-refresh (SR) mode
|
|
|
|
* - lines are large relative to FIFO size (buffer can hold up to 2)
|
|
|
|
* - lines are small relative to FIFO size (buffer can hold more than 2
|
|
|
|
* lines), so need to account for TLB latency
|
|
|
|
*
|
|
|
|
* The normal calculation is:
|
|
|
|
* watermark = dotclock * bytes per pixel * latency
|
|
|
|
* where latency is platform & configuration dependent (we assume pessimal
|
|
|
|
* values here).
|
|
|
|
*
|
|
|
|
* The SR calculation is:
|
|
|
|
* watermark = (trunc(latency/line time)+1) * surface width *
|
|
|
|
* bytes per pixel
|
|
|
|
* where
|
|
|
|
* line time = htotal / dotclock
|
|
|
|
* surface width = hdisplay for normal plane and 64 for cursor
|
|
|
|
* and latency is assumed to be high, as above.
|
|
|
|
*
|
|
|
|
* The final value programmed to the register should always be rounded up,
|
|
|
|
* and include an extra 2 entries to account for clock crossings.
|
|
|
|
*
|
|
|
|
* We don't use the sprite, so we can ignore that. And on Crestline we have
|
|
|
|
* to set the non-SR watermarks to 8.
|
|
|
|
*/
|
2016-10-31 20:37:03 +00:00
|
|
|
void intel_update_watermarks(struct intel_crtc *crtc)
|
2012-04-17 01:20:35 +00:00
|
|
|
{
|
2016-10-31 20:37:03 +00:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
2012-04-17 01:20:35 +00:00
|
|
|
|
|
|
|
if (dev_priv->display.update_wm)
|
2013-09-10 08:40:40 +00:00
|
|
|
dev_priv->display.update_wm(crtc);
|
2012-04-17 01:20:35 +00:00
|
|
|
}
|
|
|
|
|
2016-01-18 07:19:47 +00:00
|
|
|
/*
|
2012-08-09 14:46:01 +00:00
|
|
|
* Lock protecting IPS related data structures
|
|
|
|
*/
|
|
|
|
DEFINE_SPINLOCK(mchdev_lock);
|
|
|
|
|
|
|
|
/* Global for IPS driver to get at the current i915 device. Protected by
|
|
|
|
* mchdev_lock. */
|
|
|
|
static struct drm_i915_private *i915_mch_dev;
|
|
|
|
|
2016-05-06 13:48:28 +00:00
|
|
|
bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
|
2012-04-18 18:29:23 +00:00
|
|
|
{
|
|
|
|
u16 rgvswctl;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
assert_spin_locked(&mchdev_lock);
|
|
|
|
|
2012-04-18 18:29:23 +00:00
|
|
|
rgvswctl = I915_READ16(MEMSWCTL);
|
|
|
|
if (rgvswctl & MEMCTL_CMD_STS) {
|
|
|
|
DRM_DEBUG("gpu busy, RCS change rejected\n");
|
|
|
|
return false; /* still busy with another command */
|
|
|
|
}
|
|
|
|
|
|
|
|
rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
|
|
|
|
(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
|
|
|
|
I915_WRITE16(MEMSWCTL, rgvswctl);
|
|
|
|
POSTING_READ16(MEMSWCTL);
|
|
|
|
|
|
|
|
rgvswctl |= MEMCTL_CMD_STS;
|
|
|
|
I915_WRITE16(MEMSWCTL, rgvswctl);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-05-06 13:48:28 +00:00
|
|
|
static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:23 +00:00
|
|
|
{
|
2016-02-11 10:27:32 +00:00
|
|
|
u32 rgvmodectl;
|
2012-04-18 18:29:23 +00:00
|
|
|
u8 fmax, fmin, fstart, vstart;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
|
|
|
|
2016-02-11 10:27:32 +00:00
|
|
|
rgvmodectl = I915_READ(MEMMODECTL);
|
|
|
|
|
2012-04-18 18:29:23 +00:00
|
|
|
/* Enable temp reporting */
|
|
|
|
I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
|
|
|
|
I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
|
|
|
|
|
|
|
|
/* 100ms RC evaluation intervals */
|
|
|
|
I915_WRITE(RCUPEI, 100000);
|
|
|
|
I915_WRITE(RCDNEI, 100000);
|
|
|
|
|
|
|
|
/* Set max/min thresholds to 90ms and 80ms respectively */
|
|
|
|
I915_WRITE(RCBMAXAVG, 90000);
|
|
|
|
I915_WRITE(RCBMINAVG, 80000);
|
|
|
|
|
|
|
|
I915_WRITE(MEMIHYST, 1);
|
|
|
|
|
|
|
|
/* Set up min, max, and cur for interrupt handling */
|
|
|
|
fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
|
|
|
|
fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
|
|
|
|
fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
|
|
|
|
MEMMODE_FSTART_SHIFT;
|
|
|
|
|
2015-09-18 17:03:19 +00:00
|
|
|
vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
|
2012-04-18 18:29:23 +00:00
|
|
|
PXVFREQ_PX_SHIFT;
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
|
|
|
|
dev_priv->ips.fstart = fstart;
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.max_delay = fstart;
|
|
|
|
dev_priv->ips.min_delay = fmin;
|
|
|
|
dev_priv->ips.cur_delay = fstart;
|
2012-04-18 18:29:23 +00:00
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
|
|
|
|
fmax, fmin, fstart);
|
|
|
|
|
|
|
|
I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Interrupts will be enabled in ironlake_irq_postinstall
|
|
|
|
*/
|
|
|
|
|
|
|
|
I915_WRITE(VIDSTART, vstart);
|
|
|
|
POSTING_READ(VIDSTART);
|
|
|
|
|
|
|
|
rgvmodectl |= MEMMODE_SWMODE_EN;
|
|
|
|
I915_WRITE(MEMMODECTL, rgvmodectl);
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
|
2012-04-18 18:29:23 +00:00
|
|
|
DRM_ERROR("stuck trying to change perf mode\n");
|
2015-07-20 08:58:21 +00:00
|
|
|
mdelay(1);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2016-05-06 13:48:28 +00:00
|
|
|
ironlake_set_drps(dev_priv, fstart);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2015-09-18 17:03:20 +00:00
|
|
|
dev_priv->ips.last_count1 = I915_READ(DMIEC) +
|
|
|
|
I915_READ(DDREC) + I915_READ(CSIEC);
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
|
2015-09-18 17:03:20 +00:00
|
|
|
dev_priv->ips.last_count2 = I915_READ(GFXEC);
|
2014-07-16 21:05:06 +00:00
|
|
|
dev_priv->ips.last_time2 = ktime_get_raw_ns();
|
2012-08-09 14:46:01 +00:00
|
|
|
|
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-18 18:29:23 +00:00
|
|
|
}
|
|
|
|
|
2016-05-06 13:48:28 +00:00
|
|
|
static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:23 +00:00
|
|
|
{
|
2012-08-09 14:46:01 +00:00
|
|
|
u16 rgvswctl;
|
|
|
|
|
|
|
|
spin_lock_irq(&mchdev_lock);
|
|
|
|
|
|
|
|
rgvswctl = I915_READ16(MEMSWCTL);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
|
|
|
/* Ack interrupts, disable EFC interrupt */
|
|
|
|
I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
|
|
|
|
I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
|
|
|
|
I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
|
|
|
|
I915_WRITE(DEIIR, DE_PCU_EVENT);
|
|
|
|
I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
|
|
|
|
|
|
|
|
/* Go back to the starting frequency */
|
2016-05-06 13:48:28 +00:00
|
|
|
ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
|
2015-07-20 08:58:21 +00:00
|
|
|
mdelay(1);
|
2012-04-18 18:29:23 +00:00
|
|
|
rgvswctl |= MEMCTL_CMD_STS;
|
|
|
|
I915_WRITE(MEMSWCTL, rgvswctl);
|
2015-07-20 08:58:21 +00:00
|
|
|
mdelay(1);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-18 18:29:23 +00:00
|
|
|
}
|
|
|
|
|
2012-07-26 09:50:05 +00:00
|
|
|
/* There's a funny hw issue where the hw returns all 0 when reading from
|
|
|
|
* GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
|
|
|
|
* ourselves, instead of doing a rmw cycle (which might result in us clearing
|
|
|
|
* all limits and the gpu stuck at whatever frequency it is at atm).
|
|
|
|
*/
|
2015-03-06 05:37:19 +00:00
|
|
|
static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
|
2012-04-18 18:29:23 +00:00
|
|
|
{
|
2012-04-28 07:56:39 +00:00
|
|
|
u32 limits;
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-07-26 09:16:14 +00:00
|
|
|
/* Only set the down limit when we've reached the lowest level to avoid
|
|
|
|
* getting more interrupts, otherwise leave this clear. This prevents a
|
|
|
|
* race in the hw when coming out of rc6: There's a tiny window where
|
|
|
|
* the hw runs at the minimal clock before selecting the desired
|
|
|
|
* frequency, if the down threshold expires in that window we will not
|
|
|
|
* receive a down interrupt. */
|
2016-04-07 08:08:05 +00:00
|
|
|
if (IS_GEN9(dev_priv)) {
|
2015-03-06 05:37:19 +00:00
|
|
|
limits = (dev_priv->rps.max_freq_softlimit) << 23;
|
|
|
|
if (val <= dev_priv->rps.min_freq_softlimit)
|
|
|
|
limits |= (dev_priv->rps.min_freq_softlimit) << 14;
|
|
|
|
} else {
|
|
|
|
limits = dev_priv->rps.max_freq_softlimit << 24;
|
|
|
|
if (val <= dev_priv->rps.min_freq_softlimit)
|
|
|
|
limits |= dev_priv->rps.min_freq_softlimit << 16;
|
|
|
|
}
|
2012-07-26 09:16:14 +00:00
|
|
|
|
|
|
|
return limits;
|
|
|
|
}
|
|
|
|
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
|
|
|
|
{
|
|
|
|
int new_power;
|
2015-03-06 05:37:18 +00:00
|
|
|
u32 threshold_up = 0, threshold_down = 0; /* in % */
|
|
|
|
u32 ei_up = 0, ei_down = 0;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
|
|
|
|
new_power = dev_priv->rps.power;
|
|
|
|
switch (dev_priv->rps.power) {
|
|
|
|
case LOW_POWER:
|
2016-07-02 14:35:59 +00:00
|
|
|
if (val > dev_priv->rps.efficient_freq + 1 &&
|
|
|
|
val > dev_priv->rps.cur_freq)
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
new_power = BETWEEN;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case BETWEEN:
|
2016-07-02 14:35:59 +00:00
|
|
|
if (val <= dev_priv->rps.efficient_freq &&
|
|
|
|
val < dev_priv->rps.cur_freq)
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
new_power = LOW_POWER;
|
2016-07-02 14:35:59 +00:00
|
|
|
else if (val >= dev_priv->rps.rp0_freq &&
|
|
|
|
val > dev_priv->rps.cur_freq)
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
new_power = HIGH_POWER;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case HIGH_POWER:
|
2016-07-02 14:35:59 +00:00
|
|
|
if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
|
|
|
|
val < dev_priv->rps.cur_freq)
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
new_power = BETWEEN;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* Max/min bins are special */
|
2015-03-18 09:48:21 +00:00
|
|
|
if (val <= dev_priv->rps.min_freq_softlimit)
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
new_power = LOW_POWER;
|
2015-03-18 09:48:21 +00:00
|
|
|
if (val >= dev_priv->rps.max_freq_softlimit)
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
new_power = HIGH_POWER;
|
|
|
|
if (new_power == dev_priv->rps.power)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Note the units here are not exactly 1us, but 1280ns. */
|
|
|
|
switch (new_power) {
|
|
|
|
case LOW_POWER:
|
|
|
|
/* Upclock if more than 95% busy over 16ms */
|
2015-03-06 05:37:18 +00:00
|
|
|
ei_up = 16000;
|
|
|
|
threshold_up = 95;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
|
|
|
|
/* Downclock if less than 85% busy over 32ms */
|
2015-03-06 05:37:18 +00:00
|
|
|
ei_down = 32000;
|
|
|
|
threshold_down = 85;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case BETWEEN:
|
|
|
|
/* Upclock if more than 90% busy over 13ms */
|
2015-03-06 05:37:18 +00:00
|
|
|
ei_up = 13000;
|
|
|
|
threshold_up = 90;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
|
|
|
|
/* Downclock if less than 75% busy over 32ms */
|
2015-03-06 05:37:18 +00:00
|
|
|
ei_down = 32000;
|
|
|
|
threshold_down = 75;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case HIGH_POWER:
|
|
|
|
/* Upclock if more than 85% busy over 10ms */
|
2015-03-06 05:37:18 +00:00
|
|
|
ei_up = 10000;
|
|
|
|
threshold_up = 85;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
|
|
|
|
/* Downclock if less than 60% busy over 32ms */
|
2015-03-06 05:37:18 +00:00
|
|
|
ei_down = 32000;
|
|
|
|
threshold_down = 60;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2015-03-06 05:37:18 +00:00
|
|
|
I915_WRITE(GEN6_RP_UP_EI,
|
2016-07-02 14:35:59 +00:00
|
|
|
GT_INTERVAL_FROM_US(dev_priv, ei_up));
|
2015-03-06 05:37:18 +00:00
|
|
|
I915_WRITE(GEN6_RP_UP_THRESHOLD,
|
2016-07-02 14:35:59 +00:00
|
|
|
GT_INTERVAL_FROM_US(dev_priv,
|
|
|
|
ei_up * threshold_up / 100));
|
2015-03-06 05:37:18 +00:00
|
|
|
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_EI,
|
2016-07-02 14:35:59 +00:00
|
|
|
GT_INTERVAL_FROM_US(dev_priv, ei_down));
|
2015-03-06 05:37:18 +00:00
|
|
|
I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
|
2016-07-02 14:35:59 +00:00
|
|
|
GT_INTERVAL_FROM_US(dev_priv,
|
|
|
|
ei_down * threshold_down / 100));
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RP_CONTROL,
|
|
|
|
GEN6_RP_MEDIA_TURBO |
|
|
|
|
GEN6_RP_MEDIA_HW_NORMAL_MODE |
|
|
|
|
GEN6_RP_MEDIA_IS_GFX |
|
|
|
|
GEN6_RP_ENABLE |
|
|
|
|
GEN6_RP_UP_BUSY_AVG |
|
|
|
|
GEN6_RP_DOWN_IDLE_AVG);
|
2015-03-06 05:37:18 +00:00
|
|
|
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
dev_priv->rps.power = new_power;
|
2015-04-07 15:20:28 +00:00
|
|
|
dev_priv->rps.up_threshold = threshold_up;
|
|
|
|
dev_priv->rps.down_threshold = threshold_down;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
dev_priv->rps.last_adj = 0;
|
|
|
|
}
|
|
|
|
|
2014-03-28 08:03:34 +00:00
|
|
|
static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
|
|
|
|
{
|
|
|
|
u32 mask = 0;
|
|
|
|
|
|
|
|
if (val > dev_priv->rps.min_freq_softlimit)
|
2015-03-18 09:48:23 +00:00
|
|
|
mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
|
2014-03-28 08:03:34 +00:00
|
|
|
if (val < dev_priv->rps.max_freq_softlimit)
|
2015-03-18 09:48:23 +00:00
|
|
|
mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
|
2014-03-28 08:03:34 +00:00
|
|
|
|
2014-07-10 19:31:19 +00:00
|
|
|
mask &= dev_priv->pm_rps_events;
|
|
|
|
|
2014-12-19 17:33:26 +00:00
|
|
|
return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
|
2014-03-28 08:03:34 +00:00
|
|
|
}
|
|
|
|
|
2014-02-04 17:37:01 +00:00
|
|
|
/* gen6_set_rps is called to update the frequency request, but should also be
|
|
|
|
* called when the range (min_delay and max_delay) is modified so that we can
|
|
|
|
* update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
|
2017-01-26 10:19:19 +00:00
|
|
|
static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
|
2012-07-26 09:16:14 +00:00
|
|
|
{
|
2012-11-02 18:14:01 +00:00
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
2015-03-18 09:48:21 +00:00
|
|
|
WARN_ON(val > dev_priv->rps.max_freq);
|
|
|
|
WARN_ON(val < dev_priv->rps.min_freq);
|
2012-08-09 13:07:01 +00:00
|
|
|
|
2014-03-27 08:24:20 +00:00
|
|
|
/* min/max delay may still have been modified so be sure to
|
|
|
|
* write the limits value.
|
|
|
|
*/
|
|
|
|
if (val != dev_priv->rps.cur_freq) {
|
|
|
|
gen6_set_rps_thresholds(dev_priv, val);
|
2014-02-04 17:37:01 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_GEN9(dev_priv))
|
2015-03-06 05:37:17 +00:00
|
|
|
I915_WRITE(GEN6_RPNSWREQ,
|
|
|
|
GEN9_FREQUENCY(val));
|
2016-05-10 13:10:04 +00:00
|
|
|
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
2014-03-27 08:24:20 +00:00
|
|
|
I915_WRITE(GEN6_RPNSWREQ,
|
|
|
|
HSW_FREQUENCY(val));
|
|
|
|
else
|
|
|
|
I915_WRITE(GEN6_RPNSWREQ,
|
|
|
|
GEN6_FREQUENCY(val) |
|
|
|
|
GEN6_OFFSET(0) |
|
|
|
|
GEN6_AGGRESSIVE_TURBO);
|
2014-02-04 17:37:01 +00:00
|
|
|
}
|
2012-04-28 07:56:39 +00:00
|
|
|
|
|
|
|
/* Make sure we continue to get interrupts
|
|
|
|
* until we hit the minimum or maximum frequencies.
|
|
|
|
*/
|
2015-03-06 05:37:19 +00:00
|
|
|
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
|
2014-03-28 08:03:34 +00:00
|
|
|
I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
|
2012-04-28 07:56:39 +00:00
|
|
|
|
2012-09-08 02:43:41 +00:00
|
|
|
POSTING_READ(GEN6_RPNSWREQ);
|
|
|
|
|
2014-03-20 01:31:11 +00:00
|
|
|
dev_priv->rps.cur_freq = val;
|
2015-11-17 16:14:26 +00:00
|
|
|
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
|
2017-01-26 10:19:19 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-04-18 18:29:23 +00:00
|
|
|
}
|
|
|
|
|
2017-01-26 10:19:19 +00:00
|
|
|
static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
|
2015-02-02 17:09:50 +00:00
|
|
|
{
|
2017-01-26 10:19:19 +00:00
|
|
|
int err;
|
|
|
|
|
2015-02-02 17:09:50 +00:00
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
2015-03-18 09:48:21 +00:00
|
|
|
WARN_ON(val > dev_priv->rps.max_freq);
|
|
|
|
WARN_ON(val < dev_priv->rps.min_freq);
|
2015-02-02 17:09:50 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
|
2015-02-02 17:09:50 +00:00
|
|
|
"Odd GPU freq value\n"))
|
|
|
|
val &= ~1;
|
|
|
|
|
2015-07-10 13:01:40 +00:00
|
|
|
I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
|
|
|
|
|
2015-04-07 15:20:28 +00:00
|
|
|
if (val != dev_priv->rps.cur_freq) {
|
2017-01-26 10:19:19 +00:00
|
|
|
err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2015-04-07 15:20:28 +00:00
|
|
|
if (!IS_CHERRYVIEW(dev_priv))
|
|
|
|
gen6_set_rps_thresholds(dev_priv, val);
|
|
|
|
}
|
2015-02-02 17:09:50 +00:00
|
|
|
|
|
|
|
dev_priv->rps.cur_freq = val;
|
|
|
|
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
|
2017-01-26 10:19:19 +00:00
|
|
|
|
|
|
|
return 0;
|
2015-02-02 17:09:50 +00:00
|
|
|
}
|
|
|
|
|
2015-05-09 12:34:44 +00:00
|
|
|
/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
|
2014-01-30 17:38:16 +00:00
|
|
|
*
|
|
|
|
* * If Gfx is Idle, then
|
2015-05-09 12:34:44 +00:00
|
|
|
* 1. Forcewake Media well.
|
|
|
|
* 2. Request idle freq.
|
|
|
|
* 3. Release Forcewake of Media well.
|
2014-01-30 17:38:16 +00:00
|
|
|
*/
|
|
|
|
static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2015-03-18 09:48:21 +00:00
|
|
|
u32 val = dev_priv->rps.idle_freq;
|
2017-01-26 10:19:19 +00:00
|
|
|
int err;
|
2014-06-28 05:56:11 +00:00
|
|
|
|
2015-03-18 09:48:21 +00:00
|
|
|
if (dev_priv->rps.cur_freq <= val)
|
2014-01-30 17:38:16 +00:00
|
|
|
return;
|
|
|
|
|
2017-01-02 15:28:45 +00:00
|
|
|
/* The punit delays the write of the frequency and voltage until it
|
|
|
|
* determines the GPU is awake. During normal usage we don't want to
|
|
|
|
* waste power changing the frequency if the GPU is sleeping (rc6).
|
|
|
|
* However, the GPU and driver is now idle and we do not want to delay
|
|
|
|
* switching to minimum voltage (reducing power whilst idle) as we do
|
|
|
|
* not expect to be woken in the near future and so must flush the
|
|
|
|
* change by waking the device.
|
|
|
|
*
|
|
|
|
* We choose to take the media powerwell (either would do to trick the
|
|
|
|
* punit into committing the voltage change) as that takes a lot less
|
|
|
|
* power than the render powerwell.
|
|
|
|
*/
|
2015-05-09 12:34:44 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
|
2017-01-26 10:19:19 +00:00
|
|
|
err = valleyview_set_rps(dev_priv, val);
|
2015-05-09 12:34:44 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
|
2017-01-26 10:19:19 +00:00
|
|
|
|
|
|
|
if (err)
|
|
|
|
DRM_ERROR("Failed to set RPS for idle\n");
|
2014-01-30 17:38:16 +00:00
|
|
|
}
|
|
|
|
|
2015-03-18 09:48:22 +00:00
|
|
|
void gen6_rps_busy(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
if (dev_priv->rps.enabled) {
|
|
|
|
if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
|
|
|
|
gen6_rps_reset_ei(dev_priv);
|
|
|
|
I915_WRITE(GEN6_PMINTRMSK,
|
|
|
|
gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
|
2016-06-20 09:58:27 +00:00
|
|
|
|
2016-07-04 07:08:36 +00:00
|
|
|
gen6_enable_rps_interrupts(dev_priv);
|
|
|
|
|
2016-06-20 09:58:27 +00:00
|
|
|
/* Ensure we start at the user's desired frequency */
|
2017-01-26 10:19:19 +00:00
|
|
|
if (intel_set_rps(dev_priv,
|
|
|
|
clamp(dev_priv->rps.cur_freq,
|
|
|
|
dev_priv->rps.min_freq_softlimit,
|
|
|
|
dev_priv->rps.max_freq_softlimit)))
|
|
|
|
DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
|
2015-03-18 09:48:22 +00:00
|
|
|
}
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
}
|
|
|
|
|
drm/i915: Boost RPS frequency for CPU stalls
If we encounter a situation where the CPU blocks waiting for results
from the GPU, give the GPU a kick to boost its the frequency.
This should work to reduce user interface stalls and to quickly promote
mesa to high frequencies - but the cost is that our requested frequency
stalls high (as we do not idle for long enough before rc6 to start
reducing frequencies, nor are we aggressive at down clocking an
underused GPU). However, this should be mitigated by rc6 itself powering
off the GPU when idle, and that energy use is dependent upon the workload
of the GPU in addition to its frequency (e.g. the math or sampler
functions only consume power when used). Still, this is likely to
adversely affect light workloads.
In particular, this nearly eliminates the highly noticeable wake-up lag
in animations from idle. For example, expose or workspace transitions.
(However, given the situation where we fail to downclock, our requested
frequency is almost always the maximum, except for Baytrail where we
manually downclock upon idling. This often masks the latency of
upclocking after being idle, so animations are typically smooth - at the
cost of increased power consumption.)
Stéphane raised the concern that this will punish good applications and
reward bad applications - but due to the nature of how mesa performs its
client throttling, I believe all mesa applications will be roughly
equally affected. To address this concern, and to prevent applications
like compositors from permanently boosting the RPS state, we ratelimit the
frequency of the wait-boosts each client recieves.
Unfortunately, this techinique is ineffective with Ironlake - which also
has dynamic render power states and suffers just as dramatically. For
Ironlake, the thermal/power headroom is shared with the CPU through
Intelligent Power Sharing and the intel-ips module. This leaves us with
no GPU boost frequencies available when coming out of idle, and due to
hardware limitations we cannot change the arbitration between the CPU and
GPU quickly enough to be effective.
v2: Limit each client to receiving a single boost for each active period.
Tested by QA to only marginally increase power, and to demonstrably
increase throughput in games. No latency measurements yet.
v3: Cater for front-buffer rendering with manual throttling.
v4: Tidy up.
v5: Sadly the compositor needs frequent boosts as it may never idle, but
due to its picking mechanism (using ReadPixels) may require frequent
waits. Those waits, along with the waits for the vrefresh swap, conspire
to keep the GPU at low frequencies despite the interactive latency. To
overcome this we ditch the one-boost-per-active-period and just ratelimit
the number of wait-boosts each client can receive.
Reported-and-tested-by: Paul Neumann <paul104x@yahoo.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68716
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: No extern for function prototypes in headers.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:56 +00:00
|
|
|
void gen6_rps_idle(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2016-07-04 07:08:36 +00:00
|
|
|
/* Flush our bottom-half so that it does not race with us
|
|
|
|
* setting the idle frequency and so that it is bounded by
|
|
|
|
* our rpm wakeref. And then disable the interrupts to stop any
|
|
|
|
* futher RPS reclocking whilst we are asleep.
|
|
|
|
*/
|
|
|
|
gen6_disable_rps_interrupts(dev_priv);
|
|
|
|
|
drm/i915: Boost RPS frequency for CPU stalls
If we encounter a situation where the CPU blocks waiting for results
from the GPU, give the GPU a kick to boost its the frequency.
This should work to reduce user interface stalls and to quickly promote
mesa to high frequencies - but the cost is that our requested frequency
stalls high (as we do not idle for long enough before rc6 to start
reducing frequencies, nor are we aggressive at down clocking an
underused GPU). However, this should be mitigated by rc6 itself powering
off the GPU when idle, and that energy use is dependent upon the workload
of the GPU in addition to its frequency (e.g. the math or sampler
functions only consume power when used). Still, this is likely to
adversely affect light workloads.
In particular, this nearly eliminates the highly noticeable wake-up lag
in animations from idle. For example, expose or workspace transitions.
(However, given the situation where we fail to downclock, our requested
frequency is almost always the maximum, except for Baytrail where we
manually downclock upon idling. This often masks the latency of
upclocking after being idle, so animations are typically smooth - at the
cost of increased power consumption.)
Stéphane raised the concern that this will punish good applications and
reward bad applications - but due to the nature of how mesa performs its
client throttling, I believe all mesa applications will be roughly
equally affected. To address this concern, and to prevent applications
like compositors from permanently boosting the RPS state, we ratelimit the
frequency of the wait-boosts each client recieves.
Unfortunately, this techinique is ineffective with Ironlake - which also
has dynamic render power states and suffers just as dramatically. For
Ironlake, the thermal/power headroom is shared with the CPU through
Intelligent Power Sharing and the intel-ips module. This leaves us with
no GPU boost frequencies available when coming out of idle, and due to
hardware limitations we cannot change the arbitration between the CPU and
GPU quickly enough to be effective.
v2: Limit each client to receiving a single boost for each active period.
Tested by QA to only marginally increase power, and to demonstrably
increase throughput in games. No latency measurements yet.
v3: Cater for front-buffer rendering with manual throttling.
v4: Tidy up.
v5: Sadly the compositor needs frequent boosts as it may never idle, but
due to its picking mechanism (using ReadPixels) may require frequent
waits. Those waits, along with the waits for the vrefresh swap, conspire
to keep the GPU at low frequencies despite the interactive latency. To
overcome this we ditch the one-boost-per-active-period and just ratelimit
the number of wait-boosts each client can receive.
Reported-and-tested-by: Paul Neumann <paul104x@yahoo.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68716
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: No extern for function prototypes in headers.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:56 +00:00
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
2013-10-10 20:58:50 +00:00
|
|
|
if (dev_priv->rps.enabled) {
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2014-01-30 17:38:16 +00:00
|
|
|
vlv_set_rps_idle(dev_priv);
|
2014-09-29 13:07:19 +00:00
|
|
|
else
|
2016-05-10 13:10:04 +00:00
|
|
|
gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
|
2013-10-10 20:58:50 +00:00
|
|
|
dev_priv->rps.last_adj = 0;
|
2016-05-23 14:42:48 +00:00
|
|
|
I915_WRITE(GEN6_PMINTRMSK,
|
|
|
|
gen6_sanitize_rps_pm_mask(dev_priv, ~0));
|
2013-10-10 20:58:50 +00:00
|
|
|
}
|
2015-05-21 20:01:47 +00:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2015-04-07 15:20:32 +00:00
|
|
|
|
2015-05-21 20:01:47 +00:00
|
|
|
spin_lock(&dev_priv->rps.client_lock);
|
2015-04-07 15:20:32 +00:00
|
|
|
while (!list_empty(&dev_priv->rps.clients))
|
|
|
|
list_del_init(dev_priv->rps.clients.next);
|
2015-05-21 20:01:47 +00:00
|
|
|
spin_unlock(&dev_priv->rps.client_lock);
|
drm/i915: Boost RPS frequency for CPU stalls
If we encounter a situation where the CPU blocks waiting for results
from the GPU, give the GPU a kick to boost its the frequency.
This should work to reduce user interface stalls and to quickly promote
mesa to high frequencies - but the cost is that our requested frequency
stalls high (as we do not idle for long enough before rc6 to start
reducing frequencies, nor are we aggressive at down clocking an
underused GPU). However, this should be mitigated by rc6 itself powering
off the GPU when idle, and that energy use is dependent upon the workload
of the GPU in addition to its frequency (e.g. the math or sampler
functions only consume power when used). Still, this is likely to
adversely affect light workloads.
In particular, this nearly eliminates the highly noticeable wake-up lag
in animations from idle. For example, expose or workspace transitions.
(However, given the situation where we fail to downclock, our requested
frequency is almost always the maximum, except for Baytrail where we
manually downclock upon idling. This often masks the latency of
upclocking after being idle, so animations are typically smooth - at the
cost of increased power consumption.)
Stéphane raised the concern that this will punish good applications and
reward bad applications - but due to the nature of how mesa performs its
client throttling, I believe all mesa applications will be roughly
equally affected. To address this concern, and to prevent applications
like compositors from permanently boosting the RPS state, we ratelimit the
frequency of the wait-boosts each client recieves.
Unfortunately, this techinique is ineffective with Ironlake - which also
has dynamic render power states and suffers just as dramatically. For
Ironlake, the thermal/power headroom is shared with the CPU through
Intelligent Power Sharing and the intel-ips module. This leaves us with
no GPU boost frequencies available when coming out of idle, and due to
hardware limitations we cannot change the arbitration between the CPU and
GPU quickly enough to be effective.
v2: Limit each client to receiving a single boost for each active period.
Tested by QA to only marginally increase power, and to demonstrably
increase throughput in games. No latency measurements yet.
v3: Cater for front-buffer rendering with manual throttling.
v4: Tidy up.
v5: Sadly the compositor needs frequent boosts as it may never idle, but
due to its picking mechanism (using ReadPixels) may require frequent
waits. Those waits, along with the waits for the vrefresh swap, conspire
to keep the GPU at low frequencies despite the interactive latency. To
overcome this we ditch the one-boost-per-active-period and just ratelimit
the number of wait-boosts each client can receive.
Reported-and-tested-by: Paul Neumann <paul104x@yahoo.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68716
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: No extern for function prototypes in headers.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:56 +00:00
|
|
|
}
|
|
|
|
|
2015-04-07 15:20:32 +00:00
|
|
|
void gen6_rps_boost(struct drm_i915_private *dev_priv,
|
2015-04-27 12:41:24 +00:00
|
|
|
struct intel_rps_client *rps,
|
|
|
|
unsigned long submitted)
|
drm/i915: Boost RPS frequency for CPU stalls
If we encounter a situation where the CPU blocks waiting for results
from the GPU, give the GPU a kick to boost its the frequency.
This should work to reduce user interface stalls and to quickly promote
mesa to high frequencies - but the cost is that our requested frequency
stalls high (as we do not idle for long enough before rc6 to start
reducing frequencies, nor are we aggressive at down clocking an
underused GPU). However, this should be mitigated by rc6 itself powering
off the GPU when idle, and that energy use is dependent upon the workload
of the GPU in addition to its frequency (e.g. the math or sampler
functions only consume power when used). Still, this is likely to
adversely affect light workloads.
In particular, this nearly eliminates the highly noticeable wake-up lag
in animations from idle. For example, expose or workspace transitions.
(However, given the situation where we fail to downclock, our requested
frequency is almost always the maximum, except for Baytrail where we
manually downclock upon idling. This often masks the latency of
upclocking after being idle, so animations are typically smooth - at the
cost of increased power consumption.)
Stéphane raised the concern that this will punish good applications and
reward bad applications - but due to the nature of how mesa performs its
client throttling, I believe all mesa applications will be roughly
equally affected. To address this concern, and to prevent applications
like compositors from permanently boosting the RPS state, we ratelimit the
frequency of the wait-boosts each client recieves.
Unfortunately, this techinique is ineffective with Ironlake - which also
has dynamic render power states and suffers just as dramatically. For
Ironlake, the thermal/power headroom is shared with the CPU through
Intelligent Power Sharing and the intel-ips module. This leaves us with
no GPU boost frequencies available when coming out of idle, and due to
hardware limitations we cannot change the arbitration between the CPU and
GPU quickly enough to be effective.
v2: Limit each client to receiving a single boost for each active period.
Tested by QA to only marginally increase power, and to demonstrably
increase throughput in games. No latency measurements yet.
v3: Cater for front-buffer rendering with manual throttling.
v4: Tidy up.
v5: Sadly the compositor needs frequent boosts as it may never idle, but
due to its picking mechanism (using ReadPixels) may require frequent
waits. Those waits, along with the waits for the vrefresh swap, conspire
to keep the GPU at low frequencies despite the interactive latency. To
overcome this we ditch the one-boost-per-active-period and just ratelimit
the number of wait-boosts each client can receive.
Reported-and-tested-by: Paul Neumann <paul104x@yahoo.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68716
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: No extern for function prototypes in headers.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:56 +00:00
|
|
|
{
|
2015-05-21 20:01:47 +00:00
|
|
|
/* This is intentionally racy! We peek at the state here, then
|
|
|
|
* validate inside the RPS worker.
|
|
|
|
*/
|
2016-07-04 07:08:31 +00:00
|
|
|
if (!(dev_priv->gt.awake &&
|
2015-05-21 20:01:47 +00:00
|
|
|
dev_priv->rps.enabled &&
|
2016-07-13 08:10:35 +00:00
|
|
|
dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
|
2015-05-21 20:01:47 +00:00
|
|
|
return;
|
2015-03-18 09:48:22 +00:00
|
|
|
|
2015-04-27 12:41:24 +00:00
|
|
|
/* Force a RPS boost (and don't count it against the client) if
|
|
|
|
* the GPU is severely congested.
|
|
|
|
*/
|
2015-05-21 20:01:48 +00:00
|
|
|
if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
|
2015-04-27 12:41:24 +00:00
|
|
|
rps = NULL;
|
|
|
|
|
2015-05-21 20:01:47 +00:00
|
|
|
spin_lock(&dev_priv->rps.client_lock);
|
|
|
|
if (rps == NULL || list_empty(&rps->link)) {
|
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
if (dev_priv->rps.interrupts_enabled) {
|
|
|
|
dev_priv->rps.client_boost = true;
|
2016-07-04 07:08:36 +00:00
|
|
|
schedule_work(&dev_priv->rps.work);
|
2015-05-21 20:01:47 +00:00
|
|
|
}
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2015-04-07 15:20:32 +00:00
|
|
|
|
2015-04-27 12:41:22 +00:00
|
|
|
if (rps != NULL) {
|
|
|
|
list_add(&rps->link, &dev_priv->rps.clients);
|
|
|
|
rps->boosts++;
|
2015-04-07 15:20:32 +00:00
|
|
|
} else
|
|
|
|
dev_priv->rps.boosts++;
|
2013-10-10 20:58:50 +00:00
|
|
|
}
|
2015-05-21 20:01:47 +00:00
|
|
|
spin_unlock(&dev_priv->rps.client_lock);
|
drm/i915: Boost RPS frequency for CPU stalls
If we encounter a situation where the CPU blocks waiting for results
from the GPU, give the GPU a kick to boost its the frequency.
This should work to reduce user interface stalls and to quickly promote
mesa to high frequencies - but the cost is that our requested frequency
stalls high (as we do not idle for long enough before rc6 to start
reducing frequencies, nor are we aggressive at down clocking an
underused GPU). However, this should be mitigated by rc6 itself powering
off the GPU when idle, and that energy use is dependent upon the workload
of the GPU in addition to its frequency (e.g. the math or sampler
functions only consume power when used). Still, this is likely to
adversely affect light workloads.
In particular, this nearly eliminates the highly noticeable wake-up lag
in animations from idle. For example, expose or workspace transitions.
(However, given the situation where we fail to downclock, our requested
frequency is almost always the maximum, except for Baytrail where we
manually downclock upon idling. This often masks the latency of
upclocking after being idle, so animations are typically smooth - at the
cost of increased power consumption.)
Stéphane raised the concern that this will punish good applications and
reward bad applications - but due to the nature of how mesa performs its
client throttling, I believe all mesa applications will be roughly
equally affected. To address this concern, and to prevent applications
like compositors from permanently boosting the RPS state, we ratelimit the
frequency of the wait-boosts each client recieves.
Unfortunately, this techinique is ineffective with Ironlake - which also
has dynamic render power states and suffers just as dramatically. For
Ironlake, the thermal/power headroom is shared with the CPU through
Intelligent Power Sharing and the intel-ips module. This leaves us with
no GPU boost frequencies available when coming out of idle, and due to
hardware limitations we cannot change the arbitration between the CPU and
GPU quickly enough to be effective.
v2: Limit each client to receiving a single boost for each active period.
Tested by QA to only marginally increase power, and to demonstrably
increase throughput in games. No latency measurements yet.
v3: Cater for front-buffer rendering with manual throttling.
v4: Tidy up.
v5: Sadly the compositor needs frequent boosts as it may never idle, but
due to its picking mechanism (using ReadPixels) may require frequent
waits. Those waits, along with the waits for the vrefresh swap, conspire
to keep the GPU at low frequencies despite the interactive latency. To
overcome this we ditch the one-boost-per-active-period and just ratelimit
the number of wait-boosts each client can receive.
Reported-and-tested-by: Paul Neumann <paul104x@yahoo.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68716
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: No extern for function prototypes in headers.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:56 +00:00
|
|
|
}
|
|
|
|
|
2017-01-26 10:19:19 +00:00
|
|
|
int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
|
2013-04-17 22:54:58 +00:00
|
|
|
{
|
2017-01-26 10:19:19 +00:00
|
|
|
int err;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
2017-01-26 10:19:19 +00:00
|
|
|
err = valleyview_set_rps(dev_priv, val);
|
2015-02-02 17:09:50 +00:00
|
|
|
else
|
2017-01-26 10:19:19 +00:00
|
|
|
err = gen6_set_rps(dev_priv, val);
|
|
|
|
|
|
|
|
return err;
|
2013-04-17 22:54:58 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
|
2014-11-04 17:07:05 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
2015-01-20 12:23:04 +00:00
|
|
|
I915_WRITE(GEN9_PG_ENABLE, 0);
|
2014-11-04 17:07:05 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen9_disable_rps(struct drm_i915_private *dev_priv)
|
2016-04-22 18:35:45 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(GEN6_RP_CONTROL, 0);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen6_disable_rps(struct drm_i915_private *dev_priv)
|
2013-04-23 17:09:28 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
2013-07-12 20:43:27 +00:00
|
|
|
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
|
2016-04-22 18:35:45 +00:00
|
|
|
I915_WRITE(GEN6_RP_CONTROL, 0);
|
2013-07-12 20:43:27 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
|
2014-05-23 15:30:15 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
|
2013-07-12 20:43:27 +00:00
|
|
|
{
|
2014-08-18 17:35:27 +00:00
|
|
|
/* we're doing forcewake before Disabling RC6,
|
|
|
|
* This what the BIOS expects when going into suspend */
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2014-08-18 17:35:27 +00:00
|
|
|
|
2013-07-12 20:43:27 +00:00
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
2013-04-23 17:09:28 +00:00
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2013-04-23 17:09:28 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
|
2013-10-18 19:32:07 +00:00
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
2014-04-14 17:24:25 +00:00
|
|
|
if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
|
|
|
|
mode = GEN6_RC_CTL_RC6_ENABLE;
|
|
|
|
else
|
|
|
|
mode = 0;
|
|
|
|
}
|
2016-05-10 13:10:04 +00:00
|
|
|
if (HAS_RC6p(dev_priv))
|
2016-06-29 16:13:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("Enabling RC6 states: "
|
|
|
|
"RC6 %s RC6p %s RC6pp %s\n",
|
|
|
|
onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
|
|
|
|
onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
|
|
|
|
onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
|
2014-10-07 14:06:50 +00:00
|
|
|
|
|
|
|
else
|
2016-06-29 16:13:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
|
|
|
|
onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
|
2013-10-18 19:32:07 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
|
2016-02-05 18:43:29 +00:00
|
|
|
{
|
2016-03-30 13:57:10 +00:00
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2016-02-05 18:43:29 +00:00
|
|
|
bool enable_rc6 = true;
|
|
|
|
unsigned long rc6_ctx_base;
|
2016-06-29 16:13:55 +00:00
|
|
|
u32 rc_ctl;
|
|
|
|
int rc_sw_target;
|
|
|
|
|
|
|
|
rc_ctl = I915_READ(GEN6_RC_CONTROL);
|
|
|
|
rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
|
|
|
|
RC_SW_TARGET_STATE_SHIFT;
|
|
|
|
DRM_DEBUG_DRIVER("BIOS enabled RC states: "
|
|
|
|
"HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
|
|
|
|
onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
|
|
|
|
onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
|
|
|
|
rc_sw_target);
|
2016-02-05 18:43:29 +00:00
|
|
|
|
|
|
|
if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
|
2016-06-29 16:13:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
|
2016-02-05 18:43:29 +00:00
|
|
|
enable_rc6 = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The exact context size is not known for BXT, so assume a page size
|
|
|
|
* for this check.
|
|
|
|
*/
|
|
|
|
rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
|
2016-03-30 13:57:10 +00:00
|
|
|
if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
|
|
|
|
(rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
|
|
|
|
ggtt->stolen_reserved_size))) {
|
2016-06-29 16:13:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
|
2016-02-05 18:43:29 +00:00
|
|
|
enable_rc6 = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
|
|
|
|
((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
|
|
|
|
((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
|
|
|
|
((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
|
2016-06-29 16:13:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
|
2016-02-05 18:43:29 +00:00
|
|
|
enable_rc6 = false;
|
|
|
|
}
|
|
|
|
|
2016-06-29 16:13:55 +00:00
|
|
|
if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
|
|
|
|
!I915_READ(GEN8_PUSHBUS_ENABLE) ||
|
|
|
|
!I915_READ(GEN8_PUSHBUS_SHIFT)) {
|
|
|
|
DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
|
|
|
|
enable_rc6 = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!I915_READ(GEN6_GFXPAUSE)) {
|
|
|
|
DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
|
|
|
|
enable_rc6 = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!I915_READ(GEN8_MISC_CTRL0)) {
|
|
|
|
DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
|
2016-02-05 18:43:29 +00:00
|
|
|
enable_rc6 = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return enable_rc6;
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
|
2012-04-18 18:29:23 +00:00
|
|
|
{
|
2015-06-15 21:23:54 +00:00
|
|
|
/* No RC6 before Ironlake and code is gone for ilk. */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->gen < 6)
|
2014-04-18 13:01:02 +00:00
|
|
|
return 0;
|
|
|
|
|
2016-02-05 18:43:29 +00:00
|
|
|
if (!enable_rc6)
|
|
|
|
return 0;
|
|
|
|
|
2016-12-02 08:23:49 +00:00
|
|
|
if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
|
2016-02-05 18:43:29 +00:00
|
|
|
DRM_INFO("RC6 disabled by BIOS\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-08-08 21:35:40 +00:00
|
|
|
/* Respect the kernel parameter if it is set */
|
2014-04-18 13:01:02 +00:00
|
|
|
if (enable_rc6 >= 0) {
|
|
|
|
int mask;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (HAS_RC6p(dev_priv))
|
2014-04-18 13:01:02 +00:00
|
|
|
mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
|
|
|
|
INTEL_RC6pp_ENABLE;
|
|
|
|
else
|
|
|
|
mask = INTEL_RC6_ENABLE;
|
|
|
|
|
|
|
|
if ((enable_rc6 & mask) != enable_rc6)
|
2016-06-29 16:13:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
|
|
|
|
"(requested %d, valid %d)\n",
|
|
|
|
enable_rc6 & mask, enable_rc6, mask);
|
2014-04-18 13:01:02 +00:00
|
|
|
|
|
|
|
return enable_rc6 & mask;
|
|
|
|
}
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_IVYBRIDGE(dev_priv))
|
2014-01-29 04:25:38 +00:00
|
|
|
return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
|
2014-01-29 04:25:39 +00:00
|
|
|
|
|
|
|
return INTEL_RC6_ENABLE;
|
2012-04-18 18:29:23 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
|
2014-04-01 00:16:42 +00:00
|
|
|
{
|
|
|
|
/* All of these values are in units of 50MHz */
|
2016-07-13 08:10:33 +00:00
|
|
|
|
2014-11-19 22:21:52 +00:00
|
|
|
/* static values from HW: RP0 > RP1 > RPn (min_freq) */
|
2016-12-02 08:23:49 +00:00
|
|
|
if (IS_GEN9_LP(dev_priv)) {
|
2016-07-13 08:10:33 +00:00
|
|
|
u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
|
2015-06-25 21:54:07 +00:00
|
|
|
dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
|
|
|
|
dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
|
|
|
|
dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
|
|
|
|
} else {
|
2016-07-13 08:10:33 +00:00
|
|
|
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
|
2015-06-25 21:54:07 +00:00
|
|
|
dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
|
|
|
|
dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
|
|
|
|
dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
|
|
|
|
}
|
2014-04-01 00:16:42 +00:00
|
|
|
/* hw_max = RP0 until we check for overclocking */
|
2016-07-13 08:10:33 +00:00
|
|
|
dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
|
2014-04-01 00:16:42 +00:00
|
|
|
|
2014-11-19 22:21:52 +00:00
|
|
|
dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
|
2017-01-23 18:32:37 +00:00
|
|
|
IS_GEN9_BC(dev_priv)) {
|
2016-07-13 08:10:33 +00:00
|
|
|
u32 ddcc_status = 0;
|
|
|
|
|
|
|
|
if (sandybridge_pcode_read(dev_priv,
|
|
|
|
HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
|
|
|
|
&ddcc_status) == 0)
|
2014-11-19 22:21:52 +00:00
|
|
|
dev_priv->rps.efficient_freq =
|
2015-02-11 07:06:46 +00:00
|
|
|
clamp_t(u8,
|
|
|
|
((ddcc_status >> 8) & 0xff),
|
|
|
|
dev_priv->rps.min_freq,
|
|
|
|
dev_priv->rps.max_freq);
|
2014-11-19 22:21:52 +00:00
|
|
|
}
|
|
|
|
|
2017-01-23 18:32:37 +00:00
|
|
|
if (IS_GEN9_BC(dev_priv)) {
|
2015-06-29 09:20:19 +00:00
|
|
|
/* Store the frequency values in 16.66 MHZ units, which is
|
2016-07-13 08:10:33 +00:00
|
|
|
* the natural hardware unit for SKL
|
|
|
|
*/
|
2015-06-29 09:20:19 +00:00
|
|
|
dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
|
|
|
|
dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
|
|
|
|
dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
|
|
|
|
dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
|
|
|
|
dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
|
|
|
|
}
|
2014-04-01 00:16:42 +00:00
|
|
|
}
|
|
|
|
|
2016-07-13 08:10:32 +00:00
|
|
|
static void reset_rps(struct drm_i915_private *dev_priv,
|
2017-01-26 10:19:19 +00:00
|
|
|
int (*set)(struct drm_i915_private *, u8))
|
2016-07-13 08:10:32 +00:00
|
|
|
{
|
|
|
|
u8 freq = dev_priv->rps.cur_freq;
|
|
|
|
|
|
|
|
/* force a reset */
|
|
|
|
dev_priv->rps.power = -1;
|
|
|
|
dev_priv->rps.cur_freq = -1;
|
|
|
|
|
2017-01-26 10:19:19 +00:00
|
|
|
if (set(dev_priv, freq))
|
|
|
|
DRM_ERROR("Failed to reset RPS to initial values\n");
|
2016-07-13 08:10:32 +00:00
|
|
|
}
|
|
|
|
|
2015-01-16 18:07:25 +00:00
|
|
|
/* See the Gen9_GT_PM_Programming_Guide doc for the below */
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen9_enable_rps(struct drm_i915_private *dev_priv)
|
2015-01-16 18:07:25 +00:00
|
|
|
{
|
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
|
|
|
|
2015-03-06 05:37:20 +00:00
|
|
|
/* Program defaults and thresholds for RPS*/
|
|
|
|
I915_WRITE(GEN6_RC_VIDEO_FREQ,
|
|
|
|
GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
|
|
|
|
|
|
|
|
/* 1 second timeout*/
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
|
|
|
|
GT_INTERVAL_FROM_US(dev_priv, 1000000));
|
|
|
|
|
2015-01-16 18:07:25 +00:00
|
|
|
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
|
|
|
|
|
2015-03-06 05:37:20 +00:00
|
|
|
/* Leaning on the below call to gen6_set_rps to program/setup the
|
|
|
|
* Up/Down EI & threshold registers, as well as the RP_CONTROL,
|
|
|
|
* RP_INTERRUPT_LIMITS & RPNSWREQ registers */
|
2016-07-13 08:10:32 +00:00
|
|
|
reset_rps(dev_priv, gen6_set_rps);
|
2015-01-16 18:07:25 +00:00
|
|
|
|
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
|
2014-11-04 17:07:05 +00:00
|
|
|
{
|
2016-03-16 11:00:36 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2014-11-04 17:07:05 +00:00
|
|
|
uint32_t rc6_mask = 0;
|
|
|
|
|
|
|
|
/* 1a: Software RC state - RC0 */
|
|
|
|
I915_WRITE(GEN6_RC_STATE, 0);
|
|
|
|
|
|
|
|
/* 1b: Get forcewake during program sequence. Although the driver
|
|
|
|
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2014-11-04 17:07:05 +00:00
|
|
|
|
|
|
|
/* 2a: Disable RC states. */
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
|
|
|
|
|
|
|
/* 2b: Program RC6 thresholds.*/
|
2015-09-12 04:47:53 +00:00
|
|
|
|
|
|
|
/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_SKYLAKE(dev_priv))
|
2015-09-12 04:47:53 +00:00
|
|
|
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
|
|
|
|
else
|
|
|
|
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
|
2014-11-04 17:07:05 +00:00
|
|
|
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
|
|
|
|
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id)
|
2016-03-16 11:00:36 +00:00
|
|
|
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
|
2015-09-12 04:47:54 +00:00
|
|
|
|
2016-05-13 14:36:30 +00:00
|
|
|
if (HAS_GUC(dev_priv))
|
2015-09-12 04:47:54 +00:00
|
|
|
I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
|
|
|
|
|
2014-11-04 17:07:05 +00:00
|
|
|
I915_WRITE(GEN6_RC_SLEEP, 0);
|
|
|
|
|
2015-01-20 12:23:04 +00:00
|
|
|
/* 2c: Program Coarse Power Gating Policies. */
|
|
|
|
I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
|
|
|
|
I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
|
|
|
|
|
2014-11-04 17:07:05 +00:00
|
|
|
/* 3a: Enable RC6 */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (intel_enable_rc6() & INTEL_RC6_ENABLE)
|
2014-11-04 17:07:05 +00:00
|
|
|
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
|
2016-01-14 10:53:34 +00:00
|
|
|
DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
|
2017-01-25 17:26:01 +00:00
|
|
|
I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL,
|
|
|
|
GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
|
2014-11-04 17:07:05 +00:00
|
|
|
|
2015-04-12 05:58:14 +00:00
|
|
|
/*
|
|
|
|
* 3b: Enable Coarse Power Gating only when RC6 is enabled.
|
2015-09-12 04:47:51 +00:00
|
|
|
* WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
|
2015-04-12 05:58:14 +00:00
|
|
|
*/
|
2016-05-10 13:10:04 +00:00
|
|
|
if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
|
2015-09-12 04:47:51 +00:00
|
|
|
I915_WRITE(GEN9_PG_ENABLE, 0);
|
|
|
|
else
|
|
|
|
I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
|
|
|
|
(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
|
2015-01-20 12:23:04 +00:00
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2014-11-04 17:07:05 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen8_enable_rps(struct drm_i915_private *dev_priv)
|
2013-11-03 04:07:52 +00:00
|
|
|
{
|
2016-03-16 11:00:36 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2014-11-19 22:21:52 +00:00
|
|
|
uint32_t rc6_mask = 0;
|
2013-11-03 04:07:52 +00:00
|
|
|
|
|
|
|
/* 1a: Software RC state - RC0 */
|
|
|
|
I915_WRITE(GEN6_RC_STATE, 0);
|
|
|
|
|
|
|
|
/* 1c & 1d: Get forcewake during program sequence. Although the driver
|
|
|
|
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2013-11-03 04:07:52 +00:00
|
|
|
|
|
|
|
/* 2a: Disable RC states. */
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
|
|
|
|
|
|
|
/* 2b: Program RC6 thresholds.*/
|
|
|
|
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
|
|
|
|
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
|
|
|
|
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id)
|
2016-03-16 11:00:36 +00:00
|
|
|
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
|
2013-11-03 04:07:52 +00:00
|
|
|
I915_WRITE(GEN6_RC_SLEEP, 0);
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_BROADWELL(dev_priv))
|
2014-04-09 18:44:06 +00:00
|
|
|
I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
|
|
|
|
else
|
|
|
|
I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
|
2013-11-03 04:07:52 +00:00
|
|
|
|
|
|
|
/* 3: Enable RC6 */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (intel_enable_rc6() & INTEL_RC6_ENABLE)
|
2013-11-03 04:07:52 +00:00
|
|
|
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
|
2016-05-10 13:10:04 +00:00
|
|
|
intel_print_rc6_info(dev_priv, rc6_mask);
|
|
|
|
if (IS_BROADWELL(dev_priv))
|
2014-04-09 18:44:06 +00:00
|
|
|
I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
|
|
|
|
GEN7_RC_CTL_TO_MODE |
|
|
|
|
rc6_mask);
|
|
|
|
else
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
|
|
|
|
GEN6_RC_CTL_EI_MODE(1) |
|
|
|
|
rc6_mask);
|
2013-11-03 04:07:52 +00:00
|
|
|
|
|
|
|
/* 4 Program defaults and thresholds for RPS*/
|
2014-04-01 00:16:41 +00:00
|
|
|
I915_WRITE(GEN6_RPNSWREQ,
|
|
|
|
HSW_FREQUENCY(dev_priv->rps.rp1_freq));
|
|
|
|
I915_WRITE(GEN6_RC_VIDEO_FREQ,
|
|
|
|
HSW_FREQUENCY(dev_priv->rps.rp1_freq));
|
2014-09-29 13:07:19 +00:00
|
|
|
/* NB: Docs say 1s, and 1000000 - which aren't equivalent */
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
|
|
|
|
|
|
|
|
/* Docs recommend 900MHz, and 300 MHz respectively */
|
|
|
|
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
|
|
|
|
dev_priv->rps.max_freq_softlimit << 24 |
|
|
|
|
dev_priv->rps.min_freq_softlimit << 16);
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
|
|
|
|
I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
|
2013-11-03 04:07:52 +00:00
|
|
|
|
|
|
|
/* 5: Enable RPS */
|
2014-09-29 13:07:19 +00:00
|
|
|
I915_WRITE(GEN6_RP_CONTROL,
|
|
|
|
GEN6_RP_MEDIA_TURBO |
|
|
|
|
GEN6_RP_MEDIA_HW_NORMAL_MODE |
|
|
|
|
GEN6_RP_MEDIA_IS_GFX |
|
|
|
|
GEN6_RP_ENABLE |
|
|
|
|
GEN6_RP_UP_BUSY_AVG |
|
|
|
|
GEN6_RP_DOWN_IDLE_AVG);
|
|
|
|
|
|
|
|
/* 6: Ring frequency + overclocking (our driver does this later */
|
|
|
|
|
2016-07-13 08:10:32 +00:00
|
|
|
reset_rps(dev_priv, gen6_set_rps);
|
2014-09-29 13:07:19 +00:00
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2013-11-03 04:07:52 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void gen6_enable_rps(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:23 +00:00
|
|
|
{
|
2016-03-16 11:00:36 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2016-07-13 08:10:34 +00:00
|
|
|
u32 rc6vids, rc6_mask = 0;
|
2012-04-18 18:29:23 +00:00
|
|
|
u32 gtfifodbg;
|
|
|
|
int rc6_mode;
|
2016-03-24 11:20:38 +00:00
|
|
|
int ret;
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-11-02 18:14:01 +00:00
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
2012-06-24 14:42:33 +00:00
|
|
|
|
2012-04-18 18:29:23 +00:00
|
|
|
/* Here begins a magic sequence of register writes to enable
|
|
|
|
* auto-downclocking.
|
|
|
|
*
|
|
|
|
* Perhaps there might be some value in exposing these to
|
|
|
|
* userspace...
|
|
|
|
*/
|
|
|
|
I915_WRITE(GEN6_RC_STATE, 0);
|
|
|
|
|
|
|
|
/* Clear the DBG now so we don't confuse earlier errors */
|
2016-04-13 18:09:30 +00:00
|
|
|
gtfifodbg = I915_READ(GTFIFODBG);
|
|
|
|
if (gtfifodbg) {
|
2012-04-18 18:29:23 +00:00
|
|
|
DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
|
|
|
|
I915_WRITE(GTFIFODBG, gtfifodbg);
|
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
|
|
|
/* disable the counters and set deterministic thresholds */
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
|
|
|
|
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
|
|
|
|
I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
|
|
|
|
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
|
|
|
|
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
|
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id)
|
2016-03-16 11:00:36 +00:00
|
|
|
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
|
|
|
I915_WRITE(GEN6_RC_SLEEP, 0);
|
|
|
|
I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_IVYBRIDGE(dev_priv))
|
2013-08-13 18:55:17 +00:00
|
|
|
I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
|
|
|
|
else
|
|
|
|
I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
|
2013-01-30 03:41:59 +00:00
|
|
|
I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
|
2012-04-18 18:29:23 +00:00
|
|
|
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
|
|
|
|
|
2012-07-02 14:51:05 +00:00
|
|
|
/* Check if we are enabling RC6 */
|
2016-05-10 13:10:04 +00:00
|
|
|
rc6_mode = intel_enable_rc6();
|
2012-04-18 18:29:23 +00:00
|
|
|
if (rc6_mode & INTEL_RC6_ENABLE)
|
|
|
|
rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
|
|
|
|
|
2012-07-02 14:51:05 +00:00
|
|
|
/* We don't use those on Haswell */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (!IS_HASWELL(dev_priv)) {
|
2012-07-02 14:51:05 +00:00
|
|
|
if (rc6_mode & INTEL_RC6p_ENABLE)
|
|
|
|
rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-07-02 14:51:05 +00:00
|
|
|
if (rc6_mode & INTEL_RC6pp_ENABLE)
|
|
|
|
rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
|
|
|
|
}
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
intel_print_rc6_info(dev_priv, rc6_mask);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL,
|
|
|
|
rc6_mask |
|
|
|
|
GEN6_RC_CTL_EI_MODE(1) |
|
|
|
|
GEN6_RC_CTL_HW_ENABLE);
|
|
|
|
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
/* Power down if completely idle for over 50ms */
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
|
2012-04-18 18:29:23 +00:00
|
|
|
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
|
|
|
|
|
2016-07-13 08:10:32 +00:00
|
|
|
reset_rps(dev_priv, gen6_set_rps);
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-09-26 17:34:01 +00:00
|
|
|
rc6vids = 0;
|
|
|
|
ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_GEN6(dev_priv) && ret) {
|
2012-09-26 17:34:01 +00:00
|
|
|
DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
|
2012-09-26 17:34:01 +00:00
|
|
|
DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
|
|
|
|
GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
|
|
|
|
rc6vids &= 0xffff00;
|
|
|
|
rc6vids |= GEN6_ENCODE_RC6_VID(450);
|
|
|
|
ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
|
|
|
|
if (ret)
|
|
|
|
DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
|
|
|
|
}
|
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2012-04-18 18:29:23 +00:00
|
|
|
}
|
|
|
|
|
2016-07-13 08:10:38 +00:00
|
|
|
static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:23 +00:00
|
|
|
{
|
|
|
|
int min_freq = 15;
|
2013-04-12 18:10:13 +00:00
|
|
|
unsigned int gpu_freq;
|
|
|
|
unsigned int max_ia_freq, min_ring_freq;
|
2015-06-29 09:20:20 +00:00
|
|
|
unsigned int max_gpu_freq, min_gpu_freq;
|
2012-04-18 18:29:23 +00:00
|
|
|
int scaling_factor = 180;
|
2013-10-07 20:15:48 +00:00
|
|
|
struct cpufreq_policy *policy;
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-11-02 18:14:01 +00:00
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
2012-06-24 14:42:33 +00:00
|
|
|
|
2013-10-07 20:15:48 +00:00
|
|
|
policy = cpufreq_cpu_get(0);
|
|
|
|
if (policy) {
|
|
|
|
max_ia_freq = policy->cpuinfo.max_freq;
|
|
|
|
cpufreq_cpu_put(policy);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Default to measured freq if none found, PCU will ensure we
|
|
|
|
* don't go over
|
|
|
|
*/
|
2012-04-18 18:29:23 +00:00
|
|
|
max_ia_freq = tsc_khz;
|
2013-10-07 20:15:48 +00:00
|
|
|
}
|
2012-04-18 18:29:23 +00:00
|
|
|
|
|
|
|
/* Convert from kHz to MHz */
|
|
|
|
max_ia_freq /= 1000;
|
|
|
|
|
2013-10-23 05:05:09 +00:00
|
|
|
min_ring_freq = I915_READ(DCLK) & 0xf;
|
2013-10-02 16:25:02 +00:00
|
|
|
/* convert DDR frequency from units of 266.6MHz to bandwidth */
|
|
|
|
min_ring_freq = mult_frac(min_ring_freq, 8, 3);
|
2013-04-12 18:10:13 +00:00
|
|
|
|
2017-01-23 18:32:37 +00:00
|
|
|
if (IS_GEN9_BC(dev_priv)) {
|
2015-06-29 09:20:20 +00:00
|
|
|
/* Convert GT frequency to 50 HZ units */
|
|
|
|
min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
|
|
|
|
max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
|
|
|
|
} else {
|
|
|
|
min_gpu_freq = dev_priv->rps.min_freq;
|
|
|
|
max_gpu_freq = dev_priv->rps.max_freq;
|
|
|
|
}
|
|
|
|
|
2012-04-18 18:29:23 +00:00
|
|
|
/*
|
|
|
|
* For each potential GPU frequency, load a ring frequency we'd like
|
|
|
|
* to use for memory access. We do this by specifying the IA frequency
|
|
|
|
* the PCU should use as a reference to determine the ring frequency.
|
|
|
|
*/
|
2015-06-29 09:20:20 +00:00
|
|
|
for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
|
|
|
|
int diff = max_gpu_freq - gpu_freq;
|
2013-04-12 18:10:13 +00:00
|
|
|
unsigned int ia_freq = 0, ring_freq = 0;
|
|
|
|
|
2017-01-23 18:32:37 +00:00
|
|
|
if (IS_GEN9_BC(dev_priv)) {
|
2015-06-29 09:20:20 +00:00
|
|
|
/*
|
|
|
|
* ring_freq = 2 * GT. ring_freq is in 100MHz units
|
|
|
|
* No floor required for ring frequency on SKL.
|
|
|
|
*/
|
|
|
|
ring_freq = gpu_freq;
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (INTEL_INFO(dev_priv)->gen >= 8) {
|
2013-11-03 04:07:49 +00:00
|
|
|
/* max(2 * GT, DDR). NB: GT is 50MHz units */
|
|
|
|
ring_freq = max(min_ring_freq, gpu_freq);
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (IS_HASWELL(dev_priv)) {
|
2013-10-02 16:25:02 +00:00
|
|
|
ring_freq = mult_frac(gpu_freq, 5, 4);
|
2013-04-12 18:10:13 +00:00
|
|
|
ring_freq = max(min_ring_freq, ring_freq);
|
|
|
|
/* leave ia_freq as the default, chosen by cpufreq */
|
|
|
|
} else {
|
|
|
|
/* On older processors, there is no separate ring
|
|
|
|
* clock domain, so in order to boost the bandwidth
|
|
|
|
* of the ring, we need to upclock the CPU (ia_freq).
|
|
|
|
*
|
|
|
|
* For GPU frequencies less than 750MHz,
|
|
|
|
* just use the lowest ring freq.
|
|
|
|
*/
|
|
|
|
if (gpu_freq < min_freq)
|
|
|
|
ia_freq = 800;
|
|
|
|
else
|
|
|
|
ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
|
|
|
|
ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
|
|
|
|
}
|
2012-04-18 18:29:23 +00:00
|
|
|
|
2012-09-26 17:34:00 +00:00
|
|
|
sandybridge_pcode_write(dev_priv,
|
|
|
|
GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
|
2013-04-12 18:10:13 +00:00
|
|
|
ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
|
|
|
|
ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
|
|
|
|
gpu_freq);
|
2012-04-18 18:29:23 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-27 23:03:53 +00:00
|
|
|
static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
|
2014-05-27 10:29:30 +00:00
|
|
|
{
|
|
|
|
u32 val, rp0;
|
|
|
|
|
2015-10-07 08:17:46 +00:00
|
|
|
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
|
2014-05-27 10:29:30 +00:00
|
|
|
|
2016-08-31 16:13:02 +00:00
|
|
|
switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
|
2015-10-07 08:17:46 +00:00
|
|
|
case 8:
|
|
|
|
/* (2 * 4) config */
|
|
|
|
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
|
|
|
|
break;
|
|
|
|
case 12:
|
|
|
|
/* (2 * 6) config */
|
|
|
|
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
/* (2 * 8) config */
|
|
|
|
default:
|
|
|
|
/* Setting (2 * 8) Min RP0 for any other combination */
|
|
|
|
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
|
|
|
|
break;
|
2015-01-17 05:35:59 +00:00
|
|
|
}
|
2015-10-07 08:17:46 +00:00
|
|
|
|
|
|
|
rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
|
|
|
|
|
2014-05-27 10:29:30 +00:00
|
|
|
return rp0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 val, rpe;
|
|
|
|
|
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
|
|
|
|
rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
|
|
|
|
|
|
|
|
return rpe;
|
|
|
|
}
|
|
|
|
|
2014-07-12 13:16:14 +00:00
|
|
|
static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 val, rp1;
|
|
|
|
|
2015-10-07 08:17:46 +00:00
|
|
|
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
|
|
|
|
rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
|
|
|
|
|
2014-07-12 13:16:14 +00:00
|
|
|
return rp1;
|
|
|
|
}
|
|
|
|
|
2014-07-10 07:46:21 +00:00
|
|
|
static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 val, rp1;
|
|
|
|
|
|
|
|
val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
|
|
|
|
|
|
|
|
rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
|
|
|
|
|
|
|
|
return rp1;
|
|
|
|
}
|
|
|
|
|
2014-06-27 23:03:53 +00:00
|
|
|
static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
|
2013-04-17 22:54:58 +00:00
|
|
|
{
|
|
|
|
u32 val, rp0;
|
|
|
|
|
2013-05-22 12:36:20 +00:00
|
|
|
val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
|
2013-04-17 22:54:58 +00:00
|
|
|
|
|
|
|
rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
|
|
|
|
/* Clamp to max */
|
|
|
|
rp0 = min_t(u32, rp0, 0xea);
|
|
|
|
|
|
|
|
return rp0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 val, rpe;
|
|
|
|
|
2013-05-22 12:36:20 +00:00
|
|
|
val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
|
2013-04-17 22:54:58 +00:00
|
|
|
rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
|
2013-05-22 12:36:20 +00:00
|
|
|
val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
|
2013-04-17 22:54:58 +00:00
|
|
|
rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
|
|
|
|
|
|
|
|
return rpe;
|
|
|
|
}
|
|
|
|
|
2014-06-27 23:03:53 +00:00
|
|
|
static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
|
2013-04-17 22:54:58 +00:00
|
|
|
{
|
2014-12-04 16:39:35 +00:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
|
|
|
|
/*
|
|
|
|
* According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
|
|
|
|
* for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
|
|
|
|
* a BYT-M B0 the above register contains 0xbf. Moreover when setting
|
|
|
|
* a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
|
|
|
|
* to make sure it matches what Punit accepts.
|
|
|
|
*/
|
|
|
|
return max_t(u32, val, 0xc0);
|
2013-04-17 22:54:58 +00:00
|
|
|
}
|
|
|
|
|
2014-03-31 12:10:44 +00:00
|
|
|
/* Check that the pctx buffer wasn't move under us. */
|
|
|
|
static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
|
|
|
|
|
|
|
|
WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
|
|
|
|
dev_priv->vlv_pctx->stolen->start);
|
|
|
|
}
|
|
|
|
|
2014-05-23 15:30:15 +00:00
|
|
|
|
|
|
|
/* Check that the pcbr address is not empty. */
|
|
|
|
static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
|
|
|
|
|
|
|
|
WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
|
2014-05-23 15:30:15 +00:00
|
|
|
{
|
2016-03-18 08:42:57 +00:00
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2016-03-30 13:57:10 +00:00
|
|
|
unsigned long pctx_paddr, paddr;
|
2014-05-23 15:30:15 +00:00
|
|
|
u32 pcbr;
|
|
|
|
int pctx_size = 32*1024;
|
|
|
|
|
|
|
|
pcbr = I915_READ(VLV_PCBR);
|
|
|
|
if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
|
2014-11-07 19:33:46 +00:00
|
|
|
DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
|
2014-05-23 15:30:15 +00:00
|
|
|
paddr = (dev_priv->mm.stolen_base +
|
2016-03-18 08:42:57 +00:00
|
|
|
(ggtt->stolen_size - pctx_size));
|
2014-05-23 15:30:15 +00:00
|
|
|
|
|
|
|
pctx_paddr = (paddr & (~4095));
|
|
|
|
I915_WRITE(VLV_PCBR, pctx_paddr);
|
|
|
|
}
|
2014-11-07 19:33:46 +00:00
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
|
2014-05-23 15:30:15 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
|
2013-05-08 17:45:13 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *pctx;
|
|
|
|
unsigned long pctx_paddr;
|
|
|
|
u32 pcbr;
|
|
|
|
int pctx_size = 24*1024;
|
|
|
|
|
|
|
|
pcbr = I915_READ(VLV_PCBR);
|
|
|
|
if (pcbr) {
|
|
|
|
/* BIOS set it up already, grab the pre-alloc'd space */
|
|
|
|
int pcbr_offset;
|
|
|
|
|
|
|
|
pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
|
2016-12-01 14:16:36 +00:00
|
|
|
pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
|
2013-05-08 17:45:13 +00:00
|
|
|
pcbr_offset,
|
2013-07-04 11:06:28 +00:00
|
|
|
I915_GTT_OFFSET_NONE,
|
2013-05-08 17:45:13 +00:00
|
|
|
pctx_size);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2014-11-07 19:33:46 +00:00
|
|
|
DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
|
|
|
|
|
2013-05-08 17:45:13 +00:00
|
|
|
/*
|
|
|
|
* From the Gunit register HAS:
|
|
|
|
* The Gfx driver is expected to program this register and ensure
|
|
|
|
* proper allocation within Gfx stolen memory. For example, this
|
|
|
|
* register should be programmed such than the PCBR range does not
|
|
|
|
* overlap with other ranges, such as the frame buffer, protected
|
|
|
|
* memory, or any other relevant ranges.
|
|
|
|
*/
|
2016-12-01 14:16:36 +00:00
|
|
|
pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
|
2013-05-08 17:45:13 +00:00
|
|
|
if (!pctx) {
|
|
|
|
DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
|
2016-02-11 10:27:30 +00:00
|
|
|
goto out;
|
2013-05-08 17:45:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
|
|
|
|
I915_WRITE(VLV_PCBR, pctx_paddr);
|
|
|
|
|
|
|
|
out:
|
2014-11-07 19:33:46 +00:00
|
|
|
DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
|
2013-05-08 17:45:13 +00:00
|
|
|
dev_priv->vlv_pctx = pctx;
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
|
2014-03-31 12:10:44 +00:00
|
|
|
{
|
|
|
|
if (WARN_ON(!dev_priv->vlv_pctx))
|
|
|
|
return;
|
|
|
|
|
2016-10-28 12:58:43 +00:00
|
|
|
i915_gem_object_put(dev_priv->vlv_pctx);
|
2014-03-31 12:10:44 +00:00
|
|
|
dev_priv->vlv_pctx = NULL;
|
|
|
|
}
|
|
|
|
|
2016-03-04 19:43:02 +00:00
|
|
|
static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
dev_priv->rps.gpll_ref_freq =
|
|
|
|
vlv_get_cck_clock(dev_priv, "GPLL ref",
|
|
|
|
CCK_GPLL_CLOCK_CONTROL,
|
|
|
|
dev_priv->czclk_freq);
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
|
|
|
|
dev_priv->rps.gpll_ref_freq);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
|
2014-04-14 17:24:41 +00:00
|
|
|
{
|
2014-08-18 11:42:44 +00:00
|
|
|
u32 val;
|
2014-04-14 17:24:41 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
valleyview_setup_pctx(dev_priv);
|
2014-04-14 17:24:41 +00:00
|
|
|
|
2016-03-04 19:43:02 +00:00
|
|
|
vlv_init_gpll_ref_freq(dev_priv);
|
|
|
|
|
2014-08-18 11:42:44 +00:00
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
|
|
|
|
switch ((val >> 6) & 3) {
|
|
|
|
case 0:
|
|
|
|
case 1:
|
|
|
|
dev_priv->mem_freq = 800;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
dev_priv->mem_freq = 1066;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
dev_priv->mem_freq = 1333;
|
|
|
|
break;
|
|
|
|
}
|
2014-11-10 20:55:14 +00:00
|
|
|
DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
|
2014-08-18 11:42:44 +00:00
|
|
|
|
2014-04-14 17:24:41 +00:00
|
|
|
dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
|
|
|
|
dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
|
|
|
|
DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
|
2014-04-14 17:24:41 +00:00
|
|
|
dev_priv->rps.max_freq);
|
|
|
|
|
|
|
|
dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
|
|
|
|
DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
|
2014-04-14 17:24:41 +00:00
|
|
|
dev_priv->rps.efficient_freq);
|
|
|
|
|
2014-07-10 07:46:21 +00:00
|
|
|
dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
|
|
|
|
DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
|
2014-07-10 07:46:21 +00:00
|
|
|
dev_priv->rps.rp1_freq);
|
|
|
|
|
2014-04-14 17:24:41 +00:00
|
|
|
dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
|
|
|
|
DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
|
2014-04-14 17:24:41 +00:00
|
|
|
dev_priv->rps.min_freq);
|
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
|
2014-05-23 15:30:15 +00:00
|
|
|
{
|
2014-08-18 11:42:44 +00:00
|
|
|
u32 val;
|
2014-05-27 10:29:30 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
cherryview_setup_pctx(dev_priv);
|
2014-05-27 10:29:30 +00:00
|
|
|
|
2016-03-04 19:43:02 +00:00
|
|
|
vlv_init_gpll_ref_freq(dev_priv);
|
|
|
|
|
2015-05-26 17:42:30 +00:00
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
2014-11-07 19:33:43 +00:00
|
|
|
val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
|
2015-05-26 17:42:30 +00:00
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
2014-11-07 19:33:43 +00:00
|
|
|
|
2014-08-18 11:42:44 +00:00
|
|
|
switch ((val >> 2) & 0x7) {
|
|
|
|
case 3:
|
|
|
|
dev_priv->mem_freq = 2000;
|
|
|
|
break;
|
2015-09-24 20:29:18 +00:00
|
|
|
default:
|
2014-08-18 11:42:44 +00:00
|
|
|
dev_priv->mem_freq = 1600;
|
|
|
|
break;
|
|
|
|
}
|
2014-11-10 20:55:14 +00:00
|
|
|
DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
|
2014-08-18 11:42:44 +00:00
|
|
|
|
2014-05-27 10:29:30 +00:00
|
|
|
dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
|
|
|
|
dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
|
|
|
|
DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
|
2014-05-27 10:29:30 +00:00
|
|
|
dev_priv->rps.max_freq);
|
|
|
|
|
|
|
|
dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
|
|
|
|
DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
|
2014-05-27 10:29:30 +00:00
|
|
|
dev_priv->rps.efficient_freq);
|
|
|
|
|
2014-07-12 13:16:14 +00:00
|
|
|
dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
|
|
|
|
DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
|
2014-07-12 13:16:14 +00:00
|
|
|
dev_priv->rps.rp1_freq);
|
|
|
|
|
2015-05-09 12:45:46 +00:00
|
|
|
/* PUnit validated range is only [RPe, RP0] */
|
|
|
|
dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
|
2014-05-27 10:29:30 +00:00
|
|
|
DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
|
drm/i915: Use intel_gpu_freq() and intel_freq_opcode()
Replace all the vlv_gpu_freq(), vlv_freq_opcode(),
*GT_FREQUENCY_MULTIPLIER, and /GT_FREQUENCY_MULTIPLIER instances
with intel_gpu_freq() and intel_freq_opcode() calls.
Most of the change was performed with the following semantic patch:
@@
expression E;
@@
(
- E * GT_FREQUENCY_MULTIPLIER
+ intel_gpu_freq(dev_priv, E)
|
- E *= GT_FREQUENCY_MULTIPLIER
+ E = intel_gpu_freq(dev_priv, E)
|
- E /= GT_FREQUENCY_MULTIPLIER
+ E = intel_freq_opcode(dev_priv, E)
|
- do_div(E, GT_FREQUENCY_MULTIPLIER)
+ E = intel_freq_opcode(dev_priv, E)
)
@@
expression E1, E2;
@@
(
- vlv_gpu_freq(E1, E2)
+ intel_gpu_freq(E1, E2)
|
- vlv_freq_opcode(E1, E2)
+ intel_freq_opcode(E1, E2)
)
@@
expression E1, E2, E3, E4;
@@
(
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_gpu_freq(E3, E4);
- } else {
- E2 = intel_gpu_freq(E3, E4);
- }
+ E2 = intel_gpu_freq(E3, E4);
|
- if (IS_VALLEYVIEW(E1)) {
- E2 = intel_freq_opcode(E3, E4);
- } else {
- E2 = intel_freq_opcode(E3, E4);
- }
+ E2 = intel_freq_opcode(E3, E4);
)
One hunk was manually undone as intel_gpu_freq() ended up
calling itself. Supposedly it would be possible to exclude
certain functions via !=~, but I couldn't get that to work.
Also the removal of vlv_gpu_freq() and vlv_opcode_freq() compat
wrappers was done manually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-23 19:04:26 +00:00
|
|
|
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
|
2014-05-27 10:29:30 +00:00
|
|
|
dev_priv->rps.min_freq);
|
|
|
|
|
2014-08-18 11:42:43 +00:00
|
|
|
WARN_ONCE((dev_priv->rps.max_freq |
|
|
|
|
dev_priv->rps.efficient_freq |
|
|
|
|
dev_priv->rps.rp1_freq |
|
|
|
|
dev_priv->rps.min_freq) & 1,
|
|
|
|
"Odd GPU freq values\n");
|
2014-05-23 15:30:15 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
|
2014-04-14 17:24:41 +00:00
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
valleyview_cleanup_pctx(dev_priv);
|
2014-04-14 17:24:41 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
|
2014-05-23 15:30:15 +00:00
|
|
|
{
|
2016-03-16 11:00:36 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2014-05-27 10:29:30 +00:00
|
|
|
u32 gtfifodbg, val, rc6_mode = 0, pcbr;
|
2014-05-23 15:30:15 +00:00
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
|
|
|
|
2016-04-13 18:09:30 +00:00
|
|
|
gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
|
|
|
|
GT_FIFO_FREE_ENTRIES_CHV);
|
2014-05-23 15:30:15 +00:00
|
|
|
if (gtfifodbg) {
|
|
|
|
DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
|
|
|
|
gtfifodbg);
|
|
|
|
I915_WRITE(GTFIFODBG, gtfifodbg);
|
|
|
|
}
|
|
|
|
|
|
|
|
cherryview_check_pctx(dev_priv);
|
|
|
|
|
|
|
|
/* 1a & 1b: Get forcewake during program sequence. Although the driver
|
|
|
|
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2014-05-23 15:30:15 +00:00
|
|
|
|
2015-01-19 11:50:47 +00:00
|
|
|
/* Disable RC states. */
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
|
|
|
|
2014-05-23 15:30:15 +00:00
|
|
|
/* 2a: Program RC6 thresholds.*/
|
|
|
|
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
|
|
|
|
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
|
|
|
|
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
|
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id)
|
2016-03-16 11:00:36 +00:00
|
|
|
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
|
2014-05-23 15:30:15 +00:00
|
|
|
I915_WRITE(GEN6_RC_SLEEP, 0);
|
|
|
|
|
2015-03-28 09:53:35 +00:00
|
|
|
/* TO threshold set to 500 us ( 0x186 * 1.28 us) */
|
|
|
|
I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
|
2014-05-23 15:30:15 +00:00
|
|
|
|
|
|
|
/* allows RC6 residency counter to work */
|
|
|
|
I915_WRITE(VLV_COUNTER_CONTROL,
|
|
|
|
_MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
|
|
|
|
VLV_MEDIA_RC6_COUNT_EN |
|
|
|
|
VLV_RENDER_RC6_COUNT_EN));
|
|
|
|
|
|
|
|
/* For now we assume BIOS is allocating and populating the PCBR */
|
|
|
|
pcbr = I915_READ(VLV_PCBR);
|
|
|
|
|
|
|
|
/* 3: Enable RC6 */
|
2016-05-10 13:10:04 +00:00
|
|
|
if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
|
|
|
|
(pcbr >> VLV_PCBR_ADDR_SHIFT))
|
2015-01-19 11:50:50 +00:00
|
|
|
rc6_mode = GEN7_RC_CTL_TO_MODE;
|
2014-05-23 15:30:15 +00:00
|
|
|
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
|
|
|
|
|
2014-05-27 10:29:30 +00:00
|
|
|
/* 4 Program defaults and thresholds for RPS*/
|
2015-01-19 11:50:49 +00:00
|
|
|
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
|
2014-05-27 10:29:30 +00:00
|
|
|
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
|
|
|
|
I915_WRITE(GEN6_RP_UP_EI, 66000);
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_EI, 350000);
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
|
|
|
|
|
|
|
|
/* 5: Enable RPS */
|
|
|
|
I915_WRITE(GEN6_RP_CONTROL,
|
|
|
|
GEN6_RP_MEDIA_HW_NORMAL_MODE |
|
2015-01-21 17:37:59 +00:00
|
|
|
GEN6_RP_MEDIA_IS_GFX |
|
2014-05-27 10:29:30 +00:00
|
|
|
GEN6_RP_ENABLE |
|
|
|
|
GEN6_RP_UP_BUSY_AVG |
|
|
|
|
GEN6_RP_DOWN_IDLE_AVG);
|
|
|
|
|
2015-04-29 03:06:24 +00:00
|
|
|
/* Setting Fixed Bias */
|
|
|
|
val = VLV_OVERRIDE_EN |
|
|
|
|
VLV_SOC_TDP_EN |
|
|
|
|
CHV_BIAS_CPU_50_SOC_50;
|
|
|
|
vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
|
|
|
|
|
2014-05-27 10:29:30 +00:00
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
|
|
|
|
|
2014-11-07 19:33:45 +00:00
|
|
|
/* RPS code assumes GPLL is used */
|
|
|
|
WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
|
|
|
|
|
2015-09-03 08:16:09 +00:00
|
|
|
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
|
2014-05-27 10:29:30 +00:00
|
|
|
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
|
|
|
|
|
2016-07-13 08:10:32 +00:00
|
|
|
reset_rps(dev_priv, valleyview_set_rps);
|
2014-05-27 10:29:30 +00:00
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2014-05-23 15:30:15 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
|
2013-04-17 22:54:58 +00:00
|
|
|
{
|
2016-03-16 11:00:36 +00:00
|
|
|
struct intel_engine_cs *engine;
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
enum intel_engine_id id;
|
2014-03-20 01:31:13 +00:00
|
|
|
u32 gtfifodbg, val, rc6_mode = 0;
|
2013-04-17 22:54:58 +00:00
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
|
|
|
|
2014-03-31 12:10:44 +00:00
|
|
|
valleyview_check_pctx(dev_priv);
|
|
|
|
|
2016-04-13 18:09:30 +00:00
|
|
|
gtfifodbg = I915_READ(GTFIFODBG);
|
|
|
|
if (gtfifodbg) {
|
2013-09-27 17:40:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
|
|
|
|
gtfifodbg);
|
2013-04-17 22:54:58 +00:00
|
|
|
I915_WRITE(GTFIFODBG, gtfifodbg);
|
|
|
|
}
|
|
|
|
|
2013-11-23 09:25:42 +00:00
|
|
|
/* If VLV, Forcewake all wells, else re-direct to regular path */
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
2013-04-17 22:54:58 +00:00
|
|
|
|
2015-01-19 11:50:47 +00:00
|
|
|
/* Disable RC states. */
|
|
|
|
I915_WRITE(GEN6_RC_CONTROL, 0);
|
|
|
|
|
2015-01-19 11:50:48 +00:00
|
|
|
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
|
2013-04-17 22:54:58 +00:00
|
|
|
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
|
|
|
|
I915_WRITE(GEN6_RP_UP_EI, 66000);
|
|
|
|
I915_WRITE(GEN6_RP_DOWN_EI, 350000);
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RP_CONTROL,
|
|
|
|
GEN6_RP_MEDIA_TURBO |
|
|
|
|
GEN6_RP_MEDIA_HW_NORMAL_MODE |
|
|
|
|
GEN6_RP_MEDIA_IS_GFX |
|
|
|
|
GEN6_RP_ENABLE |
|
|
|
|
GEN6_RP_UP_BUSY_AVG |
|
|
|
|
GEN6_RP_DOWN_IDLE_CONT);
|
|
|
|
|
|
|
|
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
|
|
|
|
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
|
|
|
|
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
|
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
for_each_engine(engine, dev_priv, id)
|
2016-03-16 11:00:36 +00:00
|
|
|
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
|
2013-04-17 22:54:58 +00:00
|
|
|
|
2013-11-15 17:32:11 +00:00
|
|
|
I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
|
2013-04-17 22:54:58 +00:00
|
|
|
|
|
|
|
/* allows RC6 residency counter to work */
|
2013-09-27 00:55:57 +00:00
|
|
|
I915_WRITE(VLV_COUNTER_CONTROL,
|
2014-07-03 21:33:01 +00:00
|
|
|
_MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
|
|
|
|
VLV_RENDER_RC0_COUNT_EN |
|
2013-09-27 00:55:57 +00:00
|
|
|
VLV_MEDIA_RC6_COUNT_EN |
|
|
|
|
VLV_RENDER_RC6_COUNT_EN));
|
2014-07-03 21:33:01 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (intel_enable_rc6() & INTEL_RC6_ENABLE)
|
2013-11-15 17:32:12 +00:00
|
|
|
rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
|
2013-10-18 19:32:07 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
intel_print_rc6_info(dev_priv, rc6_mode);
|
2013-10-18 19:32:07 +00:00
|
|
|
|
2013-09-19 16:33:13 +00:00
|
|
|
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
|
2013-04-17 22:54:58 +00:00
|
|
|
|
2015-04-29 03:06:24 +00:00
|
|
|
/* Setting Fixed Bias */
|
|
|
|
val = VLV_OVERRIDE_EN |
|
|
|
|
VLV_SOC_TDP_EN |
|
|
|
|
VLV_BIAS_CPU_125_SOC_875;
|
|
|
|
vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
|
|
|
|
|
2013-05-22 12:36:20 +00:00
|
|
|
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
|
2013-04-17 22:54:58 +00:00
|
|
|
|
2014-11-07 19:33:45 +00:00
|
|
|
/* RPS code assumes GPLL is used */
|
|
|
|
WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
|
|
|
|
|
2015-09-03 08:16:09 +00:00
|
|
|
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
|
2013-04-17 22:54:58 +00:00
|
|
|
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
|
|
|
|
|
2016-07-13 08:10:32 +00:00
|
|
|
reset_rps(dev_priv, valleyview_set_rps);
|
2013-04-17 22:54:58 +00:00
|
|
|
|
2015-01-16 09:34:40 +00:00
|
|
|
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
2013-04-17 22:54:58 +00:00
|
|
|
}
|
|
|
|
|
2012-04-18 18:29:24 +00:00
|
|
|
static unsigned long intel_pxfreq(u32 vidfreq)
|
|
|
|
{
|
|
|
|
unsigned long freq;
|
|
|
|
int div = (vidfreq & 0x3f0000) >> 16;
|
|
|
|
int post = (vidfreq & 0x3000) >> 12;
|
|
|
|
int pre = (vidfreq & 0x7);
|
|
|
|
|
|
|
|
if (!pre)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
freq = ((div * 133333) / ((1<<post) * pre));
|
|
|
|
|
|
|
|
return freq;
|
|
|
|
}
|
|
|
|
|
2012-04-26 21:28:12 +00:00
|
|
|
static const struct cparams {
|
|
|
|
u16 i;
|
|
|
|
u16 t;
|
|
|
|
u16 m;
|
|
|
|
u16 c;
|
|
|
|
} cparams[] = {
|
|
|
|
{ 1, 1333, 301, 28664 },
|
|
|
|
{ 1, 1066, 294, 24460 },
|
|
|
|
{ 1, 800, 294, 25192 },
|
|
|
|
{ 0, 1333, 276, 27605 },
|
|
|
|
{ 0, 1066, 276, 27605 },
|
|
|
|
{ 0, 800, 231, 23784 },
|
|
|
|
};
|
|
|
|
|
2012-09-25 09:16:12 +00:00
|
|
|
static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
|
2012-04-26 21:28:12 +00:00
|
|
|
{
|
|
|
|
u64 total_count, diff, ret;
|
|
|
|
u32 count1, count2, count3, m = 0, c = 0;
|
|
|
|
unsigned long now = jiffies_to_msecs(jiffies), diff1;
|
|
|
|
int i;
|
|
|
|
|
2012-08-09 14:44:54 +00:00
|
|
|
assert_spin_locked(&mchdev_lock);
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
diff1 = now - dev_priv->ips.last_time1;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
/* Prevent division-by-zero if we are asking too fast.
|
|
|
|
* Also, we don't get interesting results if we are polling
|
|
|
|
* faster than once in 10ms, so just return the saved value
|
|
|
|
* in such cases.
|
|
|
|
*/
|
|
|
|
if (diff1 <= 10)
|
2012-08-08 21:35:39 +00:00
|
|
|
return dev_priv->ips.chipset_power;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
count1 = I915_READ(DMIEC);
|
|
|
|
count2 = I915_READ(DDREC);
|
|
|
|
count3 = I915_READ(CSIEC);
|
|
|
|
|
|
|
|
total_count = count1 + count2 + count3;
|
|
|
|
|
|
|
|
/* FIXME: handle per-counter overflow */
|
2012-08-08 21:35:39 +00:00
|
|
|
if (total_count < dev_priv->ips.last_count1) {
|
|
|
|
diff = ~0UL - dev_priv->ips.last_count1;
|
2012-04-26 21:28:12 +00:00
|
|
|
diff += total_count;
|
|
|
|
} else {
|
2012-08-08 21:35:39 +00:00
|
|
|
diff = total_count - dev_priv->ips.last_count1;
|
2012-04-26 21:28:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cparams); i++) {
|
2012-08-08 21:35:39 +00:00
|
|
|
if (cparams[i].i == dev_priv->ips.c_m &&
|
|
|
|
cparams[i].t == dev_priv->ips.r_t) {
|
2012-04-26 21:28:12 +00:00
|
|
|
m = cparams[i].m;
|
|
|
|
c = cparams[i].c;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
diff = div_u64(diff, diff1);
|
|
|
|
ret = ((m * diff) + c);
|
|
|
|
ret = div_u64(ret, 10);
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.last_count1 = total_count;
|
|
|
|
dev_priv->ips.last_time1 = now;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.chipset_power = ret;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-09-25 09:16:12 +00:00
|
|
|
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
unsigned long val;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->gen != 5)
|
2012-09-25 09:16:12 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
spin_lock_irq(&mchdev_lock);
|
|
|
|
|
|
|
|
val = __i915_chipset_val(dev_priv);
|
|
|
|
|
|
|
|
spin_unlock_irq(&mchdev_lock);
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-04-26 21:28:12 +00:00
|
|
|
unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
unsigned long m, x, b;
|
|
|
|
u32 tsfs;
|
|
|
|
|
|
|
|
tsfs = I915_READ(TSFS);
|
|
|
|
|
|
|
|
m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
|
|
|
|
x = I915_READ8(TR1);
|
|
|
|
|
|
|
|
b = tsfs & TSFS_INTR_MASK;
|
|
|
|
|
|
|
|
return ((m * x) / 127) - b;
|
|
|
|
}
|
|
|
|
|
2014-12-01 16:01:05 +00:00
|
|
|
static int _pxvid_to_vd(u8 pxvid)
|
|
|
|
{
|
|
|
|
if (pxvid == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (pxvid >= 8 && pxvid < 31)
|
|
|
|
pxvid = 31;
|
|
|
|
|
|
|
|
return (pxvid + 2) * 125;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
|
2012-04-26 21:28:12 +00:00
|
|
|
{
|
2014-12-01 16:01:05 +00:00
|
|
|
const int vd = _pxvid_to_vd(pxvid);
|
|
|
|
const int vm = vd - 1125;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->is_mobile)
|
2014-12-01 16:01:05 +00:00
|
|
|
return vm > 0 ? vm : 0;
|
|
|
|
|
|
|
|
return vd;
|
2012-04-26 21:28:12 +00:00
|
|
|
}
|
|
|
|
|
2012-08-09 14:44:54 +00:00
|
|
|
static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
|
2012-04-26 21:28:12 +00:00
|
|
|
{
|
2014-07-16 21:05:06 +00:00
|
|
|
u64 now, diff, diffms;
|
2012-04-26 21:28:12 +00:00
|
|
|
u32 count;
|
|
|
|
|
2012-08-09 14:44:54 +00:00
|
|
|
assert_spin_locked(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
2014-07-16 21:05:06 +00:00
|
|
|
now = ktime_get_raw_ns();
|
|
|
|
diffms = now - dev_priv->ips.last_time2;
|
|
|
|
do_div(diffms, NSEC_PER_MSEC);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
/* Don't divide by 0 */
|
|
|
|
if (!diffms)
|
|
|
|
return;
|
|
|
|
|
|
|
|
count = I915_READ(GFXEC);
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
if (count < dev_priv->ips.last_count2) {
|
|
|
|
diff = ~0UL - dev_priv->ips.last_count2;
|
2012-04-26 21:28:12 +00:00
|
|
|
diff += count;
|
|
|
|
} else {
|
2012-08-08 21:35:39 +00:00
|
|
|
diff = count - dev_priv->ips.last_count2;
|
2012-04-26 21:28:12 +00:00
|
|
|
}
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.last_count2 = count;
|
|
|
|
dev_priv->ips.last_time2 = now;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
/* More magic constants... */
|
|
|
|
diff = diff * 1181;
|
|
|
|
diff = div_u64(diff, diffms * 10);
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.gfx_power = diff;
|
2012-04-26 21:28:12 +00:00
|
|
|
}
|
|
|
|
|
2012-08-09 14:44:54 +00:00
|
|
|
void i915_update_gfx_val(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2016-05-10 13:10:04 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->gen != 5)
|
2012-08-09 14:44:54 +00:00
|
|
|
return;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2012-08-09 14:44:54 +00:00
|
|
|
|
|
|
|
__i915_update_gfx_val(dev_priv);
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-08-09 14:44:54 +00:00
|
|
|
}
|
|
|
|
|
2012-09-25 09:16:12 +00:00
|
|
|
static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
|
2012-04-26 21:28:12 +00:00
|
|
|
{
|
|
|
|
unsigned long t, corr, state1, corr2, state2;
|
|
|
|
u32 pxvid, ext_v;
|
|
|
|
|
2012-08-09 14:44:54 +00:00
|
|
|
assert_spin_locked(&mchdev_lock);
|
|
|
|
|
2015-09-18 17:03:19 +00:00
|
|
|
pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
|
2012-04-26 21:28:12 +00:00
|
|
|
pxvid = (pxvid >> 24) & 0x7f;
|
|
|
|
ext_v = pvid_to_extvid(dev_priv, pxvid);
|
|
|
|
|
|
|
|
state1 = ext_v;
|
|
|
|
|
|
|
|
t = i915_mch_val(dev_priv);
|
|
|
|
|
|
|
|
/* Revel in the empirically derived constants */
|
|
|
|
|
|
|
|
/* Correction factor in 1/100000 units */
|
|
|
|
if (t > 80)
|
|
|
|
corr = ((t * 2349) + 135940);
|
|
|
|
else if (t >= 50)
|
|
|
|
corr = ((t * 964) + 29317);
|
|
|
|
else /* < 50 */
|
|
|
|
corr = ((t * 301) + 1004);
|
|
|
|
|
|
|
|
corr = corr * ((150142 * state1) / 10000 - 78642);
|
|
|
|
corr /= 100000;
|
2012-08-08 21:35:39 +00:00
|
|
|
corr2 = (corr * dev_priv->ips.corr);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
state2 = (corr2 * state1) / 10000;
|
|
|
|
state2 /= 100; /* convert to mW */
|
|
|
|
|
2012-08-09 14:44:54 +00:00
|
|
|
__i915_update_gfx_val(dev_priv);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
return dev_priv->ips.gfx_power + state2;
|
2012-04-26 21:28:12 +00:00
|
|
|
}
|
|
|
|
|
2012-09-25 09:16:12 +00:00
|
|
|
unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
unsigned long val;
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->gen != 5)
|
2012-09-25 09:16:12 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
spin_lock_irq(&mchdev_lock);
|
|
|
|
|
|
|
|
val = __i915_gfx_val(dev_priv);
|
|
|
|
|
|
|
|
spin_unlock_irq(&mchdev_lock);
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-04-26 21:28:12 +00:00
|
|
|
/**
|
|
|
|
* i915_read_mch_val - return value for IPS use
|
|
|
|
*
|
|
|
|
* Calculate and return a value for the IPS driver to use when deciding whether
|
|
|
|
* we have thermal and power headroom to increase CPU or GPU power budget.
|
|
|
|
*/
|
|
|
|
unsigned long i915_read_mch_val(void)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
unsigned long chipset_val, graphics_val, ret = 0;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
if (!i915_mch_dev)
|
|
|
|
goto out_unlock;
|
|
|
|
dev_priv = i915_mch_dev;
|
|
|
|
|
2012-09-25 09:16:12 +00:00
|
|
|
chipset_val = __i915_chipset_val(dev_priv);
|
|
|
|
graphics_val = __i915_gfx_val(dev_priv);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
ret = chipset_val + graphics_val;
|
|
|
|
|
|
|
|
out_unlock:
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(i915_read_mch_val);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_gpu_raise - raise GPU frequency limit
|
|
|
|
*
|
|
|
|
* Raise the limit; IPS indicates we have thermal headroom.
|
|
|
|
*/
|
|
|
|
bool i915_gpu_raise(void)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
bool ret = true;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
if (!i915_mch_dev) {
|
|
|
|
ret = false;
|
|
|
|
goto out_unlock;
|
|
|
|
}
|
|
|
|
dev_priv = i915_mch_dev;
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
|
|
|
|
dev_priv->ips.max_delay--;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
out_unlock:
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(i915_gpu_raise);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_gpu_lower - lower GPU frequency limit
|
|
|
|
*
|
|
|
|
* IPS indicates we're close to a thermal limit, so throttle back the GPU
|
|
|
|
* frequency maximum.
|
|
|
|
*/
|
|
|
|
bool i915_gpu_lower(void)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
bool ret = true;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
if (!i915_mch_dev) {
|
|
|
|
ret = false;
|
|
|
|
goto out_unlock;
|
|
|
|
}
|
|
|
|
dev_priv = i915_mch_dev;
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
|
|
|
|
dev_priv->ips.max_delay++;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
out_unlock:
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(i915_gpu_lower);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_gpu_busy - indicate GPU business to IPS
|
|
|
|
*
|
|
|
|
* Tell the IPS driver whether or not the GPU is busy.
|
|
|
|
*/
|
|
|
|
bool i915_gpu_busy(void)
|
|
|
|
{
|
|
|
|
bool ret = false;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2016-08-05 09:14:11 +00:00
|
|
|
if (i915_mch_dev)
|
|
|
|
ret = i915_mch_dev->gt.awake;
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(i915_gpu_busy);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_gpu_turbo_disable - disable graphics turbo
|
|
|
|
*
|
|
|
|
* Disable graphics turbo by resetting the max frequency and setting the
|
|
|
|
* current frequency to the default.
|
|
|
|
*/
|
|
|
|
bool i915_gpu_turbo_disable(void)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv;
|
|
|
|
bool ret = true;
|
|
|
|
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
if (!i915_mch_dev) {
|
|
|
|
ret = false;
|
|
|
|
goto out_unlock;
|
|
|
|
}
|
|
|
|
dev_priv = i915_mch_dev;
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.max_delay = dev_priv->ips.fstart;
|
2012-04-26 21:28:12 +00:00
|
|
|
|
2016-05-06 13:48:28 +00:00
|
|
|
if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
|
2012-04-26 21:28:12 +00:00
|
|
|
ret = false;
|
|
|
|
|
|
|
|
out_unlock:
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Tells the intel_ips driver that the i915 driver is now loaded, if
|
|
|
|
* IPS got loaded first.
|
|
|
|
*
|
|
|
|
* This awkward dance is so that neither module has to depend on the
|
|
|
|
* other in order for IPS to do the appropriate communication of
|
|
|
|
* GPU turbo limits to i915.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
ips_ping_for_i915_load(void)
|
|
|
|
{
|
|
|
|
void (*link)(void);
|
|
|
|
|
|
|
|
link = symbol_get(ips_link_to_i915_driver);
|
|
|
|
if (link) {
|
|
|
|
link();
|
|
|
|
symbol_put(ips_link_to_i915_driver);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2012-08-09 14:44:54 +00:00
|
|
|
/* We only register the i915 ips part with intel-ips once everything is
|
|
|
|
* set up, to avoid intel-ips sneaking in and reading bogus values. */
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
i915_mch_dev = dev_priv;
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
|
|
|
|
ips_ping_for_i915_load();
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_gpu_ips_teardown(void)
|
|
|
|
{
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_lock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
i915_mch_dev = NULL;
|
2012-08-09 14:46:01 +00:00
|
|
|
spin_unlock_irq(&mchdev_lock);
|
2012-04-26 21:28:12 +00:00
|
|
|
}
|
2014-01-30 17:38:16 +00:00
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
static void intel_init_emon(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:24 +00:00
|
|
|
{
|
|
|
|
u32 lcfuse;
|
|
|
|
u8 pxw[16];
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Disable to program */
|
|
|
|
I915_WRITE(ECR, 0);
|
|
|
|
POSTING_READ(ECR);
|
|
|
|
|
|
|
|
/* Program energy weights for various events */
|
|
|
|
I915_WRITE(SDEW, 0x15040d00);
|
|
|
|
I915_WRITE(CSIEW0, 0x007f0000);
|
|
|
|
I915_WRITE(CSIEW1, 0x1e220004);
|
|
|
|
I915_WRITE(CSIEW2, 0x04000004);
|
|
|
|
|
|
|
|
for (i = 0; i < 5; i++)
|
2015-09-18 17:03:19 +00:00
|
|
|
I915_WRITE(PEW(i), 0);
|
2012-04-18 18:29:24 +00:00
|
|
|
for (i = 0; i < 3; i++)
|
2015-09-18 17:03:19 +00:00
|
|
|
I915_WRITE(DEW(i), 0);
|
2012-04-18 18:29:24 +00:00
|
|
|
|
|
|
|
/* Program P-state weights to account for frequency power adjustment */
|
|
|
|
for (i = 0; i < 16; i++) {
|
2015-09-18 17:03:19 +00:00
|
|
|
u32 pxvidfreq = I915_READ(PXVFREQ(i));
|
2012-04-18 18:29:24 +00:00
|
|
|
unsigned long freq = intel_pxfreq(pxvidfreq);
|
|
|
|
unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
|
|
|
|
PXVFREQ_PX_SHIFT;
|
|
|
|
unsigned long val;
|
|
|
|
|
|
|
|
val = vid * vid;
|
|
|
|
val *= (freq / 1000);
|
|
|
|
val *= 255;
|
|
|
|
val /= (127*127*900);
|
|
|
|
if (val > 0xff)
|
|
|
|
DRM_ERROR("bad pxval: %ld\n", val);
|
|
|
|
pxw[i] = val;
|
|
|
|
}
|
|
|
|
/* Render standby states get 0 weight */
|
|
|
|
pxw[14] = 0;
|
|
|
|
pxw[15] = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
|
|
|
|
(pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
|
2015-09-18 17:03:19 +00:00
|
|
|
I915_WRITE(PXW(i), val);
|
2012-04-18 18:29:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Adjust magic regs to magic values (more experimental results) */
|
|
|
|
I915_WRITE(OGW0, 0);
|
|
|
|
I915_WRITE(OGW1, 0);
|
|
|
|
I915_WRITE(EG0, 0x00007f00);
|
|
|
|
I915_WRITE(EG1, 0x0000000e);
|
|
|
|
I915_WRITE(EG2, 0x000e0000);
|
|
|
|
I915_WRITE(EG3, 0x68000300);
|
|
|
|
I915_WRITE(EG4, 0x42000000);
|
|
|
|
I915_WRITE(EG5, 0x00140031);
|
|
|
|
I915_WRITE(EG6, 0);
|
|
|
|
I915_WRITE(EG7, 0);
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++)
|
2015-09-18 17:03:19 +00:00
|
|
|
I915_WRITE(PXWL(i), 0);
|
2012-04-18 18:29:24 +00:00
|
|
|
|
|
|
|
/* Enable PMON + select events */
|
|
|
|
I915_WRITE(ECR, 0x80000019);
|
|
|
|
|
|
|
|
lcfuse = I915_READ(LCFUSE02);
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
|
2012-04-18 18:29:24 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
|
2014-03-31 12:10:44 +00:00
|
|
|
{
|
2015-12-15 18:10:31 +00:00
|
|
|
/*
|
|
|
|
* RPM depends on RC6 to save restore the GT HW context, so make RC6 a
|
|
|
|
* requirement.
|
|
|
|
*/
|
|
|
|
if (!i915.enable_rc6) {
|
|
|
|
DRM_INFO("RC6 disabled, disabling runtime PM support\n");
|
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
}
|
2014-04-18 13:01:02 +00:00
|
|
|
|
2016-08-10 12:58:24 +00:00
|
|
|
mutex_lock(&dev_priv->drm.struct_mutex);
|
2016-07-13 08:10:33 +00:00
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
/* Initialize RPS limits (for userspace) */
|
2016-05-10 13:10:04 +00:00
|
|
|
if (IS_CHERRYVIEW(dev_priv))
|
|
|
|
cherryview_init_gt_powersave(dev_priv);
|
|
|
|
else if (IS_VALLEYVIEW(dev_priv))
|
|
|
|
valleyview_init_gt_powersave(dev_priv);
|
2016-08-02 10:15:27 +00:00
|
|
|
else if (INTEL_GEN(dev_priv) >= 6)
|
2016-07-13 08:10:33 +00:00
|
|
|
gen6_init_rps_frequencies(dev_priv);
|
|
|
|
|
|
|
|
/* Derive initial user preferences/limits from the hardware limits */
|
|
|
|
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
|
|
|
|
dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
|
|
|
|
|
|
|
|
dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
|
|
|
|
dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
|
|
|
|
|
|
|
|
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
|
|
|
dev_priv->rps.min_freq_softlimit =
|
|
|
|
max_t(int,
|
|
|
|
dev_priv->rps.efficient_freq,
|
|
|
|
intel_freq_opcode(dev_priv, 450));
|
|
|
|
|
2016-07-13 08:10:34 +00:00
|
|
|
/* After setting max-softlimit, find the overclock max freq */
|
|
|
|
if (IS_GEN6(dev_priv) ||
|
|
|
|
IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
|
|
|
|
u32 params = 0;
|
|
|
|
|
|
|
|
sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms);
|
|
|
|
if (params & BIT(31)) { /* OC supported */
|
|
|
|
DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
|
|
|
|
(dev_priv->rps.max_freq & 0xff) * 50,
|
|
|
|
(params & 0xff) * 50);
|
|
|
|
dev_priv->rps.max_freq = params & 0xff;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-07-13 08:10:35 +00:00
|
|
|
/* Finally allow us to boost to max by default */
|
|
|
|
dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
|
|
|
|
|
2016-07-13 08:10:33 +00:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2016-08-10 12:58:24 +00:00
|
|
|
mutex_unlock(&dev_priv->drm.struct_mutex);
|
2016-07-21 20:16:19 +00:00
|
|
|
|
|
|
|
intel_autoenable_gt_powersave(dev_priv);
|
2014-03-31 12:10:44 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
|
2014-03-31 12:10:44 +00:00
|
|
|
{
|
2016-08-02 11:07:33 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv))
|
2016-05-10 13:10:04 +00:00
|
|
|
valleyview_cleanup_gt_powersave(dev_priv);
|
2015-12-15 18:10:31 +00:00
|
|
|
|
|
|
|
if (!i915.enable_rc6)
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
2014-03-31 12:10:44 +00:00
|
|
|
}
|
|
|
|
|
2016-07-21 20:16:19 +00:00
|
|
|
/**
|
|
|
|
* intel_suspend_gt_powersave - suspend PM work and helper threads
|
|
|
|
* @dev_priv: i915 device
|
|
|
|
*
|
|
|
|
* We don't want to disable RC6 or other features here, we just want
|
|
|
|
* to make sure any work we've queued has finished and won't bother
|
|
|
|
* us while we're suspended.
|
|
|
|
*/
|
|
|
|
void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (INTEL_GEN(dev_priv) < 6)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
|
|
|
/* gen6_rps_idle() will be called later to disable interrupts */
|
|
|
|
}
|
|
|
|
|
2016-07-13 08:10:37 +00:00
|
|
|
void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
dev_priv->rps.enabled = true; /* force disabling */
|
|
|
|
intel_disable_gt_powersave(dev_priv);
|
2016-07-21 20:16:19 +00:00
|
|
|
|
|
|
|
gen6_reset_rps_interrupts(dev_priv);
|
2014-06-12 15:35:45 +00:00
|
|
|
}
|
|
|
|
|
2016-05-10 13:10:04 +00:00
|
|
|
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
|
2012-06-24 14:42:32 +00:00
|
|
|
{
|
2016-07-13 08:10:37 +00:00
|
|
|
if (!READ_ONCE(dev_priv->rps.enabled))
|
|
|
|
return;
|
2014-05-12 15:35:04 +00:00
|
|
|
|
2016-07-13 08:10:37 +00:00
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
2014-11-19 13:30:02 +00:00
|
|
|
|
2016-07-13 08:10:37 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 9) {
|
|
|
|
gen9_disable_rc6(dev_priv);
|
|
|
|
gen9_disable_rps(dev_priv);
|
|
|
|
} else if (IS_CHERRYVIEW(dev_priv)) {
|
|
|
|
cherryview_disable_rps(dev_priv);
|
|
|
|
} else if (IS_VALLEYVIEW(dev_priv)) {
|
|
|
|
valleyview_disable_rps(dev_priv);
|
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
|
|
|
gen6_disable_rps(dev_priv);
|
|
|
|
} else if (IS_IRONLAKE_M(dev_priv)) {
|
|
|
|
ironlake_disable_drps(dev_priv);
|
2012-06-29 21:32:16 +00:00
|
|
|
}
|
2016-07-13 08:10:37 +00:00
|
|
|
|
|
|
|
dev_priv->rps.enabled = false;
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2012-06-24 14:42:32 +00:00
|
|
|
}
|
|
|
|
|
2016-07-13 08:10:37 +00:00
|
|
|
void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
|
2012-11-02 18:14:00 +00:00
|
|
|
{
|
2016-07-21 20:16:19 +00:00
|
|
|
/* We shouldn't be disabling as we submit, so this should be less
|
|
|
|
* racy than it appears!
|
|
|
|
*/
|
2016-07-13 08:10:37 +00:00
|
|
|
if (READ_ONCE(dev_priv->rps.enabled))
|
|
|
|
return;
|
2012-11-02 18:14:00 +00:00
|
|
|
|
2016-07-13 08:10:37 +00:00
|
|
|
/* Powersaving is controlled by the host when inside a VM */
|
|
|
|
if (intel_vgpu_active(dev_priv))
|
|
|
|
return;
|
2013-04-17 22:54:58 +00:00
|
|
|
|
2016-07-13 08:10:37 +00:00
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
2016-05-10 13:10:04 +00:00
|
|
|
|
|
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
|
|
cherryview_enable_rps(dev_priv);
|
|
|
|
} else if (IS_VALLEYVIEW(dev_priv)) {
|
|
|
|
valleyview_enable_rps(dev_priv);
|
2016-07-13 08:10:37 +00:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 9) {
|
2016-05-10 13:10:04 +00:00
|
|
|
gen9_enable_rc6(dev_priv);
|
|
|
|
gen9_enable_rps(dev_priv);
|
2017-01-23 18:32:37 +00:00
|
|
|
if (IS_GEN9_BC(dev_priv))
|
2016-07-13 08:10:38 +00:00
|
|
|
gen6_update_ring_freq(dev_priv);
|
2016-05-10 13:10:04 +00:00
|
|
|
} else if (IS_BROADWELL(dev_priv)) {
|
|
|
|
gen8_enable_rps(dev_priv);
|
2016-07-13 08:10:38 +00:00
|
|
|
gen6_update_ring_freq(dev_priv);
|
2016-07-13 08:10:37 +00:00
|
|
|
} else if (INTEL_GEN(dev_priv) >= 6) {
|
2016-05-10 13:10:04 +00:00
|
|
|
gen6_enable_rps(dev_priv);
|
2016-07-13 08:10:38 +00:00
|
|
|
gen6_update_ring_freq(dev_priv);
|
2016-07-13 08:10:37 +00:00
|
|
|
} else if (IS_IRONLAKE_M(dev_priv)) {
|
|
|
|
ironlake_enable_drps(dev_priv);
|
|
|
|
intel_init_emon(dev_priv);
|
2013-04-17 22:54:58 +00:00
|
|
|
}
|
2015-03-18 09:48:21 +00:00
|
|
|
|
|
|
|
WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
|
|
|
|
WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
|
|
|
|
|
|
|
|
WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
|
|
|
|
WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
|
|
|
|
|
2016-07-21 20:16:19 +00:00
|
|
|
dev_priv->rps.enabled = true;
|
2016-07-13 08:10:37 +00:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
}
|
2014-11-19 13:30:03 +00:00
|
|
|
|
2016-07-21 20:16:19 +00:00
|
|
|
static void __intel_autoenable_gt_powersave(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
|
|
|
|
struct intel_engine_cs *rcs;
|
|
|
|
struct drm_i915_gem_request *req;
|
|
|
|
|
|
|
|
if (READ_ONCE(dev_priv->rps.enabled))
|
|
|
|
goto out;
|
|
|
|
|
drm/i915: Allocate intel_engine_cs structure only for the enabled engines
With the possibility of addition of many more number of rings in future,
the drm_i915_private structure could bloat as an array, of type
intel_engine_cs, is embedded inside it.
struct intel_engine_cs engine[I915_NUM_ENGINES];
Though this is still fine as generally there is only a single instance of
drm_i915_private structure used, but not all of the possible rings would be
enabled or active on most of the platforms. Some memory can be saved by
allocating intel_engine_cs structure only for the enabled/active engines.
Currently the engine/ring ID is kept static and dev_priv->engine[] is simply
indexed using the enums defined in intel_engine_id.
To save memory and continue using the static engine/ring IDs, 'engine' is
defined as an array of pointers.
struct intel_engine_cs *engine[I915_NUM_ENGINES];
dev_priv->engine[engine_ID] will be NULL for disabled engine instances.
There is a text size reduction of 928 bytes, from 1028200 to 1027272, for
i915.o file (but for i915.ko file text size remain same as 1193131 bytes).
v2:
- Remove the engine iterator field added in drm_i915_private structure,
instead pass a local iterator variable to the for_each_engine**
macros. (Chris)
- Do away with intel_engine_initialized() and instead directly use the
NULL pointer check on engine pointer. (Chris)
v3:
- Remove for_each_engine_id() macro, as the updated macro for_each_engine()
can be used in place of it. (Chris)
- Protect the access to Render engine Fault register with a NULL check, as
engine specific init is done later in Driver load sequence.
v4:
- Use !!dev_priv->engine[VCS] style for the engine check in getparam. (Chris)
- Kill the superfluous init_engine_lists().
v5:
- Cleanup the intel_engines_init() & intel_engines_setup(), with respect to
allocation of intel_engine_cs structure. (Chris)
v6:
- Rebase.
v7:
- Optimize the for_each_engine_masked() macro. (Chris)
- Change the type of 'iter' local variable to enum intel_engine_id. (Chris)
- Rebase.
v8: Rebase.
v9: Rebase.
v10:
- For index calculation use engine ID instead of pointer based arithmetic in
intel_engine_sync_index() as engine pointers are not contiguous now (Chris)
- For appropriateness, rename local enum variable 'iter' to 'id'. (Joonas)
- Use for_each_engine macro for cleanup in intel_engines_init() and remove
check for NULL engine pointer in cleanup() routines. (Joonas)
v11: Rebase.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1476378888-7372-1-git-send-email-akash.goel@intel.com
2016-10-13 17:14:48 +00:00
|
|
|
rcs = dev_priv->engine[RCS];
|
drm/i915: Unify active context tracking between legacy/execlists/guc
The requests conversion introduced a nasty bug where we could generate a
new request in the middle of constructing a request if we needed to idle
the system in order to evict space for a context. The request to idle
would be executed (and waited upon) before the current one, creating a
minor havoc in the seqno accounting, as we will consider the current
request to already be completed (prior to deferred seqno assignment) but
ring->last_retired_head would have been updated and still could allow
us to overwrite the current request before execution.
We also employed two different mechanisms to track the active context
until it was switched out. The legacy method allowed for waiting upon an
active context (it could forcibly evict any vma, including context's),
but the execlists method took a step backwards by pinning the vma for
the entire active lifespan of the context (the only way to evict was to
idle the entire GPU, not individual contexts). However, to circumvent
the tricky issue of locking (i.e. we cannot take struct_mutex at the
time of i915_gem_request_submit(), where we would want to move the
previous context onto the active tracker and unpin it), we take the
execlists approach and keep the contexts pinned until retirement.
The benefit of the execlists approach, more important for execlists than
legacy, was the reduction in work in pinning the context for each
request - as the context was kept pinned until idle, it could short
circuit the pinning for all active contexts.
We introduce new engine vfuncs to pin and unpin the context
respectively. The context is pinned at the start of the request, and
only unpinned when the following request is retired (this ensures that
the context is idle and coherent in main memory before we unpin it). We
move the engine->last_context tracking into the retirement itself
(rather than during request submission) in order to allow the submission
to be reordered or unwound without undue difficultly.
And finally an ulterior motive for unifying context handling was to
prepare for mock requests.
v2: Rename to last_retired_context, split out legacy_context tracking
for MI_SET_CONTEXT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161218153724.8439-3-chris@chris-wilson.co.uk
2016-12-18 15:37:20 +00:00
|
|
|
if (rcs->last_retired_context)
|
2016-07-21 20:16:19 +00:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (!rcs->init_context)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->drm.struct_mutex);
|
|
|
|
|
|
|
|
req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
|
|
|
|
if (IS_ERR(req))
|
|
|
|
goto unlock;
|
|
|
|
|
|
|
|
if (!i915.enable_execlists && i915_switch_context(req) == 0)
|
|
|
|
rcs->init_context(req);
|
|
|
|
|
|
|
|
/* Mark the device busy, calling intel_enable_gt_powersave() */
|
|
|
|
i915_add_request_no_flush(req);
|
|
|
|
|
|
|
|
unlock:
|
|
|
|
mutex_unlock(&dev_priv->drm.struct_mutex);
|
|
|
|
out:
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (READ_ONCE(dev_priv->rps.enabled))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (IS_IRONLAKE_M(dev_priv)) {
|
|
|
|
ironlake_enable_drps(dev_priv);
|
|
|
|
intel_init_emon(dev_priv);
|
|
|
|
} else if (INTEL_INFO(dev_priv)->gen >= 6) {
|
|
|
|
/*
|
|
|
|
* PCU communication is slow and this doesn't need to be
|
|
|
|
* done at any specific time, so do this out of our fast path
|
|
|
|
* to make resume and init faster.
|
|
|
|
*
|
|
|
|
* We depend on the HW RC6 power context save/restore
|
|
|
|
* mechanism when entering D3 through runtime PM suspend. So
|
|
|
|
* disable RPM until RPS/RC6 is properly setup. We can only
|
|
|
|
* get here via the driver load/system resume/runtime resume
|
|
|
|
* paths, so the _noresume version is enough (and in case of
|
|
|
|
* runtime resume it's necessary).
|
|
|
|
*/
|
|
|
|
if (queue_delayed_work(dev_priv->wq,
|
|
|
|
&dev_priv->rps.autoenable_work,
|
|
|
|
round_jiffies_up_relative(HZ)))
|
|
|
|
intel_runtime_pm_get_noresume(dev_priv);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-10-31 21:52:31 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* On Ibex Peak and Cougar Point, we need to disable clock
|
|
|
|
* gating for the panel power sequencer or it will fail to
|
|
|
|
* start up when no ports are active.
|
|
|
|
*/
|
|
|
|
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
|
2013-06-07 07:47:04 +00:00
|
|
|
{
|
2015-05-26 17:27:23 +00:00
|
|
|
enum pipe pipe;
|
2013-06-07 07:47:04 +00:00
|
|
|
|
2014-08-18 12:49:10 +00:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2013-06-07 07:47:04 +00:00
|
|
|
I915_WRITE(DSPCNTR(pipe),
|
|
|
|
I915_READ(DSPCNTR(pipe)) |
|
|
|
|
DISPPLANE_TRICKLE_FEED_DISABLE);
|
2015-05-26 17:27:23 +00:00
|
|
|
|
|
|
|
I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
|
|
|
|
POSTING_READ(DSPSURF(pipe));
|
2013-06-07 07:47:04 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
|
2013-12-05 13:51:37 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
|
|
|
|
I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
|
|
|
|
I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Don't touch WM1S_LP_EN here.
|
|
|
|
* Doing so could cause underruns.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
2012-10-19 16:55:41 +00:00
|
|
|
uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2013-06-07 16:41:09 +00:00
|
|
|
/*
|
|
|
|
* Required for FBC
|
|
|
|
* WaFbcDisableDpfcClockGating:ilk
|
|
|
|
*/
|
2012-10-19 16:55:42 +00:00
|
|
|
dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
|
2012-04-18 18:29:25 +00:00
|
|
|
|
|
|
|
I915_WRITE(PCH_3DCGDIS0,
|
|
|
|
MARIUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
SVSMUNIT_CLOCK_GATE_DISABLE);
|
|
|
|
I915_WRITE(PCH_3DCGDIS1,
|
|
|
|
VFMUNIT_CLOCK_GATE_DISABLE);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* According to the spec the following bits should be set in
|
|
|
|
* order to enable memory self-refresh
|
|
|
|
* The bit 22/21 of 0x42004
|
|
|
|
* The bit 5 of 0x42020
|
|
|
|
* The bit 15 of 0x45000
|
|
|
|
*/
|
|
|
|
I915_WRITE(ILK_DISPLAY_CHICKEN2,
|
|
|
|
(I915_READ(ILK_DISPLAY_CHICKEN2) |
|
|
|
|
ILK_DPARB_GATE | ILK_VSDPFD_FULL));
|
2012-10-19 16:55:42 +00:00
|
|
|
dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(DISP_ARB_CTL,
|
|
|
|
(I915_READ(DISP_ARB_CTL) |
|
|
|
|
DISP_FBC_WM_DIS));
|
2013-12-05 13:51:37 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
ilk_init_lp_watermarks(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Based on the document from hardware guys the following bits
|
|
|
|
* should be set unconditionally in order to enable FBC.
|
|
|
|
* The bit 22 of 0x42000
|
|
|
|
* The bit 22 of 0x42004
|
|
|
|
* The bit 7,8,9 of 0x42020.
|
|
|
|
*/
|
2016-10-13 10:02:58 +00:00
|
|
|
if (IS_IRONLAKE_M(dev_priv)) {
|
2013-06-14 14:23:24 +00:00
|
|
|
/* WaFbcAsynchFlipDisableFbcQueue:ilk */
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(ILK_DISPLAY_CHICKEN1,
|
|
|
|
I915_READ(ILK_DISPLAY_CHICKEN1) |
|
|
|
|
ILK_FBCQ_DIS);
|
|
|
|
I915_WRITE(ILK_DISPLAY_CHICKEN2,
|
|
|
|
I915_READ(ILK_DISPLAY_CHICKEN2) |
|
|
|
|
ILK_DPARB_GATE);
|
|
|
|
}
|
|
|
|
|
2012-10-19 16:55:42 +00:00
|
|
|
I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
|
|
|
|
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(ILK_DISPLAY_CHICKEN2,
|
|
|
|
I915_READ(ILK_DISPLAY_CHICKEN2) |
|
|
|
|
ILK_ELPIN_409_SELECT);
|
|
|
|
I915_WRITE(_3D_CHICKEN2,
|
|
|
|
_3D_CHICKEN2_WM_READ_PIPELINED << 16 |
|
|
|
|
_3D_CHICKEN2_WM_READ_PIPELINED);
|
2012-10-18 09:49:51 +00:00
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisableRenderCachePipelinedFlush:ilk */
|
2012-10-18 09:49:51 +00:00
|
|
|
I915_WRITE(CACHE_MODE_0,
|
|
|
|
_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
|
2012-10-31 21:52:31 +00:00
|
|
|
|
2014-04-04 11:44:38 +00:00
|
|
|
/* WaDisable_RenderCache_OperationalFlush:ilk */
|
|
|
|
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
g4x_disable_trickle_feed(dev_priv);
|
2013-06-07 07:47:03 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
ibx_init_clock_gating(dev_priv);
|
2012-10-31 21:52:31 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-10-31 21:52:31 +00:00
|
|
|
{
|
|
|
|
int pipe;
|
2013-04-08 18:48:07 +00:00
|
|
|
uint32_t val;
|
2012-10-31 21:52:31 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* On Ibex Peak and Cougar Point, we need to disable clock
|
|
|
|
* gating for the panel power sequencer or it will fail to
|
|
|
|
* start up when no ports are active.
|
|
|
|
*/
|
2013-10-02 17:34:19 +00:00
|
|
|
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
PCH_DPLUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
PCH_CPUNIT_CLOCK_GATE_DISABLE);
|
2012-10-31 21:52:31 +00:00
|
|
|
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
|
|
|
|
DPLS_EDP_PPS_FIX_DIS);
|
2012-12-11 10:46:29 +00:00
|
|
|
/* The below fixes the weird display corruption, a few pixels shifted
|
|
|
|
* downward, on (only) LVDS of some HP laptops with IVY.
|
|
|
|
*/
|
2014-08-18 12:49:10 +00:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2013-04-08 18:48:08 +00:00
|
|
|
val = I915_READ(TRANS_CHICKEN2(pipe));
|
|
|
|
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
|
|
|
|
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
|
2013-05-09 23:03:18 +00:00
|
|
|
if (dev_priv->vbt.fdi_rx_polarity_inverted)
|
2013-04-08 18:48:07 +00:00
|
|
|
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
|
2013-04-08 18:48:08 +00:00
|
|
|
val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
|
|
|
|
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
|
|
|
|
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
|
2013-04-08 18:48:07 +00:00
|
|
|
I915_WRITE(TRANS_CHICKEN2(pipe), val);
|
|
|
|
}
|
2012-10-31 21:52:31 +00:00
|
|
|
/* WADP0ClockGatingDisable */
|
2014-08-18 12:49:10 +00:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2012-10-31 21:52:31 +00:00
|
|
|
I915_WRITE(TRANS_CHICKEN1(pipe),
|
|
|
|
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
|
|
|
|
}
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
|
2013-02-09 20:03:42 +00:00
|
|
|
{
|
|
|
|
uint32_t tmp;
|
|
|
|
|
|
|
|
tmp = I915_READ(MCH_SSKPD);
|
2014-08-04 09:17:25 +00:00
|
|
|
if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
|
|
|
|
DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
|
|
|
|
tmp);
|
2013-02-09 20:03:42 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
2012-10-19 16:55:41 +00:00
|
|
|
uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2012-10-19 16:55:41 +00:00
|
|
|
I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
|
2012-04-18 18:29:25 +00:00
|
|
|
|
|
|
|
I915_WRITE(ILK_DISPLAY_CHICKEN2,
|
|
|
|
I915_READ(ILK_DISPLAY_CHICKEN2) |
|
|
|
|
ILK_ELPIN_409_SELECT);
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisableHiZPlanesWhenMSAAEnabled:snb */
|
2012-12-14 22:38:28 +00:00
|
|
|
I915_WRITE(_3D_CHICKEN,
|
|
|
|
_MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
|
|
|
|
|
2014-04-04 11:44:38 +00:00
|
|
|
/* WaDisable_RenderCache_OperationalFlush:snb */
|
|
|
|
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
|
|
|
|
2014-02-04 19:59:15 +00:00
|
|
|
/*
|
|
|
|
* BSpec recoomends 8x4 when MSAA is used,
|
|
|
|
* however in practice 16x4 seems fastest.
|
2014-02-05 10:43:47 +00:00
|
|
|
*
|
|
|
|
* Note that PS/WM thread counts depend on the WIZ hashing
|
|
|
|
* disable bit, which we don't touch here, but it's good
|
|
|
|
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
|
2014-02-04 19:59:15 +00:00
|
|
|
*/
|
|
|
|
I915_WRITE(GEN6_GT_MODE,
|
2014-12-08 17:33:51 +00:00
|
|
|
_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
|
2014-02-04 19:59:15 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
ilk_init_lp_watermarks(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
|
|
|
|
I915_WRITE(CACHE_MODE_0,
|
2012-04-26 20:02:54 +00:00
|
|
|
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
|
2012-04-18 18:29:25 +00:00
|
|
|
|
|
|
|
I915_WRITE(GEN6_UCGCTL1,
|
|
|
|
I915_READ(GEN6_UCGCTL1) |
|
|
|
|
GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
GEN6_CSUNIT_CLOCK_GATE_DISABLE);
|
|
|
|
|
|
|
|
/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
|
|
|
|
* gating disable must be set. Failure to set it results in
|
|
|
|
* flickering pixels due to Z write ordering failures after
|
|
|
|
* some amount of runtime in the Mesa "fire" demo, and Unigine
|
|
|
|
* Sanctuary and Tropics, and apparently anything else with
|
|
|
|
* alpha test or pixel discard.
|
|
|
|
*
|
|
|
|
* According to the spec, bit 11 (RCCUNIT) must also be set,
|
|
|
|
* but we didn't debug actual testcases to find it out.
|
2012-06-14 18:04:47 +00:00
|
|
|
*
|
2014-01-22 19:32:47 +00:00
|
|
|
* WaDisableRCCUnitClockGating:snb
|
|
|
|
* WaDisableRCPBUnitClockGating:snb
|
2012-04-18 18:29:25 +00:00
|
|
|
*/
|
|
|
|
I915_WRITE(GEN6_UCGCTL2,
|
|
|
|
GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
|
|
|
|
|
2014-02-04 19:59:16 +00:00
|
|
|
/* WaStripsFansDisableFastClipPerformanceFix:snb */
|
2014-02-04 19:59:17 +00:00
|
|
|
I915_WRITE(_3D_CHICKEN3,
|
|
|
|
_MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2014-02-04 19:59:18 +00:00
|
|
|
/*
|
|
|
|
* Bspec says:
|
|
|
|
* "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
|
|
|
|
* 3DSTATE_SF number of SF output attributes is more than 16."
|
|
|
|
*/
|
|
|
|
I915_WRITE(_3D_CHICKEN3,
|
|
|
|
_MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
|
|
|
|
|
2012-04-18 18:29:25 +00:00
|
|
|
/*
|
|
|
|
* According to the spec the following bits should be
|
|
|
|
* set in order to enable memory self-refresh and fbc:
|
|
|
|
* The bit21 and bit22 of 0x42000
|
|
|
|
* The bit21 and bit22 of 0x42004
|
|
|
|
* The bit5 and bit7 of 0x42020
|
|
|
|
* The bit14 of 0x70180
|
|
|
|
* The bit14 of 0x71180
|
2013-06-14 14:23:24 +00:00
|
|
|
*
|
|
|
|
* WaFbcAsynchFlipDisableFbcQueue:snb
|
2012-04-18 18:29:25 +00:00
|
|
|
*/
|
|
|
|
I915_WRITE(ILK_DISPLAY_CHICKEN1,
|
|
|
|
I915_READ(ILK_DISPLAY_CHICKEN1) |
|
|
|
|
ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
|
|
|
|
I915_WRITE(ILK_DISPLAY_CHICKEN2,
|
|
|
|
I915_READ(ILK_DISPLAY_CHICKEN2) |
|
|
|
|
ILK_DPARB_GATE | ILK_VSDPFD_FULL);
|
2012-10-19 16:55:41 +00:00
|
|
|
I915_WRITE(ILK_DSPCLK_GATE_D,
|
|
|
|
I915_READ(ILK_DSPCLK_GATE_D) |
|
|
|
|
ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
|
|
|
|
ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
g4x_disable_trickle_feed(dev_priv);
|
2012-10-04 02:34:24 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
cpt_init_clock_gating(dev_priv);
|
2013-02-09 20:03:42 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
gen6_check_mch_setup(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
|
|
|
|
|
2014-01-22 19:32:59 +00:00
|
|
|
/*
|
2014-01-22 19:33:01 +00:00
|
|
|
* WaVSThreadDispatchOverride:ivb,vlv
|
2014-01-22 19:32:59 +00:00
|
|
|
*
|
|
|
|
* This actually overrides the dispatch
|
|
|
|
* mode for all thread types.
|
|
|
|
*/
|
2012-04-18 18:29:25 +00:00
|
|
|
reg &= ~GEN7_FF_SCHED_MASK;
|
|
|
|
reg |= GEN7_FF_TS_SCHED_HW;
|
|
|
|
reg |= GEN7_FF_VS_SCHED_HW;
|
|
|
|
reg |= GEN7_FF_DS_SCHED_HW;
|
|
|
|
|
|
|
|
I915_WRITE(GEN7_FF_THREAD_MODE, reg);
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-11-20 17:12:07 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* TODO: this bit should only be enabled when really needed, then
|
|
|
|
* disabled when not needed anymore in order to save power.
|
|
|
|
*/
|
2016-10-13 10:02:52 +00:00
|
|
|
if (HAS_PCH_LPT_LP(dev_priv))
|
2012-11-20 17:12:07 +00:00
|
|
|
I915_WRITE(SOUTH_DSPCLK_GATE_D,
|
|
|
|
I915_READ(SOUTH_DSPCLK_GATE_D) |
|
|
|
|
PCH_LP_PARTITION_LEVEL_DISABLE);
|
2013-04-17 21:15:49 +00:00
|
|
|
|
|
|
|
/* WADPOClockGatingDisable:hsw */
|
2015-09-18 17:03:31 +00:00
|
|
|
I915_WRITE(TRANS_CHICKEN1(PIPE_A),
|
|
|
|
I915_READ(TRANS_CHICKEN1(PIPE_A)) |
|
2013-04-17 21:15:49 +00:00
|
|
|
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
|
2012-11-20 17:12:07 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:23 +00:00
|
|
|
static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
|
2013-04-17 11:04:50 +00:00
|
|
|
{
|
2016-10-13 10:02:52 +00:00
|
|
|
if (HAS_PCH_LPT_LP(dev_priv)) {
|
2013-04-17 11:04:50 +00:00
|
|
|
uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
|
|
|
|
|
|
|
|
val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
|
|
|
|
I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-03 12:54:21 +00:00
|
|
|
static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
|
|
|
|
int general_prio_credits,
|
|
|
|
int high_prio_credits)
|
|
|
|
{
|
|
|
|
u32 misccpctl;
|
|
|
|
|
|
|
|
/* WaTempDisableDOPClkGating:bdw */
|
|
|
|
misccpctl = I915_READ(GEN7_MISCCPCTL);
|
|
|
|
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_L3SQCREG1,
|
|
|
|
L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
|
|
|
|
L3_HIGH_PRIO_CREDITS(high_prio_credits));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait at least 100 clocks before re-enabling clock gating.
|
|
|
|
* See the definition of L3SQCREG1 in BSpec.
|
|
|
|
*/
|
|
|
|
POSTING_READ(GEN8_L3SQCREG1);
|
|
|
|
udelay(1);
|
|
|
|
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
|
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
|
2016-06-07 14:19:01 +00:00
|
|
|
{
|
2016-10-31 20:37:22 +00:00
|
|
|
gen9_init_clock_gating(dev_priv);
|
2016-06-07 14:19:01 +00:00
|
|
|
|
|
|
|
/* WaDisableSDEUnitClockGating:kbl */
|
|
|
|
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
|
|
|
|
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
|
|
|
|
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
|
2016-06-07 14:19:05 +00:00
|
|
|
|
|
|
|
/* WaDisableGamClockGating:kbl */
|
|
|
|
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
|
|
|
|
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
|
|
|
|
GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
|
2016-06-07 14:19:18 +00:00
|
|
|
|
|
|
|
/* WaFbcNukeOnHostModify:kbl */
|
|
|
|
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
|
|
|
|
ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
|
2016-06-07 14:19:01 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
|
2016-05-19 07:14:20 +00:00
|
|
|
{
|
2016-10-31 20:37:22 +00:00
|
|
|
gen9_init_clock_gating(dev_priv);
|
2016-06-07 14:19:09 +00:00
|
|
|
|
|
|
|
/* WAC6entrylatency:skl */
|
|
|
|
I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
|
|
|
|
FBC_LLC_FULLY_OPEN);
|
2016-06-07 14:19:18 +00:00
|
|
|
|
|
|
|
/* WaFbcNukeOnHostModify:skl */
|
|
|
|
I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
|
|
|
|
ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
|
2016-05-19 07:14:20 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
|
2013-11-03 04:07:06 +00:00
|
|
|
{
|
2014-03-03 17:31:46 +00:00
|
|
|
enum pipe pipe;
|
2013-11-03 04:07:06 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
ilk_init_lp_watermarks(dev_priv);
|
2013-11-03 04:07:40 +00:00
|
|
|
|
2013-12-12 23:28:04 +00:00
|
|
|
/* WaSwitchSolVfFArbitrationPriority:bdw */
|
2013-11-03 04:07:40 +00:00
|
|
|
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
|
2013-11-03 04:07:54 +00:00
|
|
|
|
2013-12-12 23:28:04 +00:00
|
|
|
/* WaPsrDPAMaskVBlankInSRD:bdw */
|
2013-11-03 04:07:54 +00:00
|
|
|
I915_WRITE(CHICKEN_PAR1_1,
|
|
|
|
I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
|
|
|
|
|
2013-12-12 23:28:04 +00:00
|
|
|
/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
|
2014-08-18 12:49:10 +00:00
|
|
|
for_each_pipe(dev_priv, pipe) {
|
2014-03-03 17:31:46 +00:00
|
|
|
I915_WRITE(CHICKEN_PIPESL_1(pipe),
|
2014-03-05 11:05:45 +00:00
|
|
|
I915_READ(CHICKEN_PIPESL_1(pipe)) |
|
2014-03-05 11:05:47 +00:00
|
|
|
BDW_DPRS_MASK_VBLANK_SRD);
|
2013-11-03 04:07:54 +00:00
|
|
|
}
|
2013-12-13 01:26:03 +00:00
|
|
|
|
2013-12-12 23:28:04 +00:00
|
|
|
/* WaVSRefCountFullforceMissDisable:bdw */
|
|
|
|
/* WaDSRefCountFullforceMissDisable:bdw */
|
|
|
|
I915_WRITE(GEN7_FF_THREAD_MODE,
|
|
|
|
I915_READ(GEN7_FF_THREAD_MODE) &
|
|
|
|
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
|
2014-02-04 19:59:21 +00:00
|
|
|
|
2014-02-27 19:59:01 +00:00
|
|
|
I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
|
|
|
|
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
|
2014-02-27 19:59:02 +00:00
|
|
|
|
|
|
|
/* WaDisableSDEUnitClockGating:bdw */
|
|
|
|
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
|
|
|
|
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
|
2014-03-26 18:41:51 +00:00
|
|
|
|
2016-05-03 12:54:21 +00:00
|
|
|
/* WaProgramL3SqcReg1Default:bdw */
|
|
|
|
gen8_set_l3sqc_credits(dev_priv, 30, 2);
|
2015-05-19 17:32:56 +00:00
|
|
|
|
2015-05-19 17:32:57 +00:00
|
|
|
/*
|
|
|
|
* WaGttCachingOffByDefault:bdw
|
|
|
|
* GTT cache may not work with big pages, so if those
|
|
|
|
* are ever enabled GTT cache may need to be disabled.
|
|
|
|
*/
|
|
|
|
I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
|
|
|
|
|
2016-06-07 14:19:02 +00:00
|
|
|
/* WaKVMNotificationOnConfigChange:bdw */
|
|
|
|
I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
|
|
|
|
| KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
lpt_init_clock_gating(dev_priv);
|
2013-11-03 04:07:06 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-07-02 14:51:09 +00:00
|
|
|
{
|
2016-10-31 20:37:22 +00:00
|
|
|
ilk_init_lp_watermarks(dev_priv);
|
2012-07-02 14:51:09 +00:00
|
|
|
|
2013-10-02 22:53:16 +00:00
|
|
|
/* L3 caching of data atomics doesn't work -- disable it. */
|
|
|
|
I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
|
|
|
|
I915_WRITE(HSW_ROW_CHICKEN3,
|
|
|
|
_MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* This is required by WaCatErrorRejectionIssue:hsw */
|
2012-07-02 14:51:09 +00:00
|
|
|
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
|
|
|
|
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
|
|
|
|
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
|
|
|
|
|
2014-01-22 19:33:00 +00:00
|
|
|
/* WaVSRefCountFullforceMissDisable:hsw */
|
|
|
|
I915_WRITE(GEN7_FF_THREAD_MODE,
|
|
|
|
I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
|
2012-07-02 14:51:09 +00:00
|
|
|
|
2014-04-04 11:44:38 +00:00
|
|
|
/* WaDisable_RenderCache_OperationalFlush:hsw */
|
|
|
|
I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
|
|
|
|
2014-01-28 05:29:33 +00:00
|
|
|
/* enable HiZ Raw Stall Optimization */
|
|
|
|
I915_WRITE(CACHE_MODE_0_GEN7,
|
|
|
|
_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisable4x2SubspanOptimization:hsw */
|
2012-07-02 14:51:09 +00:00
|
|
|
I915_WRITE(CACHE_MODE_1,
|
|
|
|
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
|
2012-07-02 14:51:10 +00:00
|
|
|
|
2014-02-04 19:59:20 +00:00
|
|
|
/*
|
|
|
|
* BSpec recommends 8x4 when MSAA is used,
|
|
|
|
* however in practice 16x4 seems fastest.
|
2014-02-05 10:43:47 +00:00
|
|
|
*
|
|
|
|
* Note that PS/WM thread counts depend on the WIZ hashing
|
|
|
|
* disable bit, which we don't touch here, but it's good
|
|
|
|
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
|
2014-02-04 19:59:20 +00:00
|
|
|
*/
|
|
|
|
I915_WRITE(GEN7_GT_MODE,
|
2014-12-08 17:33:51 +00:00
|
|
|
_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
|
2014-02-04 19:59:20 +00:00
|
|
|
|
drm/i915: Make sample_c messages go faster on Haswell.
Haswell significantly improved the performance of sampler_c messages,
but the optimization appears to be off by default. Later platforms
remove this bit, and apparently always enable the optimization.
Improves performance in "Counter Strike: Global Offensive" by 18%
at default settings on Iris Pro.
This may break sampling of paletted formats (P8/A8P8/P8A8). It's
unclear whether it affects sampling of paletted formats in general,
or just the sample_c message (which is never used).
While libva does have support for using paletted formats (primarily
for OSDs), that support appears to have been broken for at least a
year, so I couldn't observe a regression from this:
I tried to get libva-intel to use paletted formats, and observe a
regression...but the only thing I found that used it was mplayer's OSD
(on screen display). Even without my patch, the colors were totally
wrong with that, and it's according to a few distro wikis, that's been
the case for over a year.
If libva's code for paletted formats /is/ broken, they could always
add code to disable this bit using the command validator when fixing
it.
Further investigation from Haihao shows that libva mplayer OSD seems
to work at least on his setup (still unclear what's wron with Ken's),
and that it's not affected by this patch. Quoting the discussion
between Haihao and Ken:
> > > If you use "-vo gl" or "-vo xv", the OSD is solid white text with a black
> > > border around it. I presume that it's supposed to be white with vaapi as
> > > well, but I guess I'm not entirely sure.
> > >
> > > It's possible that the optimization doesn't affect the palette as long as
> > > you never use sample_c with the paletted textures.
> >
> > I verified the palette takes effect in the following way:
> >
> > 1. Only support P8A8 format in the driver
> >
> > 2. ran the above command and I saw white OSD text
> >
> > 3. Only support P4A4 format in the driver and don't use
> > 3DSTATE_SAMPLER_PALETTE_LOAD0 to load the value to the texture palette,
> > so the palette keeps unchanged.
> >
> > 4. ran the above command and I saw black OSD text.
> >
> > 5. Load the right value to the texture palette and ran the above command
> > again, I saw white OSD text.
> >
> > Hence I think sample_c with the paletted textures is used in the driver.
>
> That sounds like the palette is actually working, then. Great :)
>
> I doubt that libva would use sample_c - sampling with a shadow comparison?
> It looks like it just uses sample and sample+killpix.
You are right, libva driver doesn't use sample_c message.
> I'm pretty sure the sample_c optimization just uses the palette memory as
> storage for some stuff, so it's quite possible it just works if you're
> only using sample and sample+killpix.
Thanks for the explanation, it makes sense to me.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: Add wa name from Ville's review to the comment and copypaste
the explanation why we don't care about libva (already broken) from
Ken. Also add conclusion from libva devs that&why this is all fine.]
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: "Xiang, Haihao" <haihao.xiang@intel.com>
Cc: libva@lists.freedesktop.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-01-01 00:23:00 +00:00
|
|
|
/* WaSampleCChickenBitEnable:hsw */
|
|
|
|
I915_WRITE(HALF_SLICE_CHICKEN3,
|
|
|
|
_MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaSwitchSolVfFArbitrationPriority:hsw */
|
2013-03-20 21:49:14 +00:00
|
|
|
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
|
|
|
|
|
2013-05-03 20:23:45 +00:00
|
|
|
/* WaRsPkgCStateDisplayPMReq:hsw */
|
|
|
|
I915_WRITE(CHICKEN_PAR1_1,
|
|
|
|
I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
|
2012-07-02 14:51:10 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
lpt_init_clock_gating(dev_priv);
|
2012-07-02 14:51:09 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
2012-05-05 01:58:59 +00:00
|
|
|
uint32_t snpcr;
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
ilk_init_lp_watermarks(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2012-10-19 16:55:41 +00:00
|
|
|
I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisableEarlyCull:ivb */
|
2012-10-02 22:43:41 +00:00
|
|
|
I915_WRITE(_3D_CHICKEN3,
|
|
|
|
_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisableBackToBackFlipFix:ivb */
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(IVB_CHICKEN3,
|
|
|
|
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
|
|
|
|
CHICKEN3_DGMG_DONE_FIX_DISABLE);
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisablePSDDualDispatchEnable:ivb */
|
2016-10-13 10:02:58 +00:00
|
|
|
if (IS_IVB_GT1(dev_priv))
|
2012-10-25 19:15:45 +00:00
|
|
|
I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
|
|
|
|
_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
|
|
|
|
|
2014-04-04 11:44:38 +00:00
|
|
|
/* WaDisable_RenderCache_OperationalFlush:ivb */
|
|
|
|
I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
|
|
|
|
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaApplyL3ControlAndL3ChickenMode:ivb */
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(GEN7_L3CNTLREG1,
|
|
|
|
GEN7_WA_FOR_GEN7_L3_CONTROL);
|
|
|
|
I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
|
2012-10-25 19:15:42 +00:00
|
|
|
GEN7_WA_L3_CHICKEN_MODE);
|
2016-10-13 10:02:58 +00:00
|
|
|
if (IS_IVB_GT1(dev_priv))
|
2012-10-25 19:15:42 +00:00
|
|
|
I915_WRITE(GEN7_ROW_CHICKEN2,
|
|
|
|
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
|
2014-01-22 19:32:44 +00:00
|
|
|
else {
|
|
|
|
/* must write both registers */
|
|
|
|
I915_WRITE(GEN7_ROW_CHICKEN2,
|
|
|
|
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
|
2012-10-25 19:15:42 +00:00
|
|
|
I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
|
|
|
|
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
|
2014-01-22 19:32:44 +00:00
|
|
|
}
|
2012-04-18 18:29:25 +00:00
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaForceL3Serialization:ivb */
|
2012-10-02 22:43:38 +00:00
|
|
|
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
|
|
|
|
~L3SQ_URB_READ_CAM_MATCH_DISABLE);
|
|
|
|
|
2014-01-22 19:32:53 +00:00
|
|
|
/*
|
2012-06-14 18:04:47 +00:00
|
|
|
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
|
2013-05-03 17:48:10 +00:00
|
|
|
* This implements the WaDisableRCZUnitClockGating:ivb workaround.
|
2012-06-14 18:04:47 +00:00
|
|
|
*/
|
|
|
|
I915_WRITE(GEN6_UCGCTL2,
|
2014-01-22 19:32:48 +00:00
|
|
|
GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
|
2012-06-14 18:04:47 +00:00
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* This is required by WaCatErrorRejectionIssue:ivb */
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
|
|
|
|
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
|
|
|
|
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
g4x_disable_trickle_feed(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
|
|
|
|
gen7_setup_fixed_func_scheduler(dev_priv);
|
2012-04-24 14:00:21 +00:00
|
|
|
|
2014-03-04 09:41:43 +00:00
|
|
|
if (0) { /* causes HiZ corruption on ivb:gt1 */
|
|
|
|
/* enable HiZ Raw Stall Optimization */
|
|
|
|
I915_WRITE(CACHE_MODE_0_GEN7,
|
|
|
|
_MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
|
|
|
|
}
|
2014-01-28 05:29:34 +00:00
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisable4x2SubspanOptimization:ivb */
|
2012-04-24 14:00:21 +00:00
|
|
|
I915_WRITE(CACHE_MODE_1,
|
|
|
|
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
|
2012-05-05 01:58:59 +00:00
|
|
|
|
2014-02-04 19:59:19 +00:00
|
|
|
/*
|
|
|
|
* BSpec recommends 8x4 when MSAA is used,
|
|
|
|
* however in practice 16x4 seems fastest.
|
2014-02-05 10:43:47 +00:00
|
|
|
*
|
|
|
|
* Note that PS/WM thread counts depend on the WIZ hashing
|
|
|
|
* disable bit, which we don't touch here, but it's good
|
|
|
|
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
|
2014-02-04 19:59:19 +00:00
|
|
|
*/
|
|
|
|
I915_WRITE(GEN7_GT_MODE,
|
2014-12-08 17:33:51 +00:00
|
|
|
_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
|
2014-02-04 19:59:19 +00:00
|
|
|
|
2012-05-05 01:58:59 +00:00
|
|
|
snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
|
|
|
|
snpcr &= ~GEN6_MBC_SNPCR_MASK;
|
|
|
|
snpcr |= GEN6_MBC_SNPCR_MED;
|
|
|
|
I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
|
2012-10-31 21:52:31 +00:00
|
|
|
|
2016-10-13 10:02:53 +00:00
|
|
|
if (!HAS_PCH_NOP(dev_priv))
|
2016-10-31 20:37:22 +00:00
|
|
|
cpt_init_clock_gating(dev_priv);
|
2013-02-09 20:03:42 +00:00
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
gen6_check_mch_setup(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisableEarlyCull:vlv */
|
2012-10-02 22:43:41 +00:00
|
|
|
I915_WRITE(_3D_CHICKEN3,
|
|
|
|
_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisableBackToBackFlipFix:vlv */
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(IVB_CHICKEN3,
|
|
|
|
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
|
|
|
|
CHICKEN3_DGMG_DONE_FIX_DISABLE);
|
|
|
|
|
2014-01-22 19:32:39 +00:00
|
|
|
/* WaPsdDispatchEnable:vlv */
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisablePSDDualDispatchEnable:vlv */
|
2012-10-25 19:15:45 +00:00
|
|
|
I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
|
2013-03-08 18:45:51 +00:00
|
|
|
_MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
|
|
|
|
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
|
2012-10-25 19:15:45 +00:00
|
|
|
|
2014-04-04 11:44:38 +00:00
|
|
|
/* WaDisable_RenderCache_OperationalFlush:vlv */
|
|
|
|
I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaForceL3Serialization:vlv */
|
2012-10-02 22:43:38 +00:00
|
|
|
I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
|
|
|
|
~L3SQ_URB_READ_CAM_MATCH_DISABLE);
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* WaDisableDopClockGating:vlv */
|
2012-10-25 19:15:42 +00:00
|
|
|
I915_WRITE(GEN7_ROW_CHICKEN2,
|
|
|
|
_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
|
|
|
|
|
2013-05-03 17:48:10 +00:00
|
|
|
/* This is required by WaCatErrorRejectionIssue:vlv */
|
2012-04-18 18:29:25 +00:00
|
|
|
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
|
|
|
|
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
|
|
|
|
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
|
|
|
|
|
2014-01-22 19:33:01 +00:00
|
|
|
gen7_setup_fixed_func_scheduler(dev_priv);
|
|
|
|
|
2014-01-22 19:32:56 +00:00
|
|
|
/*
|
2012-06-14 18:04:47 +00:00
|
|
|
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
|
2013-05-03 17:48:10 +00:00
|
|
|
* This implements the WaDisableRCZUnitClockGating:vlv workaround.
|
2012-06-14 18:04:47 +00:00
|
|
|
*/
|
|
|
|
I915_WRITE(GEN6_UCGCTL2,
|
2014-01-22 19:32:56 +00:00
|
|
|
GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
|
2012-06-14 18:04:47 +00:00
|
|
|
|
2014-03-24 17:30:07 +00:00
|
|
|
/* WaDisableL3Bank2xClockGate:vlv
|
|
|
|
* Disabling L3 clock gating- MMIO 940c[25] = 1
|
|
|
|
* Set bit 25, to disable L3_BANK_2x_CLK_GATING */
|
|
|
|
I915_WRITE(GEN7_UCGCTL4,
|
|
|
|
I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
|
2012-06-14 18:04:50 +00:00
|
|
|
|
2014-01-22 19:33:03 +00:00
|
|
|
/*
|
|
|
|
* BSpec says this must be set, even though
|
|
|
|
* WaDisable4x2SubspanOptimization isn't listed for VLV.
|
|
|
|
*/
|
2012-04-24 12:04:12 +00:00
|
|
|
I915_WRITE(CACHE_MODE_1,
|
|
|
|
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
|
2012-06-20 17:53:12 +00:00
|
|
|
|
2015-01-21 17:38:01 +00:00
|
|
|
/*
|
|
|
|
* BSpec recommends 8x4 when MSAA is used,
|
|
|
|
* however in practice 16x4 seems fastest.
|
|
|
|
*
|
|
|
|
* Note that PS/WM thread counts depend on the WIZ hashing
|
|
|
|
* disable bit, which we don't touch here, but it's good
|
|
|
|
* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
|
|
|
|
*/
|
|
|
|
I915_WRITE(GEN7_GT_MODE,
|
|
|
|
_MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
|
|
|
|
|
2014-01-22 19:32:46 +00:00
|
|
|
/*
|
|
|
|
* WaIncreaseL3CreditsForVLVB0:vlv
|
|
|
|
* This is the hardware default actually.
|
|
|
|
*/
|
|
|
|
I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
|
|
|
|
|
2012-10-25 19:15:44 +00:00
|
|
|
/*
|
2013-05-03 17:48:10 +00:00
|
|
|
* WaDisableVLVClockGating_VBIIssue:vlv
|
2012-10-25 19:15:44 +00:00
|
|
|
* Disable clock gating on th GCFG unit to prevent a delay
|
|
|
|
* in the reporting of vblank events.
|
|
|
|
*/
|
2014-01-22 19:33:04 +00:00
|
|
|
I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
|
2014-04-09 10:28:10 +00:00
|
|
|
{
|
2014-04-09 10:28:35 +00:00
|
|
|
/* WaVSRefCountFullforceMissDisable:chv */
|
|
|
|
/* WaDSRefCountFullforceMissDisable:chv */
|
|
|
|
I915_WRITE(GEN7_FF_THREAD_MODE,
|
|
|
|
I915_READ(GEN7_FF_THREAD_MODE) &
|
|
|
|
~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
|
2014-04-09 10:28:36 +00:00
|
|
|
|
|
|
|
/* WaDisableSemaphoreAndSyncFlipWait:chv */
|
|
|
|
I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
|
|
|
|
_MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
|
2014-04-09 10:28:37 +00:00
|
|
|
|
|
|
|
/* WaDisableCSUnitClockGating:chv */
|
|
|
|
I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
|
|
|
|
GEN6_CSUNIT_CLOCK_GATE_DISABLE);
|
2014-04-09 10:28:38 +00:00
|
|
|
|
|
|
|
/* WaDisableSDEUnitClockGating:chv */
|
|
|
|
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
|
|
|
|
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
|
2015-05-19 17:32:57 +00:00
|
|
|
|
2016-05-03 12:54:21 +00:00
|
|
|
/*
|
|
|
|
* WaProgramL3SqcReg1Default:chv
|
|
|
|
* See gfxspecs/Related Documents/Performance Guide/
|
|
|
|
* LSQC Setting Recommendations.
|
|
|
|
*/
|
|
|
|
gen8_set_l3sqc_credits(dev_priv, 38, 2);
|
|
|
|
|
2015-05-19 17:32:57 +00:00
|
|
|
/*
|
|
|
|
* GTT cache may not work with big pages, so if those
|
|
|
|
* are ever enabled GTT cache may need to be disabled.
|
|
|
|
*/
|
|
|
|
I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
|
2014-04-09 10:28:10 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
|
|
|
uint32_t dspclk_gate;
|
|
|
|
|
|
|
|
I915_WRITE(RENCLK_GATE_D1, 0);
|
|
|
|
I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
|
|
|
|
GS_UNIT_CLOCK_GATE_DISABLE |
|
|
|
|
CL_UNIT_CLOCK_GATE_DISABLE);
|
|
|
|
I915_WRITE(RAMCLK_GATE_D, 0);
|
|
|
|
dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
OVRUNIT_CLOCK_GATE_DISABLE |
|
|
|
|
OVCUNIT_CLOCK_GATE_DISABLE;
|
2016-10-13 10:02:58 +00:00
|
|
|
if (IS_GM45(dev_priv))
|
2012-04-18 18:29:25 +00:00
|
|
|
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
|
|
|
|
I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
|
2012-10-18 09:49:51 +00:00
|
|
|
|
|
|
|
/* WaDisableRenderCachePipelinedFlush */
|
|
|
|
I915_WRITE(CACHE_MODE_0,
|
|
|
|
_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
|
2013-06-07 07:47:01 +00:00
|
|
|
|
2014-04-04 11:44:38 +00:00
|
|
|
/* WaDisable_RenderCache_OperationalFlush:g4x */
|
|
|
|
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
g4x_disable_trickle_feed(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
|
|
|
|
I915_WRITE(RENCLK_GATE_D2, 0);
|
|
|
|
I915_WRITE(DSPCLK_GATE_D, 0);
|
|
|
|
I915_WRITE(RAMCLK_GATE_D, 0);
|
|
|
|
I915_WRITE16(DEUC, 0);
|
2013-06-07 07:47:02 +00:00
|
|
|
I915_WRITE(MI_ARB_STATE,
|
|
|
|
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
|
2014-04-04 11:44:38 +00:00
|
|
|
|
|
|
|
/* WaDisable_RenderCache_OperationalFlush:gen4 */
|
|
|
|
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
|
|
|
|
I965_RCC_CLOCK_GATE_DISABLE |
|
|
|
|
I965_RCPB_CLOCK_GATE_DISABLE |
|
|
|
|
I965_ISC_CLOCK_GATE_DISABLE |
|
|
|
|
I965_FBC_CLOCK_GATE_DISABLE);
|
|
|
|
I915_WRITE(RENCLK_GATE_D2, 0);
|
2013-06-07 07:47:02 +00:00
|
|
|
I915_WRITE(MI_ARB_STATE,
|
|
|
|
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
|
2014-04-04 11:44:38 +00:00
|
|
|
|
|
|
|
/* WaDisable_RenderCache_OperationalFlush:gen4 */
|
|
|
|
I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
|
|
|
u32 dstate = I915_READ(D_STATE);
|
|
|
|
|
|
|
|
dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
|
|
|
|
DSTATE_DOT_CLOCK_GATING;
|
|
|
|
I915_WRITE(D_STATE, dstate);
|
2012-04-24 13:51:43 +00:00
|
|
|
|
2016-10-31 20:37:15 +00:00
|
|
|
if (IS_PINEVIEW(dev_priv))
|
2012-04-24 13:51:43 +00:00
|
|
|
I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
|
2012-09-09 09:54:16 +00:00
|
|
|
|
|
|
|
/* IIR "flip pending" means done if this bit is set */
|
|
|
|
I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
|
2014-02-25 13:13:38 +00:00
|
|
|
|
|
|
|
/* interrupts should cause a wake up from C3 */
|
2014-02-25 13:13:39 +00:00
|
|
|
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
|
2014-02-25 13:13:41 +00:00
|
|
|
|
|
|
|
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
|
|
|
|
I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
|
2014-08-14 22:21:54 +00:00
|
|
|
|
|
|
|
I915_WRITE(MI_ARB_STATE,
|
|
|
|
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
|
|
|
I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
|
2014-02-25 13:13:40 +00:00
|
|
|
|
|
|
|
/* interrupts should cause a wake up from C3 */
|
|
|
|
I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
|
|
|
|
_MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
|
2014-08-14 22:21:54 +00:00
|
|
|
|
|
|
|
I915_WRITE(MEM_MODE,
|
|
|
|
_MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
2014-08-14 22:21:54 +00:00
|
|
|
I915_WRITE(MEM_MODE,
|
|
|
|
_MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
|
|
|
|
_MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:25 +00:00
|
|
|
{
|
2016-10-31 20:37:22 +00:00
|
|
|
dev_priv->display.init_clock_gating(dev_priv);
|
2012-04-18 18:29:25 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:23 +00:00
|
|
|
void intel_suspend_hw(struct drm_i915_private *dev_priv)
|
2013-04-17 11:04:50 +00:00
|
|
|
{
|
2016-10-31 20:37:23 +00:00
|
|
|
if (HAS_PCH_LPT(dev_priv))
|
|
|
|
lpt_suspend_hw(dev_priv);
|
2013-04-17 11:04:50 +00:00
|
|
|
}
|
|
|
|
|
2016-10-31 20:37:22 +00:00
|
|
|
static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
|
2016-03-16 11:38:54 +00:00
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_init_clock_gating_hooks - setup the clock gating hooks
|
|
|
|
* @dev_priv: device private
|
|
|
|
*
|
|
|
|
* Setup the hooks that configure which clocks of a given platform can be
|
|
|
|
* gated and also apply various GT and display specific workarounds for these
|
|
|
|
* platforms. Note that some GT specific workarounds are applied separately
|
|
|
|
* when GPU contexts or batchbuffers start their execution.
|
|
|
|
*/
|
|
|
|
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (IS_SKYLAKE(dev_priv))
|
2016-05-19 07:14:20 +00:00
|
|
|
dev_priv->display.init_clock_gating = skylake_init_clock_gating;
|
2016-03-16 11:38:54 +00:00
|
|
|
else if (IS_KABYLAKE(dev_priv))
|
2016-06-07 14:19:01 +00:00
|
|
|
dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
|
2017-01-26 09:16:58 +00:00
|
|
|
else if (IS_BROXTON(dev_priv))
|
2016-03-16 11:38:54 +00:00
|
|
|
dev_priv->display.init_clock_gating = bxt_init_clock_gating;
|
2017-01-26 09:16:58 +00:00
|
|
|
else if (IS_GEMINILAKE(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = glk_init_clock_gating;
|
2016-03-16 11:38:54 +00:00
|
|
|
else if (IS_BROADWELL(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
|
|
|
|
else if (IS_CHERRYVIEW(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
|
|
|
|
else if (IS_HASWELL(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = haswell_init_clock_gating;
|
|
|
|
else if (IS_IVYBRIDGE(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
|
|
|
|
else if (IS_VALLEYVIEW(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
|
|
|
|
else if (IS_GEN6(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = gen6_init_clock_gating;
|
|
|
|
else if (IS_GEN5(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
|
|
|
|
else if (IS_G4X(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = g4x_init_clock_gating;
|
2016-12-07 10:13:04 +00:00
|
|
|
else if (IS_I965GM(dev_priv))
|
2016-03-16 11:38:54 +00:00
|
|
|
dev_priv->display.init_clock_gating = crestline_init_clock_gating;
|
2016-12-07 10:13:04 +00:00
|
|
|
else if (IS_I965G(dev_priv))
|
2016-03-16 11:38:54 +00:00
|
|
|
dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
|
|
|
|
else if (IS_GEN3(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = gen3_init_clock_gating;
|
|
|
|
else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = i85x_init_clock_gating;
|
|
|
|
else if (IS_GEN2(dev_priv))
|
|
|
|
dev_priv->display.init_clock_gating = i830_init_clock_gating;
|
|
|
|
else {
|
|
|
|
MISSING_CASE(INTEL_DEVID(dev_priv));
|
|
|
|
dev_priv->display.init_clock_gating = nop_init_clock_gating;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-04-18 18:29:26 +00:00
|
|
|
/* Set up chip specific power management-related functions */
|
2016-10-31 20:37:25 +00:00
|
|
|
void intel_init_pm(struct drm_i915_private *dev_priv)
|
2012-04-18 18:29:26 +00:00
|
|
|
{
|
2014-12-08 16:09:10 +00:00
|
|
|
intel_fbc_init(dev_priv);
|
2012-04-18 18:29:26 +00:00
|
|
|
|
2012-04-26 21:28:17 +00:00
|
|
|
/* For cxsr */
|
2016-10-31 20:37:15 +00:00
|
|
|
if (IS_PINEVIEW(dev_priv))
|
2016-10-31 20:37:16 +00:00
|
|
|
i915_pineview_get_mem_freq(dev_priv);
|
2016-10-13 10:03:10 +00:00
|
|
|
else if (IS_GEN5(dev_priv))
|
2016-10-31 20:37:16 +00:00
|
|
|
i915_ironlake_get_mem_freq(dev_priv);
|
2012-04-26 21:28:17 +00:00
|
|
|
|
2012-04-18 18:29:26 +00:00
|
|
|
/* For FIFO watermark updates */
|
2016-10-31 20:37:25 +00:00
|
|
|
if (INTEL_GEN(dev_priv) >= 9) {
|
2016-10-31 20:37:24 +00:00
|
|
|
skl_setup_wm_latency(dev_priv);
|
2016-11-08 12:55:33 +00:00
|
|
|
dev_priv->display.initial_watermarks = skl_initial_wm;
|
2016-11-08 12:55:32 +00:00
|
|
|
dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
|
2016-05-12 14:06:03 +00:00
|
|
|
dev_priv->display.compute_global_watermarks = skl_compute_wm;
|
2016-10-13 10:02:53 +00:00
|
|
|
} else if (HAS_PCH_SPLIT(dev_priv)) {
|
2016-10-31 20:37:24 +00:00
|
|
|
ilk_setup_wm_latency(dev_priv);
|
2013-08-01 13:18:50 +00:00
|
|
|
|
2016-10-13 10:03:10 +00:00
|
|
|
if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
|
2014-01-07 14:14:10 +00:00
|
|
|
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
|
2016-10-13 10:03:10 +00:00
|
|
|
(!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
|
2014-01-07 14:14:10 +00:00
|
|
|
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
|
2015-09-24 22:53:16 +00:00
|
|
|
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
|
drm/i915: Add two-stage ILK-style watermark programming (v11)
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
v6:
- Rebase
v7:
- Further rebase
v8:
- A few minor indentation and line length fixes
v9:
- Yet another rebase since Maarten's patches reworked a bunch of the
code (wm_pre, wm_post, etc.) that this was previously based on.
v10:
- Move wm_mutex to dev_priv to protect against racing commits against
disjoint CRTC sets. (Maarten)
- Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
v11:
- Now that we've moved to atomic watermark updates, make sure we call
the proper function to program watermarks in
{ironlake,haswell}_crtc_enable(); the failure to do so on the
previous patch iteration led to us not actually programming the
watermarks before turning on the CRTC, which was the cause of the
underruns that the CI system was seeing.
- Fix inverted logic for determining when to optimize watermarks. We
were needlessly optimizing when the intermediate/optimal values were
the same (harmless), but not actually optimizing when they differed
(also harmless, but wasteful from a power/bandwidth perspective).
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
2016-02-24 01:20:13 +00:00
|
|
|
dev_priv->display.compute_intermediate_wm =
|
|
|
|
ilk_compute_intermediate_wm;
|
|
|
|
dev_priv->display.initial_watermarks =
|
|
|
|
ilk_initial_watermarks;
|
|
|
|
dev_priv->display.optimize_watermarks =
|
|
|
|
ilk_optimize_watermarks;
|
2014-01-07 14:14:10 +00:00
|
|
|
} else {
|
|
|
|
DRM_DEBUG_KMS("Failed to read display plane latency. "
|
|
|
|
"Disable CxSR\n");
|
|
|
|
}
|
2016-11-28 17:37:07 +00:00
|
|
|
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
2016-10-31 20:37:24 +00:00
|
|
|
vlv_setup_wm_latency(dev_priv);
|
2015-06-24 19:00:06 +00:00
|
|
|
dev_priv->display.update_wm = vlv_update_wm;
|
2016-10-31 20:37:15 +00:00
|
|
|
} else if (IS_PINEVIEW(dev_priv)) {
|
2016-10-13 10:02:58 +00:00
|
|
|
if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
|
2012-04-18 18:29:26 +00:00
|
|
|
dev_priv->is_ddr3,
|
|
|
|
dev_priv->fsb_freq,
|
|
|
|
dev_priv->mem_freq)) {
|
|
|
|
DRM_INFO("failed to find known CxSR latency "
|
|
|
|
"(found ddr%s fsb freq %d, mem freq %d), "
|
|
|
|
"disabling CxSR\n",
|
|
|
|
(dev_priv->is_ddr3 == 1) ? "3" : "2",
|
|
|
|
dev_priv->fsb_freq, dev_priv->mem_freq);
|
|
|
|
/* Disable CxSR and never update its watermark again */
|
2014-07-01 09:36:17 +00:00
|
|
|
intel_set_memory_cxsr(dev_priv, false);
|
2012-04-18 18:29:26 +00:00
|
|
|
dev_priv->display.update_wm = NULL;
|
|
|
|
} else
|
|
|
|
dev_priv->display.update_wm = pineview_update_wm;
|
2016-10-13 10:03:06 +00:00
|
|
|
} else if (IS_G4X(dev_priv)) {
|
2012-04-18 18:29:26 +00:00
|
|
|
dev_priv->display.update_wm = g4x_update_wm;
|
2016-10-13 10:03:10 +00:00
|
|
|
} else if (IS_GEN4(dev_priv)) {
|
2012-04-18 18:29:26 +00:00
|
|
|
dev_priv->display.update_wm = i965_update_wm;
|
2016-10-13 10:03:10 +00:00
|
|
|
} else if (IS_GEN3(dev_priv)) {
|
2012-04-18 18:29:26 +00:00
|
|
|
dev_priv->display.update_wm = i9xx_update_wm;
|
|
|
|
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
|
2016-10-13 10:03:10 +00:00
|
|
|
} else if (IS_GEN2(dev_priv)) {
|
2016-10-31 20:37:25 +00:00
|
|
|
if (INTEL_INFO(dev_priv)->num_pipes == 1) {
|
2013-12-14 22:38:30 +00:00
|
|
|
dev_priv->display.update_wm = i845_update_wm;
|
2012-04-18 18:29:26 +00:00
|
|
|
dev_priv->display.get_fifo_size = i845_get_fifo_size;
|
2013-12-14 22:38:30 +00:00
|
|
|
} else {
|
|
|
|
dev_priv->display.update_wm = i9xx_update_wm;
|
2012-04-18 18:29:26 +00:00
|
|
|
dev_priv->display.get_fifo_size = i830_get_fifo_size;
|
2013-12-14 22:38:30 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
DRM_ERROR("unexpected fall-through in intel_init_pm\n");
|
2012-04-18 18:29:26 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-17 19:55:53 +00:00
|
|
|
static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t flags =
|
|
|
|
I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
|
|
|
|
|
|
|
|
switch (flags) {
|
|
|
|
case GEN6_PCODE_SUCCESS:
|
|
|
|
return 0;
|
|
|
|
case GEN6_PCODE_UNIMPLEMENTED_CMD:
|
|
|
|
case GEN6_PCODE_ILLEGAL_CMD:
|
|
|
|
return -ENXIO;
|
|
|
|
case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
|
2016-08-26 10:59:26 +00:00
|
|
|
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
|
2016-08-17 19:55:53 +00:00
|
|
|
return -EOVERFLOW;
|
|
|
|
case GEN6_PCODE_TIMEOUT:
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(flags)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t flags =
|
|
|
|
I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
|
|
|
|
|
|
|
|
switch (flags) {
|
|
|
|
case GEN6_PCODE_SUCCESS:
|
|
|
|
return 0;
|
|
|
|
case GEN6_PCODE_ILLEGAL_CMD:
|
|
|
|
return -ENXIO;
|
|
|
|
case GEN7_PCODE_TIMEOUT:
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
case GEN7_PCODE_ILLEGAL_DATA:
|
|
|
|
return -EINVAL;
|
|
|
|
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
|
|
|
|
return -EOVERFLOW;
|
|
|
|
default:
|
|
|
|
MISSING_CASE(flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-14 02:50:10 +00:00
|
|
|
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
|
2012-09-26 17:34:00 +00:00
|
|
|
{
|
2016-08-17 19:55:53 +00:00
|
|
|
int status;
|
|
|
|
|
2012-11-02 18:14:01 +00:00
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
2012-09-26 17:34:00 +00:00
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
/* GEN6_PCODE_* are outside of the forcewake domain, we can
|
|
|
|
* use te fw I915_READ variants to reduce the amount of work
|
|
|
|
* required when reading/writing.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
|
2012-09-26 17:34:00 +00:00
|
|
|
DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
I915_WRITE_FW(GEN6_PCODE_DATA, *val);
|
|
|
|
I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
|
|
|
|
I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
|
2012-09-26 17:34:00 +00:00
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
if (intel_wait_for_register_fw(dev_priv,
|
|
|
|
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
|
|
|
|
500)) {
|
2012-09-26 17:34:00 +00:00
|
|
|
DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
*val = I915_READ_FW(GEN6_PCODE_DATA);
|
|
|
|
I915_WRITE_FW(GEN6_PCODE_DATA, 0);
|
2012-09-26 17:34:00 +00:00
|
|
|
|
2016-08-17 19:55:53 +00:00
|
|
|
if (INTEL_GEN(dev_priv) > 6)
|
|
|
|
status = gen7_check_mailbox_status(dev_priv);
|
|
|
|
else
|
|
|
|
status = gen6_check_mailbox_status(dev_priv);
|
|
|
|
|
|
|
|
if (status) {
|
|
|
|
DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
|
|
|
|
status);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2012-09-26 17:34:00 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
|
2016-08-17 19:55:53 +00:00
|
|
|
u32 mbox, u32 val)
|
2012-09-26 17:34:00 +00:00
|
|
|
{
|
2016-08-17 19:55:53 +00:00
|
|
|
int status;
|
|
|
|
|
2012-11-02 18:14:01 +00:00
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
2012-09-26 17:34:00 +00:00
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
/* GEN6_PCODE_* are outside of the forcewake domain, we can
|
|
|
|
* use te fw I915_READ variants to reduce the amount of work
|
|
|
|
* required when reading/writing.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
|
2012-09-26 17:34:00 +00:00
|
|
|
DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
I915_WRITE_FW(GEN6_PCODE_DATA, val);
|
2016-11-28 15:29:27 +00:00
|
|
|
I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
|
2016-06-30 14:32:45 +00:00
|
|
|
I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
|
2012-09-26 17:34:00 +00:00
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
if (intel_wait_for_register_fw(dev_priv,
|
|
|
|
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
|
|
|
|
500)) {
|
2012-09-26 17:34:00 +00:00
|
|
|
DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
|
2016-06-30 14:32:45 +00:00
|
|
|
I915_WRITE_FW(GEN6_PCODE_DATA, 0);
|
2012-09-26 17:34:00 +00:00
|
|
|
|
2016-08-17 19:55:53 +00:00
|
|
|
if (INTEL_GEN(dev_priv) > 6)
|
|
|
|
status = gen7_check_mailbox_status(dev_priv);
|
|
|
|
else
|
|
|
|
status = gen6_check_mailbox_status(dev_priv);
|
|
|
|
|
|
|
|
if (status) {
|
|
|
|
DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
|
|
|
|
status);
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2012-09-26 17:34:00 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2013-04-02 18:23:05 +00:00
|
|
|
|
2016-12-05 16:27:37 +00:00
|
|
|
static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
|
|
|
|
u32 request, u32 reply_mask, u32 reply,
|
|
|
|
u32 *status)
|
|
|
|
{
|
|
|
|
u32 val = request;
|
|
|
|
|
|
|
|
*status = sandybridge_pcode_read(dev_priv, mbox, &val);
|
|
|
|
|
|
|
|
return *status || ((val & reply_mask) == reply);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* skl_pcode_request - send PCODE request until acknowledgment
|
|
|
|
* @dev_priv: device private
|
|
|
|
* @mbox: PCODE mailbox ID the request is targeted for
|
|
|
|
* @request: request ID
|
|
|
|
* @reply_mask: mask used to check for request acknowledgment
|
|
|
|
* @reply: value used to check for request acknowledgment
|
|
|
|
* @timeout_base_ms: timeout for polling with preemption enabled
|
|
|
|
*
|
|
|
|
* Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
|
|
|
|
* reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
|
|
|
|
* The request is acknowledged once the PCODE reply dword equals @reply after
|
|
|
|
* applying @reply_mask. Polling is first attempted with preemption enabled
|
|
|
|
* for @timeout_base_ms and if this times out for another 10 ms with
|
|
|
|
* preemption disabled.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
|
|
|
|
* other error as reported by PCODE.
|
|
|
|
*/
|
|
|
|
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
|
|
|
|
u32 reply_mask, u32 reply, int timeout_base_ms)
|
|
|
|
{
|
|
|
|
u32 status;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
|
|
|
|
|
|
|
|
#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
|
|
|
|
&status)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Prime the PCODE by doing a request first. Normally it guarantees
|
|
|
|
* that a subsequent request, at most @timeout_base_ms later, succeeds.
|
|
|
|
* _wait_for() doesn't guarantee when its passed condition is evaluated
|
|
|
|
* first, so send the first request explicitly.
|
|
|
|
*/
|
|
|
|
if (COND) {
|
|
|
|
ret = 0;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
ret = _wait_for(COND, timeout_base_ms * 1000, 10);
|
|
|
|
if (!ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The above can time out if the number of requests was low (2 in the
|
|
|
|
* worst case) _and_ PCODE was busy for some reason even after a
|
|
|
|
* (queued) request and @timeout_base_ms delay. As a workaround retry
|
|
|
|
* the poll with preemption disabled to maximize the number of
|
|
|
|
* requests. Increase the timeout from @timeout_base_ms to 10ms to
|
|
|
|
* account for interrupts that could reduce the number of these
|
|
|
|
* requests.
|
|
|
|
*/
|
|
|
|
DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
|
|
|
|
WARN_ON_ONCE(timeout_base_ms > 3);
|
|
|
|
preempt_disable();
|
|
|
|
ret = wait_for_atomic(COND, 10);
|
|
|
|
preempt_enable();
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret ? ret : status;
|
|
|
|
#undef COND
|
|
|
|
}
|
|
|
|
|
2014-11-10 20:55:12 +00:00
|
|
|
static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
|
|
|
|
{
|
2016-03-04 19:43:02 +00:00
|
|
|
/*
|
|
|
|
* N = val - 0xb7
|
|
|
|
* Slow = Fast = GPLL ref * N
|
|
|
|
*/
|
|
|
|
return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
|
2013-04-17 22:54:57 +00:00
|
|
|
}
|
|
|
|
|
2014-07-12 09:21:39 +00:00
|
|
|
static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
2013-04-17 22:54:57 +00:00
|
|
|
{
|
2016-03-04 19:43:02 +00:00
|
|
|
return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
|
2013-04-17 22:54:57 +00:00
|
|
|
}
|
|
|
|
|
2014-07-12 09:21:39 +00:00
|
|
|
static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
|
2014-07-12 09:24:33 +00:00
|
|
|
{
|
2016-03-04 19:43:02 +00:00
|
|
|
/*
|
|
|
|
* N = val / 2
|
|
|
|
* CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
|
|
|
|
*/
|
|
|
|
return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
|
2014-07-12 09:24:33 +00:00
|
|
|
}
|
|
|
|
|
2014-07-12 09:21:39 +00:00
|
|
|
static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
2014-07-12 09:24:33 +00:00
|
|
|
{
|
2014-08-18 11:42:43 +00:00
|
|
|
/* CHV needs even values */
|
2016-03-04 19:43:02 +00:00
|
|
|
return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
|
2014-07-12 09:24:33 +00:00
|
|
|
}
|
|
|
|
|
2015-01-23 19:04:25 +00:00
|
|
|
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
|
2014-07-12 09:24:33 +00:00
|
|
|
{
|
2016-04-07 08:08:05 +00:00
|
|
|
if (IS_GEN9(dev_priv))
|
2015-11-13 17:29:41 +00:00
|
|
|
return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
|
|
|
|
GEN9_FREQ_SCALER);
|
2016-04-07 08:08:05 +00:00
|
|
|
else if (IS_CHERRYVIEW(dev_priv))
|
2015-01-23 19:04:25 +00:00
|
|
|
return chv_gpu_freq(dev_priv, val);
|
2016-04-07 08:08:05 +00:00
|
|
|
else if (IS_VALLEYVIEW(dev_priv))
|
2015-01-23 19:04:25 +00:00
|
|
|
return byt_gpu_freq(dev_priv, val);
|
|
|
|
else
|
|
|
|
return val * GT_FREQUENCY_MULTIPLIER;
|
2014-07-12 09:24:33 +00:00
|
|
|
}
|
|
|
|
|
2015-01-23 19:04:25 +00:00
|
|
|
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
|
|
|
|
{
|
2016-04-07 08:08:05 +00:00
|
|
|
if (IS_GEN9(dev_priv))
|
2015-11-13 17:29:41 +00:00
|
|
|
return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
|
|
|
|
GT_FREQUENCY_MULTIPLIER);
|
2016-04-07 08:08:05 +00:00
|
|
|
else if (IS_CHERRYVIEW(dev_priv))
|
2015-01-23 19:04:25 +00:00
|
|
|
return chv_freq_opcode(dev_priv, val);
|
2016-04-07 08:08:05 +00:00
|
|
|
else if (IS_VALLEYVIEW(dev_priv))
|
2015-01-23 19:04:25 +00:00
|
|
|
return byt_freq_opcode(dev_priv, val);
|
|
|
|
else
|
2015-11-13 17:29:41 +00:00
|
|
|
return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
|
2015-01-23 19:04:25 +00:00
|
|
|
}
|
2014-07-12 09:24:33 +00:00
|
|
|
|
2015-04-07 15:20:31 +00:00
|
|
|
struct request_boost {
|
|
|
|
struct work_struct work;
|
2015-05-21 12:21:25 +00:00
|
|
|
struct drm_i915_gem_request *req;
|
2015-04-07 15:20:31 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static void __intel_rps_boost_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct request_boost *boost = container_of(work, struct request_boost, work);
|
2015-04-27 12:41:24 +00:00
|
|
|
struct drm_i915_gem_request *req = boost->req;
|
2015-04-07 15:20:31 +00:00
|
|
|
|
2016-07-01 16:23:16 +00:00
|
|
|
if (!i915_gem_request_completed(req))
|
2016-05-06 14:40:21 +00:00
|
|
|
gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
|
2015-04-07 15:20:31 +00:00
|
|
|
|
2016-07-20 12:31:49 +00:00
|
|
|
i915_gem_request_put(req);
|
2015-04-07 15:20:31 +00:00
|
|
|
kfree(boost);
|
|
|
|
}
|
|
|
|
|
2016-05-06 13:48:28 +00:00
|
|
|
void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
|
2015-04-07 15:20:31 +00:00
|
|
|
{
|
|
|
|
struct request_boost *boost;
|
|
|
|
|
2016-05-06 13:48:28 +00:00
|
|
|
if (req == NULL || INTEL_GEN(req->i915) < 6)
|
2015-04-07 15:20:31 +00:00
|
|
|
return;
|
|
|
|
|
2016-07-01 16:23:16 +00:00
|
|
|
if (i915_gem_request_completed(req))
|
2015-04-27 12:41:24 +00:00
|
|
|
return;
|
|
|
|
|
2015-04-07 15:20:31 +00:00
|
|
|
boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
|
|
|
|
if (boost == NULL)
|
|
|
|
return;
|
|
|
|
|
2016-07-20 12:31:49 +00:00
|
|
|
boost->req = i915_gem_request_get(req);
|
2015-04-07 15:20:31 +00:00
|
|
|
|
|
|
|
INIT_WORK(&boost->work, __intel_rps_boost_work);
|
2016-05-06 13:48:28 +00:00
|
|
|
queue_work(req->i915->wq, &boost->work);
|
2015-04-07 15:20:31 +00:00
|
|
|
}
|
|
|
|
|
2016-12-01 14:16:45 +00:00
|
|
|
void intel_pm_setup(struct drm_i915_private *dev_priv)
|
2013-07-19 19:36:52 +00:00
|
|
|
{
|
2013-12-06 09:17:53 +00:00
|
|
|
mutex_init(&dev_priv->rps.hw_lock);
|
2015-05-21 20:01:47 +00:00
|
|
|
spin_lock_init(&dev_priv->rps.client_lock);
|
2013-12-06 09:17:53 +00:00
|
|
|
|
2016-07-21 20:16:19 +00:00
|
|
|
INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
|
|
|
|
__intel_autoenable_gt_powersave);
|
2015-04-07 15:20:32 +00:00
|
|
|
INIT_LIST_HEAD(&dev_priv->rps.clients);
|
2014-03-07 23:08:15 +00:00
|
|
|
|
2014-03-07 23:08:19 +00:00
|
|
|
dev_priv->pm.suspended = false;
|
2015-12-16 00:52:19 +00:00
|
|
|
atomic_set(&dev_priv->pm.wakeref_count, 0);
|
2013-07-19 19:36:52 +00:00
|
|
|
}
|