2006-01-02 09:14:23 +00:00
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/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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2005-04-16 22:20:36 +00:00
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*/
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2006-01-02 09:14:23 +00:00
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/*
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2005-04-16 22:20:36 +00:00
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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2005-06-23 12:46:46 +00:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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2006-01-02 09:14:23 +00:00
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*/
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2005-04-16 22:20:36 +00:00
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2012-03-18 20:00:11 +00:00
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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2009-06-18 23:56:52 +00:00
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#include <linux/sysrq.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2013-10-15 17:55:29 +00:00
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#include <linux/circ_buf.h>
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2012-10-02 17:01:07 +00:00
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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2005-04-16 22:20:36 +00:00
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#include "i915_drv.h"
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2009-08-25 10:15:50 +00:00
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#include "i915_trace.h"
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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#include "intel_drv.h"
|
2005-04-16 22:20:36 +00:00
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|
2013-02-28 09:17:12 +00:00
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static const u32 hpd_ibx[] = {
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[HPD_CRT] = SDE_CRT_HOTPLUG,
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[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
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[HPD_PORT_B] = SDE_PORTB_HOTPLUG,
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[HPD_PORT_C] = SDE_PORTC_HOTPLUG,
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[HPD_PORT_D] = SDE_PORTD_HOTPLUG
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};
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static const u32 hpd_cpt[] = {
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[HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
|
2013-03-26 21:38:43 +00:00
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[HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
|
2013-02-28 09:17:12 +00:00
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[HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
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[HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
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[HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
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};
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static const u32 hpd_mask_i915[] = {
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[HPD_CRT] = CRT_HOTPLUG_INT_EN,
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[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
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[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
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[HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
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[HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
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[HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
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};
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|
2013-12-18 08:08:43 +00:00
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static const u32 hpd_status_g4x[] = {
|
2013-02-28 09:17:12 +00:00
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[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
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[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
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[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
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[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
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[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
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[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
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};
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static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
|
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[HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
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[HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
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[HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
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[HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
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[HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
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[HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
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};
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|
2014-04-01 18:37:11 +00:00
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/* IIR can theoretically queue up two events. Be paranoid. */
|
2014-04-01 18:37:14 +00:00
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#define GEN8_IRQ_RESET_NDX(type, which) do { \
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2014-04-01 18:37:11 +00:00
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I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
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POSTING_READ(GEN8_##type##_IMR(which)); \
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I915_WRITE(GEN8_##type##_IER(which), 0); \
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I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
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POSTING_READ(GEN8_##type##_IIR(which)); \
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I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
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POSTING_READ(GEN8_##type##_IIR(which)); \
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} while (0)
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|
2014-04-01 18:37:14 +00:00
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#define GEN5_IRQ_RESET(type) do { \
|
2014-04-01 18:37:09 +00:00
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I915_WRITE(type##IMR, 0xffffffff); \
|
2014-04-01 18:37:11 +00:00
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POSTING_READ(type##IMR); \
|
2014-04-01 18:37:09 +00:00
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I915_WRITE(type##IER, 0); \
|
2014-04-01 18:37:11 +00:00
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I915_WRITE(type##IIR, 0xffffffff); \
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POSTING_READ(type##IIR); \
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I915_WRITE(type##IIR, 0xffffffff); \
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POSTING_READ(type##IIR); \
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2014-04-01 18:37:09 +00:00
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} while (0)
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2014-04-01 18:37:16 +00:00
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/*
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* We should clear IMR at preinstall/uninstall, and just check at postinstall.
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*/
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#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
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u32 val = I915_READ(reg); \
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if (val) { \
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WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
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(reg), val); \
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I915_WRITE((reg), 0xffffffff); \
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POSTING_READ(reg); \
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I915_WRITE((reg), 0xffffffff); \
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POSTING_READ(reg); \
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} \
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} while (0)
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|
2014-04-01 18:37:15 +00:00
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#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
|
2014-04-01 18:37:16 +00:00
|
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GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
|
2014-04-01 18:37:15 +00:00
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I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
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I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
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POSTING_READ(GEN8_##type##_IER(which)); \
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} while (0)
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#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
|
2014-04-01 18:37:16 +00:00
|
|
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GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
|
2014-04-01 18:37:15 +00:00
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I915_WRITE(type##IMR, (imr_val)); \
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I915_WRITE(type##IER, (ier_val)); \
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POSTING_READ(type##IER); \
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} while (0)
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|
2009-06-08 06:40:19 +00:00
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/* For display hotplug interrupt */
|
2010-08-20 12:23:26 +00:00
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static void
|
2014-03-31 11:27:17 +00:00
|
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ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
|
2009-06-08 06:40:19 +00:00
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{
|
2013-06-27 11:44:58 +00:00
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assert_spin_locked(&dev_priv->irq_lock);
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|
2014-03-07 23:12:32 +00:00
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if (WARN_ON(dev_priv->pm.irqs_disabled))
|
2013-08-19 16:18:09 +00:00
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return;
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|
2010-12-04 11:30:53 +00:00
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|
|
if ((dev_priv->irq_mask & mask) != 0) {
|
|
|
|
dev_priv->irq_mask &= ~mask;
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|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(DEIMR);
|
2009-06-08 06:40:19 +00:00
|
|
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}
|
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}
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|
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|
2013-02-22 20:05:31 +00:00
|
|
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static void
|
2014-03-31 11:27:17 +00:00
|
|
|
ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
|
2009-06-08 06:40:19 +00:00
|
|
|
{
|
2013-06-27 11:44:58 +00:00
|
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assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-03-07 23:12:32 +00:00
|
|
|
if (WARN_ON(dev_priv->pm.irqs_disabled))
|
2013-08-19 16:18:09 +00:00
|
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|
return;
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|
2010-12-04 11:30:53 +00:00
|
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if ((dev_priv->irq_mask & mask) != mask) {
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|
|
|
dev_priv->irq_mask |= mask;
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|
|
|
I915_WRITE(DEIMR, dev_priv->irq_mask);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(DEIMR);
|
2009-06-08 06:40:19 +00:00
|
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|
}
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|
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|
}
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|
2013-08-06 21:57:12 +00:00
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|
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/**
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|
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* ilk_update_gt_irq - update GTIMR
|
|
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* @dev_priv: driver private
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* @interrupt_mask: mask of interrupt bits to update
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* @enabled_irq_mask: mask of interrupt bits to enable
|
|
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|
*/
|
|
|
|
static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t interrupt_mask,
|
|
|
|
uint32_t enabled_irq_mask)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-03-07 23:12:32 +00:00
|
|
|
if (WARN_ON(dev_priv->pm.irqs_disabled))
|
2013-08-19 16:18:09 +00:00
|
|
|
return;
|
|
|
|
|
2013-08-06 21:57:12 +00:00
|
|
|
dev_priv->gt_irq_mask &= ~interrupt_mask;
|
|
|
|
dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
|
|
|
|
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
|
|
|
|
POSTING_READ(GTIMR);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
|
|
|
{
|
|
|
|
ilk_update_gt_irq(dev_priv, mask, mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
|
|
|
{
|
|
|
|
ilk_update_gt_irq(dev_priv, mask, 0);
|
|
|
|
}
|
|
|
|
|
2013-08-06 21:57:13 +00:00
|
|
|
/**
|
|
|
|
* snb_update_pm_irq - update GEN6_PMIMR
|
|
|
|
* @dev_priv: driver private
|
|
|
|
* @interrupt_mask: mask of interrupt bits to update
|
|
|
|
* @enabled_irq_mask: mask of interrupt bits to enable
|
|
|
|
*/
|
|
|
|
static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t interrupt_mask,
|
|
|
|
uint32_t enabled_irq_mask)
|
|
|
|
{
|
2013-08-06 21:57:15 +00:00
|
|
|
uint32_t new_val;
|
2013-08-06 21:57:13 +00:00
|
|
|
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-03-07 23:12:32 +00:00
|
|
|
if (WARN_ON(dev_priv->pm.irqs_disabled))
|
2013-08-19 16:18:09 +00:00
|
|
|
return;
|
|
|
|
|
2013-08-06 21:57:15 +00:00
|
|
|
new_val = dev_priv->pm_irq_mask;
|
2013-08-06 21:57:14 +00:00
|
|
|
new_val &= ~interrupt_mask;
|
|
|
|
new_val |= (~enabled_irq_mask & interrupt_mask);
|
|
|
|
|
2013-08-06 21:57:15 +00:00
|
|
|
if (new_val != dev_priv->pm_irq_mask) {
|
|
|
|
dev_priv->pm_irq_mask = new_val;
|
|
|
|
I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
|
2013-08-06 21:57:14 +00:00
|
|
|
POSTING_READ(GEN6_PMIMR);
|
|
|
|
}
|
2013-08-06 21:57:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
|
|
|
{
|
|
|
|
snb_update_pm_irq(dev_priv, mask, mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
|
|
|
|
{
|
|
|
|
snb_update_pm_irq(dev_priv, mask, 0);
|
|
|
|
}
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
static bool ivb_can_enable_err_int(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_crtc *crtc;
|
|
|
|
enum pipe pipe;
|
|
|
|
|
2013-06-27 11:44:58 +00:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
|
|
|
|
|
|
|
if (crtc->cpu_fifo_underrun_disabled)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool cpt_can_enable_serr_int(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum pipe pipe;
|
|
|
|
struct intel_crtc *crtc;
|
|
|
|
|
2013-07-04 21:35:21 +00:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
|
|
|
|
|
|
|
if (crtc->pch_fifo_underrun_disabled)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-01-17 09:44:31 +00:00
|
|
|
static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 reg = PIPESTAT(pipe);
|
|
|
|
u32 pipestat = I915_READ(reg) & 0x7fff0000;
|
|
|
|
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
}
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
|
|
|
|
enum pipe pipe, bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
|
|
|
|
DE_PIPEB_FIFO_UNDERRUN;
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
ironlake_enable_display_irq(dev_priv, bit);
|
|
|
|
else
|
|
|
|
ironlake_disable_display_irq(dev_priv, bit);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
|
2013-07-09 20:59:16 +00:00
|
|
|
enum pipe pipe, bool enable)
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
if (enable) {
|
2013-07-09 20:59:16 +00:00
|
|
|
I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
if (!ivb_can_enable_err_int(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
|
|
|
|
} else {
|
2013-07-09 20:59:16 +00:00
|
|
|
bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
|
|
|
|
|
|
|
|
/* Change the state _after_ we've read out the current one. */
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
|
2013-07-09 20:59:16 +00:00
|
|
|
|
|
|
|
if (!was_enabled &&
|
|
|
|
(I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
|
|
|
|
DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
|
|
|
|
pipe_name(pipe));
|
|
|
|
}
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-07 10:05:46 +00:00
|
|
|
static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
|
|
|
|
enum pipe pipe, bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
|
|
|
|
else
|
|
|
|
dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
|
|
|
|
I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
|
|
|
|
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
|
|
|
|
}
|
|
|
|
|
2013-07-04 21:35:21 +00:00
|
|
|
/**
|
|
|
|
* ibx_display_interrupt_update - update SDEIMR
|
|
|
|
* @dev_priv: driver private
|
|
|
|
* @interrupt_mask: mask of interrupt bits to update
|
|
|
|
* @enabled_irq_mask: mask of interrupt bits to enable
|
|
|
|
*/
|
|
|
|
static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
|
|
|
|
uint32_t interrupt_mask,
|
|
|
|
uint32_t enabled_irq_mask)
|
|
|
|
{
|
|
|
|
uint32_t sdeimr = I915_READ(SDEIMR);
|
|
|
|
sdeimr &= ~interrupt_mask;
|
|
|
|
sdeimr |= (~enabled_irq_mask & interrupt_mask);
|
|
|
|
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-03-07 23:12:32 +00:00
|
|
|
if (WARN_ON(dev_priv->pm.irqs_disabled))
|
2013-08-19 16:18:09 +00:00
|
|
|
return;
|
|
|
|
|
2013-07-04 21:35:21 +00:00
|
|
|
I915_WRITE(SDEIMR, sdeimr);
|
|
|
|
POSTING_READ(SDEIMR);
|
|
|
|
}
|
|
|
|
#define ibx_enable_display_interrupt(dev_priv, bits) \
|
|
|
|
ibx_display_interrupt_update((dev_priv), (bits), (bits))
|
|
|
|
#define ibx_disable_display_interrupt(dev_priv, bits) \
|
|
|
|
ibx_display_interrupt_update((dev_priv), (bits), 0)
|
|
|
|
|
2013-07-04 21:35:24 +00:00
|
|
|
static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
|
|
|
|
enum transcoder pch_transcoder,
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-04 21:35:24 +00:00
|
|
|
uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
|
|
|
|
SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
if (enable)
|
2013-07-04 21:35:21 +00:00
|
|
|
ibx_enable_display_interrupt(dev_priv, bit);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
else
|
2013-07-04 21:35:21 +00:00
|
|
|
ibx_disable_display_interrupt(dev_priv, bit);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
|
|
|
|
enum transcoder pch_transcoder,
|
|
|
|
bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (enable) {
|
2013-07-10 06:30:23 +00:00
|
|
|
I915_WRITE(SERR_INT,
|
|
|
|
SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
if (!cpt_can_enable_serr_int(dev))
|
|
|
|
return;
|
|
|
|
|
2013-07-04 21:35:21 +00:00
|
|
|
ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
} else {
|
2013-07-10 06:30:23 +00:00
|
|
|
uint32_t tmp = I915_READ(SERR_INT);
|
|
|
|
bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
|
|
|
|
|
|
|
|
/* Change the state _after_ we've read out the current one. */
|
2013-07-04 21:35:21 +00:00
|
|
|
ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
|
2013-07-10 06:30:23 +00:00
|
|
|
|
|
|
|
if (!was_enabled &&
|
|
|
|
(tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
|
|
|
|
DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
|
|
|
|
transcoder_name(pch_transcoder));
|
|
|
|
}
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
|
|
|
|
* @dev: drm device
|
|
|
|
* @pipe: pipe
|
|
|
|
* @enable: true if we want to report FIFO underrun errors, false otherwise
|
|
|
|
*
|
|
|
|
* This function makes us disable or enable CPU fifo underruns for a specific
|
|
|
|
* pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
|
|
|
|
* reporting for one pipe may also disable all the other CPU error interruts for
|
|
|
|
* the other pipes, due to the fact that there's just one interrupt mask/enable
|
|
|
|
* bit for all the pipes.
|
|
|
|
*
|
|
|
|
* Returns the previous state of underrun reporting.
|
|
|
|
*/
|
2014-03-04 17:23:09 +00:00
|
|
|
bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
|
|
|
|
enum pipe pipe, bool enable)
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
bool ret;
|
|
|
|
|
2014-03-05 14:20:56 +00:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
ret = !intel_crtc->cpu_fifo_underrun_disabled;
|
|
|
|
|
|
|
|
if (enable == ret)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
intel_crtc->cpu_fifo_underrun_disabled = !enable;
|
|
|
|
|
2014-01-17 09:44:31 +00:00
|
|
|
if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
|
|
|
|
i9xx_clear_fifo_underrun(dev, pipe);
|
|
|
|
else if (IS_GEN5(dev) || IS_GEN6(dev))
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
|
|
|
|
else if (IS_GEN7(dev))
|
2013-07-09 20:59:16 +00:00
|
|
|
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
|
2013-11-07 10:05:46 +00:00
|
|
|
else if (IS_GEN8(dev))
|
|
|
|
broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
done:
|
2014-03-04 17:23:09 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
|
|
|
|
enum pipe pipe, bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
unsigned long flags;
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
|
|
|
ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
2014-03-04 17:23:09 +00:00
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-02-10 16:42:49 +00:00
|
|
|
static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
|
|
|
|
enum pipe pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
|
|
|
|
return !intel_crtc->cpu_fifo_underrun_disabled;
|
|
|
|
}
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
/**
|
|
|
|
* intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
|
|
|
|
* @dev: drm device
|
|
|
|
* @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
|
|
|
|
* @enable: true if we want to report FIFO underrun errors, false otherwise
|
|
|
|
*
|
|
|
|
* This function makes us disable or enable PCH fifo underruns for a specific
|
|
|
|
* PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
|
|
|
|
* underrun reporting for one transcoder may also disable all the other PCH
|
|
|
|
* error interruts for the other transcoders, due to the fact that there's just
|
|
|
|
* one interrupt mask/enable bit for all the transcoders.
|
|
|
|
*
|
|
|
|
* Returns the previous state of underrun reporting.
|
|
|
|
*/
|
|
|
|
bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
|
|
|
|
enum transcoder pch_transcoder,
|
|
|
|
bool enable)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-04 21:35:24 +00:00
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
unsigned long flags;
|
|
|
|
bool ret;
|
|
|
|
|
2013-07-04 21:35:24 +00:00
|
|
|
/*
|
|
|
|
* NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
|
|
|
|
* has only one pch transcoder A that all pipes can use. To avoid racy
|
|
|
|
* pch transcoder -> pipe lookups from interrupt code simply store the
|
|
|
|
* underrun statistics in crtc A. Since we never expose this anywhere
|
|
|
|
* nor use it outside of the fifo underrun code here using the "wrong"
|
|
|
|
* crtc on LPT won't cause issues.
|
|
|
|
*/
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
|
|
|
|
|
|
|
ret = !intel_crtc->pch_fifo_underrun_disabled;
|
|
|
|
|
|
|
|
if (enable == ret)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
intel_crtc->pch_fifo_underrun_disabled = !enable;
|
|
|
|
|
|
|
|
if (HAS_PCH_IBX(dev))
|
2013-07-04 21:35:24 +00:00
|
|
|
ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
else
|
|
|
|
cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
|
|
|
|
|
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2014-03-02 20:18:00 +00:00
|
|
|
static void
|
2014-02-10 16:42:47 +00:00
|
|
|
__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 enable_mask, u32 status_mask)
|
2008-11-04 10:03:27 +00:00
|
|
|
{
|
2013-02-20 19:16:18 +00:00
|
|
|
u32 reg = PIPESTAT(pipe);
|
2014-02-10 16:42:47 +00:00
|
|
|
u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
|
2008-11-04 10:03:27 +00:00
|
|
|
|
2013-06-27 15:52:10 +00:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-04-03 10:28:33 +00:00
|
|
|
if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
|
|
|
|
status_mask & ~PIPESTAT_INT_STATUS_MASK,
|
|
|
|
"pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
|
|
|
|
pipe_name(pipe), enable_mask, status_mask))
|
2014-02-10 16:42:47 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
if ((pipestat & enable_mask) == enable_mask)
|
2013-02-20 19:16:18 +00:00
|
|
|
return;
|
|
|
|
|
2014-02-10 16:42:49 +00:00
|
|
|
dev_priv->pipestat_irq_mask[pipe] |= status_mask;
|
|
|
|
|
2013-02-20 19:16:18 +00:00
|
|
|
/* Enable the interrupt, clear any pending status */
|
2014-02-10 16:42:47 +00:00
|
|
|
pipestat |= enable_mask | status_mask;
|
2013-02-20 19:16:18 +00:00
|
|
|
I915_WRITE(reg, pipestat);
|
|
|
|
POSTING_READ(reg);
|
2008-11-04 10:03:27 +00:00
|
|
|
}
|
|
|
|
|
2014-03-02 20:18:00 +00:00
|
|
|
static void
|
2014-02-10 16:42:47 +00:00
|
|
|
__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 enable_mask, u32 status_mask)
|
2008-11-04 10:03:27 +00:00
|
|
|
{
|
2013-02-20 19:16:18 +00:00
|
|
|
u32 reg = PIPESTAT(pipe);
|
2014-02-10 16:42:47 +00:00
|
|
|
u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
|
2008-11-04 10:03:27 +00:00
|
|
|
|
2013-06-27 15:52:10 +00:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2014-04-03 10:28:33 +00:00
|
|
|
if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
|
|
|
|
status_mask & ~PIPESTAT_INT_STATUS_MASK,
|
|
|
|
"pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
|
|
|
|
pipe_name(pipe), enable_mask, status_mask))
|
2013-02-20 19:16:18 +00:00
|
|
|
return;
|
|
|
|
|
2014-02-10 16:42:47 +00:00
|
|
|
if ((pipestat & enable_mask) == 0)
|
|
|
|
return;
|
|
|
|
|
2014-02-10 16:42:49 +00:00
|
|
|
dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
|
|
|
|
|
2014-02-10 16:42:47 +00:00
|
|
|
pipestat &= ~enable_mask;
|
2013-02-20 19:16:18 +00:00
|
|
|
I915_WRITE(reg, pipestat);
|
|
|
|
POSTING_READ(reg);
|
2008-11-04 10:03:27 +00:00
|
|
|
}
|
|
|
|
|
2014-02-10 16:42:48 +00:00
|
|
|
static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
|
|
|
|
{
|
|
|
|
u32 enable_mask = status_mask << 16;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On pipe A we don't support the PSR interrupt yet, on pipe B the
|
|
|
|
* same bit MBZ.
|
|
|
|
*/
|
|
|
|
if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
|
|
|
|
SPRITE0_FLIP_DONE_INT_EN_VLV |
|
|
|
|
SPRITE1_FLIP_DONE_INT_EN_VLV);
|
|
|
|
if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
|
|
|
|
enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
|
|
|
|
if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
|
|
|
|
enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
|
|
|
|
|
|
|
|
return enable_mask;
|
|
|
|
}
|
|
|
|
|
2014-02-10 16:42:47 +00:00
|
|
|
void
|
|
|
|
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 status_mask)
|
|
|
|
{
|
|
|
|
u32 enable_mask;
|
|
|
|
|
2014-02-10 16:42:48 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv->dev))
|
|
|
|
enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
|
|
|
|
status_mask);
|
|
|
|
else
|
|
|
|
enable_mask = status_mask << 16;
|
2014-02-10 16:42:47 +00:00
|
|
|
__i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
|
|
|
|
u32 status_mask)
|
|
|
|
{
|
|
|
|
u32 enable_mask;
|
|
|
|
|
2014-02-10 16:42:48 +00:00
|
|
|
if (IS_VALLEYVIEW(dev_priv->dev))
|
|
|
|
enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
|
|
|
|
status_mask);
|
|
|
|
else
|
|
|
|
enable_mask = status_mask << 16;
|
2014-02-10 16:42:47 +00:00
|
|
|
__i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
|
|
|
|
}
|
|
|
|
|
2009-10-28 05:10:00 +00:00
|
|
|
/**
|
2013-04-29 10:02:54 +00:00
|
|
|
* i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
|
2009-10-28 05:10:00 +00:00
|
|
|
*/
|
2013-04-29 10:02:54 +00:00
|
|
|
static void i915_enable_asle_pipestat(struct drm_device *dev)
|
2009-10-28 05:10:00 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-12-04 11:30:53 +00:00
|
|
|
unsigned long irqflags;
|
|
|
|
|
2013-04-29 10:02:54 +00:00
|
|
|
if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
|
|
|
|
return;
|
|
|
|
|
2010-12-04 11:30:53 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2009-10-28 05:10:00 +00:00
|
|
|
|
2014-02-10 16:42:47 +00:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
|
2013-04-29 10:02:53 +00:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
2013-10-21 16:04:35 +00:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A,
|
2014-02-10 16:42:47 +00:00
|
|
|
PIPE_LEGACY_BLC_EVENT_STATUS);
|
2010-12-04 11:30:53 +00:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2009-10-28 05:10:00 +00:00
|
|
|
}
|
|
|
|
|
2008-09-30 19:14:26 +00:00
|
|
|
/**
|
|
|
|
* i915_pipe_enabled - check if a pipe is enabled
|
|
|
|
* @dev: DRM device
|
|
|
|
* @pipe: pipe to check
|
|
|
|
*
|
|
|
|
* Reading certain registers when the pipe is disabled can hang the chip.
|
|
|
|
* Use this routine to make sure the PLL is running and the pipe is active
|
|
|
|
* before reading such registers if unsure.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
i915_pipe_enabled(struct drm_device *dev, int pipe)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-23 20:29:59 +00:00
|
|
|
|
2013-05-21 22:50:23 +00:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
|
|
/* Locking is horribly broken here, but whatever. */
|
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2013-05-03 15:15:39 +00:00
|
|
|
|
2013-05-21 22:50:23 +00:00
|
|
|
return intel_crtc->active;
|
|
|
|
} else {
|
|
|
|
return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
|
|
|
|
}
|
2008-09-30 19:14:26 +00:00
|
|
|
}
|
|
|
|
|
2013-10-11 18:52:44 +00:00
|
|
|
static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
/* Gen2 doesn't have a hardware frame counter */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-19 02:39:29 +00:00
|
|
|
/* Called from drm generic code, passed a 'crtc', which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-28 20:00:41 +00:00
|
|
|
static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
|
2008-09-30 19:14:26 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-09-30 19:14:26 +00:00
|
|
|
unsigned long high_frame;
|
|
|
|
unsigned long low_frame;
|
2013-09-25 16:55:26 +00:00
|
|
|
u32 high1, high2, low, pixel, vbl_start;
|
2008-09-30 19:14:26 +00:00
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe)) {
|
2009-10-09 03:39:40 +00:00
|
|
|
DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
|
2011-02-07 20:26:52 +00:00
|
|
|
"pipe %c\n", pipe_name(pipe));
|
2008-09-30 19:14:26 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-09-25 16:55:26 +00:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
|
|
|
const struct drm_display_mode *mode =
|
|
|
|
&intel_crtc->config.adjusted_mode;
|
|
|
|
|
|
|
|
vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
|
|
|
|
} else {
|
2014-02-07 15:34:05 +00:00
|
|
|
enum transcoder cpu_transcoder = (enum transcoder) pipe;
|
2013-09-25 16:55:26 +00:00
|
|
|
u32 htotal;
|
|
|
|
|
|
|
|
htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
|
|
|
|
vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
|
|
|
|
|
|
|
|
vbl_start *= htotal;
|
|
|
|
}
|
|
|
|
|
2011-02-07 20:26:52 +00:00
|
|
|
high_frame = PIPEFRAME(pipe);
|
|
|
|
low_frame = PIPEFRAMEPIXEL(pipe);
|
2010-09-11 12:48:45 +00:00
|
|
|
|
2008-09-30 19:14:26 +00:00
|
|
|
/*
|
|
|
|
* High & low register fields aren't synchronized, so make sure
|
|
|
|
* we get a low value that's stable across two reads of the high
|
|
|
|
* register.
|
|
|
|
*/
|
|
|
|
do {
|
2010-09-11 12:48:45 +00:00
|
|
|
high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
|
2013-09-25 16:55:26 +00:00
|
|
|
low = I915_READ(low_frame);
|
2010-09-11 12:48:45 +00:00
|
|
|
high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
|
2008-09-30 19:14:26 +00:00
|
|
|
} while (high1 != high2);
|
|
|
|
|
2010-09-11 12:48:45 +00:00
|
|
|
high1 >>= PIPE_FRAME_HIGH_SHIFT;
|
2013-09-25 16:55:26 +00:00
|
|
|
pixel = low & PIPE_PIXEL_MASK;
|
2010-09-11 12:48:45 +00:00
|
|
|
low >>= PIPE_FRAME_LOW_SHIFT;
|
2013-09-25 16:55:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The frame counter increments at beginning of active.
|
|
|
|
* Cook up a vblank counter by also checking the pixel
|
|
|
|
* counter against vblank start.
|
|
|
|
*/
|
2013-11-06 15:56:27 +00:00
|
|
|
return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
|
2008-09-30 19:14:26 +00:00
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
|
2009-02-06 18:22:41 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-02-07 20:26:52 +00:00
|
|
|
int reg = PIPE_FRMCOUNT_GM45(pipe);
|
2009-02-06 18:22:41 +00:00
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe)) {
|
2009-10-09 03:39:40 +00:00
|
|
|
DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
|
2011-02-07 20:26:52 +00:00
|
|
|
"pipe %c\n", pipe_name(pipe));
|
2009-02-06 18:22:41 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return I915_READ(reg);
|
|
|
|
}
|
|
|
|
|
2013-10-30 04:13:08 +00:00
|
|
|
/* raw reads, only for fast reads of display block, no need for forcewake etc. */
|
|
|
|
#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
|
|
|
|
|
2013-10-28 22:04:43 +00:00
|
|
|
static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
|
2013-09-23 10:02:07 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t status;
|
2014-03-11 10:58:46 +00:00
|
|
|
int reg;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
|
|
|
status = GEN8_PIPE_VBLANK;
|
|
|
|
reg = GEN8_DE_PIPE_ISR(pipe);
|
|
|
|
} else if (INTEL_INFO(dev)->gen >= 7) {
|
|
|
|
status = DE_PIPE_VBLANK_IVB(pipe);
|
|
|
|
reg = DEISR;
|
2013-09-23 10:02:07 +00:00
|
|
|
} else {
|
2014-03-11 10:58:46 +00:00
|
|
|
status = DE_PIPE_VBLANK(pipe);
|
|
|
|
reg = DEISR;
|
2013-09-23 10:02:07 +00:00
|
|
|
}
|
2013-10-30 04:13:08 +00:00
|
|
|
|
2014-03-11 10:58:46 +00:00
|
|
|
return __raw_i915_read32(dev_priv, reg) & status;
|
2013-09-23 10:02:07 +00:00
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
|
2013-10-28 18:50:48 +00:00
|
|
|
unsigned int flags, int *vpos, int *hpos,
|
|
|
|
ktime_t *stime, ktime_t *etime)
|
2010-12-08 03:07:19 +00:00
|
|
|
{
|
2013-09-23 11:48:50 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
|
2013-10-11 16:10:32 +00:00
|
|
|
int position;
|
2010-12-08 03:07:19 +00:00
|
|
|
int vbl_start, vbl_end, htotal, vtotal;
|
|
|
|
bool in_vbl = true;
|
|
|
|
int ret = 0;
|
2013-10-30 04:13:08 +00:00
|
|
|
unsigned long irqflags;
|
2010-12-08 03:07:19 +00:00
|
|
|
|
2013-09-23 11:48:50 +00:00
|
|
|
if (!intel_crtc->active) {
|
2010-12-08 03:07:19 +00:00
|
|
|
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
|
2011-02-07 20:26:52 +00:00
|
|
|
"pipe %c\n", pipe_name(pipe));
|
2010-12-08 03:07:19 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-09-23 11:48:50 +00:00
|
|
|
htotal = mode->crtc_htotal;
|
|
|
|
vtotal = mode->crtc_vtotal;
|
|
|
|
vbl_start = mode->crtc_vblank_start;
|
|
|
|
vbl_end = mode->crtc_vblank_end;
|
2010-12-08 03:07:19 +00:00
|
|
|
|
2013-10-28 14:31:41 +00:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
|
vbl_start = DIV_ROUND_UP(vbl_start, 2);
|
|
|
|
vbl_end /= 2;
|
|
|
|
vtotal /= 2;
|
|
|
|
}
|
|
|
|
|
2013-09-23 11:48:50 +00:00
|
|
|
ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
|
|
|
|
|
2013-10-30 04:13:08 +00:00
|
|
|
/*
|
|
|
|
* Lock uncore.lock, as we will do multiple timing critical raw
|
|
|
|
* register reads, potentially with preemption disabled, so the
|
|
|
|
* following code must not block on uncore.lock.
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
|
|
|
|
|
|
|
/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
|
|
|
|
|
|
|
|
/* Get optional system timestamp before query. */
|
|
|
|
if (stime)
|
|
|
|
*stime = ktime_get();
|
|
|
|
|
2013-10-11 18:52:43 +00:00
|
|
|
if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
|
2010-12-08 03:07:19 +00:00
|
|
|
/* No obvious pixelcount register. Only query vertical
|
|
|
|
* scanout position from Display scan line register.
|
|
|
|
*/
|
2013-10-11 18:52:43 +00:00
|
|
|
if (IS_GEN2(dev))
|
2013-10-30 04:13:08 +00:00
|
|
|
position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
|
2013-10-11 18:52:43 +00:00
|
|
|
else
|
2013-10-30 04:13:08 +00:00
|
|
|
position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
|
2013-09-23 10:02:07 +00:00
|
|
|
|
2014-03-11 10:58:45 +00:00
|
|
|
if (HAS_DDI(dev)) {
|
|
|
|
/*
|
|
|
|
* On HSW HDMI outputs there seems to be a 2 line
|
|
|
|
* difference, whereas eDP has the normal 1 line
|
|
|
|
* difference that earlier platforms have. External
|
|
|
|
* DP is unknown. For now just check for the 2 line
|
|
|
|
* difference case on all output types on HSW+.
|
|
|
|
*
|
|
|
|
* This might misinterpret the scanline counter being
|
|
|
|
* one line too far along on eDP, but that's less
|
|
|
|
* dangerous than the alternative since that would lead
|
|
|
|
* the vblank timestamp code astray when it sees a
|
|
|
|
* scanline count before vblank_start during a vblank
|
|
|
|
* interrupt.
|
|
|
|
*/
|
|
|
|
in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
|
|
|
|
if ((in_vbl && (position == vbl_start - 2 ||
|
|
|
|
position == vbl_start - 1)) ||
|
|
|
|
(!in_vbl && (position == vbl_end - 2 ||
|
|
|
|
position == vbl_end - 1)))
|
|
|
|
position = (position + 2) % vtotal;
|
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
2013-10-28 22:04:43 +00:00
|
|
|
/*
|
|
|
|
* The scanline counter increments at the leading edge
|
|
|
|
* of hsync, ie. it completely misses the active portion
|
|
|
|
* of the line. Fix up the counter at both edges of vblank
|
|
|
|
* to get a more accurate picture whether we're in vblank
|
|
|
|
* or not.
|
|
|
|
*/
|
|
|
|
in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
|
|
|
|
if ((in_vbl && position == vbl_start - 1) ||
|
|
|
|
(!in_vbl && position == vbl_end - 1))
|
|
|
|
position = (position + 1) % vtotal;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* ISR vblank status bits don't work the way we'd want
|
|
|
|
* them to work on non-PCH platforms (for
|
|
|
|
* ilk_pipe_in_vblank_locked()), and there doesn't
|
|
|
|
* appear any other way to determine if we're currently
|
|
|
|
* in vblank.
|
|
|
|
*
|
|
|
|
* Instead let's assume that we're already in vblank if
|
|
|
|
* we got called from the vblank interrupt and the
|
|
|
|
* scanline counter value indicates that we're on the
|
|
|
|
* line just prior to vblank start. This should result
|
|
|
|
* in the correct answer, unless the vblank interrupt
|
|
|
|
* delivery really got delayed for almost exactly one
|
|
|
|
* full frame/field.
|
|
|
|
*/
|
|
|
|
if (flags & DRM_CALLED_FROM_VBLIRQ &&
|
|
|
|
position == vbl_start - 1) {
|
|
|
|
position = (position + 1) % vtotal;
|
|
|
|
|
|
|
|
/* Signal this correction as "applied". */
|
|
|
|
ret |= 0x8;
|
|
|
|
}
|
|
|
|
}
|
2010-12-08 03:07:19 +00:00
|
|
|
} else {
|
|
|
|
/* Have access to pixelcount since start of frame.
|
|
|
|
* We can split this into vertical and horizontal
|
|
|
|
* scanout position.
|
|
|
|
*/
|
2013-10-30 04:13:08 +00:00
|
|
|
position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
|
2010-12-08 03:07:19 +00:00
|
|
|
|
2013-10-11 16:10:32 +00:00
|
|
|
/* convert to pixel counts */
|
|
|
|
vbl_start *= htotal;
|
|
|
|
vbl_end *= htotal;
|
|
|
|
vtotal *= htotal;
|
2010-12-08 03:07:19 +00:00
|
|
|
}
|
|
|
|
|
2013-10-30 04:13:08 +00:00
|
|
|
/* Get optional system timestamp after query. */
|
|
|
|
if (etime)
|
|
|
|
*etime = ktime_get();
|
|
|
|
|
|
|
|
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
|
|
|
2013-10-11 16:10:32 +00:00
|
|
|
in_vbl = position >= vbl_start && position < vbl_end;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* While in vblank, position will be negative
|
|
|
|
* counting up towards 0 at vbl_end. And outside
|
|
|
|
* vblank, position will be positive counting
|
|
|
|
* up since vbl_end.
|
|
|
|
*/
|
|
|
|
if (position >= vbl_start)
|
|
|
|
position -= vbl_end;
|
|
|
|
else
|
|
|
|
position += vtotal - vbl_end;
|
2010-12-08 03:07:19 +00:00
|
|
|
|
2013-10-11 18:52:43 +00:00
|
|
|
if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
|
2013-10-11 16:10:32 +00:00
|
|
|
*vpos = position;
|
|
|
|
*hpos = 0;
|
|
|
|
} else {
|
|
|
|
*vpos = position / htotal;
|
|
|
|
*hpos = position - (*vpos * htotal);
|
|
|
|
}
|
2010-12-08 03:07:19 +00:00
|
|
|
|
|
|
|
/* In vblank? */
|
|
|
|
if (in_vbl)
|
|
|
|
ret |= DRM_SCANOUTPOS_INVBL;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
|
2010-12-08 03:07:19 +00:00
|
|
|
int *max_error,
|
|
|
|
struct timeval *vblank_time,
|
|
|
|
unsigned flags)
|
|
|
|
{
|
2011-01-22 10:07:56 +00:00
|
|
|
struct drm_crtc *crtc;
|
2010-12-08 03:07:19 +00:00
|
|
|
|
2013-03-13 21:05:41 +00:00
|
|
|
if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
|
2011-01-22 10:07:56 +00:00
|
|
|
DRM_ERROR("Invalid crtc %d\n", pipe);
|
2010-12-08 03:07:19 +00:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get drm_crtc to timestamp: */
|
2011-01-22 10:07:56 +00:00
|
|
|
crtc = intel_get_crtc_for_pipe(dev, pipe);
|
|
|
|
if (crtc == NULL) {
|
|
|
|
DRM_ERROR("Invalid crtc %d\n", pipe);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!crtc->enabled) {
|
|
|
|
DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2010-12-08 03:07:19 +00:00
|
|
|
|
|
|
|
/* Helper routine in DRM core does all the work: */
|
2011-01-22 10:07:56 +00:00
|
|
|
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
|
|
|
|
vblank_time, flags,
|
2013-10-26 14:57:31 +00:00
|
|
|
crtc,
|
|
|
|
&to_intel_crtc(crtc)->config.adjusted_mode);
|
2010-12-08 03:07:19 +00:00
|
|
|
}
|
|
|
|
|
2013-09-17 11:26:34 +00:00
|
|
|
static bool intel_hpd_irq_event(struct drm_device *dev,
|
|
|
|
struct drm_connector *connector)
|
2013-04-11 14:00:26 +00:00
|
|
|
{
|
|
|
|
enum drm_connector_status old_status;
|
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
|
|
|
|
old_status = connector->status;
|
|
|
|
|
|
|
|
connector->status = connector->funcs->detect(connector, false);
|
2013-09-17 11:26:34 +00:00
|
|
|
if (old_status == connector->status)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
|
2013-04-11 14:00:26 +00:00
|
|
|
connector->base.id,
|
|
|
|
drm_get_connector_name(connector),
|
2013-09-17 11:26:34 +00:00
|
|
|
drm_get_connector_status_name(old_status),
|
|
|
|
drm_get_connector_status_name(connector->status));
|
|
|
|
|
|
|
|
return true;
|
2013-04-11 14:00:26 +00:00
|
|
|
}
|
|
|
|
|
2009-03-31 21:11:15 +00:00
|
|
|
/*
|
|
|
|
* Handle hotplug events outside the interrupt handler proper.
|
|
|
|
*/
|
2013-04-16 11:36:58 +00:00
|
|
|
#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
|
|
|
|
|
2009-03-31 21:11:15 +00:00
|
|
|
static void i915_hotplug_work_func(struct work_struct *work)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, struct drm_i915_private, hotplug_work);
|
2009-03-31 21:11:15 +00:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2009-05-06 18:48:58 +00:00
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
2013-04-16 11:36:57 +00:00
|
|
|
struct intel_connector *intel_connector;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_connector *connector;
|
|
|
|
unsigned long irqflags;
|
|
|
|
bool hpd_disabled = false;
|
2013-04-11 14:00:26 +00:00
|
|
|
bool changed = false;
|
2013-04-11 13:57:57 +00:00
|
|
|
u32 hpd_event_bits;
|
2010-09-09 14:14:28 +00:00
|
|
|
|
2012-12-01 20:03:22 +00:00
|
|
|
/* HPD irq before everything is fully set up. */
|
|
|
|
if (!dev_priv->enable_hotplug_processing)
|
|
|
|
return;
|
|
|
|
|
2011-07-25 17:04:56 +00:00
|
|
|
mutex_lock(&mode_config->mutex);
|
2011-02-11 22:44:51 +00:00
|
|
|
DRM_DEBUG_KMS("running encoder hotplug functions\n");
|
|
|
|
|
2013-04-16 11:36:57 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-04-11 13:57:57 +00:00
|
|
|
|
|
|
|
hpd_event_bits = dev_priv->hpd_event_bits;
|
|
|
|
dev_priv->hpd_event_bits = 0;
|
2013-04-16 11:36:57 +00:00
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
intel_connector = to_intel_connector(connector);
|
|
|
|
intel_encoder = intel_connector->encoder;
|
|
|
|
if (intel_encoder->hpd_pin > HPD_NONE &&
|
|
|
|
dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
|
|
|
|
connector->polled == DRM_CONNECTOR_POLL_HPD) {
|
|
|
|
DRM_INFO("HPD interrupt storm detected on connector %s: "
|
|
|
|
"switching from hotplug detection to polling\n",
|
|
|
|
drm_get_connector_name(connector));
|
|
|
|
dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
|
|
|
|
connector->polled = DRM_CONNECTOR_POLL_CONNECT
|
|
|
|
| DRM_CONNECTOR_POLL_DISCONNECT;
|
|
|
|
hpd_disabled = true;
|
|
|
|
}
|
2013-04-11 13:57:57 +00:00
|
|
|
if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
|
|
|
|
DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
|
|
|
|
drm_get_connector_name(connector), intel_encoder->hpd_pin);
|
|
|
|
}
|
2013-04-16 11:36:57 +00:00
|
|
|
}
|
|
|
|
/* if there were no outputs to poll, poll was disabled,
|
|
|
|
* therefore make sure it's enabled when disabling HPD on
|
|
|
|
* some connectors */
|
2013-04-16 11:36:58 +00:00
|
|
|
if (hpd_disabled) {
|
2013-04-16 11:36:57 +00:00
|
|
|
drm_kms_helper_poll_enable(dev);
|
2013-04-16 11:36:58 +00:00
|
|
|
mod_timer(&dev_priv->hotplug_reenable_timer,
|
|
|
|
jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
|
|
|
|
}
|
2013-04-16 11:36:57 +00:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
2013-04-11 14:00:26 +00:00
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
intel_connector = to_intel_connector(connector);
|
|
|
|
intel_encoder = intel_connector->encoder;
|
|
|
|
if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
|
|
|
|
if (intel_encoder->hot_plug)
|
|
|
|
intel_encoder->hot_plug(intel_encoder);
|
|
|
|
if (intel_hpd_irq_event(dev, connector))
|
|
|
|
changed = true;
|
|
|
|
}
|
|
|
|
}
|
2011-07-28 22:31:19 +00:00
|
|
|
mutex_unlock(&mode_config->mutex);
|
|
|
|
|
2013-04-11 14:00:26 +00:00
|
|
|
if (changed)
|
|
|
|
drm_kms_helper_hotplug_event(dev);
|
2009-03-31 21:11:15 +00:00
|
|
|
}
|
|
|
|
|
2014-01-17 11:43:51 +00:00
|
|
|
static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
del_timer_sync(&dev_priv->hotplug_reenable_timer);
|
|
|
|
}
|
|
|
|
|
2013-07-04 21:35:25 +00:00
|
|
|
static void ironlake_rps_change_irq_handler(struct drm_device *dev)
|
2010-01-29 19:27:07 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-02-02 18:30:47 +00:00
|
|
|
u32 busy_up, busy_down, max_avg, min_avg;
|
2012-08-09 14:46:01 +00:00
|
|
|
u8 new_delay;
|
|
|
|
|
2013-07-04 21:35:25 +00:00
|
|
|
spin_lock(&mchdev_lock);
|
2010-01-29 19:27:07 +00:00
|
|
|
|
2012-08-08 21:35:37 +00:00
|
|
|
I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
|
|
|
|
|
2012-08-08 21:35:39 +00:00
|
|
|
new_delay = dev_priv->ips.cur_delay;
|
2012-08-09 14:46:01 +00:00
|
|
|
|
2010-05-20 21:28:11 +00:00
|
|
|
I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
|
2010-02-02 18:30:47 +00:00
|
|
|
busy_up = I915_READ(RCPREVBSYTUPAVG);
|
|
|
|
busy_down = I915_READ(RCPREVBSYTDNAVG);
|
2010-01-29 19:27:07 +00:00
|
|
|
max_avg = I915_READ(RCBMAXAVG);
|
|
|
|
min_avg = I915_READ(RCBMINAVG);
|
|
|
|
|
|
|
|
/* Handle RCS change request from hw */
|
2010-02-02 18:30:47 +00:00
|
|
|
if (busy_up > max_avg) {
|
2012-08-08 21:35:39 +00:00
|
|
|
if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
|
|
|
|
new_delay = dev_priv->ips.cur_delay - 1;
|
|
|
|
if (new_delay < dev_priv->ips.max_delay)
|
|
|
|
new_delay = dev_priv->ips.max_delay;
|
2010-02-02 18:30:47 +00:00
|
|
|
} else if (busy_down < min_avg) {
|
2012-08-08 21:35:39 +00:00
|
|
|
if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
|
|
|
|
new_delay = dev_priv->ips.cur_delay + 1;
|
|
|
|
if (new_delay > dev_priv->ips.min_delay)
|
|
|
|
new_delay = dev_priv->ips.min_delay;
|
2010-01-29 19:27:07 +00:00
|
|
|
}
|
|
|
|
|
2010-05-20 21:28:11 +00:00
|
|
|
if (ironlake_set_drps(dev, new_delay))
|
2012-08-08 21:35:39 +00:00
|
|
|
dev_priv->ips.cur_delay = new_delay;
|
2010-01-29 19:27:07 +00:00
|
|
|
|
2013-07-04 21:35:25 +00:00
|
|
|
spin_unlock(&mchdev_lock);
|
2012-08-09 14:46:01 +00:00
|
|
|
|
2010-01-29 19:27:07 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-10-19 10:19:32 +00:00
|
|
|
static void notify_ring(struct drm_device *dev,
|
|
|
|
struct intel_ring_buffer *ring)
|
|
|
|
{
|
2011-01-20 09:52:56 +00:00
|
|
|
if (ring->obj == NULL)
|
|
|
|
return;
|
|
|
|
|
2013-09-23 20:33:19 +00:00
|
|
|
trace_i915_gem_request_complete(ring);
|
2011-01-04 22:22:17 +00:00
|
|
|
|
2010-10-19 10:19:32 +00:00
|
|
|
wake_up_all(&ring->irq_queue);
|
2013-07-03 14:22:08 +00:00
|
|
|
i915_queue_hangcheck(dev);
|
2010-10-19 10:19:32 +00:00
|
|
|
}
|
|
|
|
|
2011-04-25 18:25:20 +00:00
|
|
|
static void gen6_pm_rps_work(struct work_struct *work)
|
2010-12-17 22:19:02 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, struct drm_i915_private, rps.work);
|
2013-08-06 21:57:13 +00:00
|
|
|
u32 pm_iir;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
int new_delay, adj;
|
2011-04-25 18:25:20 +00:00
|
|
|
|
2013-07-04 21:35:28 +00:00
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
2012-08-08 21:35:35 +00:00
|
|
|
pm_iir = dev_priv->rps.pm_iir;
|
|
|
|
dev_priv->rps.pm_iir = 0;
|
2013-05-29 02:22:27 +00:00
|
|
|
/* Make sure not to corrupt PMIMR state used by ringbuffer code */
|
2014-03-15 14:53:22 +00:00
|
|
|
snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
|
2013-07-04 21:35:28 +00:00
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
2010-12-17 22:19:02 +00:00
|
|
|
|
2013-08-15 14:50:01 +00:00
|
|
|
/* Make sure we didn't queue anything we're not going to process. */
|
2014-03-15 14:53:22 +00:00
|
|
|
WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
|
2013-08-15 14:50:01 +00:00
|
|
|
|
2014-03-15 14:53:22 +00:00
|
|
|
if ((pm_iir & dev_priv->pm_rps_events) == 0)
|
2010-12-17 22:19:02 +00:00
|
|
|
return;
|
|
|
|
|
2012-11-02 18:14:01 +00:00
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
2012-04-28 07:56:39 +00:00
|
|
|
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
adj = dev_priv->rps.last_adj;
|
2013-06-25 18:38:11 +00:00
|
|
|
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
if (adj > 0)
|
|
|
|
adj *= 2;
|
|
|
|
else
|
|
|
|
adj = 1;
|
2014-03-20 01:31:11 +00:00
|
|
|
new_delay = dev_priv->rps.cur_freq + adj;
|
2013-06-25 18:38:11 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For better performance, jump directly
|
|
|
|
* to RPe if we're below it.
|
|
|
|
*/
|
2014-03-20 01:31:11 +00:00
|
|
|
if (new_delay < dev_priv->rps.efficient_freq)
|
|
|
|
new_delay = dev_priv->rps.efficient_freq;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
} else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
|
2014-03-20 01:31:11 +00:00
|
|
|
if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
|
|
|
|
new_delay = dev_priv->rps.efficient_freq;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
else
|
2014-03-20 01:31:11 +00:00
|
|
|
new_delay = dev_priv->rps.min_freq_softlimit;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
adj = 0;
|
|
|
|
} else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
|
|
|
|
if (adj < 0)
|
|
|
|
adj *= 2;
|
|
|
|
else
|
|
|
|
adj = -1;
|
2014-03-20 01:31:11 +00:00
|
|
|
new_delay = dev_priv->rps.cur_freq + adj;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
} else { /* unknown event */
|
2014-03-20 01:31:11 +00:00
|
|
|
new_delay = dev_priv->rps.cur_freq;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
}
|
2010-12-17 22:19:02 +00:00
|
|
|
|
2012-09-08 02:43:42 +00:00
|
|
|
/* sysfs frequency interfaces may have snuck in while servicing the
|
|
|
|
* interrupt
|
|
|
|
*/
|
2013-11-07 17:57:49 +00:00
|
|
|
new_delay = clamp_t(int, new_delay,
|
2014-03-20 01:31:11 +00:00
|
|
|
dev_priv->rps.min_freq_softlimit,
|
|
|
|
dev_priv->rps.max_freq_softlimit);
|
2014-01-27 16:05:05 +00:00
|
|
|
|
2014-03-20 01:31:11 +00:00
|
|
|
dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
|
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms period before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power. It is easy to observe that we currently lock into the wrong bin
and both underperform in benchmarks and consume more power than optimal
(just by repeating the task and measuring the different results).
An alternative approach, as discussed in the bspec, is to use a
continuous threshold for upclocking, and an average value for downclocking.
This is good for quickly detecting and reacting to state changes within a
frame, however it fails with the common throttling method of waiting
upon the outstanding frame - at least it is difficult to choose a
threshold that works well at 15,000fps and at 60fps. So continue to use
average busy/idle loads to determine frequency change.
v2: Use 3 power zones to keep frequencies low in steady-state mostly
idle (e.g. scrolling, interactive 2D drawing), and frequencies high
for demanding games. In between those end-states, we use a
fast-reclocking algorithm to converge more quickly on the desired bin.
v3: Bug fixes - make sure we reset adj after switching power zones.
v4: Tune - drop the continuous busy thresholds as it prevents us from
choosing the right frequency for glxgears style swap benchmarks. Instead
the goal is to be able to find the right clocks irrespective of the
wait-boost.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin@gmail.com>
Cc: Owen Taylor <otaylor@redhat.com>
Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Cc: "Zhuang, Lena" <lena.zhuang@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-09-25 16:34:57 +00:00
|
|
|
|
|
|
|
if (IS_VALLEYVIEW(dev_priv->dev))
|
|
|
|
valleyview_set_rps(dev_priv->dev, new_delay);
|
|
|
|
else
|
|
|
|
gen6_set_rps(dev_priv->dev, new_delay);
|
2010-12-17 22:19:02 +00:00
|
|
|
|
2012-11-02 18:14:01 +00:00
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
2010-12-17 22:19:02 +00:00
|
|
|
}
|
|
|
|
|
2012-05-25 23:56:22 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* ivybridge_parity_work - Workqueue called when a parity error interrupt
|
|
|
|
* occurred.
|
|
|
|
* @work: workqueue struct
|
|
|
|
*
|
|
|
|
* Doesn't actually do anything except notify userspace. As a consequence of
|
|
|
|
* this event, userspace should try to remap the bad rows since statistically
|
|
|
|
* it is likely the same row is more likely to go bad again.
|
|
|
|
*/
|
|
|
|
static void ivybridge_parity_work(struct work_struct *work)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, struct drm_i915_private, l3_parity.error_work);
|
2012-05-25 23:56:22 +00:00
|
|
|
u32 error_status, row, bank, subbank;
|
2013-09-19 18:13:41 +00:00
|
|
|
char *parity_event[6];
|
2012-05-25 23:56:22 +00:00
|
|
|
uint32_t misccpctl;
|
|
|
|
unsigned long flags;
|
2013-09-19 18:13:41 +00:00
|
|
|
uint8_t slice = 0;
|
2012-05-25 23:56:22 +00:00
|
|
|
|
|
|
|
/* We must turn off DOP level clock gating to access the L3 registers.
|
|
|
|
* In order to prevent a get/put style interface, acquire struct mutex
|
|
|
|
* any time we access those registers.
|
|
|
|
*/
|
|
|
|
mutex_lock(&dev_priv->dev->struct_mutex);
|
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
/* If we've screwed up tracking, just let the interrupt fire again */
|
|
|
|
if (WARN_ON(!dev_priv->l3_parity.which_slice))
|
|
|
|
goto out;
|
|
|
|
|
2012-05-25 23:56:22 +00:00
|
|
|
misccpctl = I915_READ(GEN7_MISCCPCTL);
|
|
|
|
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
|
|
|
|
POSTING_READ(GEN7_MISCCPCTL);
|
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
|
|
|
|
u32 reg;
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
slice--;
|
|
|
|
if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
|
|
|
|
break;
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
dev_priv->l3_parity.which_slice &= ~(1<<slice);
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
reg = GEN7_L3CDERRST1 + (slice * 0x200);
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
error_status = I915_READ(reg);
|
|
|
|
row = GEN7_PARITY_ERROR_ROW(error_status);
|
|
|
|
bank = GEN7_PARITY_ERROR_BANK(error_status);
|
|
|
|
subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
|
|
|
|
|
|
|
|
I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
|
|
|
|
parity_event[0] = I915_L3_PARITY_UEVENT "=1";
|
|
|
|
parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
|
|
|
|
parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
|
|
|
|
parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
|
|
|
|
parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
|
|
|
|
parity_event[5] = NULL;
|
|
|
|
|
2013-10-11 04:07:25 +00:00
|
|
|
kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
|
2013-09-19 18:13:41 +00:00
|
|
|
KOBJ_CHANGE, parity_event);
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
|
|
|
|
slice, row, bank, subbank);
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
kfree(parity_event[4]);
|
|
|
|
kfree(parity_event[3]);
|
|
|
|
kfree(parity_event[2]);
|
|
|
|
kfree(parity_event[1]);
|
|
|
|
}
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
out:
|
|
|
|
WARN_ON(dev_priv->l3_parity.which_slice);
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
|
|
|
ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->dev->struct_mutex);
|
2012-05-25 23:56:22 +00:00
|
|
|
}
|
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
|
2012-05-25 23:56:22 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:01:40 +00:00
|
|
|
if (!HAS_L3_DPF(dev))
|
2012-05-25 23:56:22 +00:00
|
|
|
return;
|
|
|
|
|
2013-07-04 21:35:25 +00:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2013-09-19 18:13:41 +00:00
|
|
|
ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
|
2013-07-04 21:35:25 +00:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
iir &= GT_PARITY_ERROR(dev);
|
|
|
|
if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
|
|
|
|
dev_priv->l3_parity.which_slice |= 1 << 1;
|
|
|
|
|
|
|
|
if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
|
|
|
|
dev_priv->l3_parity.which_slice |= 1 << 0;
|
|
|
|
|
2012-11-02 18:55:07 +00:00
|
|
|
queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
|
2012-05-25 23:56:22 +00:00
|
|
|
}
|
|
|
|
|
2013-07-12 22:56:30 +00:00
|
|
|
static void ilk_gt_irq_handler(struct drm_device *dev,
|
|
|
|
struct drm_i915_private *dev_priv,
|
|
|
|
u32 gt_iir)
|
|
|
|
{
|
|
|
|
if (gt_iir &
|
|
|
|
(GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
|
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
|
|
|
if (gt_iir & ILK_BSD_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[VCS]);
|
|
|
|
}
|
|
|
|
|
2012-03-30 18:24:35 +00:00
|
|
|
static void snb_gt_irq_handler(struct drm_device *dev,
|
|
|
|
struct drm_i915_private *dev_priv,
|
|
|
|
u32 gt_iir)
|
|
|
|
{
|
|
|
|
|
2013-05-29 02:22:29 +00:00
|
|
|
if (gt_iir &
|
|
|
|
(GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
|
2012-03-30 18:24:35 +00:00
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
2013-05-29 02:22:29 +00:00
|
|
|
if (gt_iir & GT_BSD_USER_INTERRUPT)
|
2012-03-30 18:24:35 +00:00
|
|
|
notify_ring(dev, &dev_priv->ring[VCS]);
|
2013-05-29 02:22:29 +00:00
|
|
|
if (gt_iir & GT_BLT_USER_INTERRUPT)
|
2012-03-30 18:24:35 +00:00
|
|
|
notify_ring(dev, &dev_priv->ring[BCS]);
|
|
|
|
|
2013-05-29 02:22:29 +00:00
|
|
|
if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
|
|
|
|
GT_BSD_CS_ERROR_INTERRUPT |
|
|
|
|
GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
|
2014-02-25 15:11:26 +00:00
|
|
|
i915_handle_error(dev, false, "GT error interrupt 0x%08x",
|
|
|
|
gt_iir);
|
2012-03-30 18:24:35 +00:00
|
|
|
}
|
2012-05-25 23:56:22 +00:00
|
|
|
|
2013-09-19 18:13:41 +00:00
|
|
|
if (gt_iir & GT_PARITY_ERROR(dev))
|
|
|
|
ivybridge_parity_error_irq_handler(dev, gt_iir);
|
2012-03-30 18:24:35 +00:00
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
|
|
|
|
struct drm_i915_private *dev_priv,
|
|
|
|
u32 master_ctl)
|
|
|
|
{
|
|
|
|
u32 rcs, bcs, vcs;
|
|
|
|
uint32_t tmp = 0;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
|
|
|
if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
|
|
|
|
tmp = I915_READ(GEN8_GT_IIR(0));
|
|
|
|
if (tmp) {
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
|
|
|
|
bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
|
|
|
|
if (rcs & GT_RENDER_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
|
|
|
if (bcs & GT_RENDER_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[BCS]);
|
|
|
|
I915_WRITE(GEN8_GT_IIR(0), tmp);
|
|
|
|
} else
|
|
|
|
DRM_ERROR("The master control interrupt lied (GT0)!\n");
|
|
|
|
}
|
|
|
|
|
2014-04-17 02:37:38 +00:00
|
|
|
if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
tmp = I915_READ(GEN8_GT_IIR(1));
|
|
|
|
if (tmp) {
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
|
|
|
|
if (vcs & GT_RENDER_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[VCS]);
|
2014-04-17 02:37:38 +00:00
|
|
|
vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
|
|
|
|
if (vcs & GT_RENDER_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[VCS2]);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
I915_WRITE(GEN8_GT_IIR(1), tmp);
|
|
|
|
} else
|
|
|
|
DRM_ERROR("The master control interrupt lied (GT1)!\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (master_ctl & GEN8_GT_VECS_IRQ) {
|
|
|
|
tmp = I915_READ(GEN8_GT_IIR(3));
|
|
|
|
if (tmp) {
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
|
|
|
|
if (vcs & GT_RENDER_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[VECS]);
|
|
|
|
I915_WRITE(GEN8_GT_IIR(3), tmp);
|
|
|
|
} else
|
|
|
|
DRM_ERROR("The master control interrupt lied (GT3)!\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-04-16 11:36:54 +00:00
|
|
|
#define HPD_STORM_DETECT_PERIOD 1000
|
|
|
|
#define HPD_STORM_THRESHOLD 5
|
|
|
|
|
2013-06-27 15:52:12 +00:00
|
|
|
static inline void intel_hpd_irq_handler(struct drm_device *dev,
|
2013-06-27 15:52:11 +00:00
|
|
|
u32 hotplug_trigger,
|
|
|
|
const u32 *hpd)
|
2013-04-16 11:36:54 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-04-16 11:36:54 +00:00
|
|
|
int i;
|
2013-06-27 15:52:12 +00:00
|
|
|
bool storm_detected = false;
|
2013-04-16 11:36:54 +00:00
|
|
|
|
2013-06-27 15:52:14 +00:00
|
|
|
if (!hotplug_trigger)
|
|
|
|
return;
|
|
|
|
|
2014-01-16 17:56:54 +00:00
|
|
|
DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
|
|
|
|
hotplug_trigger);
|
|
|
|
|
2013-06-27 15:52:15 +00:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2013-04-16 11:36:54 +00:00
|
|
|
for (i = 1; i < HPD_NUM_PINS; i++) {
|
2013-04-16 11:36:55 +00:00
|
|
|
|
2014-04-24 10:03:17 +00:00
|
|
|
if (hpd[i] & hotplug_trigger &&
|
|
|
|
dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
|
|
|
|
/*
|
|
|
|
* On GMCH platforms the interrupt mask bits only
|
|
|
|
* prevent irq generation, not the setting of the
|
|
|
|
* hotplug bits itself. So only WARN about unexpected
|
|
|
|
* interrupts on saner platforms.
|
|
|
|
*/
|
|
|
|
WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
|
|
|
|
"Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
|
|
|
|
hotplug_trigger, i, hpd[i]);
|
|
|
|
|
|
|
|
continue;
|
|
|
|
}
|
2013-07-26 12:14:24 +00:00
|
|
|
|
2013-04-16 11:36:54 +00:00
|
|
|
if (!(hpd[i] & hotplug_trigger) ||
|
|
|
|
dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
|
|
|
|
continue;
|
|
|
|
|
2013-05-07 12:10:29 +00:00
|
|
|
dev_priv->hpd_event_bits |= (1 << i);
|
2013-04-16 11:36:54 +00:00
|
|
|
if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
|
|
|
|
dev_priv->hpd_stats[i].hpd_last_jiffies
|
|
|
|
+ msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
|
|
|
|
dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
|
|
|
|
dev_priv->hpd_stats[i].hpd_cnt = 0;
|
2013-07-26 12:14:24 +00:00
|
|
|
DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
|
2013-04-16 11:36:54 +00:00
|
|
|
} else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
|
|
|
|
dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
|
2013-04-11 13:57:57 +00:00
|
|
|
dev_priv->hpd_event_bits &= ~(1 << i);
|
2013-04-16 11:36:54 +00:00
|
|
|
DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
|
2013-06-27 15:52:12 +00:00
|
|
|
storm_detected = true;
|
2013-04-16 11:36:54 +00:00
|
|
|
} else {
|
|
|
|
dev_priv->hpd_stats[i].hpd_cnt++;
|
2013-07-26 12:14:24 +00:00
|
|
|
DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
|
|
|
|
dev_priv->hpd_stats[i].hpd_cnt);
|
2013-04-16 11:36:54 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-27 15:52:12 +00:00
|
|
|
if (storm_detected)
|
|
|
|
dev_priv->display.hpd_irq_setup(dev);
|
2013-06-27 15:52:15 +00:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2013-06-27 15:52:13 +00:00
|
|
|
|
2013-09-02 14:22:25 +00:00
|
|
|
/*
|
|
|
|
* Our hotplug handler can grab modeset locks (by calling down into the
|
|
|
|
* fb helpers). Hence it must not be run on our own dev-priv->wq work
|
|
|
|
* queue for otherwise the flush_work in the pageflip code will
|
|
|
|
* deadlock.
|
|
|
|
*/
|
|
|
|
schedule_work(&dev_priv->hotplug_work);
|
2013-04-16 11:36:54 +00:00
|
|
|
}
|
|
|
|
|
2012-12-01 12:53:44 +00:00
|
|
|
static void gmbus_irq_handler(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-12-01 12:53:45 +00:00
|
|
|
|
|
|
|
wake_up_all(&dev_priv->gmbus_wait_queue);
|
2012-12-01 12:53:44 +00:00
|
|
|
}
|
|
|
|
|
2012-12-01 12:53:47 +00:00
|
|
|
static void dp_aux_irq_handler(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 12:53:48 +00:00
|
|
|
|
|
|
|
wake_up_all(&dev_priv->gmbus_wait_queue);
|
2012-12-01 12:53:47 +00:00
|
|
|
}
|
|
|
|
|
2013-10-15 17:55:27 +00:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
2013-10-18 14:37:07 +00:00
|
|
|
static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
|
|
|
|
uint32_t crc0, uint32_t crc1,
|
|
|
|
uint32_t crc2, uint32_t crc3,
|
|
|
|
uint32_t crc4)
|
2013-10-15 17:55:27 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
|
|
|
|
struct intel_pipe_crc_entry *entry;
|
2013-10-15 17:55:30 +00:00
|
|
|
int head, tail;
|
2013-10-15 17:55:29 +00:00
|
|
|
|
2013-10-21 13:29:30 +00:00
|
|
|
spin_lock(&pipe_crc->lock);
|
|
|
|
|
2013-10-15 17:55:37 +00:00
|
|
|
if (!pipe_crc->entries) {
|
2013-10-21 13:29:30 +00:00
|
|
|
spin_unlock(&pipe_crc->lock);
|
2013-10-15 17:55:37 +00:00
|
|
|
DRM_ERROR("spurious interrupt\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-10-21 13:29:30 +00:00
|
|
|
head = pipe_crc->head;
|
|
|
|
tail = pipe_crc->tail;
|
2013-10-15 17:55:29 +00:00
|
|
|
|
|
|
|
if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
|
2013-10-21 13:29:30 +00:00
|
|
|
spin_unlock(&pipe_crc->lock);
|
2013-10-15 17:55:29 +00:00
|
|
|
DRM_ERROR("CRC buffer overflowing\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
entry = &pipe_crc->entries[head];
|
2013-10-15 17:55:27 +00:00
|
|
|
|
2013-10-16 20:55:49 +00:00
|
|
|
entry->frame = dev->driver->get_vblank_counter(dev, pipe);
|
2013-10-16 20:55:46 +00:00
|
|
|
entry->crc[0] = crc0;
|
|
|
|
entry->crc[1] = crc1;
|
|
|
|
entry->crc[2] = crc2;
|
|
|
|
entry->crc[3] = crc3;
|
|
|
|
entry->crc[4] = crc4;
|
2013-10-15 17:55:29 +00:00
|
|
|
|
|
|
|
head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
|
2013-10-21 13:29:30 +00:00
|
|
|
pipe_crc->head = head;
|
|
|
|
|
|
|
|
spin_unlock(&pipe_crc->lock);
|
2013-10-15 17:55:40 +00:00
|
|
|
|
|
|
|
wake_up_interruptible(&pipe_crc->wq);
|
2013-10-15 17:55:27 +00:00
|
|
|
}
|
2013-10-18 14:37:07 +00:00
|
|
|
#else
|
|
|
|
static inline void
|
|
|
|
display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
|
|
|
|
uint32_t crc0, uint32_t crc1,
|
|
|
|
uint32_t crc2, uint32_t crc3,
|
|
|
|
uint32_t crc4) {}
|
|
|
|
#endif
|
|
|
|
|
2013-10-16 20:55:46 +00:00
|
|
|
|
2013-10-18 14:37:07 +00:00
|
|
|
static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
|
2013-10-16 20:55:52 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-10-18 14:37:07 +00:00
|
|
|
display_pipe_crc_irq_handler(dev, pipe,
|
|
|
|
I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
|
|
|
|
0, 0, 0, 0);
|
2013-10-16 20:55:52 +00:00
|
|
|
}
|
|
|
|
|
2013-10-18 14:37:07 +00:00
|
|
|
static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
|
2013-10-16 20:55:46 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-10-18 14:37:07 +00:00
|
|
|
display_pipe_crc_irq_handler(dev, pipe,
|
|
|
|
I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
|
2013-10-16 20:55:46 +00:00
|
|
|
}
|
2013-10-16 20:55:48 +00:00
|
|
|
|
2013-10-18 14:37:07 +00:00
|
|
|
static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
|
2013-10-16 20:55:48 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-10-16 20:55:53 +00:00
|
|
|
uint32_t res1, res2;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 3)
|
|
|
|
res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
|
|
|
|
else
|
|
|
|
res1 = 0;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
|
|
|
|
res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
|
|
|
|
else
|
|
|
|
res2 = 0;
|
2013-10-16 20:55:48 +00:00
|
|
|
|
2013-10-18 14:37:07 +00:00
|
|
|
display_pipe_crc_irq_handler(dev, pipe,
|
|
|
|
I915_READ(PIPE_CRC_RES_RED(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_GREEN(pipe)),
|
|
|
|
I915_READ(PIPE_CRC_RES_BLUE(pipe)),
|
|
|
|
res1, res2);
|
2013-10-16 20:55:48 +00:00
|
|
|
}
|
2013-10-15 17:55:27 +00:00
|
|
|
|
2013-08-15 14:51:32 +00:00
|
|
|
/* The RPS events need forcewake, so we add them to a work queue and mask their
|
|
|
|
* IMR bits until the work is done. Other interrupts can be processed without
|
|
|
|
* the work queue. */
|
|
|
|
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
|
2013-05-29 02:22:24 +00:00
|
|
|
{
|
2014-03-15 14:53:22 +00:00
|
|
|
if (pm_iir & dev_priv->pm_rps_events) {
|
2013-07-04 21:35:28 +00:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2014-03-15 14:53:22 +00:00
|
|
|
dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
|
|
|
|
snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
|
2013-07-04 21:35:28 +00:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2013-07-04 21:35:27 +00:00
|
|
|
|
|
|
|
queue_work(dev_priv->wq, &dev_priv->rps.work);
|
2013-05-29 02:22:24 +00:00
|
|
|
}
|
|
|
|
|
2013-08-15 14:51:32 +00:00
|
|
|
if (HAS_VEBOX(dev_priv->dev)) {
|
|
|
|
if (pm_iir & PM_VEBOX_USER_INTERRUPT)
|
|
|
|
notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
|
2013-05-29 02:22:31 +00:00
|
|
|
|
2013-08-15 14:51:32 +00:00
|
|
|
if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
|
2014-02-25 15:11:26 +00:00
|
|
|
i915_handle_error(dev_priv->dev, false,
|
|
|
|
"VEBOX CS error interrupt 0x%08x",
|
|
|
|
pm_iir);
|
2013-08-15 14:51:32 +00:00
|
|
|
}
|
2013-05-29 02:22:31 +00:00
|
|
|
}
|
2013-05-29 02:22:24 +00:00
|
|
|
}
|
|
|
|
|
2014-02-04 19:35:46 +00:00
|
|
|
static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-02-10 16:42:49 +00:00
|
|
|
u32 pipe_stats[I915_MAX_PIPES] = { };
|
2014-02-04 19:35:46 +00:00
|
|
|
int pipe;
|
|
|
|
|
2014-02-04 19:35:47 +00:00
|
|
|
spin_lock(&dev_priv->irq_lock);
|
2014-02-04 19:35:46 +00:00
|
|
|
for_each_pipe(pipe) {
|
2014-02-10 16:42:49 +00:00
|
|
|
int reg;
|
2014-02-12 16:55:36 +00:00
|
|
|
u32 mask, iir_bit = 0;
|
2014-02-10 16:42:49 +00:00
|
|
|
|
2014-02-12 16:55:36 +00:00
|
|
|
/*
|
|
|
|
* PIPESTAT bits get signalled even when the interrupt is
|
|
|
|
* disabled with the mask bits, and some of the status bits do
|
|
|
|
* not generate interrupts at all (like the underrun bit). Hence
|
|
|
|
* we need to be careful that we only handle what we want to
|
|
|
|
* handle.
|
|
|
|
*/
|
|
|
|
mask = 0;
|
|
|
|
if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
|
|
|
|
mask |= PIPE_FIFO_UNDERRUN_STATUS;
|
|
|
|
|
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
|
|
|
iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
|
|
|
|
break;
|
|
|
|
case PIPE_B:
|
|
|
|
iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (iir & iir_bit)
|
|
|
|
mask |= dev_priv->pipestat_irq_mask[pipe];
|
|
|
|
|
|
|
|
if (!mask)
|
2014-02-10 16:42:49 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
reg = PIPESTAT(pipe);
|
2014-02-12 16:55:36 +00:00
|
|
|
mask |= PIPESTAT_INT_ENABLE_MASK;
|
|
|
|
pipe_stats[pipe] = I915_READ(reg) & mask;
|
2014-02-04 19:35:46 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the PIPE*STAT regs before the IIR
|
|
|
|
*/
|
2014-02-10 16:42:49 +00:00
|
|
|
if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
|
|
|
|
PIPESTAT_INT_STATUS_MASK))
|
2014-02-04 19:35:46 +00:00
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
|
|
|
}
|
2014-02-04 19:35:47 +00:00
|
|
|
spin_unlock(&dev_priv->irq_lock);
|
2014-02-04 19:35:46 +00:00
|
|
|
|
|
|
|
for_each_pipe(pipe) {
|
|
|
|
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
|
|
|
|
drm_handle_vblank(dev, pipe);
|
|
|
|
|
2014-02-04 19:35:48 +00:00
|
|
|
if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
|
2014-02-04 19:35:46 +00:00
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip(dev, pipe);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
|
|
|
|
intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
|
|
|
|
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
|
|
|
|
gmbus_irq_handler(dev);
|
|
|
|
}
|
|
|
|
|
2014-04-01 07:54:36 +00:00
|
|
|
static void i9xx_hpd_irq_handler(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
|
|
|
|
|
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
|
|
|
|
|
|
|
|
intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
|
|
|
|
} else {
|
|
|
|
u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
|
|
|
|
|
|
|
|
intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
|
|
|
|
hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
|
|
|
|
/*
|
|
|
|
* Make sure hotplug status is cleared before we clear IIR, or else we
|
|
|
|
* may miss hotplug events.
|
|
|
|
*/
|
|
|
|
POSTING_READ(PORT_HOTPLUG_STAT);
|
|
|
|
}
|
|
|
|
|
2012-10-02 13:10:55 +00:00
|
|
|
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
|
2012-03-28 20:39:38 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-28 20:39:38 +00:00
|
|
|
u32 iir, gt_iir, pm_iir;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
|
|
|
while (true) {
|
|
|
|
iir = I915_READ(VLV_IIR);
|
|
|
|
gt_iir = I915_READ(GTIIR);
|
|
|
|
pm_iir = I915_READ(GEN6_PMIIR);
|
|
|
|
|
|
|
|
if (gt_iir == 0 && pm_iir == 0 && iir == 0)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
2012-03-30 18:24:35 +00:00
|
|
|
snb_gt_irq_handler(dev, dev_priv, gt_iir);
|
2012-03-28 20:39:38 +00:00
|
|
|
|
2014-02-04 19:35:46 +00:00
|
|
|
valleyview_pipestat_irq_handler(dev, iir);
|
2012-06-20 17:53:11 +00:00
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
/* Consume port. Then clear IIR or we'll miss events */
|
2014-04-01 07:54:36 +00:00
|
|
|
if (iir & I915_DISPLAY_PORT_INTERRUPT)
|
|
|
|
i9xx_hpd_irq_handler(dev);
|
2012-03-28 20:39:38 +00:00
|
|
|
|
2013-08-15 14:50:01 +00:00
|
|
|
if (pm_iir)
|
2013-07-04 21:35:25 +00:00
|
|
|
gen6_rps_irq_handler(dev_priv, pm_iir);
|
2012-03-28 20:39:38 +00:00
|
|
|
|
|
|
|
I915_WRITE(GTIIR, gt_iir);
|
|
|
|
I915_WRITE(GEN6_PMIIR, pm_iir);
|
|
|
|
I915_WRITE(VLV_IIR, iir);
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-06-06 19:45:44 +00:00
|
|
|
static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
|
2011-01-04 23:09:39 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-02-07 20:26:52 +00:00
|
|
|
int pipe;
|
2013-04-16 11:36:54 +00:00
|
|
|
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
|
2011-01-04 23:09:39 +00:00
|
|
|
|
2013-06-27 15:52:14 +00:00
|
|
|
intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
|
|
|
|
|
2013-04-17 14:48:48 +00:00
|
|
|
if (pch_iir & SDE_AUDIO_POWER_MASK) {
|
|
|
|
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
|
|
|
|
SDE_AUDIO_POWER_SHIFT);
|
2011-01-04 23:09:39 +00:00
|
|
|
DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
|
2013-04-17 14:48:48 +00:00
|
|
|
port_name(port));
|
|
|
|
}
|
2011-01-04 23:09:39 +00:00
|
|
|
|
2012-12-01 12:53:47 +00:00
|
|
|
if (pch_iir & SDE_AUX_MASK)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
|
2011-01-04 23:09:39 +00:00
|
|
|
if (pch_iir & SDE_GMBUS)
|
2012-12-01 12:53:44 +00:00
|
|
|
gmbus_irq_handler(dev);
|
2011-01-04 23:09:39 +00:00
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_HDCP_MASK)
|
|
|
|
DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_TRANS_MASK)
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_POISON)
|
|
|
|
DRM_ERROR("PCH poison interrupt\n");
|
|
|
|
|
2011-02-07 20:26:52 +00:00
|
|
|
if (pch_iir & SDE_FDI_MASK)
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(FDI_RX_IIR(pipe)));
|
2011-01-04 23:09:39 +00:00
|
|
|
|
|
|
|
if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
|
|
|
|
DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
|
|
|
|
false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("PCH transcoder A FIFO underrun\n");
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
|
|
|
|
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
|
|
|
|
false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("PCH transcoder B FIFO underrun\n");
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ivb_err_int_handler(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 err_int = I915_READ(GEN7_ERR_INT);
|
2013-10-16 20:55:52 +00:00
|
|
|
enum pipe pipe;
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
2013-04-12 20:57:58 +00:00
|
|
|
if (err_int & ERR_INT_POISON)
|
|
|
|
DRM_ERROR("Poison interrupt\n");
|
|
|
|
|
2013-10-16 20:55:52 +00:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
|
|
|
|
if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
|
|
|
|
false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("Pipe %c FIFO underrun\n",
|
|
|
|
pipe_name(pipe));
|
2013-10-16 20:55:52 +00:00
|
|
|
}
|
2013-10-15 17:55:27 +00:00
|
|
|
|
2013-10-16 20:55:52 +00:00
|
|
|
if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
|
|
|
|
if (IS_IVYBRIDGE(dev))
|
2013-10-18 14:37:07 +00:00
|
|
|
ivb_pipe_crc_irq_handler(dev, pipe);
|
2013-10-16 20:55:52 +00:00
|
|
|
else
|
2013-10-18 14:37:07 +00:00
|
|
|
hsw_pipe_crc_irq_handler(dev, pipe);
|
2013-10-16 20:55:52 +00:00
|
|
|
}
|
|
|
|
}
|
2013-10-15 17:55:27 +00:00
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
I915_WRITE(GEN7_ERR_INT, err_int);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpt_serr_int_handler(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 serr_int = I915_READ(SERR_INT);
|
|
|
|
|
2013-04-12 20:57:58 +00:00
|
|
|
if (serr_int & SERR_INT_POISON)
|
|
|
|
DRM_ERROR("PCH poison interrupt\n");
|
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
|
|
|
|
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
|
|
|
|
false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("PCH transcoder A FIFO underrun\n");
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
|
|
|
|
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
|
|
|
|
false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("PCH transcoder B FIFO underrun\n");
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
|
|
|
|
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
|
|
|
|
false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("PCH transcoder C FIFO underrun\n");
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
I915_WRITE(SERR_INT, serr_int);
|
2011-01-04 23:09:39 +00:00
|
|
|
}
|
|
|
|
|
2012-06-06 19:45:44 +00:00
|
|
|
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-06-06 19:45:44 +00:00
|
|
|
int pipe;
|
2013-04-16 11:36:54 +00:00
|
|
|
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
|
2012-06-06 19:45:44 +00:00
|
|
|
|
2013-06-27 15:52:14 +00:00
|
|
|
intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
|
|
|
|
|
2013-04-17 14:48:48 +00:00
|
|
|
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
|
|
|
|
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
|
|
|
|
SDE_AUDIO_POWER_SHIFT_CPT);
|
|
|
|
DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
|
|
|
|
port_name(port));
|
|
|
|
}
|
2012-06-06 19:45:44 +00:00
|
|
|
|
|
|
|
if (pch_iir & SDE_AUX_MASK_CPT)
|
2012-12-01 12:53:47 +00:00
|
|
|
dp_aux_irq_handler(dev);
|
2012-06-06 19:45:44 +00:00
|
|
|
|
|
|
|
if (pch_iir & SDE_GMBUS_CPT)
|
2012-12-01 12:53:44 +00:00
|
|
|
gmbus_irq_handler(dev);
|
2012-06-06 19:45:44 +00:00
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
|
|
|
|
DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
|
|
|
|
DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
|
|
|
|
|
|
|
|
if (pch_iir & SDE_FDI_MASK_CPT)
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
|
|
|
|
pipe_name(pipe),
|
|
|
|
I915_READ(FDI_RX_IIR(pipe)));
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
if (pch_iir & SDE_ERROR_CPT)
|
|
|
|
cpt_serr_int_handler(dev);
|
2012-06-06 19:45:44 +00:00
|
|
|
}
|
|
|
|
|
2013-07-12 19:35:10 +00:00
|
|
|
static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-10-21 16:04:36 +00:00
|
|
|
enum pipe pipe;
|
2013-07-12 19:35:10 +00:00
|
|
|
|
|
|
|
if (de_iir & DE_AUX_CHANNEL_A)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_GSE)
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_POISON)
|
|
|
|
DRM_ERROR("Poison interrupt\n");
|
|
|
|
|
2013-10-21 16:04:36 +00:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
if (de_iir & DE_PIPE_VBLANK(pipe))
|
|
|
|
drm_handle_vblank(dev, pipe);
|
2013-10-16 20:55:48 +00:00
|
|
|
|
2013-10-21 16:04:36 +00:00
|
|
|
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
|
|
|
|
if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("Pipe %c FIFO underrun\n",
|
|
|
|
pipe_name(pipe));
|
2013-10-16 20:55:48 +00:00
|
|
|
|
2013-10-21 16:04:36 +00:00
|
|
|
if (de_iir & DE_PIPE_CRC_DONE(pipe))
|
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2013-07-12 19:35:10 +00:00
|
|
|
|
2013-10-21 16:04:36 +00:00
|
|
|
/* plane/pipes map 1:1 on ilk+ */
|
|
|
|
if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
|
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip_plane(dev, pipe);
|
|
|
|
}
|
2013-07-12 19:35:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* check event from PCH */
|
|
|
|
if (de_iir & DE_PCH_EVENT) {
|
|
|
|
u32 pch_iir = I915_READ(SDEIIR);
|
|
|
|
|
|
|
|
if (HAS_PCH_CPT(dev))
|
|
|
|
cpt_irq_handler(dev, pch_iir);
|
|
|
|
else
|
|
|
|
ibx_irq_handler(dev, pch_iir);
|
|
|
|
|
|
|
|
/* should clear PCH hotplug event before clear CPU irq */
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
|
|
|
|
ironlake_rps_change_irq_handler(dev);
|
|
|
|
}
|
|
|
|
|
2013-07-12 19:35:11 +00:00
|
|
|
static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-03-03 17:31:46 +00:00
|
|
|
enum pipe pipe;
|
2013-07-12 19:35:11 +00:00
|
|
|
|
|
|
|
if (de_iir & DE_ERR_INT_IVB)
|
|
|
|
ivb_err_int_handler(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_AUX_CHANNEL_A_IVB)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
|
|
|
|
if (de_iir & DE_GSE_IVB)
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
2014-03-03 17:31:46 +00:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
|
|
|
|
drm_handle_vblank(dev, pipe);
|
2013-10-21 16:04:36 +00:00
|
|
|
|
|
|
|
/* plane/pipes map 1:1 on ilk+ */
|
2014-03-03 17:31:46 +00:00
|
|
|
if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
|
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip_plane(dev, pipe);
|
2013-07-12 19:35:11 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check event from PCH */
|
|
|
|
if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
|
|
|
|
u32 pch_iir = I915_READ(SDEIIR);
|
|
|
|
|
|
|
|
cpt_irq_handler(dev, pch_iir);
|
|
|
|
|
|
|
|
/* clear PCH hotplug event before clear CPU irq */
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-12 22:56:30 +00:00
|
|
|
static irqreturn_t ironlake_irq_handler(int irq, void *arg)
|
2011-04-06 19:13:38 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-12 22:56:30 +00:00
|
|
|
u32 de_iir, gt_iir, de_ier, sde_ier = 0;
|
2012-05-09 20:45:44 +00:00
|
|
|
irqreturn_t ret = IRQ_NONE;
|
2011-04-06 19:13:38 +00:00
|
|
|
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
/* We get interrupts on unclaimed registers, so check for this before we
|
|
|
|
* do any I915_{READ,WRITE}. */
|
2013-07-19 19:36:52 +00:00
|
|
|
intel_uncore_check_errors(dev);
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
2011-04-06 19:13:38 +00:00
|
|
|
/* disable master interrupt before clearing iir */
|
|
|
|
de_ier = I915_READ(DEIER);
|
|
|
|
I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
|
2013-07-12 19:35:14 +00:00
|
|
|
POSTING_READ(DEIER);
|
2011-04-06 19:13:38 +00:00
|
|
|
|
drm/i915: also disable south interrupts when handling them
From the docs:
"IIR can queue up to two interrupt events. When the IIR is cleared,
it will set itself again after one clock if a second event was
stored."
"Only the rising edge of the PCH Display interrupt will cause the
North Display IIR (DEIIR) PCH Display Interrupt even bit to be set,
so all PCH Display Interrupts, including back to back interrupts,
must be cleared before a new PCH Display interrupt can cause DEIIR
to be set".
The current code works fine because we don't get many interrupts, but
if we enable the PCH FIFO underrun interrupts we'll start getting so
many interrupts that at some point new PCH interrupts won't cause
DEIIR to be set.
The initial implementation I tried was to turn the code that checks
SDEIIR into a loop, but we can still get interrupts even after the
loop is done (and before the irq handler finishes), so we have to
either disable the interrupts or mask them. In the end I concluded
that just disabling the PCH interrupts is enough, you don't even need
the loop, so this is what this patch implements. I've tested it and it
passes the 2 "PCH FIFO underrun interrupt storms" I can reproduce:
the "ironlake_crtc_disable" case and the "wrong watermarks" case.
In other words, here's how to reproduce the problem fixed by this
patch:
1 - Enable PCH FIFO underrun interrupts (SERR_INT on SNB+)
2 - Boot the machine
3 - While booting we'll get tons of PCH FIFO underrun interrupts
4 - Plug a new monitor
5 - Run xrandr, notice it won't detect the new monitor
6 - Read SDEIIR and notice it's not 0 while DEIIR is 0
Q: Can't we just clear DEIIR before SDEIIR?
A: It doesn't work. SDEIIR has to be completely cleared (including the
interrupts stored on its back queue) before it can flip DEIIR's bit to
1 again, and even while you're clearing it you'll be getting more and
more interrupts.
Q: Why does it work by just disabling+enabling the south interrupts?
A: Because when we re-enable them, if there's something on the SDEIIR
register (maybe an interrupt stored on the queue), the re-enabling
will make DEIIR's bit flip to 1, and since we'll already have
interrupts enabled we'll get another interrupt, then run our irq
handler again to process the "back" interrupts.
v2: Even bigger commit message, added code comments.
Note that this fixes missed dp aux irqs which have been reported for
3.9-rc1. This regression has been introduced by switching to
irq-driven dp aux transactions with
commit 9ee32fea5fe810ec06af3a15e4c65478de56d4f5
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat Dec 1 13:53:48 2012 +0100
drm/i915: irq-drive the dp aux communication
References: http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg18588.html
References: https://lkml.org/lkml/2013/2/26/769
Tested-by: Imre Deak <imre.deak@intel.com>
Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Pimp commit message with references for the dp aux irq
timeout regression this fixes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-22 20:05:28 +00:00
|
|
|
/* Disable south interrupts. We'll only write to SDEIIR once, so further
|
|
|
|
* interrupts will will be stored on its back queue, and then we'll be
|
|
|
|
* able to process them after we restore SDEIER (as soon as we restore
|
|
|
|
* it, we'll get an interrupt if SDEIIR still has something to process
|
|
|
|
* due to its back queue). */
|
2013-04-05 20:12:41 +00:00
|
|
|
if (!HAS_PCH_NOP(dev)) {
|
|
|
|
sde_ier = I915_READ(SDEIER);
|
|
|
|
I915_WRITE(SDEIER, 0);
|
|
|
|
POSTING_READ(SDEIER);
|
|
|
|
}
|
drm/i915: also disable south interrupts when handling them
From the docs:
"IIR can queue up to two interrupt events. When the IIR is cleared,
it will set itself again after one clock if a second event was
stored."
"Only the rising edge of the PCH Display interrupt will cause the
North Display IIR (DEIIR) PCH Display Interrupt even bit to be set,
so all PCH Display Interrupts, including back to back interrupts,
must be cleared before a new PCH Display interrupt can cause DEIIR
to be set".
The current code works fine because we don't get many interrupts, but
if we enable the PCH FIFO underrun interrupts we'll start getting so
many interrupts that at some point new PCH interrupts won't cause
DEIIR to be set.
The initial implementation I tried was to turn the code that checks
SDEIIR into a loop, but we can still get interrupts even after the
loop is done (and before the irq handler finishes), so we have to
either disable the interrupts or mask them. In the end I concluded
that just disabling the PCH interrupts is enough, you don't even need
the loop, so this is what this patch implements. I've tested it and it
passes the 2 "PCH FIFO underrun interrupt storms" I can reproduce:
the "ironlake_crtc_disable" case and the "wrong watermarks" case.
In other words, here's how to reproduce the problem fixed by this
patch:
1 - Enable PCH FIFO underrun interrupts (SERR_INT on SNB+)
2 - Boot the machine
3 - While booting we'll get tons of PCH FIFO underrun interrupts
4 - Plug a new monitor
5 - Run xrandr, notice it won't detect the new monitor
6 - Read SDEIIR and notice it's not 0 while DEIIR is 0
Q: Can't we just clear DEIIR before SDEIIR?
A: It doesn't work. SDEIIR has to be completely cleared (including the
interrupts stored on its back queue) before it can flip DEIIR's bit to
1 again, and even while you're clearing it you'll be getting more and
more interrupts.
Q: Why does it work by just disabling+enabling the south interrupts?
A: Because when we re-enable them, if there's something on the SDEIIR
register (maybe an interrupt stored on the queue), the re-enabling
will make DEIIR's bit flip to 1, and since we'll already have
interrupts enabled we'll get another interrupt, then run our irq
handler again to process the "back" interrupts.
v2: Even bigger commit message, added code comments.
Note that this fixes missed dp aux irqs which have been reported for
3.9-rc1. This regression has been introduced by switching to
irq-driven dp aux transactions with
commit 9ee32fea5fe810ec06af3a15e4c65478de56d4f5
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat Dec 1 13:53:48 2012 +0100
drm/i915: irq-drive the dp aux communication
References: http://www.mail-archive.com/intel-gfx@lists.freedesktop.org/msg18588.html
References: https://lkml.org/lkml/2013/2/26/769
Tested-by: Imre Deak <imre.deak@intel.com>
Reported-by: Sedat Dilek <sedat.dilek@gmail.com>
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Pimp commit message with references for the dp aux irq
timeout regression this fixes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-22 20:05:28 +00:00
|
|
|
|
2011-04-06 19:13:38 +00:00
|
|
|
gt_iir = I915_READ(GTIIR);
|
2012-05-09 20:45:44 +00:00
|
|
|
if (gt_iir) {
|
2013-07-19 21:57:55 +00:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6)
|
2013-07-12 22:56:30 +00:00
|
|
|
snb_gt_irq_handler(dev, dev_priv, gt_iir);
|
2013-07-19 21:57:55 +00:00
|
|
|
else
|
|
|
|
ilk_gt_irq_handler(dev, dev_priv, gt_iir);
|
2012-05-09 20:45:44 +00:00
|
|
|
I915_WRITE(GTIIR, gt_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
2011-04-06 19:13:38 +00:00
|
|
|
}
|
|
|
|
|
2012-05-09 20:45:44 +00:00
|
|
|
de_iir = I915_READ(DEIIR);
|
|
|
|
if (de_iir) {
|
2013-07-12 22:56:30 +00:00
|
|
|
if (INTEL_INFO(dev)->gen >= 7)
|
|
|
|
ivb_display_irq_handler(dev, de_iir);
|
|
|
|
else
|
|
|
|
ilk_display_irq_handler(dev, de_iir);
|
2012-05-09 20:45:44 +00:00
|
|
|
I915_WRITE(DEIIR, de_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
2011-04-06 19:13:38 +00:00
|
|
|
}
|
|
|
|
|
2013-07-12 22:56:30 +00:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
|
|
|
u32 pm_iir = I915_READ(GEN6_PMIIR);
|
|
|
|
if (pm_iir) {
|
2013-08-15 14:51:32 +00:00
|
|
|
gen6_rps_irq_handler(dev_priv, pm_iir);
|
2013-07-12 22:56:30 +00:00
|
|
|
I915_WRITE(GEN6_PMIIR, pm_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
2012-05-09 20:45:44 +00:00
|
|
|
}
|
2011-04-06 19:13:38 +00:00
|
|
|
|
|
|
|
I915_WRITE(DEIER, de_ier);
|
|
|
|
POSTING_READ(DEIER);
|
2013-04-05 20:12:41 +00:00
|
|
|
if (!HAS_PCH_NOP(dev)) {
|
|
|
|
I915_WRITE(SDEIER, sde_ier);
|
|
|
|
POSTING_READ(SDEIER);
|
|
|
|
}
|
2011-04-06 19:13:38 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
static irqreturn_t gen8_irq_handler(int irq, void *arg)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = arg;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 master_ctl;
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
uint32_t tmp = 0;
|
2013-11-07 10:05:40 +00:00
|
|
|
enum pipe pipe;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
|
|
|
master_ctl = I915_READ(GEN8_MASTER_IRQ);
|
|
|
|
master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
|
|
|
|
if (!master_ctl)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, 0);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
|
|
|
ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
|
|
|
|
|
|
|
|
if (master_ctl & GEN8_DE_MISC_IRQ) {
|
|
|
|
tmp = I915_READ(GEN8_DE_MISC_IIR);
|
|
|
|
if (tmp & GEN8_DE_MISC_GSE)
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
else if (tmp)
|
|
|
|
DRM_ERROR("Unexpected DE Misc interrupt\n");
|
|
|
|
else
|
|
|
|
DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
|
|
|
|
|
|
|
|
if (tmp) {
|
|
|
|
I915_WRITE(GEN8_DE_MISC_IIR, tmp);
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-07 13:49:55 +00:00
|
|
|
if (master_ctl & GEN8_DE_PORT_IRQ) {
|
|
|
|
tmp = I915_READ(GEN8_DE_PORT_IIR);
|
|
|
|
if (tmp & GEN8_AUX_CHANNEL_A)
|
|
|
|
dp_aux_irq_handler(dev);
|
|
|
|
else if (tmp)
|
|
|
|
DRM_ERROR("Unexpected DE Port interrupt\n");
|
|
|
|
else
|
|
|
|
DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
|
|
|
|
|
|
|
|
if (tmp) {
|
|
|
|
I915_WRITE(GEN8_DE_PORT_IIR, tmp);
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-11-07 10:05:40 +00:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
uint32_t pipe_iir;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2013-11-07 10:05:40 +00:00
|
|
|
if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
|
|
|
|
continue;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2013-11-07 10:05:40 +00:00
|
|
|
pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
|
|
|
|
if (pipe_iir & GEN8_PIPE_VBLANK)
|
|
|
|
drm_handle_vblank(dev, pipe);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2014-04-08 00:22:44 +00:00
|
|
|
if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
|
2013-11-07 10:05:40 +00:00
|
|
|
intel_prepare_page_flip(dev, pipe);
|
|
|
|
intel_finish_page_flip_plane(dev, pipe);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
2013-11-07 10:05:40 +00:00
|
|
|
|
2013-11-07 10:05:44 +00:00
|
|
|
if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
|
|
|
|
hsw_pipe_crc_irq_handler(dev, pipe);
|
|
|
|
|
2013-11-07 10:05:46 +00:00
|
|
|
if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
|
|
|
|
if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
|
|
|
|
false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("Pipe %c FIFO underrun\n",
|
|
|
|
pipe_name(pipe));
|
2013-11-07 10:05:46 +00:00
|
|
|
}
|
|
|
|
|
2013-11-07 13:49:24 +00:00
|
|
|
if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
|
|
|
|
DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
|
|
|
|
pipe_name(pipe),
|
|
|
|
pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
|
|
|
|
}
|
2013-11-07 10:05:40 +00:00
|
|
|
|
|
|
|
if (pipe_iir) {
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
|
|
|
|
} else
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
|
|
|
|
}
|
|
|
|
|
2013-11-07 10:05:43 +00:00
|
|
|
if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
|
|
|
|
/*
|
|
|
|
* FIXME(BDW): Assume for now that the new interrupt handling
|
|
|
|
* scheme also closed the SDE interrupt handling race we've seen
|
|
|
|
* on older pch-split platforms. But this needs testing.
|
|
|
|
*/
|
|
|
|
u32 pch_iir = I915_READ(SDEIIR);
|
|
|
|
|
|
|
|
cpt_irq_handler(dev, pch_iir);
|
|
|
|
|
|
|
|
if (pch_iir) {
|
|
|
|
I915_WRITE(SDEIIR, pch_iir);
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-09-08 19:57:13 +00:00
|
|
|
static void i915_error_wake_up(struct drm_i915_private *dev_priv,
|
|
|
|
bool reset_completed)
|
|
|
|
{
|
|
|
|
struct intel_ring_buffer *ring;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Notify all waiters for GPU completion events that reset state has
|
|
|
|
* been changed, and that they need to restart their wait after
|
|
|
|
* checking for potential errors (and bail out to drop locks if there is
|
|
|
|
* a gpu reset pending so that i915_error_work_func can acquire them).
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
|
|
|
|
for_each_ring(ring, dev_priv, i)
|
|
|
|
wake_up_all(&ring->irq_queue);
|
|
|
|
|
|
|
|
/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
|
|
|
|
wake_up_all(&dev_priv->pending_flip_queue);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Signal tasks blocked in i915_gem_wait_for_error that the pending
|
|
|
|
* reset state is cleared.
|
|
|
|
*/
|
|
|
|
if (reset_completed)
|
|
|
|
wake_up_all(&dev_priv->gpu_error.reset_queue);
|
|
|
|
}
|
|
|
|
|
2009-07-11 20:48:03 +00:00
|
|
|
/**
|
|
|
|
* i915_error_work_func - do process context error handling work
|
|
|
|
* @work: work struct
|
|
|
|
*
|
|
|
|
* Fire an error uevent so userspace can see that a hang or error
|
|
|
|
* was detected.
|
|
|
|
*/
|
|
|
|
static void i915_error_work_func(struct work_struct *work)
|
|
|
|
{
|
2012-11-15 16:17:22 +00:00
|
|
|
struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
|
|
|
|
work);
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(error, struct drm_i915_private, gpu_error);
|
2009-07-11 20:48:03 +00:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2013-07-19 16:16:42 +00:00
|
|
|
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
|
|
|
|
char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
|
|
|
|
char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
|
2013-09-08 19:57:13 +00:00
|
|
|
int ret;
|
2009-07-11 20:48:03 +00:00
|
|
|
|
2013-10-11 04:07:25 +00:00
|
|
|
kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
|
2009-09-14 21:48:46 +00:00
|
|
|
|
2012-12-06 15:23:37 +00:00
|
|
|
/*
|
|
|
|
* Note that there's only one work item which does gpu resets, so we
|
|
|
|
* need not worry about concurrent gpu resets potentially incrementing
|
|
|
|
* error->reset_counter twice. We only need to take care of another
|
|
|
|
* racing irq/hangcheck declaring the gpu dead for a second time. A
|
|
|
|
* quick check for that is good enough: schedule_work ensures the
|
|
|
|
* correct ordering between hang detection and this work item, and since
|
|
|
|
* the reset in-progress bit is only ever set by code outside of this
|
|
|
|
* work we don't need to worry about any other races.
|
|
|
|
*/
|
|
|
|
if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
|
2010-09-19 11:38:26 +00:00
|
|
|
DRM_DEBUG_DRIVER("resetting chip\n");
|
2013-10-11 04:07:25 +00:00
|
|
|
kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
|
2012-12-06 15:23:37 +00:00
|
|
|
reset_event);
|
2012-11-15 16:17:22 +00:00
|
|
|
|
2014-04-22 22:09:04 +00:00
|
|
|
/*
|
|
|
|
* In most cases it's guaranteed that we get here with an RPM
|
|
|
|
* reference held, for example because there is a pending GPU
|
|
|
|
* request that won't finish until the reset is done. This
|
|
|
|
* isn't the case at least when we get here by doing a
|
|
|
|
* simulated reset via debugs, so get an RPM reference.
|
|
|
|
*/
|
|
|
|
intel_runtime_pm_get(dev_priv);
|
2013-09-08 19:57:13 +00:00
|
|
|
/*
|
|
|
|
* All state reset _must_ be completed before we update the
|
|
|
|
* reset counter, for otherwise waiters might miss the reset
|
|
|
|
* pending state and not properly drop locks, resulting in
|
|
|
|
* deadlocks with the reset work.
|
|
|
|
*/
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 08:01:42 +00:00
|
|
|
ret = i915_reset(dev);
|
|
|
|
|
2013-09-08 19:57:13 +00:00
|
|
|
intel_display_handle_reset(dev);
|
|
|
|
|
2014-04-22 22:09:04 +00:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 08:01:42 +00:00
|
|
|
if (ret == 0) {
|
|
|
|
/*
|
|
|
|
* After all the gem state is reset, increment the reset
|
|
|
|
* counter and wake up everyone waiting for the reset to
|
|
|
|
* complete.
|
|
|
|
*
|
|
|
|
* Since unlock operations are a one-sided barrier only,
|
|
|
|
* we need to insert a barrier here to order any seqno
|
|
|
|
* updates before
|
|
|
|
* the counter increment.
|
|
|
|
*/
|
|
|
|
smp_mb__before_atomic_inc();
|
|
|
|
atomic_inc(&dev_priv->gpu_error.reset_counter);
|
|
|
|
|
2013-10-11 04:07:25 +00:00
|
|
|
kobject_uevent_env(&dev->primary->kdev->kobj,
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 08:01:42 +00:00
|
|
|
KOBJ_CHANGE, reset_done_event);
|
2012-11-15 16:17:22 +00:00
|
|
|
} else {
|
2013-11-12 12:44:19 +00:00
|
|
|
atomic_set_mask(I915_WEDGED, &error->reset_counter);
|
2009-09-14 21:48:46 +00:00
|
|
|
}
|
2012-11-15 16:17:22 +00:00
|
|
|
|
2013-09-08 19:57:13 +00:00
|
|
|
/*
|
|
|
|
* Note: The wake_up also serves as a memory barrier so that
|
|
|
|
* waiters see the update value of the reset counter atomic_t.
|
|
|
|
*/
|
|
|
|
i915_error_wake_up(dev_priv, true);
|
2009-09-14 21:48:46 +00:00
|
|
|
}
|
2009-07-11 20:48:03 +00:00
|
|
|
}
|
|
|
|
|
2010-05-27 12:18:12 +00:00
|
|
|
static void i915_report_and_clear_eir(struct drm_device *dev)
|
2009-07-11 20:48:03 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-08-23 22:18:09 +00:00
|
|
|
uint32_t instdone[I915_NUM_INSTDONE_REG];
|
2009-07-11 20:48:03 +00:00
|
|
|
u32 eir = I915_READ(EIR);
|
2012-08-22 18:32:15 +00:00
|
|
|
int pipe, i;
|
2009-07-11 20:48:03 +00:00
|
|
|
|
2010-05-27 12:18:12 +00:00
|
|
|
if (!eir)
|
|
|
|
return;
|
2009-07-11 20:48:03 +00:00
|
|
|
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err("render error detected, EIR: 0x%08x\n", eir);
|
2009-07-11 20:48:03 +00:00
|
|
|
|
2012-08-23 22:18:09 +00:00
|
|
|
i915_get_extra_instdone(dev, instdone);
|
|
|
|
|
2009-07-11 20:48:03 +00:00
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
|
|
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
|
|
|
|
pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
|
2012-08-22 18:32:15 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(instdone); i++)
|
|
|
|
pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
|
|
|
|
pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
|
2009-07-11 20:48:03 +00:00
|
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(IPEIR_I965);
|
2009-07-11 20:48:03 +00:00
|
|
|
}
|
|
|
|
if (eir & GM45_ERROR_PAGE_TABLE) {
|
|
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err("page table error\n");
|
|
|
|
pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
|
2009-07-11 20:48:03 +00:00
|
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(PGTBL_ER);
|
2009-07-11 20:48:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-16 23:32:17 +00:00
|
|
|
if (!IS_GEN2(dev)) {
|
2009-07-11 20:48:03 +00:00
|
|
|
if (eir & I915_ERROR_PAGE_TABLE) {
|
|
|
|
u32 pgtbl_err = I915_READ(PGTBL_ER);
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err("page table error\n");
|
|
|
|
pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
|
2009-07-11 20:48:03 +00:00
|
|
|
I915_WRITE(PGTBL_ER, pgtbl_err);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(PGTBL_ER);
|
2009-07-11 20:48:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (eir & I915_ERROR_MEMORY_REFRESH) {
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err("memory refresh error:\n");
|
2011-02-07 20:26:52 +00:00
|
|
|
for_each_pipe(pipe)
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err("pipe %c stat: 0x%08x\n",
|
2011-02-07 20:26:52 +00:00
|
|
|
pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
|
2009-07-11 20:48:03 +00:00
|
|
|
/* pipestat has already been acked */
|
|
|
|
}
|
|
|
|
if (eir & I915_ERROR_INSTRUCTION) {
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err("instruction error\n");
|
|
|
|
pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
|
2012-08-22 18:32:15 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(instdone); i++)
|
|
|
|
pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
|
2010-09-16 23:32:17 +00:00
|
|
|
if (INTEL_INFO(dev)->gen < 4) {
|
2009-07-11 20:48:03 +00:00
|
|
|
u32 ipeir = I915_READ(IPEIR);
|
|
|
|
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
|
|
|
|
pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
|
|
|
|
pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
|
2009-07-11 20:48:03 +00:00
|
|
|
I915_WRITE(IPEIR, ipeir);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(IPEIR);
|
2009-07-11 20:48:03 +00:00
|
|
|
} else {
|
|
|
|
u32 ipeir = I915_READ(IPEIR_I965);
|
|
|
|
|
2012-03-18 20:00:11 +00:00
|
|
|
pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
|
|
|
|
pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
|
|
|
|
pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
|
|
|
|
pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
|
2009-07-11 20:48:03 +00:00
|
|
|
I915_WRITE(IPEIR_I965, ipeir);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(IPEIR_I965);
|
2009-07-11 20:48:03 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(EIR, eir);
|
2010-11-16 15:55:10 +00:00
|
|
|
POSTING_READ(EIR);
|
2009-07-11 20:48:03 +00:00
|
|
|
eir = I915_READ(EIR);
|
|
|
|
if (eir) {
|
|
|
|
/*
|
|
|
|
* some errors might have become stuck,
|
|
|
|
* mask them.
|
|
|
|
*/
|
|
|
|
DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
|
|
|
|
I915_WRITE(EMR, I915_READ(EMR) | eir);
|
|
|
|
I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
|
|
}
|
2010-05-27 12:18:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* i915_handle_error - handle an error interrupt
|
|
|
|
* @dev: drm device
|
|
|
|
*
|
|
|
|
* Do some basic checking of regsiter state at error interrupt time and
|
|
|
|
* dump it to the syslog. Also call i915_capture_error_state() to make
|
|
|
|
* sure we get a record and make it available in debugfs. Fire a uevent
|
|
|
|
* so userspace knows something bad happened (should trigger collection
|
|
|
|
* of a ring dump etc.).
|
|
|
|
*/
|
2014-02-25 15:11:26 +00:00
|
|
|
void i915_handle_error(struct drm_device *dev, bool wedged,
|
|
|
|
const char *fmt, ...)
|
2010-05-27 12:18:12 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-02-25 15:11:26 +00:00
|
|
|
va_list args;
|
|
|
|
char error_msg[80];
|
2010-05-27 12:18:12 +00:00
|
|
|
|
2014-02-25 15:11:26 +00:00
|
|
|
va_start(args, fmt);
|
|
|
|
vscnprintf(error_msg, sizeof(error_msg), fmt, args);
|
|
|
|
va_end(args);
|
|
|
|
|
|
|
|
i915_capture_error_state(dev, wedged, error_msg);
|
2010-05-27 12:18:12 +00:00
|
|
|
i915_report_and_clear_eir(dev);
|
2009-07-11 20:48:03 +00:00
|
|
|
|
2009-09-14 21:48:47 +00:00
|
|
|
if (wedged) {
|
drm/i915: create a race-free reset detection
With the previous patch the state transition handling of the reset
code itself is now (hopefully) race free and solid. But that still
leaves out everyone else - with the various lock-free wait paths
we have there's the possibility that the reset happens between the
point where we read the seqno we should wait on and the actual wait.
And if __wait_seqno then never sees the RESET_IN_PROGRESS state, we'll
happily wait for a seqno which will in all likelyhood never signal.
In practice this is not a big problem since the X server gets
constantly interrupted, and can then submit more work (hopefully) to
unblock everyone else: As soon as a new seqno write lands, all waiters
will unblock. But running the i-g-t reset testcase ZZ_hangman can
expose this race, especially on slower hw with fewer cpu cores.
Now looking forward to ARB_robustness and friends that's not the best
possible behaviour, hence this patch adds a reset_counter to be able
to detect any reset, even if a given thread never observed the
in-progress state.
The important part is to correctly order things:
- The write side needs to increment the counter after any seqno gets
reset. Hence we need to do that at the end of the reset work, and
again wake everyone up. We also need to place a barrier in between
any possible seqno changes and the counter increment, since any
unlock operations only guarantee that nothing leaks out, but not
that at later load operation gets moved ahead.
- On the read side we need to ensure that no reset can sneak in and
invalidate the seqno. In all cases we can use the one-sided barrier
that unlock operations guarantee (of the lock protecting the
respective seqno/ring pair) to ensure correct ordering. Hence it is
sufficient to place the atomic read before the mutex/spin_unlock and
no additional barriers are required.
The end-result of all this is that we need to wake up everyone twice
in a reset operation:
- First, before the reset starts, to get any lockholders of the locks,
so that the reset can proceed.
- Second, after the reset is completed, to allow waiters to properly
and reliably detect the reset condition and bail out.
I admit that this entire reset_counter thing smells a bit like
overkill, but I think it's justified since it makes it really explicit
what the bail-out condition is. And we need a reset counter anyway to
implement ARB_robustness, and imo with finer-grained locking on the
horizont this is the most resilient scheme I could think of.
v2: Drop spurious change in the wait_for_error EXIT_COND - we only
need to wait until we leave the reset-in-progress wedged state.
v3: Don't play tricks with barriers in the throttle ioctl, the
spin_unlock is barrier enough.
I've also considered using a little helper to grab the current
reset_counter, but then decided that hiding the atomic_read isn't a
great idea, since having it explicitly show up in the code is a nice
remainder to reviews to check the memory barriers.
v4: Add a comment to explain why we need to fall through in
__wait_seqno in the end variable assignments.
v5: Review from Damien:
- s/smb/smp/ in a comment
- don't increment the reset counter after we've set it to WEDGED. Now
we (again) properly wedge the gpu when the reset fails.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-06 08:01:42 +00:00
|
|
|
atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
|
|
|
|
&dev_priv->gpu_error.reset_counter);
|
2009-09-14 21:48:47 +00:00
|
|
|
|
2009-09-14 21:48:45 +00:00
|
|
|
/*
|
2013-09-08 19:57:13 +00:00
|
|
|
* Wakeup waiting processes so that the reset work function
|
|
|
|
* i915_error_work_func doesn't deadlock trying to grab various
|
|
|
|
* locks. By bumping the reset counter first, the woken
|
|
|
|
* processes will see a reset in progress and back off,
|
|
|
|
* releasing their locks and then wait for the reset completion.
|
|
|
|
* We must do this for _all_ gpu waiters that might hold locks
|
|
|
|
* that the reset work needs to acquire.
|
|
|
|
*
|
|
|
|
* Note: The wake_up serves as the required memory barrier to
|
|
|
|
* ensure that the waiters see the updated value of the reset
|
|
|
|
* counter atomic_t.
|
2009-09-14 21:48:45 +00:00
|
|
|
*/
|
2013-09-08 19:57:13 +00:00
|
|
|
i915_error_wake_up(dev_priv, false);
|
2009-09-14 21:48:45 +00:00
|
|
|
}
|
|
|
|
|
2013-09-04 15:36:14 +00:00
|
|
|
/*
|
|
|
|
* Our reset work can grab modeset locks (since it needs to reset the
|
|
|
|
* state of outstanding pagelips). Hence it must not be run on our own
|
|
|
|
* dev-priv->wq work queue for otherwise the flush_work in the pageflip
|
|
|
|
* code will deadlock.
|
|
|
|
*/
|
|
|
|
schedule_work(&dev_priv->gpu_error.work);
|
2009-07-11 20:48:03 +00:00
|
|
|
}
|
|
|
|
|
2013-02-19 13:16:39 +00:00
|
|
|
static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
|
2010-09-01 16:47:52 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-09-01 16:47:52 +00:00
|
|
|
struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2010-11-08 19:18:58 +00:00
|
|
|
struct drm_i915_gem_object *obj;
|
2010-09-01 16:47:52 +00:00
|
|
|
struct intel_unpin_work *work;
|
|
|
|
unsigned long flags;
|
|
|
|
bool stall_detected;
|
|
|
|
|
|
|
|
/* Ignore early vblank irqs */
|
|
|
|
if (intel_crtc == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
work = intel_crtc->unpin_work;
|
|
|
|
|
2012-12-03 11:36:30 +00:00
|
|
|
if (work == NULL ||
|
|
|
|
atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
|
|
|
|
!work->enable_stall_check) {
|
2010-09-01 16:47:52 +00:00
|
|
|
/* Either the pending flip IRQ arrived, or we're too early. Don't check */
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Potential stall - if we see that the flip has happened, assume a missed interrupt */
|
2010-11-08 19:18:58 +00:00
|
|
|
obj = work->pending_flip_obj;
|
2010-09-16 23:32:17 +00:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
2011-02-07 20:26:52 +00:00
|
|
|
int dspsurf = DSPSURF(intel_crtc->plane);
|
2012-03-30 23:20:16 +00:00
|
|
|
stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
|
2013-07-05 21:41:04 +00:00
|
|
|
i915_gem_obj_ggtt_offset(obj);
|
2010-09-01 16:47:52 +00:00
|
|
|
} else {
|
2011-02-07 20:26:52 +00:00
|
|
|
int dspaddr = DSPADDR(intel_crtc->plane);
|
2013-07-05 21:41:04 +00:00
|
|
|
stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
|
2014-04-01 22:22:40 +00:00
|
|
|
crtc->y * crtc->primary->fb->pitches[0] +
|
|
|
|
crtc->x * crtc->primary->fb->bits_per_pixel/8);
|
2010-09-01 16:47:52 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
|
|
|
if (stall_detected) {
|
|
|
|
DRM_DEBUG_DRIVER("Pageflip stall detected\n");
|
|
|
|
intel_prepare_page_flip(dev, intel_crtc->plane);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-19 02:39:29 +00:00
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-28 20:00:41 +00:00
|
|
|
static int i915_enable_vblank(struct drm_device *dev, int pipe)
|
2008-09-30 19:14:26 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-10-16 18:31:38 +00:00
|
|
|
unsigned long irqflags;
|
2009-01-08 18:42:15 +00:00
|
|
|
|
2010-09-11 12:48:45 +00:00
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
2009-01-08 18:42:15 +00:00
|
|
|
return -EINVAL;
|
2008-09-30 19:14:26 +00:00
|
|
|
|
2010-12-04 11:30:53 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2011-04-07 20:58:17 +00:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
2008-11-04 10:03:27 +00:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
2014-02-10 16:42:47 +00:00
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2008-10-16 18:31:38 +00:00
|
|
|
else
|
2008-11-04 10:03:27 +00:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
2014-02-10 16:42:47 +00:00
|
|
|
PIPE_VBLANK_INTERRUPT_STATUS);
|
2011-02-05 10:08:21 +00:00
|
|
|
|
|
|
|
/* maintain vblank delivery even in deep C-states */
|
2014-02-07 19:12:47 +00:00
|
|
|
if (INTEL_INFO(dev)->gen == 3)
|
2012-04-24 12:04:12 +00:00
|
|
|
I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
|
2010-12-04 11:30:53 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2011-02-05 10:08:21 +00:00
|
|
|
|
2008-09-30 19:14:26 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
|
2011-04-07 20:58:17 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-04-07 20:58:17 +00:00
|
|
|
unsigned long irqflags;
|
2013-07-12 23:00:08 +00:00
|
|
|
uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
|
2013-10-21 16:04:36 +00:00
|
|
|
DE_PIPE_VBLANK(pipe);
|
2011-04-07 20:58:17 +00:00
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-07-12 23:00:08 +00:00
|
|
|
ironlake_enable_display_irq(dev_priv, bit);
|
2011-04-06 19:13:38 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-28 20:39:38 +00:00
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2012-06-20 17:53:11 +00:00
|
|
|
i915_enable_pipestat(dev_priv, pipe,
|
2014-02-10 16:42:47 +00:00
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2012-03-28 20:39:38 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
static int gen8_enable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-11-07 10:05:45 +00:00
|
|
|
dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
|
|
|
|
I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
|
|
|
|
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-10-19 02:39:29 +00:00
|
|
|
/* Called from drm generic code, passed 'crtc' which
|
|
|
|
* we use as a pipe index
|
|
|
|
*/
|
2011-06-28 20:00:41 +00:00
|
|
|
static void i915_disable_vblank(struct drm_device *dev, int pipe)
|
2008-09-30 19:14:26 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2008-10-16 18:31:38 +00:00
|
|
|
unsigned long irqflags;
|
2008-09-30 19:14:26 +00:00
|
|
|
|
2010-12-04 11:30:53 +00:00
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2014-02-07 19:12:47 +00:00
|
|
|
if (INTEL_INFO(dev)->gen == 3)
|
2012-04-24 12:04:12 +00:00
|
|
|
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
|
2011-02-05 10:08:21 +00:00
|
|
|
|
2011-04-07 20:58:17 +00:00
|
|
|
i915_disable_pipestat(dev_priv, pipe,
|
2014-02-10 16:42:47 +00:00
|
|
|
PIPE_VBLANK_INTERRUPT_STATUS |
|
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2011-04-07 20:58:17 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
|
2011-04-07 20:58:17 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-04-07 20:58:17 +00:00
|
|
|
unsigned long irqflags;
|
2013-07-12 23:00:08 +00:00
|
|
|
uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
|
2013-10-21 16:04:36 +00:00
|
|
|
DE_PIPE_VBLANK(pipe);
|
2011-04-07 20:58:17 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-07-12 23:00:08 +00:00
|
|
|
ironlake_disable_display_irq(dev_priv, bit);
|
2011-04-06 19:13:38 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-28 20:39:38 +00:00
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2012-06-20 17:53:11 +00:00
|
|
|
i915_disable_pipestat(dev_priv, pipe,
|
2014-02-10 16:42:47 +00:00
|
|
|
PIPE_START_VBLANK_INTERRUPT_STATUS);
|
2012-03-28 20:39:38 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
static void gen8_disable_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
if (!i915_pipe_enabled(dev, pipe))
|
|
|
|
return;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2013-11-07 10:05:45 +00:00
|
|
|
dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
|
|
|
|
I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
|
|
|
|
POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2010-10-27 13:44:35 +00:00
|
|
|
static u32
|
|
|
|
ring_last_seqno(struct intel_ring_buffer *ring)
|
2010-05-21 01:08:56 +00:00
|
|
|
{
|
2010-10-27 13:44:35 +00:00
|
|
|
return list_entry(ring->request_list.prev,
|
|
|
|
struct drm_i915_gem_request, list)->seqno;
|
|
|
|
}
|
|
|
|
|
2013-06-10 10:20:20 +00:00
|
|
|
static bool
|
|
|
|
ring_idle(struct intel_ring_buffer *ring, u32 seqno)
|
|
|
|
{
|
|
|
|
return (list_empty(&ring->request_list) ||
|
|
|
|
i915_seqno_passed(seqno, ring_last_seqno(ring)));
|
2009-09-14 21:48:44 +00:00
|
|
|
}
|
|
|
|
|
2014-03-14 23:08:56 +00:00
|
|
|
static bool
|
|
|
|
ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
|
|
|
|
{
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
|
|
|
/*
|
|
|
|
* FIXME: gen8 semaphore support - currently we don't emit
|
|
|
|
* semaphores on bdw anyway, but this needs to be addressed when
|
|
|
|
* we merge that code.
|
|
|
|
*/
|
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
|
|
|
|
return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
|
|
|
|
MI_SEMAPHORE_REGISTER);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-03-18 09:26:04 +00:00
|
|
|
static struct intel_ring_buffer *
|
|
|
|
semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
|
|
|
struct intel_ring_buffer *signaller;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
|
|
|
|
/*
|
|
|
|
* FIXME: gen8 semaphore support - currently we don't emit
|
|
|
|
* semaphores on bdw anyway, but this needs to be addressed when
|
|
|
|
* we merge that code.
|
|
|
|
*/
|
|
|
|
return NULL;
|
|
|
|
} else {
|
|
|
|
u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
|
|
|
|
|
|
|
|
for_each_ring(signaller, dev_priv, i) {
|
|
|
|
if(ring == signaller)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (sync_bits ==
|
|
|
|
signaller->semaphore_register[ring->id])
|
|
|
|
return signaller;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
|
|
|
|
ring->id, ipehr);
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2013-06-10 10:20:21 +00:00
|
|
|
static struct intel_ring_buffer *
|
|
|
|
semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
|
2013-03-14 15:52:05 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
2014-03-14 23:08:55 +00:00
|
|
|
u32 cmd, ipehr, head;
|
|
|
|
int i;
|
2013-03-14 15:52:05 +00:00
|
|
|
|
|
|
|
ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
|
2014-03-14 23:08:56 +00:00
|
|
|
if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
|
2013-06-10 10:20:21 +00:00
|
|
|
return NULL;
|
2013-03-14 15:52:05 +00:00
|
|
|
|
2014-03-14 23:08:55 +00:00
|
|
|
/*
|
|
|
|
* HEAD is likely pointing to the dword after the actual command,
|
|
|
|
* so scan backwards until we find the MBOX. But limit it to just 3
|
|
|
|
* dwords. Note that we don't care about ACTHD here since that might
|
|
|
|
* point at at batch, and semaphores are always emitted into the
|
|
|
|
* ringbuffer itself.
|
2013-03-14 15:52:05 +00:00
|
|
|
*/
|
2014-03-14 23:08:55 +00:00
|
|
|
head = I915_READ_HEAD(ring) & HEAD_ADDR;
|
|
|
|
|
|
|
|
for (i = 4; i; --i) {
|
|
|
|
/*
|
|
|
|
* Be paranoid and presume the hw has gone off into the wild -
|
|
|
|
* our ring is smaller than what the hardware (and hence
|
|
|
|
* HEAD_ADDR) allows. Also handles wrap-around.
|
|
|
|
*/
|
|
|
|
head &= ring->size - 1;
|
|
|
|
|
|
|
|
/* This here seems to blow up */
|
|
|
|
cmd = ioread32(ring->virtual_start + head);
|
2013-03-14 15:52:05 +00:00
|
|
|
if (cmd == ipehr)
|
|
|
|
break;
|
|
|
|
|
2014-03-14 23:08:55 +00:00
|
|
|
head -= 4;
|
|
|
|
}
|
2013-03-14 15:52:05 +00:00
|
|
|
|
2014-03-14 23:08:55 +00:00
|
|
|
if (!i)
|
|
|
|
return NULL;
|
2013-03-14 15:52:05 +00:00
|
|
|
|
2014-03-14 23:08:55 +00:00
|
|
|
*seqno = ioread32(ring->virtual_start + head + 4) + 1;
|
2014-03-18 09:26:04 +00:00
|
|
|
return semaphore_wait_to_signaller_ring(ring, ipehr);
|
2013-03-14 15:52:05 +00:00
|
|
|
}
|
|
|
|
|
2013-06-10 10:20:21 +00:00
|
|
|
static int semaphore_passed(struct intel_ring_buffer *ring)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
|
|
|
struct intel_ring_buffer *signaller;
|
|
|
|
u32 seqno, ctl;
|
|
|
|
|
|
|
|
ring->hangcheck.deadlock = true;
|
|
|
|
|
|
|
|
signaller = semaphore_waits_for(ring, &seqno);
|
|
|
|
if (signaller == NULL || signaller->hangcheck.deadlock)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/* cursory check for an unkickable deadlock */
|
|
|
|
ctl = I915_READ_CTL(signaller);
|
|
|
|
if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct intel_ring_buffer *ring;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for_each_ring(ring, dev_priv, i)
|
|
|
|
ring->hangcheck.deadlock = false;
|
|
|
|
}
|
|
|
|
|
2013-06-12 09:35:32 +00:00
|
|
|
static enum intel_ring_hangcheck_action
|
2014-03-21 12:41:53 +00:00
|
|
|
ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
|
2010-12-04 11:30:53 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = ring->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-06-10 10:20:20 +00:00
|
|
|
u32 tmp;
|
|
|
|
|
2013-06-10 10:20:21 +00:00
|
|
|
if (ring->hangcheck.acthd != acthd)
|
2013-08-11 09:44:01 +00:00
|
|
|
return HANGCHECK_ACTIVE;
|
2013-06-10 10:20:21 +00:00
|
|
|
|
2013-06-10 10:20:20 +00:00
|
|
|
if (IS_GEN2(dev))
|
2013-08-11 09:44:01 +00:00
|
|
|
return HANGCHECK_HUNG;
|
2013-06-10 10:20:20 +00:00
|
|
|
|
|
|
|
/* Is the chip hanging on a WAIT_FOR_EVENT?
|
|
|
|
* If so we can simply poke the RB_WAIT bit
|
|
|
|
* and break the hang. This should work on
|
|
|
|
* all but the second generation chipsets.
|
|
|
|
*/
|
|
|
|
tmp = I915_READ_CTL(ring);
|
2010-12-04 11:30:53 +00:00
|
|
|
if (tmp & RING_WAIT) {
|
2014-02-25 15:11:26 +00:00
|
|
|
i915_handle_error(dev, false,
|
|
|
|
"Kicking stuck wait on %s",
|
|
|
|
ring->name);
|
2010-12-04 11:30:53 +00:00
|
|
|
I915_WRITE_CTL(ring, tmp);
|
2013-08-11 09:44:01 +00:00
|
|
|
return HANGCHECK_KICK;
|
2013-06-10 10:20:21 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
|
|
|
|
switch (semaphore_passed(ring)) {
|
|
|
|
default:
|
2013-08-11 09:44:01 +00:00
|
|
|
return HANGCHECK_HUNG;
|
2013-06-10 10:20:21 +00:00
|
|
|
case 1:
|
2014-02-25 15:11:26 +00:00
|
|
|
i915_handle_error(dev, false,
|
|
|
|
"Kicking stuck semaphore on %s",
|
|
|
|
ring->name);
|
2013-06-10 10:20:21 +00:00
|
|
|
I915_WRITE_CTL(ring, tmp);
|
2013-08-11 09:44:01 +00:00
|
|
|
return HANGCHECK_KICK;
|
2013-06-10 10:20:21 +00:00
|
|
|
case 0:
|
2013-08-11 09:44:01 +00:00
|
|
|
return HANGCHECK_WAIT;
|
2013-06-10 10:20:21 +00:00
|
|
|
}
|
2013-06-10 10:20:20 +00:00
|
|
|
}
|
2013-05-13 13:32:11 +00:00
|
|
|
|
2013-08-11 09:44:01 +00:00
|
|
|
return HANGCHECK_HUNG;
|
2013-05-13 13:32:11 +00:00
|
|
|
}
|
|
|
|
|
2009-09-14 21:48:44 +00:00
|
|
|
/**
|
|
|
|
* This is called when the chip hasn't reported back with completed
|
2013-05-30 06:04:29 +00:00
|
|
|
* batchbuffers in a long time. We keep track per ring seqno progress and
|
|
|
|
* if there are no progress, hangcheck score for that ring is increased.
|
|
|
|
* Further, acthd is inspected to see if the ring is stuck. On stuck case
|
|
|
|
* we kick the ring. If we see no progress on three subsequent calls
|
|
|
|
* we assume chip is wedged and try to fix it by resetting the chip.
|
2009-09-14 21:48:44 +00:00
|
|
|
*/
|
2013-08-08 21:28:56 +00:00
|
|
|
static void i915_hangcheck_elapsed(unsigned long data)
|
2009-09-14 21:48:44 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *)data;
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-05-11 13:29:30 +00:00
|
|
|
struct intel_ring_buffer *ring;
|
|
|
|
int i;
|
2013-05-30 06:04:29 +00:00
|
|
|
int busy_count = 0, rings_hung = 0;
|
2013-06-10 10:20:20 +00:00
|
|
|
bool stuck[I915_NUM_RINGS] = { 0 };
|
|
|
|
#define BUSY 1
|
|
|
|
#define KICK 5
|
|
|
|
#define HUNG 20
|
2010-10-27 13:44:35 +00:00
|
|
|
|
2014-01-21 09:24:25 +00:00
|
|
|
if (!i915.enable_hangcheck)
|
2011-06-29 17:26:42 +00:00
|
|
|
return;
|
|
|
|
|
2012-05-11 13:29:30 +00:00
|
|
|
for_each_ring(ring, dev_priv, i) {
|
2014-03-21 12:41:53 +00:00
|
|
|
u64 acthd;
|
|
|
|
u32 seqno;
|
2013-06-10 10:20:20 +00:00
|
|
|
bool busy = true;
|
2013-05-30 06:04:29 +00:00
|
|
|
|
2013-06-10 10:20:21 +00:00
|
|
|
semaphore_clear_deadlocks(dev_priv);
|
|
|
|
|
2013-05-30 06:04:29 +00:00
|
|
|
seqno = ring->get_seqno(ring, false);
|
|
|
|
acthd = intel_ring_get_active_head(ring);
|
2012-05-11 13:29:30 +00:00
|
|
|
|
2013-06-10 10:20:20 +00:00
|
|
|
if (ring->hangcheck.seqno == seqno) {
|
|
|
|
if (ring_idle(ring, seqno)) {
|
2013-09-06 13:03:28 +00:00
|
|
|
ring->hangcheck.action = HANGCHECK_IDLE;
|
|
|
|
|
2013-06-10 10:20:20 +00:00
|
|
|
if (waitqueue_active(&ring->irq_queue)) {
|
|
|
|
/* Issue a wake-up to catch stuck h/w. */
|
2013-09-25 16:34:55 +00:00
|
|
|
if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
|
2013-10-28 08:24:13 +00:00
|
|
|
if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
|
|
|
|
DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
|
|
|
|
ring->name);
|
|
|
|
else
|
|
|
|
DRM_INFO("Fake missed irq on %s\n",
|
|
|
|
ring->name);
|
2013-09-25 16:34:55 +00:00
|
|
|
wake_up_all(&ring->irq_queue);
|
|
|
|
}
|
|
|
|
/* Safeguard against driver failure */
|
|
|
|
ring->hangcheck.score += BUSY;
|
2013-06-10 10:20:20 +00:00
|
|
|
} else
|
|
|
|
busy = false;
|
2013-05-30 06:04:29 +00:00
|
|
|
} else {
|
2013-06-10 10:20:21 +00:00
|
|
|
/* We always increment the hangcheck score
|
|
|
|
* if the ring is busy and still processing
|
|
|
|
* the same request, so that no single request
|
|
|
|
* can run indefinitely (such as a chain of
|
|
|
|
* batches). The only time we do not increment
|
|
|
|
* the hangcheck score on this ring, if this
|
|
|
|
* ring is in a legitimate wait for another
|
|
|
|
* ring. In that case the waiting ring is a
|
|
|
|
* victim and we want to be sure we catch the
|
|
|
|
* right culprit. Then every time we do kick
|
|
|
|
* the ring, add a small increment to the
|
|
|
|
* score so that we can catch a batch that is
|
|
|
|
* being repeatedly kicked and so responsible
|
|
|
|
* for stalling the machine.
|
|
|
|
*/
|
2013-06-12 09:35:32 +00:00
|
|
|
ring->hangcheck.action = ring_stuck(ring,
|
|
|
|
acthd);
|
|
|
|
|
|
|
|
switch (ring->hangcheck.action) {
|
2013-09-06 13:03:28 +00:00
|
|
|
case HANGCHECK_IDLE:
|
2013-08-11 09:44:01 +00:00
|
|
|
case HANGCHECK_WAIT:
|
2013-06-10 10:20:21 +00:00
|
|
|
break;
|
2013-08-11 09:44:01 +00:00
|
|
|
case HANGCHECK_ACTIVE:
|
2013-08-11 09:44:02 +00:00
|
|
|
ring->hangcheck.score += BUSY;
|
2013-06-10 10:20:21 +00:00
|
|
|
break;
|
2013-08-11 09:44:01 +00:00
|
|
|
case HANGCHECK_KICK:
|
2013-08-11 09:44:02 +00:00
|
|
|
ring->hangcheck.score += KICK;
|
2013-06-10 10:20:21 +00:00
|
|
|
break;
|
2013-08-11 09:44:01 +00:00
|
|
|
case HANGCHECK_HUNG:
|
2013-08-11 09:44:02 +00:00
|
|
|
ring->hangcheck.score += HUNG;
|
2013-06-10 10:20:21 +00:00
|
|
|
stuck[i] = true;
|
|
|
|
break;
|
|
|
|
}
|
2013-05-30 06:04:29 +00:00
|
|
|
}
|
2013-06-10 10:20:20 +00:00
|
|
|
} else {
|
2013-09-06 13:03:28 +00:00
|
|
|
ring->hangcheck.action = HANGCHECK_ACTIVE;
|
|
|
|
|
2013-06-10 10:20:20 +00:00
|
|
|
/* Gradually reduce the count so that we catch DoS
|
|
|
|
* attempts across multiple batches.
|
|
|
|
*/
|
|
|
|
if (ring->hangcheck.score > 0)
|
|
|
|
ring->hangcheck.score--;
|
2012-04-10 16:00:41 +00:00
|
|
|
}
|
|
|
|
|
2013-05-30 06:04:29 +00:00
|
|
|
ring->hangcheck.seqno = seqno;
|
|
|
|
ring->hangcheck.acthd = acthd;
|
2013-06-10 10:20:20 +00:00
|
|
|
busy_count += busy;
|
2010-10-27 13:44:35 +00:00
|
|
|
}
|
2010-01-08 22:25:16 +00:00
|
|
|
|
2013-05-24 14:16:07 +00:00
|
|
|
for_each_ring(ring, dev_priv, i) {
|
2014-01-30 17:04:43 +00:00
|
|
|
if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
|
2013-08-28 08:57:59 +00:00
|
|
|
DRM_INFO("%s on %s\n",
|
|
|
|
stuck[i] ? "stuck" : "no progress",
|
|
|
|
ring->name);
|
2013-06-10 10:20:22 +00:00
|
|
|
rings_hung++;
|
2013-05-24 14:16:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-05-30 06:04:29 +00:00
|
|
|
if (rings_hung)
|
2014-02-25 15:11:26 +00:00
|
|
|
return i915_handle_error(dev, true, "Ring hung");
|
2009-09-14 21:48:44 +00:00
|
|
|
|
2013-05-30 06:04:29 +00:00
|
|
|
if (busy_count)
|
|
|
|
/* Reset timer case chip hangs without another request
|
|
|
|
* being added */
|
2013-07-03 14:22:08 +00:00
|
|
|
i915_queue_hangcheck(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_queue_hangcheck(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-01-21 09:24:25 +00:00
|
|
|
if (!i915.enable_hangcheck)
|
2013-07-03 14:22:08 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
mod_timer(&dev_priv->gpu_error.hangcheck_timer,
|
|
|
|
round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
|
2009-09-14 21:48:44 +00:00
|
|
|
}
|
|
|
|
|
2014-04-01 18:37:23 +00:00
|
|
|
static void ibx_irq_reset(struct drm_device *dev)
|
2013-06-05 17:21:51 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (HAS_PCH_NOP(dev))
|
|
|
|
return;
|
|
|
|
|
2014-04-01 18:37:14 +00:00
|
|
|
GEN5_IRQ_RESET(SDE);
|
2014-04-01 18:37:17 +00:00
|
|
|
|
|
|
|
if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
|
|
|
|
I915_WRITE(SERR_INT, 0xffffffff);
|
2014-04-01 18:37:22 +00:00
|
|
|
}
|
2014-04-01 18:37:17 +00:00
|
|
|
|
2014-04-01 18:37:22 +00:00
|
|
|
/*
|
|
|
|
* SDEIER is also touched by the interrupt handler to work around missed PCH
|
|
|
|
* interrupts. Hence we can't update it after the interrupt handler is enabled -
|
|
|
|
* instead we unconditionally enable all PCH interrupt sources here, but then
|
|
|
|
* only unmask them as needed with SDEIMR.
|
|
|
|
*
|
|
|
|
* This function needs to be called before interrupts are enabled.
|
|
|
|
*/
|
|
|
|
static void ibx_irq_pre_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (HAS_PCH_NOP(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
WARN_ON(I915_READ(SDEIER) != 0);
|
2013-06-05 17:21:51 +00:00
|
|
|
I915_WRITE(SDEIER, 0xffffffff);
|
|
|
|
POSTING_READ(SDEIER);
|
|
|
|
}
|
|
|
|
|
2014-04-01 18:37:19 +00:00
|
|
|
static void gen5_gt_irq_reset(struct drm_device *dev)
|
2013-07-12 20:43:25 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-04-01 18:37:14 +00:00
|
|
|
GEN5_IRQ_RESET(GT);
|
2014-04-01 18:37:09 +00:00
|
|
|
if (INTEL_INFO(dev)->gen >= 6)
|
2014-04-01 18:37:14 +00:00
|
|
|
GEN5_IRQ_RESET(GEN6_PM);
|
2013-07-12 20:43:25 +00:00
|
|
|
}
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* drm_dma.h hooks
|
|
|
|
*/
|
2014-04-01 18:37:25 +00:00
|
|
|
static void ironlake_irq_reset(struct drm_device *dev)
|
2009-06-08 06:40:19 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2009-06-08 06:40:19 +00:00
|
|
|
|
2014-04-01 18:37:27 +00:00
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
2012-01-05 00:05:26 +00:00
|
|
|
|
2014-04-01 18:37:14 +00:00
|
|
|
GEN5_IRQ_RESET(DE);
|
2014-04-01 18:37:18 +00:00
|
|
|
if (IS_GEN7(dev))
|
|
|
|
I915_WRITE(GEN7_ERR_INT, 0xffffffff);
|
2009-06-08 06:40:19 +00:00
|
|
|
|
2014-04-01 18:37:19 +00:00
|
|
|
gen5_gt_irq_reset(dev);
|
2009-11-03 18:57:21 +00:00
|
|
|
|
2014-04-01 18:37:23 +00:00
|
|
|
ibx_irq_reset(dev);
|
2013-05-29 02:22:25 +00:00
|
|
|
}
|
2009-11-03 18:57:21 +00:00
|
|
|
|
2014-04-01 18:37:25 +00:00
|
|
|
static void ironlake_irq_preinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
ironlake_irq_reset(dev);
|
2013-05-29 02:22:25 +00:00
|
|
|
}
|
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
static void valleyview_irq_preinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-03-28 20:39:38 +00:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
/* VLV magic */
|
|
|
|
I915_WRITE(VLV_IMR, 0);
|
|
|
|
I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
|
|
|
|
I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
|
|
|
|
I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
|
|
|
|
|
|
|
|
/* and GT */
|
|
|
|
I915_WRITE(GTIIR, I915_READ(GTIIR));
|
|
|
|
I915_WRITE(GTIIR, I915_READ(GTIIR));
|
2013-07-12 20:43:25 +00:00
|
|
|
|
2014-04-01 18:37:19 +00:00
|
|
|
gen5_gt_irq_reset(dev);
|
2012-03-28 20:39:38 +00:00
|
|
|
|
|
|
|
I915_WRITE(DPINVGTT, 0xff);
|
|
|
|
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0xffff);
|
|
|
|
I915_WRITE(VLV_IIR, 0xffffffff);
|
|
|
|
I915_WRITE(VLV_IMR, 0xffffffff);
|
|
|
|
I915_WRITE(VLV_IER, 0x0);
|
|
|
|
POSTING_READ(VLV_IER);
|
|
|
|
}
|
|
|
|
|
2014-04-01 18:37:26 +00:00
|
|
|
static void gen8_irq_reset(struct drm_device *dev)
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int pipe;
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, 0);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
2014-04-01 18:37:14 +00:00
|
|
|
GEN8_IRQ_RESET_NDX(GT, 0);
|
|
|
|
GEN8_IRQ_RESET_NDX(GT, 1);
|
|
|
|
GEN8_IRQ_RESET_NDX(GT, 2);
|
|
|
|
GEN8_IRQ_RESET_NDX(GT, 3);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2014-04-01 18:37:26 +00:00
|
|
|
for_each_pipe(pipe)
|
2014-04-01 18:37:14 +00:00
|
|
|
GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2014-04-01 18:37:14 +00:00
|
|
|
GEN5_IRQ_RESET(GEN8_DE_PORT_);
|
|
|
|
GEN5_IRQ_RESET(GEN8_DE_MISC_);
|
|
|
|
GEN5_IRQ_RESET(GEN8_PCU_);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2014-04-01 18:37:23 +00:00
|
|
|
ibx_irq_reset(dev);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
2014-01-10 21:13:09 +00:00
|
|
|
|
2014-04-01 18:37:26 +00:00
|
|
|
static void gen8_irq_preinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
gen8_irq_reset(dev);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
|
|
|
|
2013-03-27 14:55:01 +00:00
|
|
|
static void ibx_hpd_irq_setup(struct drm_device *dev)
|
2011-09-19 20:31:02 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-27 14:55:01 +00:00
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
|
|
struct intel_encoder *intel_encoder;
|
2013-07-04 21:35:21 +00:00
|
|
|
u32 hotplug_irqs, hotplug, enabled_irqs = 0;
|
2013-03-27 14:55:01 +00:00
|
|
|
|
|
|
|
if (HAS_PCH_IBX(dev)) {
|
2013-07-04 21:35:21 +00:00
|
|
|
hotplug_irqs = SDE_HOTPLUG_MASK;
|
2013-03-27 14:55:01 +00:00
|
|
|
list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
|
2013-04-16 11:36:57 +00:00
|
|
|
if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
|
2013-07-04 21:35:21 +00:00
|
|
|
enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
|
2013-03-27 14:55:01 +00:00
|
|
|
} else {
|
2013-07-04 21:35:21 +00:00
|
|
|
hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
|
2013-03-27 14:55:01 +00:00
|
|
|
list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
|
2013-04-16 11:36:57 +00:00
|
|
|
if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
|
2013-07-04 21:35:21 +00:00
|
|
|
enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
|
2013-03-27 14:55:01 +00:00
|
|
|
}
|
2011-09-19 20:31:02 +00:00
|
|
|
|
2013-07-04 21:35:21 +00:00
|
|
|
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
|
2013-03-27 14:55:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable digital hotplug on the PCH, and configure the DP short pulse
|
|
|
|
* duration to 2ms (which is the minimum in the Display Port spec)
|
|
|
|
*
|
|
|
|
* This register is the same on all known PCH chips.
|
|
|
|
*/
|
2011-09-19 20:31:02 +00:00
|
|
|
hotplug = I915_READ(PCH_PORT_HOTPLUG);
|
|
|
|
hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
|
|
|
|
hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
|
|
|
|
hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
|
|
|
|
hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
|
|
|
|
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
|
|
|
|
}
|
|
|
|
|
2013-02-08 19:35:15 +00:00
|
|
|
static void ibx_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-27 14:55:01 +00:00
|
|
|
u32 mask;
|
2013-02-28 09:17:12 +00:00
|
|
|
|
2013-05-29 19:43:05 +00:00
|
|
|
if (HAS_PCH_NOP(dev))
|
|
|
|
return;
|
|
|
|
|
2014-04-01 18:37:17 +00:00
|
|
|
if (HAS_PCH_IBX(dev))
|
2014-03-07 19:34:46 +00:00
|
|
|
mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
|
2014-04-01 18:37:17 +00:00
|
|
|
else
|
2014-03-07 19:34:46 +00:00
|
|
|
mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
2014-04-01 18:37:16 +00:00
|
|
|
GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
|
2013-02-08 19:35:15 +00:00
|
|
|
I915_WRITE(SDEIMR, ~mask);
|
|
|
|
}
|
|
|
|
|
2013-07-12 20:43:26 +00:00
|
|
|
static void gen5_gt_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pm_irqs, gt_irqs;
|
|
|
|
|
|
|
|
pm_irqs = gt_irqs = 0;
|
|
|
|
|
|
|
|
dev_priv->gt_irq_mask = ~0;
|
2013-09-19 18:01:40 +00:00
|
|
|
if (HAS_L3_DPF(dev)) {
|
2013-07-12 20:43:26 +00:00
|
|
|
/* L3 parity interrupt is always unmasked. */
|
2013-09-19 18:13:41 +00:00
|
|
|
dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
|
|
|
|
gt_irqs |= GT_PARITY_ERROR(dev);
|
2013-07-12 20:43:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
gt_irqs |= GT_RENDER_USER_INTERRUPT;
|
|
|
|
if (IS_GEN5(dev)) {
|
|
|
|
gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
|
|
|
|
ILK_BSD_USER_INTERRUPT;
|
|
|
|
} else {
|
|
|
|
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
|
|
|
|
}
|
|
|
|
|
2014-04-01 18:37:15 +00:00
|
|
|
GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
|
2013-07-12 20:43:26 +00:00
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
2014-03-15 14:53:22 +00:00
|
|
|
pm_irqs |= dev_priv->pm_rps_events;
|
2013-07-12 20:43:26 +00:00
|
|
|
|
|
|
|
if (HAS_VEBOX(dev))
|
|
|
|
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
|
|
|
|
|
2013-08-06 21:57:15 +00:00
|
|
|
dev_priv->pm_irq_mask = 0xffffffff;
|
2014-04-01 18:37:15 +00:00
|
|
|
GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
|
2013-07-12 20:43:26 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
static int ironlake_irq_postinstall(struct drm_device *dev)
|
2009-06-08 06:40:19 +00:00
|
|
|
{
|
2013-06-27 11:44:58 +00:00
|
|
|
unsigned long irqflags;
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-12 23:01:56 +00:00
|
|
|
u32 display_mask, extra_mask;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 7) {
|
|
|
|
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
|
|
|
|
DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
|
|
|
|
DE_PLANEB_FLIP_DONE_IVB |
|
2014-03-07 19:34:46 +00:00
|
|
|
DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
|
2013-07-12 23:01:56 +00:00
|
|
|
extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
|
2014-03-07 19:34:46 +00:00
|
|
|
DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
|
2013-07-12 23:01:56 +00:00
|
|
|
} else {
|
|
|
|
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
|
|
|
|
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
|
2013-10-16 20:55:48 +00:00
|
|
|
DE_AUX_CHANNEL_A |
|
|
|
|
DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
|
|
|
|
DE_POISON);
|
2014-03-07 19:34:46 +00:00
|
|
|
extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
|
|
|
|
DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
|
2013-07-12 23:01:56 +00:00
|
|
|
}
|
2009-06-08 06:40:19 +00:00
|
|
|
|
2010-12-04 11:30:53 +00:00
|
|
|
dev_priv->irq_mask = ~display_mask;
|
2009-06-08 06:40:19 +00:00
|
|
|
|
2014-04-01 18:37:27 +00:00
|
|
|
I915_WRITE(HWSTAM, 0xeffe);
|
|
|
|
|
2014-04-01 18:37:22 +00:00
|
|
|
ibx_irq_pre_postinstall(dev);
|
|
|
|
|
2014-04-01 18:37:15 +00:00
|
|
|
GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
|
2009-06-08 06:40:19 +00:00
|
|
|
|
2013-07-12 20:43:26 +00:00
|
|
|
gen5_gt_irq_postinstall(dev);
|
2009-06-08 06:40:19 +00:00
|
|
|
|
2013-02-08 19:35:15 +00:00
|
|
|
ibx_irq_postinstall(dev);
|
2011-09-19 20:31:02 +00:00
|
|
|
|
2010-01-29 19:27:07 +00:00
|
|
|
if (IS_IRONLAKE_M(dev)) {
|
2013-06-27 11:44:59 +00:00
|
|
|
/* Enable PCU event interrupts
|
|
|
|
*
|
|
|
|
* spinlocking not required here for correctness since interrupt
|
2013-06-27 11:44:58 +00:00
|
|
|
* setup is guaranteed to run in single-threaded context. But we
|
|
|
|
* need it to make the assert_spin_locked happy. */
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2010-01-29 19:27:07 +00:00
|
|
|
ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
|
2013-06-27 11:44:58 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2010-01-29 19:27:07 +00:00
|
|
|
}
|
|
|
|
|
2009-06-08 06:40:19 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-04 17:23:07 +00:00
|
|
|
static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 pipestat_mask;
|
|
|
|
u32 iir_mask;
|
|
|
|
|
|
|
|
pipestat_mask = PIPESTAT_INT_STATUS_MASK |
|
|
|
|
PIPE_FIFO_UNDERRUN_STATUS;
|
|
|
|
|
|
|
|
I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
|
|
|
|
I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
|
|
|
|
POSTING_READ(PIPESTAT(PIPE_A));
|
|
|
|
|
|
|
|
pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
|
|
|
|
PIPE_CRC_DONE_INTERRUPT_STATUS;
|
|
|
|
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
|
|
|
|
PIPE_GMBUS_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
|
|
|
|
|
|
|
|
iir_mask = I915_DISPLAY_PORT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
|
|
|
dev_priv->irq_mask &= ~iir_mask;
|
|
|
|
|
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
I915_WRITE(VLV_IMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
|
|
|
|
POSTING_READ(VLV_IER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
u32 pipestat_mask;
|
|
|
|
u32 iir_mask;
|
|
|
|
|
|
|
|
iir_mask = I915_DISPLAY_PORT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
2014-03-10 17:44:48 +00:00
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
2014-03-04 17:23:07 +00:00
|
|
|
|
|
|
|
dev_priv->irq_mask |= iir_mask;
|
|
|
|
I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
|
|
|
|
I915_WRITE(VLV_IMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
I915_WRITE(VLV_IIR, iir_mask);
|
|
|
|
POSTING_READ(VLV_IIR);
|
|
|
|
|
|
|
|
pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
|
|
|
|
PIPE_CRC_DONE_INTERRUPT_STATUS;
|
|
|
|
|
|
|
|
i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
|
|
|
|
PIPE_GMBUS_INTERRUPT_STATUS);
|
|
|
|
i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
|
|
|
|
|
|
|
|
pipestat_mask = PIPESTAT_INT_STATUS_MASK |
|
|
|
|
PIPE_FIFO_UNDERRUN_STATUS;
|
|
|
|
I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
|
|
|
|
I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
|
|
|
|
POSTING_READ(PIPESTAT(PIPE_A));
|
|
|
|
}
|
|
|
|
|
|
|
|
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
if (dev_priv->display_irqs_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dev_priv->display_irqs_enabled = true;
|
|
|
|
|
|
|
|
if (dev_priv->dev->irq_enabled)
|
|
|
|
valleyview_display_irqs_install(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
if (!dev_priv->display_irqs_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dev_priv->display_irqs_enabled = false;
|
|
|
|
|
|
|
|
if (dev_priv->dev->irq_enabled)
|
|
|
|
valleyview_display_irqs_uninstall(dev_priv);
|
|
|
|
}
|
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
static int valleyview_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-06-27 15:52:10 +00:00
|
|
|
unsigned long irqflags;
|
2012-03-28 20:39:38 +00:00
|
|
|
|
2014-03-04 17:23:07 +00:00
|
|
|
dev_priv->irq_mask = ~0;
|
2012-03-28 20:39:38 +00:00
|
|
|
|
2012-12-11 13:05:07 +00:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
POSTING_READ(PORT_HOTPLUG_EN);
|
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
I915_WRITE(VLV_IMR, dev_priv->irq_mask);
|
2014-03-04 17:23:07 +00:00
|
|
|
I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
|
2012-03-28 20:39:38 +00:00
|
|
|
I915_WRITE(VLV_IIR, 0xffffffff);
|
|
|
|
POSTING_READ(VLV_IER);
|
|
|
|
|
2013-06-27 15:52:10 +00:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2014-03-04 17:23:07 +00:00
|
|
|
if (dev_priv->display_irqs_enabled)
|
|
|
|
valleyview_display_irqs_install(dev_priv);
|
2013-06-27 15:52:10 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2012-06-20 17:53:11 +00:00
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
I915_WRITE(VLV_IIR, 0xffffffff);
|
|
|
|
I915_WRITE(VLV_IIR, 0xffffffff);
|
|
|
|
|
2013-07-12 20:43:26 +00:00
|
|
|
gen5_gt_irq_postinstall(dev);
|
2012-03-28 20:39:38 +00:00
|
|
|
|
|
|
|
/* ack & enable invalid PTE error interrupts */
|
|
|
|
#if 0 /* FIXME: add support to irq handler for checking these bits */
|
|
|
|
I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
|
|
|
|
I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
|
2012-12-11 13:05:07 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* These are interrupts we'll toggle with the ring mask register */
|
|
|
|
uint32_t gt_interrupts[] = {
|
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
|
|
|
|
GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
|
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
|
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
|
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
|
|
|
|
0,
|
|
|
|
GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
|
|
|
|
};
|
|
|
|
|
2014-04-01 18:37:16 +00:00
|
|
|
for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
|
2014-04-01 18:37:15 +00:00
|
|
|
GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2014-04-08 00:22:44 +00:00
|
|
|
uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
|
2013-11-07 14:31:52 +00:00
|
|
|
GEN8_PIPE_CDCLK_CRC_DONE |
|
|
|
|
GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
|
2014-03-07 19:34:46 +00:00
|
|
|
uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
|
|
|
|
GEN8_PIPE_FIFO_UNDERRUN;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
int pipe;
|
2013-11-07 14:31:52 +00:00
|
|
|
dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
|
|
|
|
dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
|
|
|
|
dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2014-04-01 18:37:16 +00:00
|
|
|
for_each_pipe(pipe)
|
2014-04-01 18:37:15 +00:00
|
|
|
GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
|
|
|
|
de_pipe_enables);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2014-04-01 18:37:15 +00:00
|
|
|
GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int gen8_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-04-01 18:37:22 +00:00
|
|
|
ibx_irq_pre_postinstall(dev);
|
|
|
|
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
gen8_gt_irq_postinstall(dev_priv);
|
|
|
|
gen8_de_irq_postinstall(dev_priv);
|
|
|
|
|
|
|
|
ibx_irq_postinstall(dev);
|
|
|
|
|
|
|
|
I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
|
|
|
|
POSTING_READ(GEN8_MASTER_IRQ);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen8_irq_uninstall(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2014-04-01 18:37:24 +00:00
|
|
|
intel_hpd_irq_uninstall(dev_priv);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
|
2014-04-01 18:37:26 +00:00
|
|
|
gen8_irq_reset(dev);
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
}
|
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
static void valleyview_irq_uninstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-03-04 17:23:07 +00:00
|
|
|
unsigned long irqflags;
|
2012-03-28 20:39:38 +00:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2014-04-14 17:24:23 +00:00
|
|
|
I915_WRITE(VLV_MASTER_IER, 0);
|
|
|
|
|
2014-01-17 11:43:51 +00:00
|
|
|
intel_hpd_irq_uninstall(dev_priv);
|
2013-04-16 11:36:58 +00:00
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0xffff);
|
|
|
|
|
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
2014-03-04 17:23:07 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
if (dev_priv->display_irqs_enabled)
|
|
|
|
valleyview_display_irqs_uninstall(dev_priv);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
dev_priv->irq_mask = 0;
|
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
I915_WRITE(VLV_IIR, 0xffffffff);
|
|
|
|
I915_WRITE(VLV_IMR, 0xffffffff);
|
|
|
|
I915_WRITE(VLV_IER, 0x0);
|
|
|
|
POSTING_READ(VLV_IER);
|
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
static void ironlake_irq_uninstall(struct drm_device *dev)
|
2009-06-08 06:40:19 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-04-07 20:53:55 +00:00
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2014-01-17 11:43:51 +00:00
|
|
|
intel_hpd_irq_uninstall(dev_priv);
|
2013-04-16 11:36:58 +00:00
|
|
|
|
2014-04-01 18:37:25 +00:00
|
|
|
ironlake_irq_reset(dev);
|
2009-06-08 06:40:19 +00:00
|
|
|
}
|
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
static void i8xx_irq_preinstall(struct drm_device * dev)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-02-07 20:26:52 +00:00
|
|
|
int pipe;
|
2006-02-18 04:17:04 +00:00
|
|
|
|
2011-02-07 20:26:52 +00:00
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
2012-04-24 21:59:44 +00:00
|
|
|
I915_WRITE16(IMR, 0xffff);
|
|
|
|
I915_WRITE16(IER, 0x0);
|
|
|
|
POSTING_READ16(IER);
|
2012-04-22 20:13:57 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int i8xx_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-10-16 20:55:56 +00:00
|
|
|
unsigned long irqflags;
|
2012-04-22 20:13:57 +00:00
|
|
|
|
|
|
|
I915_WRITE16(EMR,
|
|
|
|
~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
|
|
|
|
|
|
|
|
/* Unmask the interrupts that we always want on. */
|
|
|
|
dev_priv->irq_mask =
|
|
|
|
~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
|
|
I915_WRITE16(IMR, dev_priv->irq_mask);
|
|
|
|
|
|
|
|
I915_WRITE16(IER,
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
|
|
|
|
I915_USER_INTERRUPT);
|
|
|
|
POSTING_READ16(IER);
|
|
|
|
|
2013-10-16 20:55:56 +00:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2014-02-10 16:42:47 +00:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
2013-10-16 20:55:56 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
2012-04-22 20:13:57 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-19 21:16:44 +00:00
|
|
|
/*
|
|
|
|
* Returns true when a page flip has completed.
|
|
|
|
*/
|
|
|
|
static bool i8xx_handle_vblank(struct drm_device *dev,
|
2013-11-28 15:30:01 +00:00
|
|
|
int plane, int pipe, u32 iir)
|
2013-02-19 21:16:44 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-11-28 15:30:01 +00:00
|
|
|
u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
|
2013-02-19 21:16:44 +00:00
|
|
|
|
|
|
|
if (!drm_handle_vblank(dev, pipe))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if ((iir & flip_pending) == 0)
|
|
|
|
return false;
|
|
|
|
|
2013-11-28 15:30:01 +00:00
|
|
|
intel_prepare_page_flip(dev, plane);
|
2013-02-19 21:16:44 +00:00
|
|
|
|
|
|
|
/* We detect FlipDone by looking for the change in PendingFlip from '1'
|
|
|
|
* to '0' on the following vblank, i.e. IIR has the Pendingflip
|
|
|
|
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
|
|
|
|
* the flip is completed (no longer pending). Since this doesn't raise
|
|
|
|
* an interrupt per se, we watch for the change at vblank.
|
|
|
|
*/
|
|
|
|
if (I915_READ16(ISR) & flip_pending)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
intel_finish_page_flip(dev, pipe);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-10-02 13:10:55 +00:00
|
|
|
static irqreturn_t i8xx_irq_handler(int irq, void *arg)
|
2012-04-22 20:13:57 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-22 20:13:57 +00:00
|
|
|
u16 iir, new_iir;
|
|
|
|
u32 pipe_stats[2];
|
|
|
|
unsigned long irqflags;
|
|
|
|
int pipe;
|
|
|
|
u16 flip_mask =
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
|
|
|
|
|
|
|
iir = I915_READ16(IIR);
|
|
|
|
if (iir == 0)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
while (iir & ~flip_mask) {
|
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
|
|
* have been cleared after the pipestat interrupt was received.
|
|
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
|
|
* interrupts (for non-MSI).
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2014-02-25 15:11:26 +00:00
|
|
|
i915_handle_error(dev, false,
|
|
|
|
"Command parser error, iir 0x%08x",
|
|
|
|
iir);
|
2012-04-22 20:13:57 +00:00
|
|
|
|
|
|
|
for_each_pipe(pipe) {
|
|
|
|
int reg = PIPESTAT(pipe);
|
|
|
|
pipe_stats[pipe] = I915_READ(reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the PIPE*STAT regs before the IIR
|
|
|
|
*/
|
2014-01-17 09:44:31 +00:00
|
|
|
if (pipe_stats[pipe] & 0x8000ffff)
|
2012-04-22 20:13:57 +00:00
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
I915_WRITE16(IIR, iir & ~flip_mask);
|
|
|
|
new_iir = I915_READ16(IIR); /* Flush posted writes */
|
|
|
|
|
2012-04-26 21:28:09 +00:00
|
|
|
i915_update_dri1_breadcrumb(dev);
|
2012-04-22 20:13:57 +00:00
|
|
|
|
|
|
|
if (iir & I915_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
|
|
|
|
2013-10-16 20:55:55 +00:00
|
|
|
for_each_pipe(pipe) {
|
2013-11-28 15:30:01 +00:00
|
|
|
int plane = pipe;
|
2014-01-10 07:50:12 +00:00
|
|
|
if (HAS_FBC(dev))
|
2013-11-28 15:30:01 +00:00
|
|
|
plane = !plane;
|
|
|
|
|
2013-10-16 20:55:55 +00:00
|
|
|
if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
|
2013-11-28 15:30:01 +00:00
|
|
|
i8xx_handle_vblank(dev, plane, pipe, iir))
|
|
|
|
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
|
2012-04-22 20:13:57 +00:00
|
|
|
|
2013-10-16 20:55:55 +00:00
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
2013-10-18 14:37:07 +00:00
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2014-01-17 09:44:31 +00:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
|
|
|
|
intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
|
2013-10-16 20:55:55 +00:00
|
|
|
}
|
2012-04-22 20:13:57 +00:00
|
|
|
|
|
|
|
iir = new_iir;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i8xx_irq_uninstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-22 20:13:57 +00:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
for_each_pipe(pipe) {
|
|
|
|
/* Clear enable bits; then clear status bits */
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
|
|
|
|
}
|
|
|
|
I915_WRITE16(IMR, 0xffff);
|
|
|
|
I915_WRITE16(IER, 0x0);
|
|
|
|
I915_WRITE16(IIR, I915_READ16(IIR));
|
|
|
|
}
|
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
static void i915_irq_preinstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:44 +00:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
}
|
|
|
|
|
2012-04-24 21:59:48 +00:00
|
|
|
I915_WRITE16(HWSTAM, 0xeffe);
|
2012-04-24 21:59:44 +00:00
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i915_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:50 +00:00
|
|
|
u32 enable_mask;
|
2013-10-16 20:55:56 +00:00
|
|
|
unsigned long irqflags;
|
2012-04-24 21:59:44 +00:00
|
|
|
|
2012-04-24 21:59:50 +00:00
|
|
|
I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
|
|
|
|
|
|
|
|
/* Unmask the interrupts that we always want on. */
|
|
|
|
dev_priv->irq_mask =
|
|
|
|
~(I915_ASLE_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
|
|
|
|
|
|
enable_mask =
|
|
|
|
I915_ASLE_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
|
|
|
|
I915_USER_INTERRUPT;
|
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
2012-12-11 13:05:07 +00:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
POSTING_READ(PORT_HOTPLUG_EN);
|
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
/* Enable in IER... */
|
|
|
|
enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
|
|
|
|
/* and unmask in IMR */
|
|
|
|
dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
|
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(IER, enable_mask);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
|
2013-04-29 10:02:54 +00:00
|
|
|
i915_enable_asle_pipestat(dev);
|
2012-12-11 13:05:07 +00:00
|
|
|
|
2013-10-16 20:55:56 +00:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2014-02-10 16:42:47 +00:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
2013-10-16 20:55:56 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
2012-12-11 13:05:07 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-19 21:16:44 +00:00
|
|
|
/*
|
|
|
|
* Returns true when a page flip has completed.
|
|
|
|
*/
|
|
|
|
static bool i915_handle_vblank(struct drm_device *dev,
|
|
|
|
int plane, int pipe, u32 iir)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-02-19 21:16:44 +00:00
|
|
|
u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
|
|
|
|
|
|
|
|
if (!drm_handle_vblank(dev, pipe))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if ((iir & flip_pending) == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
intel_prepare_page_flip(dev, plane);
|
|
|
|
|
|
|
|
/* We detect FlipDone by looking for the change in PendingFlip from '1'
|
|
|
|
* to '0' on the following vblank, i.e. IIR has the Pendingflip
|
|
|
|
* asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
|
|
|
|
* the flip is completed (no longer pending). Since this doesn't raise
|
|
|
|
* an interrupt per se, we watch for the change at vblank.
|
|
|
|
*/
|
|
|
|
if (I915_READ(ISR) & flip_pending)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
intel_finish_page_flip(dev, pipe);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2012-10-02 13:10:55 +00:00
|
|
|
static irqreturn_t i915_irq_handler(int irq, void *arg)
|
2012-04-24 21:59:44 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:47 +00:00
|
|
|
u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
|
2012-04-24 21:59:44 +00:00
|
|
|
unsigned long irqflags;
|
2012-04-24 21:59:50 +00:00
|
|
|
u32 flip_mask =
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
|
|
|
int pipe, ret = IRQ_NONE;
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
iir = I915_READ(IIR);
|
2012-04-24 21:59:50 +00:00
|
|
|
do {
|
|
|
|
bool irq_received = (iir & ~flip_mask) != 0;
|
2012-04-24 21:59:47 +00:00
|
|
|
bool blc_event = false;
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
|
|
* have been cleared after the pipestat interrupt was received.
|
|
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
|
|
* interrupts (for non-MSI).
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2014-02-25 15:11:26 +00:00
|
|
|
i915_handle_error(dev, false,
|
|
|
|
"Command parser error, iir 0x%08x",
|
|
|
|
iir);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
for_each_pipe(pipe) {
|
|
|
|
int reg = PIPESTAT(pipe);
|
|
|
|
pipe_stats[pipe] = I915_READ(reg);
|
|
|
|
|
2012-04-24 21:59:50 +00:00
|
|
|
/* Clear the PIPE*STAT regs before the IIR */
|
2012-04-24 21:59:44 +00:00
|
|
|
if (pipe_stats[pipe] & 0x8000ffff) {
|
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
2012-04-24 21:59:50 +00:00
|
|
|
irq_received = true;
|
2012-04-24 21:59:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
if (!irq_received)
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Consume port. Then clear IIR or we'll miss events */
|
2014-04-01 07:54:36 +00:00
|
|
|
if (I915_HAS_HOTPLUG(dev) &&
|
|
|
|
iir & I915_DISPLAY_PORT_INTERRUPT)
|
|
|
|
i9xx_hpd_irq_handler(dev);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
2012-04-24 21:59:50 +00:00
|
|
|
I915_WRITE(IIR, iir & ~flip_mask);
|
2012-04-24 21:59:44 +00:00
|
|
|
new_iir = I915_READ(IIR); /* Flush posted writes */
|
|
|
|
|
|
|
|
if (iir & I915_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
|
|
|
|
|
|
|
for_each_pipe(pipe) {
|
2012-04-24 21:59:50 +00:00
|
|
|
int plane = pipe;
|
2014-01-10 07:50:12 +00:00
|
|
|
if (HAS_FBC(dev))
|
2012-04-24 21:59:50 +00:00
|
|
|
plane = !plane;
|
2013-02-19 21:16:44 +00:00
|
|
|
|
2012-04-24 21:59:47 +00:00
|
|
|
if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
|
2013-02-19 21:16:44 +00:00
|
|
|
i915_handle_vblank(dev, plane, pipe, iir))
|
|
|
|
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
|
|
|
|
blc_event = true;
|
2013-10-16 20:55:55 +00:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
2013-10-18 14:37:07 +00:00
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2014-01-17 09:44:31 +00:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
|
|
|
|
intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
|
2012-04-24 21:59:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (blc_event || (iir & I915_ASLE_INTERRUPT))
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
|
|
|
/* With MSI, interrupts are only generated when iir
|
|
|
|
* transitions from zero to nonzero. If another bit got
|
|
|
|
* set while we were handling the existing iir bits, then
|
|
|
|
* we would never get another interrupt.
|
|
|
|
*
|
|
|
|
* This is fine on non-MSI as well, as if we hit this path
|
|
|
|
* we avoid exiting the interrupt handler only to generate
|
|
|
|
* another one.
|
|
|
|
*
|
|
|
|
* Note that for MSI this could cause a stray interrupt report
|
|
|
|
* if an interrupt landed in the time between writing IIR and
|
|
|
|
* the posting read. This should be rare enough to never
|
|
|
|
* trigger the 99% of 100,000 interrupts test for disabling
|
|
|
|
* stray interrupts.
|
|
|
|
*/
|
2012-04-24 21:59:50 +00:00
|
|
|
ret = IRQ_HANDLED;
|
2012-04-24 21:59:44 +00:00
|
|
|
iir = new_iir;
|
2012-04-24 21:59:50 +00:00
|
|
|
} while (iir & ~flip_mask);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
2012-04-26 21:28:09 +00:00
|
|
|
i915_update_dri1_breadcrumb(dev);
|
2012-04-24 21:59:47 +00:00
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i915_irq_uninstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:44 +00:00
|
|
|
int pipe;
|
|
|
|
|
2014-01-17 11:43:51 +00:00
|
|
|
intel_hpd_irq_uninstall(dev_priv);
|
2013-04-16 11:36:58 +00:00
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
|
|
|
}
|
|
|
|
|
2012-04-24 21:59:48 +00:00
|
|
|
I915_WRITE16(HWSTAM, 0xffff);
|
2012-04-24 21:59:49 +00:00
|
|
|
for_each_pipe(pipe) {
|
|
|
|
/* Clear enable bits; then clear status bits */
|
2012-04-24 21:59:44 +00:00
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
2012-04-24 21:59:49 +00:00
|
|
|
I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
|
|
|
|
}
|
2012-04-24 21:59:44 +00:00
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
|
|
|
|
I915_WRITE(IIR, I915_READ(IIR));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i965_irq_preinstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:44 +00:00
|
|
|
int pipe;
|
|
|
|
|
2012-05-11 17:01:31 +00:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
I915_WRITE(HWSTAM, 0xeffe);
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int i965_irq_postinstall(struct drm_device *dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:51 +00:00
|
|
|
u32 enable_mask;
|
2012-04-24 21:59:44 +00:00
|
|
|
u32 error_mask;
|
2013-06-27 15:52:10 +00:00
|
|
|
unsigned long irqflags;
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
/* Unmask the interrupts that we always want on. */
|
2012-04-24 21:59:51 +00:00
|
|
|
dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
|
2012-05-11 17:01:31 +00:00
|
|
|
I915_DISPLAY_PORT_INTERRUPT |
|
2012-04-24 21:59:51 +00:00
|
|
|
I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
|
|
|
|
|
|
|
|
enable_mask = ~dev_priv->irq_mask;
|
2013-02-19 13:16:39 +00:00
|
|
|
enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
|
2012-04-24 21:59:51 +00:00
|
|
|
enable_mask |= I915_USER_INTERRUPT;
|
|
|
|
|
|
|
|
if (IS_G4X(dev))
|
|
|
|
enable_mask |= I915_BSD_USER_INTERRUPT;
|
2012-04-24 21:59:44 +00:00
|
|
|
|
2013-06-27 15:52:10 +00:00
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked check happy. */
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2014-02-10 16:42:47 +00:00
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
|
|
|
i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
|
2013-06-27 15:52:10 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable some error detection, note the instruction error mask
|
|
|
|
* bit is reserved, so we leave it masked.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev)) {
|
|
|
|
error_mask = ~(GM45_ERROR_PAGE_TABLE |
|
|
|
|
GM45_ERROR_MEM_PRIV |
|
|
|
|
GM45_ERROR_CP_PRIV |
|
|
|
|
I915_ERROR_MEMORY_REFRESH);
|
|
|
|
} else {
|
|
|
|
error_mask = ~(I915_ERROR_PAGE_TABLE |
|
|
|
|
I915_ERROR_MEMORY_REFRESH);
|
|
|
|
}
|
|
|
|
I915_WRITE(EMR, error_mask);
|
|
|
|
|
|
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
|
|
I915_WRITE(IER, enable_mask);
|
|
|
|
POSTING_READ(IER);
|
|
|
|
|
2012-12-11 13:05:07 +00:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
POSTING_READ(PORT_HOTPLUG_EN);
|
|
|
|
|
2013-04-29 10:02:54 +00:00
|
|
|
i915_enable_asle_pipestat(dev);
|
2012-12-11 13:05:07 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-25 17:06:51 +00:00
|
|
|
static void i915_hpd_irq_setup(struct drm_device *dev)
|
2012-12-11 13:05:07 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-02-28 09:17:12 +00:00
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
2013-04-16 11:36:57 +00:00
|
|
|
struct intel_encoder *intel_encoder;
|
2012-12-11 13:05:07 +00:00
|
|
|
u32 hotplug_en;
|
|
|
|
|
2013-06-27 15:52:15 +00:00
|
|
|
assert_spin_locked(&dev_priv->irq_lock);
|
|
|
|
|
2013-02-25 17:06:51 +00:00
|
|
|
if (I915_HAS_HOTPLUG(dev)) {
|
|
|
|
hotplug_en = I915_READ(PORT_HOTPLUG_EN);
|
|
|
|
hotplug_en &= ~HOTPLUG_INT_EN_MASK;
|
|
|
|
/* Note HDMI and DP share hotplug bits */
|
2013-02-28 09:17:12 +00:00
|
|
|
/* enable bits are the same for all generations */
|
2013-04-16 11:36:57 +00:00
|
|
|
list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
|
|
|
|
if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
|
|
|
|
hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
|
2013-02-25 17:06:51 +00:00
|
|
|
/* Programming the CRT detection parameters tends
|
|
|
|
to generate a spurious hotplug event about three
|
|
|
|
seconds later. So just do it once.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev))
|
|
|
|
hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
|
2013-03-27 14:47:11 +00:00
|
|
|
hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
|
2013-02-25 17:06:51 +00:00
|
|
|
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
|
2012-04-24 21:59:44 +00:00
|
|
|
|
2013-02-25 17:06:51 +00:00
|
|
|
/* Ignore TV since it's buggy */
|
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
|
|
|
|
}
|
2012-04-24 21:59:44 +00:00
|
|
|
}
|
|
|
|
|
2012-10-02 13:10:55 +00:00
|
|
|
static irqreturn_t i965_irq_handler(int irq, void *arg)
|
2012-04-24 21:59:44 +00:00
|
|
|
{
|
|
|
|
struct drm_device *dev = (struct drm_device *) arg;
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:44 +00:00
|
|
|
u32 iir, new_iir;
|
|
|
|
u32 pipe_stats[I915_MAX_PIPES];
|
|
|
|
unsigned long irqflags;
|
|
|
|
int ret = IRQ_NONE, pipe;
|
2013-02-19 13:16:39 +00:00
|
|
|
u32 flip_mask =
|
|
|
|
I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
|
|
|
|
I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
iir = I915_READ(IIR);
|
|
|
|
|
|
|
|
for (;;) {
|
2014-01-17 09:35:15 +00:00
|
|
|
bool irq_received = (iir & ~flip_mask) != 0;
|
2012-04-24 21:59:46 +00:00
|
|
|
bool blc_event = false;
|
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
/* Can't rely on pipestat interrupt bit in iir as it might
|
|
|
|
* have been cleared after the pipestat interrupt was received.
|
|
|
|
* It doesn't set the bit in iir again, but it still produces
|
|
|
|
* interrupts (for non-MSI).
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
|
2014-02-25 15:11:26 +00:00
|
|
|
i915_handle_error(dev, false,
|
|
|
|
"Command parser error, iir 0x%08x",
|
|
|
|
iir);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
for_each_pipe(pipe) {
|
|
|
|
int reg = PIPESTAT(pipe);
|
|
|
|
pipe_stats[pipe] = I915_READ(reg);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the PIPE*STAT regs before the IIR
|
|
|
|
*/
|
|
|
|
if (pipe_stats[pipe] & 0x8000ffff) {
|
|
|
|
I915_WRITE(reg, pipe_stats[pipe]);
|
2014-01-17 09:35:15 +00:00
|
|
|
irq_received = true;
|
2012-04-24 21:59:44 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
|
|
|
|
if (!irq_received)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
|
|
|
/* Consume port. Then clear IIR or we'll miss events */
|
2014-04-01 07:54:36 +00:00
|
|
|
if (iir & I915_DISPLAY_PORT_INTERRUPT)
|
|
|
|
i9xx_hpd_irq_handler(dev);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
2013-02-19 13:16:39 +00:00
|
|
|
I915_WRITE(IIR, iir & ~flip_mask);
|
2012-04-24 21:59:44 +00:00
|
|
|
new_iir = I915_READ(IIR); /* Flush posted writes */
|
|
|
|
|
|
|
|
if (iir & I915_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[RCS]);
|
|
|
|
if (iir & I915_BSD_USER_INTERRUPT)
|
|
|
|
notify_ring(dev, &dev_priv->ring[VCS]);
|
|
|
|
|
|
|
|
for_each_pipe(pipe) {
|
2012-04-24 21:59:46 +00:00
|
|
|
if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
|
2013-02-19 21:16:44 +00:00
|
|
|
i915_handle_vblank(dev, pipe, pipe, iir))
|
|
|
|
flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
|
|
|
|
blc_event = true;
|
2013-10-16 20:55:55 +00:00
|
|
|
|
|
|
|
if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
|
2013-10-18 14:37:07 +00:00
|
|
|
i9xx_pipe_crc_irq_handler(dev, pipe);
|
2012-04-24 21:59:44 +00:00
|
|
|
|
2014-01-17 09:44:31 +00:00
|
|
|
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
|
|
|
|
intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
|
2014-01-17 09:44:32 +00:00
|
|
|
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
|
2014-01-17 09:44:31 +00:00
|
|
|
}
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
if (blc_event || (iir & I915_ASLE_INTERRUPT))
|
|
|
|
intel_opregion_asle_intr(dev);
|
|
|
|
|
2012-12-01 12:53:44 +00:00
|
|
|
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
|
|
|
|
gmbus_irq_handler(dev);
|
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
/* With MSI, interrupts are only generated when iir
|
|
|
|
* transitions from zero to nonzero. If another bit got
|
|
|
|
* set while we were handling the existing iir bits, then
|
|
|
|
* we would never get another interrupt.
|
|
|
|
*
|
|
|
|
* This is fine on non-MSI as well, as if we hit this path
|
|
|
|
* we avoid exiting the interrupt handler only to generate
|
|
|
|
* another one.
|
|
|
|
*
|
|
|
|
* Note that for MSI this could cause a stray interrupt report
|
|
|
|
* if an interrupt landed in the time between writing IIR and
|
|
|
|
* the posting read. This should be rare enough to never
|
|
|
|
* trigger the 99% of 100,000 interrupts test for disabling
|
|
|
|
* stray interrupts.
|
|
|
|
*/
|
|
|
|
iir = new_iir;
|
|
|
|
}
|
|
|
|
|
2012-04-26 21:28:09 +00:00
|
|
|
i915_update_dri1_breadcrumb(dev);
|
2012-04-24 21:59:46 +00:00
|
|
|
|
2012-04-24 21:59:44 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i965_irq_uninstall(struct drm_device * dev)
|
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-04-24 21:59:44 +00:00
|
|
|
int pipe;
|
|
|
|
|
|
|
|
if (!dev_priv)
|
|
|
|
return;
|
|
|
|
|
2014-01-17 11:43:51 +00:00
|
|
|
intel_hpd_irq_uninstall(dev_priv);
|
2013-04-16 11:36:58 +00:00
|
|
|
|
2012-05-11 17:01:31 +00:00
|
|
|
I915_WRITE(PORT_HOTPLUG_EN, 0);
|
|
|
|
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
|
2012-04-24 21:59:44 +00:00
|
|
|
|
|
|
|
I915_WRITE(HWSTAM, 0xffffffff);
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe), 0);
|
|
|
|
I915_WRITE(IMR, 0xffffffff);
|
|
|
|
I915_WRITE(IER, 0x0);
|
|
|
|
|
|
|
|
for_each_pipe(pipe)
|
|
|
|
I915_WRITE(PIPESTAT(pipe),
|
|
|
|
I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
|
|
|
|
I915_WRITE(IIR, I915_READ(IIR));
|
|
|
|
}
|
|
|
|
|
2014-01-17 11:43:51 +00:00
|
|
|
static void intel_hpd_irq_reenable(unsigned long data)
|
2013-04-16 11:36:58 +00:00
|
|
|
{
|
2014-03-31 11:27:17 +00:00
|
|
|
struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
|
2013-04-16 11:36:58 +00:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
|
|
unsigned long irqflags;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
|
|
|
for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
|
|
|
|
struct drm_connector *connector;
|
|
|
|
|
|
|
|
if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
|
|
|
|
|
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
|
|
|
|
if (intel_connector->encoder->hpd_pin == i) {
|
|
|
|
if (connector->polled != intel_connector->polled)
|
|
|
|
DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
|
|
|
|
drm_get_connector_name(connector));
|
|
|
|
connector->polled = intel_connector->polled;
|
|
|
|
if (!connector->polled)
|
|
|
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (dev_priv->display.hpd_irq_setup)
|
|
|
|
dev_priv->display.hpd_irq_setup(dev);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2011-06-28 20:00:41 +00:00
|
|
|
void intel_irq_init(struct drm_device *dev)
|
|
|
|
{
|
2012-04-24 21:59:41 +00:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
|
2012-11-14 16:14:04 +00:00
|
|
|
INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
|
2012-08-08 21:35:35 +00:00
|
|
|
INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
|
2012-11-02 18:55:07 +00:00
|
|
|
INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
|
2012-04-24 21:59:41 +00:00
|
|
|
|
2014-03-15 14:53:22 +00:00
|
|
|
/* Let's track the enabled rps events */
|
|
|
|
dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
|
|
|
|
|
2012-11-14 16:14:04 +00:00
|
|
|
setup_timer(&dev_priv->gpu_error.hangcheck_timer,
|
|
|
|
i915_hangcheck_elapsed,
|
2012-12-01 20:03:21 +00:00
|
|
|
(unsigned long) dev);
|
2014-01-17 11:43:51 +00:00
|
|
|
setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
|
2013-04-16 11:36:58 +00:00
|
|
|
(unsigned long) dev_priv);
|
2012-12-01 20:03:21 +00:00
|
|
|
|
2012-12-08 12:48:13 +00:00
|
|
|
pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 12:53:48 +00:00
|
|
|
|
2013-10-11 18:52:44 +00:00
|
|
|
if (IS_GEN2(dev)) {
|
|
|
|
dev->max_vblank_count = 0;
|
|
|
|
dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
|
|
|
|
} else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
|
2011-06-28 20:00:41 +00:00
|
|
|
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
|
|
|
|
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
|
2013-09-25 16:55:26 +00:00
|
|
|
} else {
|
|
|
|
dev->driver->get_vblank_counter = i915_get_vblank_counter;
|
|
|
|
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
2011-06-28 20:00:41 +00:00
|
|
|
}
|
|
|
|
|
2013-09-23 11:48:50 +00:00
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
2011-08-13 00:05:54 +00:00
|
|
|
dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
|
2013-09-23 11:48:50 +00:00
|
|
|
dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
|
|
|
|
}
|
2011-06-28 20:00:41 +00:00
|
|
|
|
2012-03-28 20:39:38 +00:00
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
|
|
dev->driver->irq_handler = valleyview_irq_handler;
|
|
|
|
dev->driver->irq_preinstall = valleyview_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = valleyview_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = valleyview_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = valleyview_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = valleyview_disable_vblank;
|
2013-02-25 17:06:48 +00:00
|
|
|
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
drm/i915/bdw: Implement interrupt changes
The interrupt handling implementation remains the same as previous
generations with the 4 types of registers, status, identity, mask, and
enable. However the layout of where the bits go have changed entirely.
To address these changes, all of the interrupt vfuncs needed special
gen8 code.
The way it works is there is a top level status register now which
informs the interrupt service routine which unit caused the interrupt,
and therefore which interrupt registers to read to process the
interrupt. For display the division is quite logical, a set of interrupt
registers for each pipe, and in addition to those, a set each for "misc"
and port.
For GT the things get a bit hairy, as seen by the code. Each of the GT
units has it's own bits defined. They all look *very similar* and
resides in 16 bits of a GT register. As an example, RCS and BCS share
register 0. To compact the code a bit, at a slight expense to
complexity, this is exactly how the code works as well. 2 structures are
added to the ring buffer so that our ring buffer interrupt handling code
knows which ring shares the interrupt registers, and a shift value (ie.
the top or bottom 16 bits of the register).
The above allows us to kept the interrupt register caching scheme, the
per interrupt enables, and the code to mask and unmask interrupts
relatively clean (again at the cost of some more complexity).
Most of the GT units mentioned above are command streamers, and so the
symmetry should work quite well for even the yet to be implemented rings
which Broadwell adds.
v2: Fixes up a couple of bugs, and is more verbose about errors in the
Broadwell interrupt handler.
v3: fix DE_MISC IER offset
v4: Simplify interrupts:
I totally misread the docs the first time I implemented interrupts, and
so this should greatly simplify the mess. Unlike GEN6, we never touch
the regular mask registers in irq_get/put.
v5: Rebased on to of recent pch hotplug setup changes.
v6: Fixup on top of moving num_pipes to intel_info.
v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
wired up ibx_hpd_irq_setup for gen8.
v8: Rebase on top of Jani's asle handling rework.
v9: Rebase on top of Ben's VECS enabling for Haswell, where he
unfortunately went OCD on the gt irq #defines. Not that they're still
not yet fully consistent:
- Used the GT_RENDER_ #defines + bdw shifts.
- Dropped the shift from the L3_PARITY stuff, seemed clearer.
- s/irq_refcount/irq_refcount.gt/
v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
refactoring from Zhao Yakui <yakui.zhao@intel.com>
v11: Rebase on top of the interrupt cleanups in upstream.
v12: Rebase on top of Ben's DPF changes in upstream.
v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
exactly needs to be done. Requested by Ben.
v14: Fix the patch.
- Drop the mask of reserved bits and assorted logic, it doesn't match
the spec.
- Do the posting read inconditionally instead of commenting it out.
- Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
- Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
we actually will need to use them.
- Enclose macros in do {} while (0) (checkpatch).
- Clear DE_MISC interrupt bits only after having processed them.
- Fix whitespace fail (checkpatch).
- Fix overtly long lines where appropriate (checkpatch).
- Don't use typedef'ed private_t (maintainer-scripts).
- Align the function parameter list correctly.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
bikeshed
2013-11-03 04:07:09 +00:00
|
|
|
} else if (IS_GEN8(dev)) {
|
|
|
|
dev->driver->irq_handler = gen8_irq_handler;
|
|
|
|
dev->driver->irq_preinstall = gen8_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = gen8_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = gen8_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = gen8_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = gen8_disable_vblank;
|
|
|
|
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
|
2011-06-28 20:00:41 +00:00
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
|
|
|
dev->driver->irq_handler = ironlake_irq_handler;
|
|
|
|
dev->driver->irq_preinstall = ironlake_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = ironlake_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = ironlake_irq_uninstall;
|
|
|
|
dev->driver->enable_vblank = ironlake_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = ironlake_disable_vblank;
|
2013-03-27 14:55:01 +00:00
|
|
|
dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
|
2011-06-28 20:00:41 +00:00
|
|
|
} else {
|
2012-04-22 20:13:57 +00:00
|
|
|
if (INTEL_INFO(dev)->gen == 2) {
|
|
|
|
dev->driver->irq_preinstall = i8xx_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = i8xx_irq_postinstall;
|
|
|
|
dev->driver->irq_handler = i8xx_irq_handler;
|
|
|
|
dev->driver->irq_uninstall = i8xx_irq_uninstall;
|
2012-04-24 21:59:44 +00:00
|
|
|
} else if (INTEL_INFO(dev)->gen == 3) {
|
|
|
|
dev->driver->irq_preinstall = i915_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = i915_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = i915_irq_uninstall;
|
|
|
|
dev->driver->irq_handler = i915_irq_handler;
|
2012-12-11 13:05:07 +00:00
|
|
|
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
2012-04-22 20:13:57 +00:00
|
|
|
} else {
|
2012-04-24 21:59:44 +00:00
|
|
|
dev->driver->irq_preinstall = i965_irq_preinstall;
|
|
|
|
dev->driver->irq_postinstall = i965_irq_postinstall;
|
|
|
|
dev->driver->irq_uninstall = i965_irq_uninstall;
|
|
|
|
dev->driver->irq_handler = i965_irq_handler;
|
2013-02-25 17:06:51 +00:00
|
|
|
dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
|
2012-04-22 20:13:57 +00:00
|
|
|
}
|
2011-06-28 20:00:41 +00:00
|
|
|
dev->driver->enable_vblank = i915_enable_vblank;
|
|
|
|
dev->driver->disable_vblank = i915_disable_vblank;
|
|
|
|
}
|
|
|
|
}
|
2012-12-11 13:05:07 +00:00
|
|
|
|
|
|
|
void intel_hpd_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-04-16 11:36:55 +00:00
|
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
|
|
struct drm_connector *connector;
|
2013-06-27 15:52:15 +00:00
|
|
|
unsigned long irqflags;
|
2013-04-16 11:36:55 +00:00
|
|
|
int i;
|
2012-12-11 13:05:07 +00:00
|
|
|
|
2013-04-16 11:36:55 +00:00
|
|
|
for (i = 1; i < HPD_NUM_PINS; i++) {
|
|
|
|
dev_priv->hpd_stats[i].hpd_cnt = 0;
|
|
|
|
dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
|
|
|
|
}
|
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
connector->polled = intel_connector->polled;
|
|
|
|
if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
|
|
|
|
connector->polled = DRM_CONNECTOR_POLL_HPD;
|
|
|
|
}
|
2013-06-27 15:52:15 +00:00
|
|
|
|
|
|
|
/* Interrupt setup is already guaranteed to be single-threaded, this is
|
|
|
|
* just to make the assert_spin_locked checks happy. */
|
|
|
|
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
|
2012-12-11 13:05:07 +00:00
|
|
|
if (dev_priv->display.hpd_irq_setup)
|
|
|
|
dev_priv->display.hpd_irq_setup(dev);
|
2013-06-27 15:52:15 +00:00
|
|
|
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
|
2012-12-11 13:05:07 +00:00
|
|
|
}
|
2013-08-19 16:18:09 +00:00
|
|
|
|
2014-03-07 23:08:15 +00:00
|
|
|
/* Disable interrupts so we can allow runtime PM. */
|
2014-03-07 23:12:32 +00:00
|
|
|
void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
|
2013-08-19 16:18:09 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-03-07 23:12:32 +00:00
|
|
|
dev->driver->irq_uninstall(dev);
|
2014-03-07 23:08:15 +00:00
|
|
|
dev_priv->pm.irqs_disabled = true;
|
2013-08-19 16:18:09 +00:00
|
|
|
}
|
|
|
|
|
2014-03-07 23:08:15 +00:00
|
|
|
/* Restore interrupts so we can recover from runtime PM. */
|
2014-03-07 23:12:32 +00:00
|
|
|
void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
|
2013-08-19 16:18:09 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-03-07 23:08:15 +00:00
|
|
|
dev_priv->pm.irqs_disabled = false;
|
2014-03-07 23:12:32 +00:00
|
|
|
dev->driver->irq_preinstall(dev);
|
|
|
|
dev->driver->irq_postinstall(dev);
|
2013-08-19 16:18:09 +00:00
|
|
|
}
|