forked from Minki/linux
drm/i915: Deobfuscate the render p-state obfuscation
The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -452,7 +452,7 @@ typedef struct drm_i915_private {
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u32 savePIPEB_DATA_N1;
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u32 savePIPEB_LINK_M1;
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u32 savePIPEB_LINK_N1;
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u32 saveRSTDBYCTL;
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u32 saveMCHBAR_RENDER_STANDBY;
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struct {
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struct drm_mm gtt_space;
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@ -272,23 +272,23 @@ static void i915_hotplug_work_func(struct work_struct *work)
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static void i915_handle_rps_change(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 slow_up, slow_down, max_avg, min_avg;
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u32 busy_up, busy_down, max_avg, min_avg;
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u16 rgvswctl;
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u8 new_delay = dev_priv->cur_delay;
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I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
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slow_up = I915_READ(RCPREVBSYTUPAVG);
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slow_down = I915_READ(RCPREVBSYTDNAVG);
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busy_up = I915_READ(RCPREVBSYTUPAVG);
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busy_down = I915_READ(RCPREVBSYTDNAVG);
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max_avg = I915_READ(RCBMAXAVG);
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min_avg = I915_READ(RCBMINAVG);
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/* Handle RCS change request from hw */
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if (slow_up > max_avg) {
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if (busy_up > max_avg) {
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if (dev_priv->cur_delay != dev_priv->max_delay)
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new_delay = dev_priv->cur_delay - 1;
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if (new_delay < dev_priv->max_delay)
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new_delay = dev_priv->max_delay;
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} else if (slow_down < min_avg) {
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} else if (busy_down < min_avg) {
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if (dev_priv->cur_delay != dev_priv->min_delay)
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new_delay = dev_priv->cur_delay + 1;
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if (new_delay > dev_priv->min_delay)
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@ -300,8 +300,8 @@ static void i915_handle_rps_change(struct drm_device *dev)
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rgvswctl = I915_READ(MEMSWCTL);
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if (rgvswctl & MEMCTL_CMD_STS) {
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DRM_ERROR("gpu slow, RCS change rejected\n");
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return; /* still slow with another command */
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DRM_ERROR("gpu busy, RCS change rejected\n");
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return; /* still busy with another command */
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}
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/* Program the new state */
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@ -907,7 +907,7 @@
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#define RCBMINAVG 0x111a0
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#define RCUPEI 0x111b0
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#define RCDNEI 0x111b4
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#define RSTDBYCTL 0x111b8
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#define MCHBAR_RENDER_STANDBY 0x111b8
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#define RCX_SW_EXIT (1<<23)
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#define RSX_STATUS_MASK 0x00700000
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#define VIDCTL 0x111c0
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@ -682,7 +682,8 @@ void i915_restore_display(struct drm_device *dev)
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I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
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I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
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I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
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I915_WRITE(RSTDBYCTL, dev_priv->saveRSTDBYCTL);
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I915_WRITE(MCHBAR_RENDER_STANDBY,
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dev_priv->saveMCHBAR_RENDER_STANDBY);
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} else {
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I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
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I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
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@ -746,7 +747,8 @@ int i915_save_state(struct drm_device *dev)
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dev_priv->saveGTIMR = I915_READ(GTIMR);
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dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
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dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
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dev_priv->saveRSTDBYCTL = I915_READ(RSTDBYCTL);
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dev_priv->saveMCHBAR_RENDER_STANDBY =
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I915_READ(MCHBAR_RENDER_STANDBY);
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} else {
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dev_priv->saveIER = I915_READ(IER);
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dev_priv->saveIMR = I915_READ(IMR);
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@ -4770,8 +4770,8 @@ void intel_init_clock_gating(struct drm_device *dev)
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if (obj_priv) {
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I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) &
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~RCX_SW_EXIT);
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I915_WRITE(MCHBAR_RENDER_STANDBY,
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I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
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}
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}
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}
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