DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright (c) 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef __INTEL_DRV_H__
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#define __INTEL_DRV_H__
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2014-05-28 21:39:03 +00:00
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#include <linux/async.h>
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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#include <linux/i2c.h>
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2013-08-06 19:32:18 +00:00
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#include <linux/hdmi.h>
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2012-10-02 17:01:07 +00:00
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#include <drm/i915_drm.h>
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2009-09-10 22:28:06 +00:00
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#include "i915_drv.h"
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2012-10-02 17:01:07 +00:00
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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2014-05-02 04:02:48 +00:00
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#include <drm/drm_dp_mst_helper.h>
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2014-09-05 20:04:46 +00:00
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#include <drm/drm_rect.h>
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2015-03-20 14:18:01 +00:00
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#include <drm/drm_atomic.h>
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2010-08-07 10:01:35 +00:00
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2013-03-27 23:03:25 +00:00
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/**
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* _wait_for - magic (register) wait macro
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*
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* Does the right thing for modeset paths when run under kdgb or similar atomic
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* contexts. Note that it's important that we check the condition again after
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* having timed out, since the timeout could be due to preemption or similar and
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* we've never had a chance to check the condition before the timeout.
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*/
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2010-08-23 16:43:35 +00:00
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#define _wait_for(COND, MS, W) ({ \
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2013-03-27 23:03:25 +00:00
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
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2010-08-07 10:01:35 +00:00
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int ret__ = 0; \
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2011-08-16 19:34:10 +00:00
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while (!(COND)) { \
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2010-08-07 10:01:35 +00:00
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if (time_after(jiffies, timeout__)) { \
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2013-03-27 23:03:25 +00:00
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if (!(COND)) \
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ret__ = -ETIMEDOUT; \
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2010-08-07 10:01:35 +00:00
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break; \
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} \
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2015-03-20 19:28:08 +00:00
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if ((W) && drm_can_sleep()) { \
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usleep_range((W)*1000, (W)*2000); \
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2012-09-02 05:59:48 +00:00
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} else { \
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cpu_relax(); \
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} \
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2010-08-07 10:01:35 +00:00
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} \
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ret__; \
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})
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2010-08-23 16:43:35 +00:00
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
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2013-03-28 10:31:04 +00:00
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#define wait_for_atomic_us(COND, US) _wait_for((COND), \
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DIV_ROUND_UP((US), 1000), 0)
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2010-08-23 16:43:35 +00:00
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2014-01-10 15:10:20 +00:00
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#define KHz(x) (1000 * (x))
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#define MHz(x) KHz(1000 * (x))
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2010-09-07 19:54:59 +00:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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/*
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* Display related stuff
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*/
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/* store information about an Ixxx DVO */
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/* The i830->i865 use multiple DVOs with multiple i2cs */
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/* the i915, i945 have a single sDVO i2c bus - which is different */
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#define MAX_OUTPUTS 6
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/* maximum connectors per crtcs in the mode set */
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2014-03-10 11:36:23 +00:00
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/* Maximum cursor sizes */
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#define GEN2_CURSOR_WIDTH 64
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#define GEN2_CURSOR_HEIGHT 64
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2014-03-28 14:17:49 +00:00
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#define MAX_CURSOR_WIDTH 256
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#define MAX_CURSOR_HEIGHT 256
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2014-03-10 11:36:23 +00:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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#define INTEL_I2C_BUS_DVO 1
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#define INTEL_I2C_BUS_SDVO 2
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/* these are outputs from the chip - integrated only
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external chips are via DVO or SDVO output */
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2014-10-27 19:47:52 +00:00
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enum intel_output_type {
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INTEL_OUTPUT_UNUSED = 0,
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INTEL_OUTPUT_ANALOG = 1,
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INTEL_OUTPUT_DVO = 2,
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INTEL_OUTPUT_SDVO = 3,
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INTEL_OUTPUT_LVDS = 4,
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INTEL_OUTPUT_TVOUT = 5,
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INTEL_OUTPUT_HDMI = 6,
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INTEL_OUTPUT_DISPLAYPORT = 7,
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INTEL_OUTPUT_EDP = 8,
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INTEL_OUTPUT_DSI = 9,
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INTEL_OUTPUT_UNKNOWN = 10,
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INTEL_OUTPUT_DP_MST = 11,
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};
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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#define INTEL_DVO_CHIP_NONE 0
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#define INTEL_DVO_CHIP_LVDS 1
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#define INTEL_DVO_CHIP_TMDS 2
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#define INTEL_DVO_CHIP_TVOUT 4
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2014-04-14 05:48:24 +00:00
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#define INTEL_DSI_VIDEO_MODE 0
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#define INTEL_DSI_COMMAND_MODE 1
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2013-08-27 12:12:17 +00:00
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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struct intel_framebuffer {
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struct drm_framebuffer base;
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2010-11-08 19:18:58 +00:00
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struct drm_i915_gem_object *obj;
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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};
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2010-08-25 21:45:57 +00:00
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struct intel_fbdev {
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struct drm_fb_helper helper;
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2014-02-07 20:10:38 +00:00
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struct intel_framebuffer *fb;
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2010-08-25 21:45:57 +00:00
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struct list_head fbdev_list;
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struct drm_display_mode *our_mode;
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2014-03-07 16:57:51 +00:00
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int preferred_bpp;
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2010-08-25 21:45:57 +00:00
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};
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DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
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2010-03-25 18:11:14 +00:00
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struct intel_encoder {
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2010-09-09 14:14:28 +00:00
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struct drm_encoder base;
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drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-05 20:34:27 +00:00
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2014-10-27 19:47:52 +00:00
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enum intel_output_type type;
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2014-03-03 14:15:28 +00:00
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unsigned int cloneable;
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2010-03-25 18:11:14 +00:00
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void (*hot_plug)(struct intel_encoder *);
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2013-03-26 23:44:52 +00:00
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bool (*compute_config)(struct intel_encoder *,
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2015-01-15 12:55:21 +00:00
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struct intel_crtc_state *);
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2012-11-26 16:22:07 +00:00
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void (*pre_pll_enable)(struct intel_encoder *);
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2012-09-06 20:15:40 +00:00
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void (*pre_enable)(struct intel_encoder *);
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2012-06-29 20:40:09 +00:00
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void (*enable)(struct intel_encoder *);
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2013-03-26 23:44:53 +00:00
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void (*mode_set)(struct intel_encoder *intel_encoder);
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2012-06-29 20:40:09 +00:00
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void (*disable)(struct intel_encoder *);
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2012-09-06 20:15:40 +00:00
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void (*post_disable)(struct intel_encoder *);
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2015-07-08 20:45:49 +00:00
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void (*post_pll_disable)(struct intel_encoder *);
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2012-07-02 11:10:34 +00:00
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/* Read out the current hw state of this connector, returning true if
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* the encoder is active. If the encoder is enabled it also set the pipe
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* it is connected to in the pipe parameter. */
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bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
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2013-05-15 00:08:26 +00:00
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/* Reconstructs the equivalent mode flags for the current hardware
|
2013-06-12 09:47:24 +00:00
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* state. This must be called _after_ display->get_pipe_config has
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2013-06-28 04:59:06 +00:00
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* pre-filled the pipe config. Note that intel_encoder->base.crtc must
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|
|
|
* be set correctly before calling this function. */
|
2013-05-15 00:08:26 +00:00
|
|
|
void (*get_config)(struct intel_encoder *,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2014-08-18 11:42:45 +00:00
|
|
|
/*
|
|
|
|
* Called during system suspend after all pending requests for the
|
|
|
|
* encoder are flushed (for example for DP AUX transactions) and
|
|
|
|
* device interrupts are disabled.
|
|
|
|
*/
|
|
|
|
void (*suspend)(struct intel_encoder *);
|
2009-08-24 05:50:24 +00:00
|
|
|
int crtc_mask;
|
2013-02-25 17:06:49 +00:00
|
|
|
enum hpd_pin hpd_pin;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
};
|
|
|
|
|
2012-10-19 11:51:49 +00:00
|
|
|
struct intel_panel {
|
2012-10-19 11:51:50 +00:00
|
|
|
struct drm_display_mode *fixed_mode;
|
2013-12-10 08:07:36 +00:00
|
|
|
struct drm_display_mode *downclock_mode;
|
2012-10-26 09:03:59 +00:00
|
|
|
int fitting_mode;
|
2013-11-08 14:48:54 +00:00
|
|
|
|
|
|
|
/* backlight */
|
|
|
|
struct {
|
2013-11-08 14:48:55 +00:00
|
|
|
bool present;
|
2013-11-08 14:48:54 +00:00
|
|
|
u32 level;
|
2014-06-24 15:27:40 +00:00
|
|
|
u32 min;
|
2013-11-08 14:48:56 +00:00
|
|
|
u32 max;
|
2013-11-08 14:48:54 +00:00
|
|
|
bool enabled;
|
2013-11-08 14:49:02 +00:00
|
|
|
bool combination_mode; /* gen 2/4 only */
|
|
|
|
bool active_low_pwm;
|
2015-06-26 09:02:10 +00:00
|
|
|
|
|
|
|
/* PWM chip */
|
2015-09-30 17:04:57 +00:00
|
|
|
bool util_pin_active_low; /* bxt+ */
|
|
|
|
u8 controller; /* bxt+ only */
|
2015-06-26 09:02:10 +00:00
|
|
|
struct pwm_device *pwm;
|
|
|
|
|
2013-11-08 14:48:54 +00:00
|
|
|
struct backlight_device *device;
|
2014-08-13 09:10:12 +00:00
|
|
|
|
2015-09-14 11:03:48 +00:00
|
|
|
/* Connector and platform specific backlight functions */
|
|
|
|
int (*setup)(struct intel_connector *connector, enum pipe pipe);
|
|
|
|
uint32_t (*get)(struct intel_connector *connector);
|
|
|
|
void (*set)(struct intel_connector *connector, uint32_t level);
|
|
|
|
void (*disable)(struct intel_connector *connector);
|
|
|
|
void (*enable)(struct intel_connector *connector);
|
|
|
|
uint32_t (*hz_to_pwm)(struct intel_connector *connector,
|
|
|
|
uint32_t hz);
|
|
|
|
void (*power)(struct intel_connector *, bool enable);
|
|
|
|
} backlight;
|
2012-10-19 11:51:49 +00:00
|
|
|
};
|
|
|
|
|
2010-03-30 06:39:28 +00:00
|
|
|
struct intel_connector {
|
|
|
|
struct drm_connector base;
|
drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-05 20:34:27 +00:00
|
|
|
/*
|
|
|
|
* The fixed encoder this connector is connected to.
|
|
|
|
*/
|
2010-09-09 15:20:55 +00:00
|
|
|
struct intel_encoder *encoder;
|
drm/i915: stage modeset output changes
This is the core of the new modeset logic.
The current code which is based upon the crtc helper code first
updates all the link of the new display pipeline and then calls the
lower-level set_mode function to execute the required callbacks to get
there. The issue with this approach is that for disabling we need to
know the _current_ display pipe state, not the new one.
Hence we need to stage the new state of the display pipe and only
update it once we have disabled the current configuration and before we
start to update the hw registers with the new configuration.
This patch here just prepares the ground by switching the new output
state computation to these staging pointers. To make it clearer,
rename the old update_output_state function to stage_output_state.
A few peculiarities:
- We're also calling the set_mode function at various places to update
properties. Hence after a successfule modeset we need to stage the
current configuration (for otherwise we might fall back again). This
happens automatically because as part of the (successful) modeset we
need to copy the staged state to the real one. But for the hw
readout code we need to make sure that this happens, too.
- Teach the new staged output state computation code the required
smarts to handle the disabling of outputs. The current code handles
this in a special case, but to better handle global modeset changes
covering more than one crtc, we want to do this all in the same
low-level modeset code.
- The actual modeset code is still a bit ugly and wants to know the new
crtc->enabled state a bit early. Follow-on patches will clean that
up, for now we have to apply the staged output configuration early,
outside of the set_mode functions.
- Improve/add comments in stage_output_state.
Essentially all that is left to do now is move the disabling code into
set_mode and then move the staged state update code also into
set_mode, at the right place between disabling things and calling the
mode_set callbacks for the new configuration.
v2: Disabling a crtc works by passing in a NULL mode or fb, userspace
doesn't hand in the list of connectors. We therefore need to detect
this case manually and tear down all the output links.
v3: Properly update the output staging pointers after having read out
the hw state.
v4: Simplify the code, add more DRM_DEBUG_KMS output and check a few
assumptions with WARN_ON. Essentially all things that I've noticed
while debugging issues in other places of the code.
v4: Correctly disable the old set of connectors when enabling an
already enabled crtc on a new set of crtc. Reported by Paulo Zanoni.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-07-05 20:34:27 +00:00
|
|
|
|
2012-07-02 11:10:34 +00:00
|
|
|
/* Reads out the current hw, returning true if the connector is enabled
|
|
|
|
* and active (i.e. dpms ON state). */
|
|
|
|
bool (*get_hw_state)(struct intel_connector *);
|
2012-10-19 11:51:49 +00:00
|
|
|
|
2014-02-11 15:12:48 +00:00
|
|
|
/*
|
|
|
|
* Removes all interfaces through which the connector is accessible
|
|
|
|
* - like sysfs, debugfs entries -, so that no new operations can be
|
|
|
|
* started on the connector. Also makes sure all currently pending
|
|
|
|
* operations finish before returing.
|
|
|
|
*/
|
|
|
|
void (*unregister)(struct intel_connector *);
|
|
|
|
|
2012-10-19 11:51:49 +00:00
|
|
|
/* Panel info for eDP and LVDS */
|
|
|
|
struct intel_panel panel;
|
2012-10-19 11:51:52 +00:00
|
|
|
|
|
|
|
/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
|
|
|
|
struct edid *edid;
|
2014-09-02 19:04:00 +00:00
|
|
|
struct edid *detect_edid;
|
2013-04-16 11:36:55 +00:00
|
|
|
|
|
|
|
/* since POLL and HPD connectors may use the same HPD line keep the native
|
|
|
|
state of connector->polled in case hotplug storm detection changes it */
|
|
|
|
u8 polled;
|
2014-05-02 04:02:48 +00:00
|
|
|
|
|
|
|
void *port; /* store this opaque as its illegal to dereference it */
|
|
|
|
|
|
|
|
struct intel_dp *mst_port;
|
2010-03-30 06:39:28 +00:00
|
|
|
};
|
|
|
|
|
2013-04-19 11:36:51 +00:00
|
|
|
typedef struct dpll {
|
|
|
|
/* given values */
|
|
|
|
int n;
|
|
|
|
int m1, m2;
|
|
|
|
int p1, p2;
|
|
|
|
/* derived values */
|
|
|
|
int dot;
|
|
|
|
int vco;
|
|
|
|
int m;
|
|
|
|
int p;
|
|
|
|
} intel_clock_t;
|
|
|
|
|
2015-06-04 08:21:28 +00:00
|
|
|
struct intel_atomic_state {
|
|
|
|
struct drm_atomic_state base;
|
|
|
|
|
2015-06-15 10:33:56 +00:00
|
|
|
unsigned int cdclk;
|
2015-06-04 08:21:28 +00:00
|
|
|
bool dpll_set;
|
|
|
|
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
|
|
|
|
};
|
|
|
|
|
2014-09-05 20:04:46 +00:00
|
|
|
struct intel_plane_state {
|
2014-12-01 23:40:13 +00:00
|
|
|
struct drm_plane_state base;
|
2014-09-05 20:04:46 +00:00
|
|
|
struct drm_rect src;
|
|
|
|
struct drm_rect dst;
|
|
|
|
struct drm_rect clip;
|
|
|
|
bool visible;
|
2014-12-24 15:59:06 +00:00
|
|
|
|
2015-04-07 22:28:36 +00:00
|
|
|
/*
|
|
|
|
* scaler_id
|
|
|
|
* = -1 : not using a scaler
|
|
|
|
* >= 0 : using a scalers
|
|
|
|
*
|
|
|
|
* plane requiring a scaler:
|
|
|
|
* - During check_plane, its bit is set in
|
|
|
|
* crtc_state->scaler_state.scaler_users by calling helper function
|
2015-06-22 07:50:32 +00:00
|
|
|
* update_scaler_plane.
|
2015-04-07 22:28:36 +00:00
|
|
|
* - scaler_id indicates the scaler it got assigned.
|
|
|
|
*
|
|
|
|
* plane doesn't require a scaler:
|
|
|
|
* - this can happen when scaling is no more required or plane simply
|
|
|
|
* got disabled.
|
|
|
|
* - During check_plane, corresponding bit is reset in
|
|
|
|
* crtc_state->scaler_state.scaler_users by calling helper function
|
2015-06-22 07:50:32 +00:00
|
|
|
* update_scaler_plane.
|
2015-04-07 22:28:36 +00:00
|
|
|
*/
|
|
|
|
int scaler_id;
|
2015-06-15 10:33:54 +00:00
|
|
|
|
|
|
|
struct drm_intel_sprite_colorkey ckey;
|
2014-09-05 20:04:46 +00:00
|
|
|
};
|
|
|
|
|
2015-01-20 12:51:52 +00:00
|
|
|
struct intel_initial_plane_config {
|
2015-02-05 17:22:18 +00:00
|
|
|
struct intel_framebuffer *fb;
|
2015-01-20 12:51:44 +00:00
|
|
|
unsigned int tiling;
|
2014-03-07 16:57:48 +00:00
|
|
|
int size;
|
|
|
|
u32 base;
|
|
|
|
};
|
|
|
|
|
2015-04-07 22:28:36 +00:00
|
|
|
#define SKL_MIN_SRC_W 8
|
|
|
|
#define SKL_MAX_SRC_W 4096
|
|
|
|
#define SKL_MIN_SRC_H 8
|
2015-04-27 20:48:39 +00:00
|
|
|
#define SKL_MAX_SRC_H 4096
|
2015-04-07 22:28:36 +00:00
|
|
|
#define SKL_MIN_DST_W 8
|
|
|
|
#define SKL_MAX_DST_W 4096
|
|
|
|
#define SKL_MIN_DST_H 8
|
2015-04-27 20:48:39 +00:00
|
|
|
#define SKL_MAX_DST_H 4096
|
2015-04-07 22:28:36 +00:00
|
|
|
|
|
|
|
struct intel_scaler {
|
|
|
|
int in_use;
|
|
|
|
uint32_t mode;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct intel_crtc_scaler_state {
|
|
|
|
#define SKL_NUM_SCALERS 2
|
|
|
|
struct intel_scaler scalers[SKL_NUM_SCALERS];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* scaler_users: keeps track of users requesting scalers on this crtc.
|
|
|
|
*
|
|
|
|
* If a bit is set, a user is using a scaler.
|
|
|
|
* Here user can be a plane or crtc as defined below:
|
|
|
|
* bits 0-30 - plane (bit position is index from drm_plane_index)
|
|
|
|
* bit 31 - crtc
|
|
|
|
*
|
|
|
|
* Instead of creating a new index to cover planes and crtc, using
|
|
|
|
* existing drm_plane_index for planes which is well less than 31
|
|
|
|
* planes and bit 31 for crtc. This should be fine to cover all
|
|
|
|
* our platforms.
|
|
|
|
*
|
|
|
|
* intel_atomic_setup_scalers will setup available scalers to users
|
|
|
|
* requesting scalers. It will gracefully fail if request exceeds
|
|
|
|
* avilability.
|
|
|
|
*/
|
|
|
|
#define SKL_CRTC_INDEX 31
|
|
|
|
unsigned scaler_users;
|
|
|
|
|
|
|
|
/* scaler used by crtc for panel fitting purpose */
|
|
|
|
int scaler_id;
|
|
|
|
};
|
|
|
|
|
2015-07-15 12:15:51 +00:00
|
|
|
/* drm_mode->private_flags */
|
|
|
|
#define I915_MODE_FLAG_INHERITED 1
|
|
|
|
|
2015-09-24 22:53:15 +00:00
|
|
|
struct intel_pipe_wm {
|
|
|
|
struct intel_wm_level wm[5];
|
|
|
|
uint32_t linetime;
|
|
|
|
bool fbc_wm_enabled;
|
|
|
|
bool pipe_enabled;
|
|
|
|
bool sprites_enabled;
|
|
|
|
bool sprites_scaled;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct skl_pipe_wm {
|
|
|
|
struct skl_wm_level wm[8];
|
|
|
|
struct skl_wm_level trans_wm;
|
|
|
|
uint32_t linetime;
|
|
|
|
};
|
|
|
|
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state {
|
2015-01-15 12:55:22 +00:00
|
|
|
struct drm_crtc_state base;
|
|
|
|
|
2013-06-06 12:55:52 +00:00
|
|
|
/**
|
|
|
|
* quirks - bitfield with hw state readout quirks
|
|
|
|
*
|
|
|
|
* For various reasons the hw state readout code might not be able to
|
|
|
|
* completely faithfully read out the current state. These cases are
|
|
|
|
* tracked with quirk flags so that fastboot and state checker can act
|
|
|
|
* accordingly.
|
|
|
|
*/
|
2014-04-13 10:00:33 +00:00
|
|
|
#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
|
2013-06-06 12:55:52 +00:00
|
|
|
unsigned long quirks;
|
|
|
|
|
2015-08-27 13:44:05 +00:00
|
|
|
bool update_pipe;
|
|
|
|
|
2013-09-04 15:25:28 +00:00
|
|
|
/* Pipe source size (ie. panel fitter input size)
|
|
|
|
* All planes will be positioned inside this space,
|
|
|
|
* and get clipped at the edges. */
|
|
|
|
int pipe_src_w, pipe_src_h;
|
|
|
|
|
2013-03-26 23:44:55 +00:00
|
|
|
/* Whether to set up the PCH/FDI. Note that we never allow sharing
|
|
|
|
* between pch encoders and cpu encoders. */
|
|
|
|
bool has_pch_encoder;
|
2013-03-26 23:44:56 +00:00
|
|
|
|
2014-11-05 22:26:08 +00:00
|
|
|
/* Are we sending infoframes on the attached port */
|
|
|
|
bool has_infoframe;
|
|
|
|
|
2013-04-17 18:15:07 +00:00
|
|
|
/* CPU Transcoder for the pipe. Currently this can only differ from the
|
|
|
|
* pipe on Haswell (where we have a special eDP transcoder). */
|
|
|
|
enum transcoder cpu_transcoder;
|
|
|
|
|
2013-03-26 23:44:56 +00:00
|
|
|
/*
|
|
|
|
* Use reduced/limited/broadcast rbg range, compressing from the full
|
|
|
|
* range fed into the crtcs.
|
|
|
|
*/
|
|
|
|
bool limited_color_range;
|
|
|
|
|
2013-04-02 21:42:31 +00:00
|
|
|
/* DP has a bunch of special case unfortunately, so mark the pipe
|
|
|
|
* accordingly. */
|
|
|
|
bool has_dp_encoder;
|
2013-04-25 15:54:44 +00:00
|
|
|
|
2014-04-24 21:54:47 +00:00
|
|
|
/* Whether we should send NULL infoframes. Required for audio. */
|
|
|
|
bool has_hdmi_sink;
|
|
|
|
|
2014-04-24 21:54:52 +00:00
|
|
|
/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
|
|
|
|
* has_dp_encoder is set. */
|
|
|
|
bool has_audio;
|
|
|
|
|
2013-04-25 15:54:44 +00:00
|
|
|
/*
|
|
|
|
* Enable dithering, used when the selected pipe bpp doesn't match the
|
|
|
|
* plane bpp.
|
|
|
|
*/
|
2013-03-26 23:44:57 +00:00
|
|
|
bool dither;
|
2013-03-28 09:42:02 +00:00
|
|
|
|
|
|
|
/* Controls for the clock computation, to override various stages. */
|
|
|
|
bool clock_set;
|
|
|
|
|
2013-04-30 12:01:45 +00:00
|
|
|
/* SDVO TV has a bunch of special case. To make multifunction encoders
|
|
|
|
* work correctly, we need to track this at runtime.*/
|
|
|
|
bool sdvo_tv_clock;
|
|
|
|
|
drm/i915: implement fdi auto-dithering
So on a bunch of setups we only have 2 fdi lanes available, e.g. hsw
VGA or 3 pipes on ivb. And seemingly a lot of modes don't quite fit
into this, among them the default 1080p mode.
The solution is to dither down the pipe a bit so that everything fits,
which this patch implements.
But ports compute their state under the assumption that the bpp they
pick will be the one selected, e.g. the display port bw computations
won't work otherwise. Now we could adjust our code to again up-dither
to the computed DP link parameters, but that's pointless.
So instead when the pipe needs to adjust parameters we need to retry
the pipe_config computation at the encoder stage. Furthermore we need
to inform encoders that they should not increase bandwidth
requirements if possible. This is required for the hdmi code, which
prefers the pipe to up-dither to either of the two possible hdmi bpc
values.
LVDS has a similar requirement, although that's probably only
theoretical in nature: It's unlikely that we'll ever see an 8bpc
high-res lvds panel (which is required to hit the 2 fdi lane limit).
eDP is the only thing which could increase the pipe_bpp setting again,
even when in the retry-loop. This could hit the WARN. Two reasons for
not bothering:
- On many eDP panels we'll get a black screen if the bpp settings
don't match vbt. So failing the modeset is the right thing to do.
But since that also means it's the only way to light up the panel,
it should work. So we shouldn't be able to hit this WARN.
- There are still opens around the eDP panel handling, and maybe we
need additional tricks. Before that happens it's imo no use trying
to be too clever.
Worst case we just need to kill that WARN or maybe fail the compute
config stage if the eDP connector can't get the bpp setting it wants.
And since this can only happen with an fdi link in between and so for
pch eDP panels it's rather unlikely to blow up, if ever.
v2: Rebased on top of a bikeshed from Paulo.
v3: Improve commit message around eDP handling with the stuff
things with Imre.
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-20 23:00:16 +00:00
|
|
|
/*
|
|
|
|
* crtc bandwidth limit, don't increase pipe bpp or clock if not really
|
|
|
|
* required. This is set in the 2nd loop of calling encoder's
|
|
|
|
* ->compute_config if the first pick doesn't work out.
|
|
|
|
*/
|
|
|
|
bool bw_constrained;
|
|
|
|
|
2013-03-28 09:42:02 +00:00
|
|
|
/* Settings for the intel dpll used on pretty much everything but
|
|
|
|
* haswell. */
|
2013-04-19 11:36:51 +00:00
|
|
|
struct dpll dpll;
|
2013-03-28 09:42:02 +00:00
|
|
|
|
2013-06-07 21:10:32 +00:00
|
|
|
/* Selected dpll when shared or DPLL_ID_PRIVATE. */
|
|
|
|
enum intel_dpll_id shared_dpll;
|
|
|
|
|
2014-11-13 14:55:17 +00:00
|
|
|
/*
|
|
|
|
* - PORT_CLK_SEL for DDI ports on HSW/BDW.
|
|
|
|
* - enum skl_dpll on SKL
|
|
|
|
*/
|
2014-06-25 19:01:54 +00:00
|
|
|
uint32_t ddi_pll_sel;
|
|
|
|
|
2013-06-05 11:34:20 +00:00
|
|
|
/* Actual register state of the dpll, for shared dpll cross-checking. */
|
|
|
|
struct intel_dpll_hw_state dpll_hw_state;
|
|
|
|
|
2013-03-26 23:44:57 +00:00
|
|
|
int pipe_bpp;
|
drm/i915: clear up the fdi/dp set_m_n confusion
There's a rather decent confusion going on around transcoder m_n
values. So let's clarify:
- All dp encoders need this, either on the pch transcoder if it's a
pch port, or on the cpu transcoder/pipe if it's a cpu port.
- fdi links need to have the right m_n values for the fdi link set in
the cpu transcoder.
To handle the pch vs transcoder stuff a bit better, extract transcoder
set_m_n helpers. To make them simpler, set intel_crtc->cpu_transcoder
als in ironlake_crtc_mode_set, so that gen5+ (where the cpu m_n
registers are all at the same offset) can use it.
Haswell modeset is decently confused about dp vs. edp vs. fdi. dp vs.
edp works exactly the same as dp (since there's no pch dp any more),
so use that as a check. And only set up the fdi m_n values if we
really have a pch encoder present (which means we have a VGA encoder).
On ilk+ we've called ironlake_set_m_n both for cpu_edp and for pch
encoders. Now that dp_set_m_n handles all dp links (thanks to the
pch encoder check), we can ditch the cpu_edp stuff from the
fdi_set_m_n function.
Since the dp_m_n values are not readily available, we need to
carefully coax the edp values out of the encoder. Hence we can't (yet)
kill this superflous complexity.
v2: Rebase on top of the ivb fdi B/C check patch - we need to properly
clear intel_crtc->fdi_lane, otherwise those checks will misfire.
v3: Rebased on top of a s/IS_HASWELL/HAS_DDI/ patch from Paulo Zanoni.
v4: Drop the addition of has_dp_encoder, it's in the wrong patch (Jesse).
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-02 21:38:10 +00:00
|
|
|
struct intel_link_m_n dp_m_n;
|
2013-06-01 15:16:21 +00:00
|
|
|
|
2014-04-05 06:43:28 +00:00
|
|
|
/* m2_n2 for eDP downclock */
|
|
|
|
struct intel_link_m_n dp_m2_n2;
|
2014-08-05 14:51:22 +00:00
|
|
|
bool has_drrs;
|
2014-04-05 06:43:28 +00:00
|
|
|
|
2013-06-01 15:16:21 +00:00
|
|
|
/*
|
|
|
|
* Frequence the dpll for the port should run at. Differs from the
|
2013-09-06 20:28:59 +00:00
|
|
|
* adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
|
|
|
|
* already multiplied by pixel_multiplier.
|
2013-03-28 09:41:58 +00:00
|
|
|
*/
|
2013-06-01 15:16:21 +00:00
|
|
|
int port_clock;
|
|
|
|
|
2013-03-26 23:44:53 +00:00
|
|
|
/* Used by SDVO (and if we ever fix it, HDMI). */
|
|
|
|
unsigned pixel_multiplier;
|
2013-04-25 19:55:01 +00:00
|
|
|
|
2015-07-06 13:39:15 +00:00
|
|
|
uint8_t lane_count;
|
|
|
|
|
2013-04-25 19:55:01 +00:00
|
|
|
/* Panel fitter controls for gen2-gen4 + VLV */
|
2013-04-25 19:55:02 +00:00
|
|
|
struct {
|
|
|
|
u32 control;
|
|
|
|
u32 pgm_ratios;
|
2013-04-25 20:52:16 +00:00
|
|
|
u32 lvds_border_bits;
|
2013-04-25 19:55:02 +00:00
|
|
|
} gmch_pfit;
|
|
|
|
|
|
|
|
/* Panel fitter placement and size for Ironlake+ */
|
|
|
|
struct {
|
|
|
|
u32 pos;
|
|
|
|
u32 size;
|
2013-08-27 16:04:17 +00:00
|
|
|
bool enabled;
|
2014-05-29 12:10:22 +00:00
|
|
|
bool force_thru;
|
2013-04-25 19:55:02 +00:00
|
|
|
} pch_pfit;
|
2013-02-13 17:04:45 +00:00
|
|
|
|
2013-02-14 15:54:22 +00:00
|
|
|
/* FDI configuration, only valid if has_pch_encoder is set. */
|
2013-02-13 17:04:45 +00:00
|
|
|
int fdi_lanes;
|
2013-02-14 15:54:22 +00:00
|
|
|
struct intel_link_m_n fdi_m_n;
|
2013-05-31 19:33:22 +00:00
|
|
|
|
|
|
|
bool ips_enabled;
|
2013-09-04 15:30:02 +00:00
|
|
|
|
|
|
|
bool double_wide;
|
2014-05-02 04:02:48 +00:00
|
|
|
|
|
|
|
bool dp_encoder_is_mst;
|
|
|
|
int pbn;
|
2015-04-07 22:28:36 +00:00
|
|
|
|
|
|
|
struct intel_crtc_scaler_state scaler_state;
|
2015-06-01 10:50:09 +00:00
|
|
|
|
|
|
|
/* w/a for waiting 2 vblanks during crtc enable */
|
|
|
|
enum pipe hsw_workaround_pipe;
|
2015-09-24 22:53:12 +00:00
|
|
|
|
|
|
|
/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
|
|
|
|
bool disable_lp_wm;
|
2015-09-24 22:53:15 +00:00
|
|
|
|
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* optimal watermarks, programmed post-vblank when this state
|
|
|
|
* is committed
|
|
|
|
*/
|
|
|
|
union {
|
|
|
|
struct intel_pipe_wm ilk;
|
|
|
|
struct skl_pipe_wm skl;
|
|
|
|
} optimal;
|
|
|
|
} wm;
|
2013-03-26 23:44:50 +00:00
|
|
|
};
|
|
|
|
|
2015-06-24 19:00:04 +00:00
|
|
|
struct vlv_wm_state {
|
|
|
|
struct vlv_pipe_wm wm[3];
|
|
|
|
struct vlv_sr_wm sr[3];
|
|
|
|
uint8_t num_active_planes;
|
|
|
|
uint8_t num_levels;
|
|
|
|
uint8_t level;
|
|
|
|
bool cxsr;
|
|
|
|
};
|
|
|
|
|
drm/i915: Replaced Blitter ring based flips with MMIO flips
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power wells. The
decision to use MMIO flips can be made based on workloads to give
100% residency for Media power well.
v2: The MMIO flips now use the interrupt driven mechanism for issuing the
flips when target seqno is reached. (Incorporating Ville's idea)
v3: Rebasing on latest code. Code restructuring after incorporating
Damien's comments
v4: Addressing Ville's review comments
-general cleanup
-updating only base addr instead of calling update_primary_plane
-extending patch for gen5+ platforms
v5: Addressed Ville's review comments
-Making mmio flip vs cs flip selection based on module parameter
-Adding check for DRIVER_MODESET feature in notify_ring before calling
notify mmio flip.
-Other changes mostly in function arguments
v6: -Having a seperate function to check condition for using mmio flips (Ville)
-propogating error code from i915_gem_check_olr (Ville)
v7: -Adding __must_check with i915_gem_check_olr (Chris)
-Renaming mmio_flip_data to mmio_flip (Chris)
-Rebasing on latest nightly
v8: -Rebasing on latest code
-squash 3rd patch in series(mmio setbase vs page flip race) with this patch
-Added new tiling mode update in intel_do_mmio_flip (Chris)
v9: -check for obj->last_write_seqno being 0 instead of obj->ring being NULL in
intel_postpone_flip, as this is a more restrictive condition (Chris)
v10: -Applied Chris's suggestions for squashing patches 2,3 into this patch.
These patches make the selection of CS vs MMIO flip at the page flip time, and
make the module parameter for using mmio flips as tristate, the states being
'force CS flips', 'force mmio flips', 'driver discretion'.
Changed the logic for driver discretion (Chris)
v11: Minor code cleanup(better readability, fixing whitespace errors, using
lockdep to check mutex locked status in postpone_flip, removal of __must_check
in function definition) (Chris)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk> # snb, ivb
[danvet: Fix up parameter alignement checkpatch spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02 11:17:17 +00:00
|
|
|
struct intel_mmio_flip {
|
2014-10-28 13:10:14 +00:00
|
|
|
struct work_struct work;
|
2015-04-27 12:41:21 +00:00
|
|
|
struct drm_i915_private *i915;
|
2015-05-21 12:21:25 +00:00
|
|
|
struct drm_i915_gem_request *req;
|
2015-04-27 12:41:16 +00:00
|
|
|
struct intel_crtc *crtc;
|
2015-10-20 15:20:21 +00:00
|
|
|
unsigned int rotation;
|
drm/i915: Replaced Blitter ring based flips with MMIO flips
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power wells. The
decision to use MMIO flips can be made based on workloads to give
100% residency for Media power well.
v2: The MMIO flips now use the interrupt driven mechanism for issuing the
flips when target seqno is reached. (Incorporating Ville's idea)
v3: Rebasing on latest code. Code restructuring after incorporating
Damien's comments
v4: Addressing Ville's review comments
-general cleanup
-updating only base addr instead of calling update_primary_plane
-extending patch for gen5+ platforms
v5: Addressed Ville's review comments
-Making mmio flip vs cs flip selection based on module parameter
-Adding check for DRIVER_MODESET feature in notify_ring before calling
notify mmio flip.
-Other changes mostly in function arguments
v6: -Having a seperate function to check condition for using mmio flips (Ville)
-propogating error code from i915_gem_check_olr (Ville)
v7: -Adding __must_check with i915_gem_check_olr (Chris)
-Renaming mmio_flip_data to mmio_flip (Chris)
-Rebasing on latest nightly
v8: -Rebasing on latest code
-squash 3rd patch in series(mmio setbase vs page flip race) with this patch
-Added new tiling mode update in intel_do_mmio_flip (Chris)
v9: -check for obj->last_write_seqno being 0 instead of obj->ring being NULL in
intel_postpone_flip, as this is a more restrictive condition (Chris)
v10: -Applied Chris's suggestions for squashing patches 2,3 into this patch.
These patches make the selection of CS vs MMIO flip at the page flip time, and
make the module parameter for using mmio flips as tristate, the states being
'force CS flips', 'force mmio flips', 'driver discretion'.
Changed the logic for driver discretion (Chris)
v11: Minor code cleanup(better readability, fixing whitespace errors, using
lockdep to check mutex locked status in postpone_flip, removal of __must_check
in function definition) (Chris)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk> # snb, ivb
[danvet: Fix up parameter alignement checkpatch spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-02 11:17:17 +00:00
|
|
|
};
|
|
|
|
|
2014-12-24 15:59:06 +00:00
|
|
|
/*
|
|
|
|
* Tracking of operations that need to be performed at the beginning/end of an
|
|
|
|
* atomic commit, outside the atomic section where interrupts are disabled.
|
|
|
|
* These are generally operations that grab mutexes or might otherwise sleep
|
|
|
|
* and thus can't be run with interrupts disabled.
|
|
|
|
*/
|
|
|
|
struct intel_crtc_atomic_commit {
|
|
|
|
/* Sleepable operations to perform before commit */
|
|
|
|
bool wait_for_flips;
|
|
|
|
bool disable_fbc;
|
2015-06-26 20:55:54 +00:00
|
|
|
bool disable_ips;
|
2015-06-24 19:00:07 +00:00
|
|
|
bool disable_cxsr;
|
2014-12-24 15:59:06 +00:00
|
|
|
bool pre_disable_primary;
|
2015-06-24 19:00:02 +00:00
|
|
|
bool update_wm_pre, update_wm_post;
|
2014-12-24 15:59:06 +00:00
|
|
|
|
|
|
|
/* Sleepable operations to perform after commit */
|
|
|
|
unsigned fb_bits;
|
|
|
|
bool wait_vblank;
|
|
|
|
bool update_fbc;
|
|
|
|
bool post_enable_primary;
|
|
|
|
unsigned update_sprite_watermarks;
|
|
|
|
};
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
struct intel_crtc {
|
|
|
|
struct drm_crtc base;
|
2009-09-10 22:28:06 +00:00
|
|
|
enum pipe pipe;
|
|
|
|
enum plane plane;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
u8 lut_r[256], lut_g[256], lut_b[256];
|
2012-07-02 09:43:47 +00:00
|
|
|
/*
|
|
|
|
* Whether the crtc and the connected output pipeline is active. Implies
|
|
|
|
* that crtc->enabled is set, i.e. the current mode configuration has
|
|
|
|
* some outputs connected to this crtc.
|
|
|
|
*/
|
|
|
|
bool active;
|
2013-10-16 14:25:52 +00:00
|
|
|
unsigned long enabled_power_domains;
|
2009-08-17 20:31:43 +00:00
|
|
|
bool lowfreq_avail;
|
2009-09-15 20:57:34 +00:00
|
|
|
struct intel_overlay *overlay;
|
2009-11-18 16:25:18 +00:00
|
|
|
struct intel_unpin_work *unpin_work;
|
2010-07-09 07:45:04 +00:00
|
|
|
|
2012-11-01 09:26:26 +00:00
|
|
|
atomic_t unpin_work_count;
|
|
|
|
|
2012-07-05 10:17:29 +00:00
|
|
|
/* Display surface base address adjustement for pageflips. Note that on
|
|
|
|
* gen4+ this only adjusts up to a tile, offsets within a tile are
|
|
|
|
* handled in the hw itself (with the TILEOFF register). */
|
|
|
|
unsigned long dspaddr_offset;
|
2015-09-14 18:20:03 +00:00
|
|
|
int adjusted_x;
|
|
|
|
int adjusted_y;
|
2012-07-05 10:17:29 +00:00
|
|
|
|
2010-11-08 19:18:58 +00:00
|
|
|
struct drm_i915_gem_object *cursor_bo;
|
2010-07-09 07:45:04 +00:00
|
|
|
uint32_t cursor_addr;
|
2014-05-30 13:35:26 +00:00
|
|
|
uint32_t cursor_cntl;
|
2014-08-13 08:57:05 +00:00
|
|
|
uint32_t cursor_size;
|
2014-05-30 13:35:26 +00:00
|
|
|
uint32_t cursor_base;
|
2011-10-12 16:51:31 +00:00
|
|
|
|
2015-01-15 12:55:25 +00:00
|
|
|
struct intel_crtc_state *config;
|
2013-03-26 23:44:50 +00:00
|
|
|
|
2013-01-29 16:13:34 +00:00
|
|
|
/* reset counter value when the last flip was submitted */
|
|
|
|
unsigned int reset_counter;
|
drm/i915: report Gen5+ CPU and PCH FIFO underruns
In this commit we enable both CPU and PCH FIFO underrun reporting and
start reporting them. We follow a few rules:
- after we receive one of these errors, we mask the interrupt, so
we won't get an "interrupt storm" and we also won't flood dmesg;
- at each mode set we enable the interrupts again, so we'll see each
message at most once per mode set;
- in the specific places where we need to ignore the errors, we
completely mask the interrupts.
The downside of this patch is that since we're completely disabling
(masking) the interrupts instead of just not printing error messages,
we will mask more than just what we want on IVB/HSW CPU interrupts
(due to GEN7_ERR_INT) and on CPT/PPT/LPT PCHs (due to SERR_INT). So
when we decide to mask PCH FIFO underruns for pipe A on CPT, we'll
also be masking PCH FIFO underruns for pipe B, because both are
reported by SERR_INT, which has to be either completely enabled or
completely disabled (in othe words, there's no way to disable/enable
specific bits of GEN7_ERR_INT and SERR_INT).
V2: Rename some functions and variables, downgrade messages to
DRM_DEBUG_DRIVER and rebase.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-04-12 20:57:57 +00:00
|
|
|
|
|
|
|
/* Access to these should be protected by dev_priv->irq_lock. */
|
|
|
|
bool cpu_fifo_underrun_disabled;
|
|
|
|
bool pch_fifo_underrun_disabled;
|
2013-10-09 16:17:55 +00:00
|
|
|
|
|
|
|
/* per-pipe watermark state */
|
|
|
|
struct {
|
|
|
|
/* watermarks currently being used */
|
2015-09-24 22:53:15 +00:00
|
|
|
union {
|
|
|
|
struct intel_pipe_wm ilk;
|
|
|
|
struct skl_pipe_wm skl;
|
|
|
|
} active;
|
2015-06-24 19:00:07 +00:00
|
|
|
/* allow CxSR on this pipe */
|
|
|
|
bool cxsr_allowed;
|
2013-10-09 16:17:55 +00:00
|
|
|
} wm;
|
2014-04-29 10:35:46 +00:00
|
|
|
|
2014-05-15 17:23:23 +00:00
|
|
|
int scanline_offset;
|
2014-12-24 15:59:06 +00:00
|
|
|
|
2015-09-15 21:19:32 +00:00
|
|
|
struct {
|
|
|
|
unsigned start_vbl_count;
|
|
|
|
ktime_t start_vbl_time;
|
|
|
|
int min_vbl, max_vbl;
|
|
|
|
int scanline_start;
|
|
|
|
} debug;
|
2015-09-01 10:15:33 +00:00
|
|
|
|
2014-12-24 15:59:06 +00:00
|
|
|
struct intel_crtc_atomic_commit atomic;
|
2015-04-07 22:28:36 +00:00
|
|
|
|
|
|
|
/* scalers available on this crtc */
|
|
|
|
int num_scalers;
|
2015-06-24 19:00:04 +00:00
|
|
|
|
|
|
|
struct vlv_wm_state wm_state;
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
};
|
|
|
|
|
2013-08-07 10:29:50 +00:00
|
|
|
struct intel_plane_wm_parameters {
|
|
|
|
uint32_t horiz_pixels;
|
2014-07-15 07:21:24 +00:00
|
|
|
uint32_t vert_pixels;
|
2015-04-27 22:47:37 +00:00
|
|
|
/*
|
|
|
|
* For packed pixel formats:
|
|
|
|
* bytes_per_pixel - holds bytes per pixel
|
|
|
|
* For planar pixel formats:
|
|
|
|
* bytes_per_pixel - holds bytes per pixel for uv-plane
|
|
|
|
* y_bytes_per_pixel - holds bytes per pixel for y-plane
|
|
|
|
*/
|
2013-08-07 10:29:50 +00:00
|
|
|
uint8_t bytes_per_pixel;
|
2015-04-27 22:47:37 +00:00
|
|
|
uint8_t y_bytes_per_pixel;
|
2013-08-07 10:29:50 +00:00
|
|
|
bool enabled;
|
|
|
|
bool scaled;
|
2015-02-27 15:12:35 +00:00
|
|
|
u64 tiling;
|
2015-03-23 11:10:38 +00:00
|
|
|
unsigned int rotation;
|
2015-06-24 19:00:03 +00:00
|
|
|
uint16_t fifo_size;
|
2013-08-07 10:29:50 +00:00
|
|
|
};
|
|
|
|
|
2011-12-13 21:19:38 +00:00
|
|
|
struct intel_plane {
|
|
|
|
struct drm_plane base;
|
2013-04-02 18:22:20 +00:00
|
|
|
int plane;
|
2011-12-13 21:19:38 +00:00
|
|
|
enum pipe pipe;
|
2012-10-22 17:19:27 +00:00
|
|
|
bool can_scale;
|
2011-12-13 21:19:38 +00:00
|
|
|
int max_downscale;
|
2015-06-24 18:59:34 +00:00
|
|
|
uint32_t frontbuffer_bit;
|
2013-05-24 14:59:18 +00:00
|
|
|
|
|
|
|
/* Since we need to change the watermarks before/after
|
|
|
|
* enabling/disabling the planes, we need to store the parameters here
|
|
|
|
* as the other pieces of the struct may not reflect the values we want
|
|
|
|
* for the watermark calculations. Currently only Haswell uses this.
|
|
|
|
*/
|
2013-08-07 10:29:50 +00:00
|
|
|
struct intel_plane_wm_parameters wm;
|
2013-05-24 14:59:18 +00:00
|
|
|
|
2015-01-22 00:35:41 +00:00
|
|
|
/*
|
|
|
|
* NOTE: Do not place new plane state fields here (e.g., when adding
|
|
|
|
* new plane properties). New runtime state should now be placed in
|
|
|
|
* the intel_plane_state structure and accessed via drm_plane->state.
|
|
|
|
*/
|
|
|
|
|
2011-12-13 21:19:38 +00:00
|
|
|
void (*update_plane)(struct drm_plane *plane,
|
2013-08-06 19:24:09 +00:00
|
|
|
struct drm_crtc *crtc,
|
2011-12-13 21:19:38 +00:00
|
|
|
struct drm_framebuffer *fb,
|
|
|
|
int crtc_x, int crtc_y,
|
|
|
|
unsigned int crtc_w, unsigned int crtc_h,
|
|
|
|
uint32_t x, uint32_t y,
|
|
|
|
uint32_t src_w, uint32_t src_h);
|
2013-08-06 19:24:09 +00:00
|
|
|
void (*disable_plane)(struct drm_plane *plane,
|
2015-06-15 10:33:47 +00:00
|
|
|
struct drm_crtc *crtc);
|
2014-12-01 23:40:16 +00:00
|
|
|
int (*check_plane)(struct drm_plane *plane,
|
2015-06-15 10:33:46 +00:00
|
|
|
struct intel_crtc_state *crtc_state,
|
2014-12-01 23:40:16 +00:00
|
|
|
struct intel_plane_state *state);
|
|
|
|
void (*commit_plane)(struct drm_plane *plane,
|
|
|
|
struct intel_plane_state *state);
|
2011-12-13 21:19:38 +00:00
|
|
|
};
|
|
|
|
|
2012-04-17 01:20:35 +00:00
|
|
|
struct intel_watermark_params {
|
|
|
|
unsigned long fifo_size;
|
|
|
|
unsigned long max_wm;
|
|
|
|
unsigned long default_wm;
|
|
|
|
unsigned long guard_size;
|
|
|
|
unsigned long cacheline_size;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct cxsr_latency {
|
|
|
|
int is_desktop;
|
|
|
|
int is_ddr3;
|
|
|
|
unsigned long fsb_freq;
|
|
|
|
unsigned long mem_freq;
|
|
|
|
unsigned long display_sr;
|
|
|
|
unsigned long display_hpll_disable;
|
|
|
|
unsigned long cursor_sr;
|
|
|
|
unsigned long cursor_hpll_disable;
|
|
|
|
};
|
|
|
|
|
2015-06-04 08:21:28 +00:00
|
|
|
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
|
2015-03-20 14:18:01 +00:00
|
|
|
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
|
2010-03-30 06:39:28 +00:00
|
|
|
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
|
2010-09-09 14:14:28 +00:00
|
|
|
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
|
2011-12-13 21:19:38 +00:00
|
|
|
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
|
2014-12-23 18:41:52 +00:00
|
|
|
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
|
2014-07-08 01:21:47 +00:00
|
|
|
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
|
2012-05-09 18:37:30 +00:00
|
|
|
struct intel_hdmi {
|
2013-02-18 22:00:26 +00:00
|
|
|
u32 hdmi_reg;
|
2012-05-09 18:37:30 +00:00
|
|
|
int ddc_bus;
|
2015-07-06 12:10:00 +00:00
|
|
|
bool limited_color_range;
|
2013-01-17 14:31:29 +00:00
|
|
|
bool color_range_auto;
|
2012-05-09 18:37:30 +00:00
|
|
|
bool has_hdmi_sink;
|
|
|
|
bool has_audio;
|
|
|
|
enum hdmi_force_audio force_audio;
|
2013-01-17 14:31:31 +00:00
|
|
|
bool rgb_quant_range_selectable;
|
2014-06-11 05:36:01 +00:00
|
|
|
enum hdmi_picture_aspect aspect_ratio;
|
2015-09-04 13:26:11 +00:00
|
|
|
struct intel_connector *attached_connector;
|
2012-05-09 18:37:30 +00:00
|
|
|
void (*write_infoframe)(struct drm_encoder *encoder,
|
2013-08-06 19:32:18 +00:00
|
|
|
enum hdmi_infoframe_type type,
|
2013-12-10 13:19:08 +00:00
|
|
|
const void *frame, ssize_t len);
|
2012-05-28 19:42:48 +00:00
|
|
|
void (*set_infoframes)(struct drm_encoder *encoder,
|
2014-04-24 21:54:47 +00:00
|
|
|
bool enable,
|
2015-09-08 10:40:49 +00:00
|
|
|
const struct drm_display_mode *adjusted_mode);
|
2014-11-05 22:26:08 +00:00
|
|
|
bool (*infoframe_enabled)(struct drm_encoder *encoder);
|
2012-05-09 18:37:30 +00:00
|
|
|
};
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
struct intel_dp_mst_encoder;
|
2012-09-18 14:58:49 +00:00
|
|
|
#define DP_MAX_DOWNSTREAM_PORTS 0x10
|
2012-06-29 19:03:35 +00:00
|
|
|
|
2015-02-13 10:02:59 +00:00
|
|
|
/*
|
|
|
|
* enum link_m_n_set:
|
|
|
|
* When platform provides two set of M_N registers for dp, we can
|
|
|
|
* program them and switch between them incase of DRRS.
|
|
|
|
* But When only one such register is provided, we have to program the
|
|
|
|
* required divider value on that registers itself based on the DRRS state.
|
|
|
|
*
|
|
|
|
* M1_N1 : Program dp_m_n on M1_N1 registers
|
|
|
|
* dp_m2_n2 on M2_N2 registers (If supported)
|
|
|
|
*
|
|
|
|
* M2_N2 : Program dp_m2_n2 on M1_N1 registers
|
|
|
|
* M2_N2 registers are not supported
|
|
|
|
*/
|
|
|
|
|
|
|
|
enum link_m_n_set {
|
|
|
|
/* Sets the m1_n1 and m2_n2 */
|
|
|
|
M1_N1 = 0,
|
|
|
|
M2_N2
|
|
|
|
};
|
|
|
|
|
2015-07-23 23:35:49 +00:00
|
|
|
struct sink_crc {
|
|
|
|
bool started;
|
|
|
|
u8 last_crc[6];
|
|
|
|
int last_count;
|
|
|
|
};
|
|
|
|
|
2012-06-29 19:03:35 +00:00
|
|
|
struct intel_dp {
|
|
|
|
uint32_t output_reg;
|
2013-02-18 22:00:25 +00:00
|
|
|
uint32_t aux_ch_ctl_reg;
|
2012-06-29 19:03:35 +00:00
|
|
|
uint32_t DP;
|
2015-08-17 15:05:12 +00:00
|
|
|
int link_rate;
|
|
|
|
uint8_t lane_count;
|
2012-06-29 19:03:35 +00:00
|
|
|
bool has_audio;
|
|
|
|
enum hdmi_force_audio force_audio;
|
2015-07-06 12:10:00 +00:00
|
|
|
bool limited_color_range;
|
2013-01-17 14:31:29 +00:00
|
|
|
bool color_range_auto;
|
2012-06-29 19:03:35 +00:00
|
|
|
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
|
2013-07-11 21:44:56 +00:00
|
|
|
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
|
2012-09-18 14:58:49 +00:00
|
|
|
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
|
2015-03-13 17:40:31 +00:00
|
|
|
/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
|
|
|
|
uint8_t num_sink_rates;
|
|
|
|
int sink_rates[DP_MAX_SUPPORTED_RATES];
|
2015-07-23 23:35:49 +00:00
|
|
|
struct sink_crc sink_crc;
|
2014-03-14 14:51:15 +00:00
|
|
|
struct drm_dp_aux aux;
|
2012-06-29 19:03:35 +00:00
|
|
|
uint8_t train_set[4];
|
|
|
|
int panel_power_up_delay;
|
|
|
|
int panel_power_down_delay;
|
|
|
|
int panel_power_cycle_delay;
|
|
|
|
int backlight_on_delay;
|
|
|
|
int backlight_off_delay;
|
|
|
|
struct delayed_work panel_vdd_work;
|
|
|
|
bool want_panel_vdd;
|
2013-12-19 16:29:40 +00:00
|
|
|
unsigned long last_power_cycle;
|
|
|
|
unsigned long last_power_on;
|
|
|
|
unsigned long last_backlight_off;
|
2014-08-04 23:04:59 +00:00
|
|
|
|
2014-07-07 20:01:46 +00:00
|
|
|
struct notifier_block edp_notifier;
|
|
|
|
|
2014-09-04 11:54:20 +00:00
|
|
|
/*
|
|
|
|
* Pipe whose power sequencer is currently locked into
|
|
|
|
* this port. Only relevant on VLV/CHV.
|
|
|
|
*/
|
|
|
|
enum pipe pps_pipe;
|
2014-10-16 18:27:30 +00:00
|
|
|
struct edp_power_seq pps_delays;
|
2014-09-04 11:54:20 +00:00
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
bool can_mst; /* this port supports mst */
|
|
|
|
bool is_mst;
|
|
|
|
int active_mst_links;
|
|
|
|
/* connector directly attached - won't be use for modeset in mst world */
|
2012-10-19 11:51:50 +00:00
|
|
|
struct intel_connector *attached_connector;
|
2014-01-21 13:35:39 +00:00
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
/* mst connector list */
|
|
|
|
struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
|
|
|
|
struct drm_dp_mst_topology_mgr mst_mgr;
|
|
|
|
|
2014-01-21 13:35:39 +00:00
|
|
|
uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
|
2014-01-21 13:37:15 +00:00
|
|
|
/*
|
|
|
|
* This function returns the value we have to program the AUX_CTL
|
|
|
|
* register with to kick off an AUX transaction.
|
|
|
|
*/
|
|
|
|
uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
|
|
|
|
bool has_aux_irq,
|
|
|
|
int send_bytes,
|
|
|
|
uint32_t aux_clock_divider);
|
2015-04-29 06:17:39 +00:00
|
|
|
bool train_set_valid;
|
2015-04-15 15:38:38 +00:00
|
|
|
|
|
|
|
/* Displayport compliance testing */
|
|
|
|
unsigned long compliance_test_type;
|
2015-05-04 14:48:20 +00:00
|
|
|
unsigned long compliance_test_data;
|
|
|
|
bool compliance_test_active;
|
2012-06-29 19:03:35 +00:00
|
|
|
};
|
|
|
|
|
2012-10-26 21:05:46 +00:00
|
|
|
struct intel_digital_port {
|
|
|
|
struct intel_encoder base;
|
2012-10-26 21:05:50 +00:00
|
|
|
enum port port;
|
2013-07-12 20:54:41 +00:00
|
|
|
u32 saved_port_bits;
|
2012-10-26 21:05:46 +00:00
|
|
|
struct intel_dp dp;
|
|
|
|
struct intel_hdmi hdmi;
|
2015-01-23 05:00:31 +00:00
|
|
|
enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-08 20:45:55 +00:00
|
|
|
bool release_cl2_override;
|
2012-10-26 21:05:46 +00:00
|
|
|
};
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
struct intel_dp_mst_encoder {
|
|
|
|
struct intel_encoder base;
|
|
|
|
enum pipe pipe;
|
|
|
|
struct intel_digital_port *primary;
|
|
|
|
void *port; /* store this opaque as its illegal to dereference it */
|
|
|
|
};
|
|
|
|
|
2015-07-08 20:45:53 +00:00
|
|
|
static inline enum dpio_channel
|
2013-04-18 21:51:36 +00:00
|
|
|
vlv_dport_to_channel(struct intel_digital_port *dport)
|
|
|
|
{
|
|
|
|
switch (dport->port) {
|
|
|
|
case PORT_B:
|
2014-04-09 10:28:15 +00:00
|
|
|
case PORT_D:
|
2013-11-06 06:36:35 +00:00
|
|
|
return DPIO_CH0;
|
2013-04-18 21:51:36 +00:00
|
|
|
case PORT_C:
|
2013-11-06 06:36:35 +00:00
|
|
|
return DPIO_CH1;
|
2013-04-18 21:51:36 +00:00
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-07-08 20:45:53 +00:00
|
|
|
static inline enum dpio_phy
|
|
|
|
vlv_dport_to_phy(struct intel_digital_port *dport)
|
|
|
|
{
|
|
|
|
switch (dport->port) {
|
|
|
|
case PORT_B:
|
|
|
|
case PORT_C:
|
|
|
|
return DPIO_PHY0;
|
|
|
|
case PORT_D:
|
|
|
|
return DPIO_PHY1;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline enum dpio_channel
|
2014-04-09 10:28:16 +00:00
|
|
|
vlv_pipe_to_channel(enum pipe pipe)
|
|
|
|
{
|
|
|
|
switch (pipe) {
|
|
|
|
case PIPE_A:
|
|
|
|
case PIPE_C:
|
|
|
|
return DPIO_CH0;
|
|
|
|
case PIPE_B:
|
|
|
|
return DPIO_CH1;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-09 14:44:14 +00:00
|
|
|
static inline struct drm_crtc *
|
|
|
|
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
return dev_priv->pipe_to_crtc_mapping[pipe];
|
|
|
|
}
|
|
|
|
|
2011-01-19 15:04:42 +00:00
|
|
|
static inline struct drm_crtc *
|
|
|
|
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
return dev_priv->plane_to_crtc_mapping[plane];
|
|
|
|
}
|
|
|
|
|
2010-09-01 16:47:52 +00:00
|
|
|
struct intel_unpin_work {
|
|
|
|
struct work_struct work;
|
2012-11-01 09:26:26 +00:00
|
|
|
struct drm_crtc *crtc;
|
2015-02-02 15:44:15 +00:00
|
|
|
struct drm_framebuffer *old_fb;
|
2010-11-08 19:18:58 +00:00
|
|
|
struct drm_i915_gem_object *pending_flip_obj;
|
2010-09-01 16:47:52 +00:00
|
|
|
struct drm_pending_vblank_event *event;
|
2012-12-03 11:36:30 +00:00
|
|
|
atomic_t pending;
|
|
|
|
#define INTEL_FLIP_INACTIVE 0
|
|
|
|
#define INTEL_FLIP_PENDING 1
|
|
|
|
#define INTEL_FLIP_COMPLETE 2
|
drm/i915: Fix mmio vs. CS flip race on ILK+
Starting from ILK, mmio flips also cause a flip done interrupt to be
signalled. This means if we first do a set_base and follow it
immediately with the CS flip, we might mistake the flip done interrupt
caused by the set_base as the flip done interrupt caused by the CS
flip.
The hardware has a flip counter which increments every time a mmio or
CS flip is issued. It basically counts the number of DSPSURF register
writes. This means we can sample the counter before we put the CS
flip into the ring, and then when we get a flip done interrupt we can
check whether the CS flip has actually performed the surface address
update, or if the interrupt was caused by a previous but yet
unfinished mmio flip.
Even with the flip counter we still have a race condition of the CS flip
base address update happens after the mmio flip done interrupt was
raised but not yet processed by the driver. When the interrupt is
eventually processed, the flip counter will already indicate that the
CS flip has been executed, but it would not actually complete until the
next start of vblank. We can use the DSPSURFLIVE register to check
whether the hardware is actually scanning out of the buffer we expect,
or if we managed hit this race window.
This covers all the cases where the CS flip actually changes the base
address. If the base address remains unchanged, we might still complete
the CS flip before it has actually completed. But since the address
didn't change anyway, the premature flip completion can't result in
userspace overwriting data that's still being scanned out.
CTG already has the flip counter and DSPSURFLIVE registers, and
although the flip done interrupt is still limited to CS flips alone,
the code now also checks the flip counter on CTG as well.
v2: s/dspsurf/gtt_offset/ (Chris)
Testcase: igt/kms_mmio_vs_cs_flip/setcrtc_vs_cs_flip
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73027
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Add g4x_ prefix to flip_count_after_eq.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-04-15 18:41:34 +00:00
|
|
|
u32 flip_count;
|
|
|
|
u32 gtt_offset;
|
2014-11-24 18:49:37 +00:00
|
|
|
struct drm_i915_gem_request *flip_queued_req;
|
2015-09-14 19:43:46 +00:00
|
|
|
u32 flip_queued_vblank;
|
|
|
|
u32 flip_ready_vblank;
|
2010-09-01 16:47:52 +00:00
|
|
|
bool enable_stall_check;
|
|
|
|
};
|
|
|
|
|
2013-09-24 16:52:53 +00:00
|
|
|
struct intel_load_detect_pipe {
|
|
|
|
struct drm_framebuffer *release_fb;
|
|
|
|
bool load_detect_temp;
|
|
|
|
int dpms_mode;
|
|
|
|
};
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
|
2013-09-24 16:52:53 +00:00
|
|
|
static inline struct intel_encoder *
|
|
|
|
intel_attached_encoder(struct drm_connector *connector)
|
2010-09-09 15:20:55 +00:00
|
|
|
{
|
|
|
|
return to_intel_connector(connector)->encoder;
|
|
|
|
}
|
|
|
|
|
2012-10-26 21:05:46 +00:00
|
|
|
static inline struct intel_digital_port *
|
|
|
|
enc_to_dig_port(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return container_of(encoder, struct intel_digital_port, base.base);
|
2013-05-08 10:14:02 +00:00
|
|
|
}
|
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
static inline struct intel_dp_mst_encoder *
|
|
|
|
enc_to_mst(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return container_of(encoder, struct intel_dp_mst_encoder, base.base);
|
|
|
|
}
|
|
|
|
|
2013-05-08 10:14:02 +00:00
|
|
|
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
return &enc_to_dig_port(encoder)->dp;
|
2012-10-26 21:05:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct intel_digital_port *
|
|
|
|
dp_to_dig_port(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
return container_of(intel_dp, struct intel_digital_port, dp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct intel_digital_port *
|
|
|
|
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
|
|
|
|
{
|
|
|
|
return container_of(intel_hdmi, struct intel_digital_port, hdmi);
|
2012-10-15 18:51:29 +00:00
|
|
|
}
|
|
|
|
|
2014-03-27 18:48:33 +00:00
|
|
|
/*
|
|
|
|
* Returns the number of planes for this pipe, ie the number of sprites + 1
|
|
|
|
* (primary plane). This doesn't count the cursor plane then.
|
|
|
|
*/
|
|
|
|
static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
|
|
|
|
}
|
2013-09-24 16:52:53 +00:00
|
|
|
|
2014-09-30 08:56:46 +00:00
|
|
|
/* intel_fifo_underrun.c */
|
2014-09-30 08:56:47 +00:00
|
|
|
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
|
2013-09-24 18:48:31 +00:00
|
|
|
enum pipe pipe, bool enable);
|
2014-09-30 08:56:47 +00:00
|
|
|
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
|
2013-09-24 18:48:31 +00:00
|
|
|
enum transcoder pch_transcoder,
|
|
|
|
bool enable);
|
2014-09-30 08:56:48 +00:00
|
|
|
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
|
|
|
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder pch_transcoder);
|
2014-09-30 08:56:47 +00:00
|
|
|
void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
|
2014-09-30 08:56:46 +00:00
|
|
|
|
|
|
|
/* i915_irq.c */
|
2014-07-16 07:49:40 +00:00
|
|
|
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
|
|
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
|
|
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
|
|
|
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
|
2014-11-19 13:30:03 +00:00
|
|
|
void gen6_reset_rps_interrupts(struct drm_device *dev);
|
2014-11-05 18:48:48 +00:00
|
|
|
void gen6_enable_rps_interrupts(struct drm_device *dev);
|
|
|
|
void gen6_disable_rps_interrupts(struct drm_device *dev);
|
2014-12-19 17:33:26 +00:00
|
|
|
u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
|
2014-09-30 08:56:44 +00:00
|
|
|
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
|
2014-06-20 16:29:20 +00:00
|
|
|
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* We only use drm_irq_uninstall() at unload and VT switch, so
|
|
|
|
* this is the only thing we need to check.
|
|
|
|
*/
|
2014-09-30 08:56:43 +00:00
|
|
|
return dev_priv->pm.irqs_enabled;
|
2014-06-20 16:29:20 +00:00
|
|
|
}
|
|
|
|
|
2014-04-29 10:35:45 +00:00
|
|
|
int intel_get_crtc_scanline(struct intel_crtc *crtc);
|
2015-03-06 18:50:48 +00:00
|
|
|
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int pipe_mask);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
/* intel_crt.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_crt_init(struct drm_device *dev);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_ddi.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_prepare_ddi(struct drm_device *dev);
|
|
|
|
void hsw_fdi_link_train(struct drm_crtc *crtc);
|
|
|
|
void intel_ddi_init(struct drm_device *dev, enum port port);
|
|
|
|
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
|
|
|
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
|
|
|
|
void intel_ddi_pll_init(struct drm_device *dev);
|
|
|
|
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
|
|
|
|
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|
|
|
enum transcoder cpu_transcoder);
|
|
|
|
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
|
|
|
|
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
|
2015-01-15 12:55:23 +00:00
|
|
|
bool intel_ddi_pll_select(struct intel_crtc *crtc,
|
|
|
|
struct intel_crtc_state *crtc_state);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
|
|
|
|
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
|
|
|
|
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
|
|
|
|
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
|
|
|
|
void intel_ddi_get_config(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2014-08-22 04:19:10 +00:00
|
|
|
struct intel_encoder *
|
|
|
|
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
2014-05-02 03:36:43 +00:00
|
|
|
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
|
2014-05-02 04:02:48 +00:00
|
|
|
void intel_ddi_clock_get(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2014-05-02 04:02:48 +00:00
|
|
|
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
|
2015-06-25 08:11:03 +00:00
|
|
|
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
2014-09-19 16:27:27 +00:00
|
|
|
/* intel_frontbuffer.c */
|
drm/i915: Track frontbuffer invalidation/flushing
So these are the guts of the new beast. This tracks when a frontbuffer
gets invalidated (due to frontbuffer rendering) and hence should be
constantly scaned out, and when it's flushed again and can be
compressed/one-shot-upload.
Rules for flushing are simple: The frontbuffer needs one more full
upload starting from the next vblank. Which means that the flushing
can _only_ be called once the frontbuffer update has been latched.
But this poses a problem for pageflips: We can't just delay the
flushing until the pageflip is latched, since that would pose the risk
that we override frontbuffer rendering that has been scheduled
in-between the pageflip ioctl and the actual latching.
To handle this track asynchronous invalidations (and also pageflip)
state per-ring and delay any in-between flushing until the rendering
has completed. And also cancel any delayed flushing if we get a new
invalidation request (whether delayed or not).
Also call intel_mark_fb_busy in both cases in all cases to make sure
that we keep the screen at the highest refresh rate both on flips,
synchronous plane updates and for frontbuffer rendering.
v2: Lots of improvements
Suggestions from Chris:
- Move invalidate/flush in flush_*_domain and set_to_*_domain.
- Drop the flush in busy_ioctl since it's redundant. Was a leftover
from an earlier concept to track flips/delayed flushes.
- Don't forget about the initial modeset enable/final disable.
Suggested by Chris.
Track flips accurately, too. Since flips complete independently of
rendering we need to track pending flips in a separate mask. Again if
an invalidate happens we need to cancel the evenutal flush to avoid
races.
v3:
Provide correct header declarations for flip functions. Currently not
needed outside of intel_display.c, but part of the proper interface.
v4: Add proper domain management to fbcon so that the fbcon buffer is
also tracked correctly.
v5: Fixup locking around the fbcon set_to_gtt_domain call.
v6: More comments from Chris:
- Split out fbcon changes.
- Drop superflous checks for potential scanout before calling intel_fb
functions - we can micro-optimize this later.
- s/intel_fb_/intel_fb_obj_/ to make it clear that this deals in gem
object. We already have precedence for fb_obj in the pin_and_fence
functions.
v7: Clarify the semantics of the flip flush handling by renaming
things a bit:
- Don't go through a gem object but take the relevant frontbuffer bits
directly. These functions center on the plane, the actual object is
irrelevant - even a flip to the same object as already active should
cause a flush.
- Add a new intel_frontbuffer_flip for synchronous plane updates. It
currently just calls intel_frontbuffer_flush since the implemenation
differs.
This way we achieve a clear split between one-shot update events on
one side and frontbuffer rendering with potentially a very long delay
between the invalidate and flush.
Chris and I also had some discussions about mark_busy and whether it
is appropriate to call from flush. But mark busy is a state which
should be derived from the 3 events (invalidate, flush, flip) we now
have by the users, like psr does by tracking relevant information in
psr.busy_frontbuffer_bits. DRRS (the only real use of mark_busy for
frontbuffer) needs to have similar logic. With that the overall
mark_busy in the core could be removed.
v8: Only when retiring gpu buffers only flush frontbuffer bits we
actually invalidated in a batch. Just for safety since before any
additional usage/invalidate we should always retire current rendering.
Suggested by Chris Wilson.
v9: Actually use intel_frontbuffer_flip in all appropriate places.
Spotted by Chris.
v10: Address more comments from Chris:
- Don't call _flip in set_base when the crtc is inactive, avoids redunancy
in the modeset case with the initial enabling of all planes.
- Add comments explaining that the initial/final plane enable/disable
still has work left to do before it's fully generic.
v11: Only invalidate for gtt/cpu access when writing. Spotted by Chris.
v12: s/_flush/_flip/ in intel_overlay.c per Chris' comment.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-19 14:01:59 +00:00
|
|
|
void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
|
2015-02-13 19:23:44 +00:00
|
|
|
enum fb_op_origin origin);
|
drm/i915: Track frontbuffer invalidation/flushing
So these are the guts of the new beast. This tracks when a frontbuffer
gets invalidated (due to frontbuffer rendering) and hence should be
constantly scaned out, and when it's flushed again and can be
compressed/one-shot-upload.
Rules for flushing are simple: The frontbuffer needs one more full
upload starting from the next vblank. Which means that the flushing
can _only_ be called once the frontbuffer update has been latched.
But this poses a problem for pageflips: We can't just delay the
flushing until the pageflip is latched, since that would pose the risk
that we override frontbuffer rendering that has been scheduled
in-between the pageflip ioctl and the actual latching.
To handle this track asynchronous invalidations (and also pageflip)
state per-ring and delay any in-between flushing until the rendering
has completed. And also cancel any delayed flushing if we get a new
invalidation request (whether delayed or not).
Also call intel_mark_fb_busy in both cases in all cases to make sure
that we keep the screen at the highest refresh rate both on flips,
synchronous plane updates and for frontbuffer rendering.
v2: Lots of improvements
Suggestions from Chris:
- Move invalidate/flush in flush_*_domain and set_to_*_domain.
- Drop the flush in busy_ioctl since it's redundant. Was a leftover
from an earlier concept to track flips/delayed flushes.
- Don't forget about the initial modeset enable/final disable.
Suggested by Chris.
Track flips accurately, too. Since flips complete independently of
rendering we need to track pending flips in a separate mask. Again if
an invalidate happens we need to cancel the evenutal flush to avoid
races.
v3:
Provide correct header declarations for flip functions. Currently not
needed outside of intel_display.c, but part of the proper interface.
v4: Add proper domain management to fbcon so that the fbcon buffer is
also tracked correctly.
v5: Fixup locking around the fbcon set_to_gtt_domain call.
v6: More comments from Chris:
- Split out fbcon changes.
- Drop superflous checks for potential scanout before calling intel_fb
functions - we can micro-optimize this later.
- s/intel_fb_/intel_fb_obj_/ to make it clear that this deals in gem
object. We already have precedence for fb_obj in the pin_and_fence
functions.
v7: Clarify the semantics of the flip flush handling by renaming
things a bit:
- Don't go through a gem object but take the relevant frontbuffer bits
directly. These functions center on the plane, the actual object is
irrelevant - even a flip to the same object as already active should
cause a flush.
- Add a new intel_frontbuffer_flip for synchronous plane updates. It
currently just calls intel_frontbuffer_flush since the implemenation
differs.
This way we achieve a clear split between one-shot update events on
one side and frontbuffer rendering with potentially a very long delay
between the invalidate and flush.
Chris and I also had some discussions about mark_busy and whether it
is appropriate to call from flush. But mark busy is a state which
should be derived from the 3 events (invalidate, flush, flip) we now
have by the users, like psr does by tracking relevant information in
psr.busy_frontbuffer_bits. DRRS (the only real use of mark_busy for
frontbuffer) needs to have similar logic. With that the overall
mark_busy in the core could be removed.
v8: Only when retiring gpu buffers only flush frontbuffer bits we
actually invalidated in a batch. Just for safety since before any
additional usage/invalidate we should always retire current rendering.
Suggested by Chris Wilson.
v9: Actually use intel_frontbuffer_flip in all appropriate places.
Spotted by Chris.
v10: Address more comments from Chris:
- Don't call _flip in set_base when the crtc is inactive, avoids redunancy
in the modeset case with the initial enabling of all planes.
- Add comments explaining that the initial/final plane enable/disable
still has work left to do before it's fully generic.
v11: Only invalidate for gtt/cpu access when writing. Spotted by Chris.
v12: s/_flush/_flip/ in intel_overlay.c per Chris' comment.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-06-19 14:01:59 +00:00
|
|
|
void intel_frontbuffer_flip_prepare(struct drm_device *dev,
|
|
|
|
unsigned frontbuffer_bits);
|
|
|
|
void intel_frontbuffer_flip_complete(struct drm_device *dev,
|
|
|
|
unsigned frontbuffer_bits);
|
|
|
|
void intel_frontbuffer_flip(struct drm_device *dev,
|
2015-06-18 09:23:24 +00:00
|
|
|
unsigned frontbuffer_bits);
|
2015-03-23 11:10:32 +00:00
|
|
|
unsigned int intel_fb_align_height(struct drm_device *dev,
|
|
|
|
unsigned int height,
|
|
|
|
uint32_t pixel_format,
|
|
|
|
uint64_t fb_format_modifier);
|
2015-07-07 23:28:51 +00:00
|
|
|
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
|
|
|
|
enum fb_op_origin origin);
|
2015-02-27 11:15:18 +00:00
|
|
|
u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
|
|
|
|
uint32_t pixel_format);
|
2014-09-19 16:27:27 +00:00
|
|
|
|
2014-10-27 14:26:43 +00:00
|
|
|
/* intel_audio.c */
|
|
|
|
void intel_init_audio(struct drm_device *dev);
|
2014-10-27 14:26:50 +00:00
|
|
|
void intel_audio_codec_enable(struct intel_encoder *encoder);
|
|
|
|
void intel_audio_codec_disable(struct intel_encoder *encoder);
|
2015-01-08 15:54:14 +00:00
|
|
|
void i915_audio_component_init(struct drm_i915_private *dev_priv);
|
|
|
|
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
|
2014-10-27 14:26:43 +00:00
|
|
|
|
2014-09-19 16:27:27 +00:00
|
|
|
/* intel_display.c */
|
2015-01-22 00:35:42 +00:00
|
|
|
extern const struct drm_plane_funcs intel_plane_funcs;
|
2014-09-19 16:27:27 +00:00
|
|
|
bool intel_has_pending_fb_unpin(struct drm_device *dev);
|
|
|
|
int intel_pch_rawclk(struct drm_device *dev);
|
2015-08-26 07:58:20 +00:00
|
|
|
int intel_hrawclk(struct drm_device *dev);
|
2014-09-19 16:27:27 +00:00
|
|
|
void intel_mark_busy(struct drm_device *dev);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_mark_idle(struct drm_device *dev);
|
|
|
|
void intel_crtc_restore_mode(struct drm_crtc *crtc);
|
2015-07-13 14:30:29 +00:00
|
|
|
int intel_display_suspend(struct drm_device *dev);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_encoder_destroy(struct drm_encoder *encoder);
|
2015-04-10 07:59:10 +00:00
|
|
|
int intel_connector_init(struct intel_connector *);
|
|
|
|
struct intel_connector *intel_connector_alloc(void);
|
2013-09-24 18:48:31 +00:00
|
|
|
bool intel_connector_get_hw_state(struct intel_connector *connector);
|
|
|
|
void intel_connector_attach_encoder(struct intel_connector *connector,
|
|
|
|
struct intel_encoder *encoder);
|
|
|
|
struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
|
|
|
|
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
|
|
|
|
struct drm_crtc *crtc);
|
2013-10-31 16:55:49 +00:00
|
|
|
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
|
2009-04-29 21:43:54 +00:00
|
|
|
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
2013-09-24 18:48:31 +00:00
|
|
|
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
2014-10-29 11:16:59 +00:00
|
|
|
bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
|
2014-09-15 12:12:21 +00:00
|
|
|
static inline void
|
|
|
|
intel_wait_for_vblank(struct drm_device *dev, int pipe)
|
|
|
|
{
|
|
|
|
drm_wait_one_vblank(dev, pipe);
|
|
|
|
}
|
2013-09-24 18:48:31 +00:00
|
|
|
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
|
2013-11-06 06:36:35 +00:00
|
|
|
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
|
2015-04-10 15:21:31 +00:00
|
|
|
struct intel_digital_port *dport,
|
|
|
|
unsigned int expected_mask);
|
2013-09-24 18:48:31 +00:00
|
|
|
bool intel_get_load_detect_pipe(struct drm_connector *connector,
|
|
|
|
struct drm_display_mode *mode,
|
2013-11-19 17:10:12 +00:00
|
|
|
struct intel_load_detect_pipe *old,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_release_load_detect_pipe(struct drm_connector *connector,
|
2015-03-20 14:18:02 +00:00
|
|
|
struct intel_load_detect_pipe *old,
|
|
|
|
struct drm_modeset_acquire_ctx *ctx);
|
2014-10-30 16:39:38 +00:00
|
|
|
int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
|
|
|
|
struct drm_framebuffer *fb,
|
2015-03-23 11:10:34 +00:00
|
|
|
const struct drm_plane_state *plane_state,
|
2015-06-18 12:14:56 +00:00
|
|
|
struct intel_engine_cs *pipelined,
|
|
|
|
struct drm_i915_gem_request **pipelined_request);
|
2014-02-10 17:00:39 +00:00
|
|
|
struct drm_framebuffer *
|
|
|
|
__intel_framebuffer_create(struct drm_device *dev,
|
2013-09-24 18:48:31 +00:00
|
|
|
struct drm_mode_fb_cmd2 *mode_cmd,
|
|
|
|
struct drm_i915_gem_object *obj);
|
|
|
|
void intel_prepare_page_flip(struct drm_device *dev, int plane);
|
|
|
|
void intel_finish_page_flip(struct drm_device *dev, int pipe);
|
|
|
|
void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
|
drm/i915: Check for a stalled page flip after each vblank
Long ago, back in the racy haydays of 915gm interrupt handling, page
flips would occasionally go astray and leave the hardware stuck, and the
display not updating. This annoyed people who relied on their systems
being able to display continuously updating information 24/7, and so
some code to detect when the driver missed the page flip completion
signal was added. Until recently, it was presumed that the interrupt
handling was now flawless, but once again Simon Farnsworth has found a
system whose display will stall. Reinstate the pageflip stall detection,
which works by checking to see if the hardware has been updated to the
new framebuffer address following each vblank. If the hardware is
scanning out from the new framebuffer, but we still think the flip is
pending, then we kick our driver into submision.
This is a continuation of the effort started with
commit 4e5359cd053bfb7d8dabe4a63624a5726848ffbc
Author: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Date: Wed Sep 1 17:47:52 2010 +0100
drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
This now includes a belt-and-braces approach to make sure the driver
(or the hardware) doesn't miss an interrupt and cause us to stop
updating the display should the unthinkable happen and the pageflip fail - i.e.
that the user is able to continue submitting flips.
v2: Cleanup, refactor, and rename
v3: Only start counting vblanks after the flip command has been seen by
the hardware.
v4: Record the seqno after we touch the ring, or else there may be no
seqno allocated yet.
v5: Rebase on mmio-flip.
v6: Rebase, rebase.
Reported-by: Simon Farnsworth <simon@farnz.org.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75502
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [v4]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05 06:13:24 +00:00
|
|
|
void intel_check_page_flip(struct drm_device *dev, int pipe);
|
2014-12-01 23:40:14 +00:00
|
|
|
int intel_prepare_plane_fb(struct drm_plane *plane,
|
2015-03-03 14:22:31 +00:00
|
|
|
const struct drm_plane_state *new_state);
|
2014-12-02 15:45:25 +00:00
|
|
|
void intel_cleanup_plane_fb(struct drm_plane *plane,
|
2015-03-03 14:22:31 +00:00
|
|
|
const struct drm_plane_state *old_state);
|
2015-01-22 00:35:43 +00:00
|
|
|
int intel_plane_atomic_get_property(struct drm_plane *plane,
|
|
|
|
const struct drm_plane_state *state,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t *val);
|
|
|
|
int intel_plane_atomic_set_property(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *state,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t val);
|
2015-06-15 10:33:44 +00:00
|
|
|
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
|
|
|
|
struct drm_plane_state *plane_state);
|
2014-06-25 19:02:02 +00:00
|
|
|
|
2015-03-23 11:10:36 +00:00
|
|
|
unsigned int
|
|
|
|
intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
|
2015-09-21 09:45:32 +00:00
|
|
|
uint64_t fb_format_modifier, unsigned int plane);
|
2015-03-23 11:10:36 +00:00
|
|
|
|
2015-03-23 11:10:37 +00:00
|
|
|
static inline bool
|
|
|
|
intel_rotation_90_or_270(unsigned int rotation)
|
|
|
|
{
|
|
|
|
return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
|
|
|
|
}
|
|
|
|
|
2015-04-10 09:07:29 +00:00
|
|
|
void intel_create_rotation_property(struct drm_device *dev,
|
|
|
|
struct intel_plane *plane);
|
|
|
|
|
2014-06-25 19:02:02 +00:00
|
|
|
/* shared dpll functions */
|
2013-09-24 16:52:53 +00:00
|
|
|
struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
|
2013-06-16 19:42:39 +00:00
|
|
|
void assert_shared_dpll(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_shared_dpll *pll,
|
|
|
|
bool state);
|
|
|
|
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
|
|
|
|
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
|
2015-01-15 12:55:23 +00:00
|
|
|
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
|
|
|
|
struct intel_crtc_state *state);
|
2014-06-25 19:02:02 +00:00
|
|
|
|
2014-10-28 11:20:22 +00:00
|
|
|
void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
|
|
|
|
const struct dpll *dpll);
|
|
|
|
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
|
|
|
|
|
2014-06-25 19:02:02 +00:00
|
|
|
/* modesetting asserts */
|
2014-09-19 16:27:27 +00:00
|
|
|
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe);
|
2013-06-16 19:42:39 +00:00
|
|
|
void assert_pll(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe, bool state);
|
|
|
|
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
|
|
|
|
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
|
|
|
|
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
|
|
|
|
enum pipe pipe, bool state);
|
|
|
|
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
|
|
|
|
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
|
2013-09-24 18:48:31 +00:00
|
|
|
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
|
2011-12-13 21:19:38 +00:00
|
|
|
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
|
|
|
|
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
|
2015-06-11 13:31:14 +00:00
|
|
|
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
|
|
|
|
int *x, int *y,
|
2013-09-24 18:48:31 +00:00
|
|
|
unsigned int tiling_mode,
|
|
|
|
unsigned int bpp,
|
|
|
|
unsigned int pitch);
|
2014-11-24 16:28:11 +00:00
|
|
|
void intel_prepare_reset(struct drm_device *dev);
|
|
|
|
void intel_finish_reset(struct drm_device *dev);
|
2014-03-07 23:08:17 +00:00
|
|
|
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
|
|
|
|
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
|
2014-11-24 08:07:39 +00:00
|
|
|
void broxton_init_cdclk(struct drm_device *dev);
|
|
|
|
void broxton_uninit_cdclk(struct drm_device *dev);
|
drm/i915/bxt: add display initialize/uninitialize sequence (PHY)
Add PHY specific display initialization sequence as per BSpec.
Note that the PHY initialization/uninitialization are done
at their current place only for simplicity, in a future patch - when more
of the runtime PM features will be enabled - these will be moved to
power well#1 and modeset encoder enabling/disabling hooks respectively.
The call to uninitialize the PHY during system/runtime suspend will be
added later in this patchset.
v1: Added function definitions in header files
v2: Imre's review comments addressed
- Moved CDCLK related definitions to i915_reg.h
- Removed defintions for CDCLK frequency
- Split uninit_cdclk() by adding a phy_uninit function
- Calculate freq and decimal based on input frequency
- Program SSA precharge based on input frequency
- Use wait_for 1ms instead 200us udelay for DE PLL locking
- Removed initial value for divider, freq, decimal, ratio.
- Replaced polling loops with wait_for
- Parameterized latency optim setting
- Fix the parts where DE PLL has to be disabled.
- Call CDCLK selection from mode set
v3: (imre)
- add note about the plan to move the cdclk/phy init to a better place
- take rps.hw_lock around pcode access
- fix DDI PHY timeout value
- squash in Vandana's "PORT_CL2CM_DW6_A BUN fix",
"DDI PHY programming register defn", "Do ddi_phy_init always",
- move PHY register macros next to the corresponding CHV/VLV macros
- move DE PLL register macros here from another patch since they are
used here first
- add BXT_ prefix to CDCLK flags
- s/COMMON_RESET/COMMON_RESET_DIS/ and clarify related code comments
- fix incorrect read value for the RMW of BXT_PHY_CTL_FAMILY_DDI
- fix using GT_DISPLAY_EDP_POWER_ON vs. GT_DISPLAY_DDI_POWER_ON
when powering on DDI ports
- fix incorrect port when setting BXT_PORT_TX_DW14_LN for DDI ports
- add missing masking when programming CDCLK_FREQ_DECIMAL
- add missing powering on for DDI-C port, rename OCL2_LDOFUSE_PWR_EN
to OCL2_LDOFUSE_PWR_DIS to reduce confusion
- add note about mismatch with bspec in the PORT_REF_DW6 fields
- factor out PHY init code to a new function, so we can call it for
PHY1 and PHY0, instead of open-coding the same
v4: (ville)
- split the CDCLK/PHY parts into two patches, update commit message
accordingly
- use the existing dpio_phy enum instead of adding a new one for the
same purpose
- flip the meaning of PHYs so that PHY_A is PHY1 and PHY_BC is PHY0 to
better match CHV
- s/BXT_PHY/_BXT_PHY/
- use _PIPE for _BXT_PHY instead of open-coding it
- drop _0_2_0_GTTMMADR suffix from BXT_P_CR_GT_DISP_PWRON
- define GT_DISPLAY_POWER_ON in a more standard way
- make a note that the CHV ConfigDB also disagrees about GRC_CODE field
definitions
- fix lane optimization refactoring fumble from v3
- add per PHY uninit functions to match the init counterparts
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-11-24 08:07:39 +00:00
|
|
|
void broxton_ddi_phy_init(struct drm_device *dev);
|
|
|
|
void broxton_ddi_phy_uninit(struct drm_device *dev);
|
2014-11-24 08:07:44 +00:00
|
|
|
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
|
|
|
|
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
|
drm/i915/skl: Deinit/init the display at suspend/resume
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
of supported frequencies. As eDP also uses DPLL0 for its link rate,
once DPLL0 is on, we restrict the possible eDP link rates the chosen
VCO.
- CDCLK also limits the bandwidth available to push pixels.
So, as a first step, this commit restore what the BIOS set, until I can
do more testing.
In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
static const struct dpll_freq {
unsigned int freq;
unsigned int decimal;
} freqs[] = {
{ .freq = 308570, .decimal = 0b01001100111},
{ .freq = 337500, .decimal = 0b01010100001},
{ .freq = 432000, .decimal = 0b01101011110},
{ .freq = 450000, .decimal = 0b01110000010},
{ .freq = 540000, .decimal = 0b10000110110},
{ .freq = 617140, .decimal = 0b10011010000},
{ .freq = 675000, .decimal = 0b10101000100},
};
static void intbits(unsigned int v)
{
int i;
for(i = 10; i >= 0; i--)
putchar('0' + ((v >> i) & 1));
}
static unsigned int freq_decimal(unsigned int freq /* in kHz */)
{
return (freq - 1000) / 500;
}
static void test_freq(const struct dpll_freq *entry)
{
unsigned int decimal = freq_decimal(entry->freq);
printf("freq: %d, expected: ", entry->freq);
intbits(entry->decimal);
printf(", got: ");
intbits(decimal);
putchar('\n');
assert(decimal == entry->decimal);
}
int main(int argc, char **argv)
{
int i;
for (i = 0; i < ARRAY_SIZE(freqs); i++)
test_freq(&freqs[i]);
return 0;
}
v2:
- Rebase on top of -nightly
- Use (freq - 1000) / 500 for the decimal frequency (Ville)
- Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
- Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
be consistent with the BXT code (Ville)
- Store boot CDCLK in ddi_pll_init (Ville)
- Merge dev_priv's skl_boot_cdclk into cdclk_freq
- Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
- Replace various '0' by SKL_DPLL0 to be a bit more explicit that
we're programming DPLL0
- Busy poll the PCU before doing the frequency change. It takes about
3/4 cycles, each separated by 10us, to get the ACK from the CPU
(Ville)
v3:
- Restore dev_priv->skl_boot_cdclk, leaving unification with
dev_priv->cdclk_freq for a later patch (Daniel, Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-21 15:37:48 +00:00
|
|
|
void skl_init_cdclk(struct drm_i915_private *dev_priv);
|
2015-10-20 12:43:12 +00:00
|
|
|
int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
|
drm/i915/skl: Deinit/init the display at suspend/resume
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
- Restoring CDCDLK
- Enabling the DDB power
Among those, only the CDCDLK one is a bit tricky. There's some
complexity in that:
- DPLL0 (which is the source for CDCLK) has two VCOs, each with a set
of supported frequencies. As eDP also uses DPLL0 for its link rate,
once DPLL0 is on, we restrict the possible eDP link rates the chosen
VCO.
- CDCLK also limits the bandwidth available to push pixels.
So, as a first step, this commit restore what the BIOS set, until I can
do more testing.
In case that's of interest for the reviewer, I've unit tested the
function that derives the decimal frequency field:
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
static const struct dpll_freq {
unsigned int freq;
unsigned int decimal;
} freqs[] = {
{ .freq = 308570, .decimal = 0b01001100111},
{ .freq = 337500, .decimal = 0b01010100001},
{ .freq = 432000, .decimal = 0b01101011110},
{ .freq = 450000, .decimal = 0b01110000010},
{ .freq = 540000, .decimal = 0b10000110110},
{ .freq = 617140, .decimal = 0b10011010000},
{ .freq = 675000, .decimal = 0b10101000100},
};
static void intbits(unsigned int v)
{
int i;
for(i = 10; i >= 0; i--)
putchar('0' + ((v >> i) & 1));
}
static unsigned int freq_decimal(unsigned int freq /* in kHz */)
{
return (freq - 1000) / 500;
}
static void test_freq(const struct dpll_freq *entry)
{
unsigned int decimal = freq_decimal(entry->freq);
printf("freq: %d, expected: ", entry->freq);
intbits(entry->decimal);
printf(", got: ");
intbits(decimal);
putchar('\n');
assert(decimal == entry->decimal);
}
int main(int argc, char **argv)
{
int i;
for (i = 0; i < ARRAY_SIZE(freqs); i++)
test_freq(&freqs[i]);
return 0;
}
v2:
- Rebase on top of -nightly
- Use (freq - 1000) / 500 for the decimal frequency (Ville)
- Fix setting the enable bit of HSW_NDE_RSTWRN_OPT (Ville)
- Rename skl_display_{resume,suspend} to skl_{init,uninit}_cdclk to
be consistent with the BXT code (Ville)
- Store boot CDCLK in ddi_pll_init (Ville)
- Merge dev_priv's skl_boot_cdclk into cdclk_freq
- Use LCPLL_PLL_LOCK instead of (1 << 30) (Ville)
- Replace various '0' by SKL_DPLL0 to be a bit more explicit that
we're programming DPLL0
- Busy poll the PCU before doing the frequency change. It takes about
3/4 cycles, each separated by 10us, to get the ACK from the CPU
(Ville)
v3:
- Restore dev_priv->skl_boot_cdclk, leaving unification with
dev_priv->cdclk_freq for a later patch (Daniel, Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-21 15:37:48 +00:00
|
|
|
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
|
2015-09-29 05:31:59 +00:00
|
|
|
void skl_enable_dc6(struct drm_i915_private *dev_priv);
|
|
|
|
void skl_disable_dc6(struct drm_i915_private *dev_priv);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_dp_get_m_n(struct intel_crtc *crtc,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2015-02-13 10:02:59 +00:00
|
|
|
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
|
2013-09-24 18:48:31 +00:00
|
|
|
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
|
|
|
|
void
|
2015-01-15 12:55:21 +00:00
|
|
|
ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
|
2013-09-24 16:52:53 +00:00
|
|
|
int dotclock);
|
2015-03-06 01:29:25 +00:00
|
|
|
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
|
|
|
|
intel_clock_t *best_clock);
|
2015-06-22 20:35:51 +00:00
|
|
|
int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
|
|
|
|
|
2013-09-24 18:48:31 +00:00
|
|
|
bool intel_crtc_active(struct drm_crtc *crtc);
|
2013-10-01 15:02:17 +00:00
|
|
|
void hsw_enable_ips(struct intel_crtc *crtc);
|
|
|
|
void hsw_disable_ips(struct intel_crtc *crtc);
|
2014-03-04 17:22:57 +00:00
|
|
|
enum intel_display_power_domain
|
|
|
|
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
|
2014-02-11 23:28:57 +00:00
|
|
|
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2014-05-21 11:04:46 +00:00
|
|
|
void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
|
2014-08-06 11:02:51 +00:00
|
|
|
void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
|
2015-06-22 07:50:32 +00:00
|
|
|
|
2015-07-13 14:30:15 +00:00
|
|
|
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
|
2015-04-27 20:48:39 +00:00
|
|
|
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
|
2012-01-03 16:05:39 +00:00
|
|
|
|
2015-03-23 11:10:37 +00:00
|
|
|
unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
|
2015-09-21 09:45:35 +00:00
|
|
|
struct drm_i915_gem_object *obj,
|
|
|
|
unsigned int plane);
|
|
|
|
|
2015-04-27 20:48:39 +00:00
|
|
|
u32 skl_plane_ctl_format(uint32_t pixel_format);
|
|
|
|
u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
|
|
|
|
u32 skl_plane_ctl_rotation(unsigned int rotation);
|
2015-03-23 11:10:37 +00:00
|
|
|
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 12:58:44 +00:00
|
|
|
/* intel_csr.c */
|
|
|
|
void intel_csr_ucode_init(struct drm_device *dev);
|
drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 14:16:16 +00:00
|
|
|
enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
|
|
|
|
enum csr_state state);
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 12:58:44 +00:00
|
|
|
void intel_csr_load_program(struct drm_device *dev);
|
|
|
|
void intel_csr_ucode_fini(struct drm_device *dev);
|
2015-04-16 08:52:10 +00:00
|
|
|
void assert_csr_loaded(struct drm_i915_private *dev_priv);
|
drm/i915/skl: Add support to load SKL CSR firmware.
Display Context Save and Restore support is needed for
various SKL Display C states like DC5, DC6.
This implementation is added based on first version of DMC CSR program
that we received from h/w team.
Here we are using request_firmware based design.
Finally this firmware should end up in linux-firmware tree.
For SKL platform its mandatory to ensure that we load this
csr program before enabling DC states like DC5/DC6.
As CSR program gets reset on various conditions, we should ensure
to load it during boot and in future change to be added to load
this system resume sequence too.
v1: Initial relese as RFC patch
v2: Design change as per Daniel, Damien and Shobit's review comments
request firmware method followed.
v3: Some optimization and functional changes.
Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
Used kmemdup to allocate and duplicate firmware content.
Ensured to free allocated buffer.
v4: Modified as per review comments from Satheesh and Daniel
Removed temporary buffer.
Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
v5:
Modified as per review comemnts from Damien.
- Changed name for functions and firmware.
- Introduced HAS_CSR.
- Reverted back previous change and used csr_buf with u8 size.
- Using cpu_to_be64 for endianness change.
Modified as per review comments from Imre.
- Modified registers and macro names to be a bit closer to bspec terminology
and the existing register naming in the driver.
- Early return for non SKL platforms in intel_load_csr_program function.
- Added locking around CSR program load function as it may be called
concurrently during system/runtime resume.
- Releasing the fw before loading the program for consistency
- Handled error path during f/w load.
v6: Modified as per review comments from Imre.
- Corrected out_freecsr sequence.
v7: Modified as per review comments from Imre.
Fail loading fw if fw->size%8!=0.
v8: Rebase to latest.
v9: Rebase on top of -nightly (Damien)
v10: Enabled support for dmc firmware ver 1.0.
According to ver 1.0 in a single binary package all the firmware's that are
required for different stepping's of the product will be stored. The package
contains the css header, followed by the package header and the actual dmc
firmwares. Package header contains the firmware/stepping mapping table and
the corresponding firmware offsets to the individual binaries, within the
package. Each individual program binary contains the header and the payload
sections whose size is specified in the header section. This changes are done
to extract the specific firmaware from the package. (Animesh)
v11: Modified as per review comemnts from Imre.
- Added code comment from bpec for header structure elements.
- Added __packed to avoid structure padding.
- Added helper functions for stepping and substepping info.
- Added code comment for CSR_MAX_FW_SIZE.
- Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
- Changed skl_stepping_info based on bspec, earlier used from config DB.
- Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
- Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
- Added sanity check for header length.
- Added sanity check for mmio address got from firmware binary.
- kmalloc done separately for dmc header and dmc firmware. (Animesh)
v12: Modified as per review comemnts from Imre.
- Corrected the typo error in skl stepping info structure.
- Added out-of-bound access for skl_stepping_info.
- Sanity check for mmio address modified.
- Sanity check added for stepping and substeppig.
- Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
v13: clarify firmware load error message.
The reason for a firmware loading failure can be obscure if the driver
is built-in. Provide an explanation to the user about the likely reason for
the failure and how to resolve it. (Imre)
v14: Suggested by Jani.
- fix s/I915/CONFIG_DRM_I915/ typo
- add fw_path to the firmware object instead of using a static ptr (Jani)
v15:
1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
with same name will help not to build kernel again.
2) Changes done as per review comments from Imre.
- Error check removed for intel_csr_ucode_init.
- Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
- fw->data used directly for parsing the header info & memory allocation
only done separately for payload. (Animesh)
v16:
- No need for out_regs label in i915_driver_load(), so removed it.
- Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
Issue: VIZ-2569
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-04 12:58:44 +00:00
|
|
|
|
2013-09-24 16:52:53 +00:00
|
|
|
/* intel_dp.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
|
|
|
|
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector);
|
2015-08-17 15:05:12 +00:00
|
|
|
void intel_dp_set_link_params(struct intel_dp *intel_dp,
|
|
|
|
const struct intel_crtc_state *pipe_config);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_dp_start_link_train(struct intel_dp *intel_dp);
|
|
|
|
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
|
|
|
|
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
|
|
|
|
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
|
2014-01-24 15:36:17 +00:00
|
|
|
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
|
2013-09-24 18:48:31 +00:00
|
|
|
bool intel_dp_compute_config(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2013-11-01 16:22:39 +00:00
|
|
|
bool intel_dp_is_edp(struct drm_device *dev, enum port port);
|
2015-01-23 05:00:31 +00:00
|
|
|
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
|
|
|
|
bool long_hpd);
|
2014-01-17 13:39:48 +00:00
|
|
|
void intel_edp_backlight_on(struct intel_dp *intel_dp);
|
|
|
|
void intel_edp_backlight_off(struct intel_dp *intel_dp);
|
2014-03-17 14:43:36 +00:00
|
|
|
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
|
2014-01-17 13:39:48 +00:00
|
|
|
void intel_edp_panel_on(struct intel_dp *intel_dp);
|
|
|
|
void intel_edp_panel_off(struct intel_dp *intel_dp);
|
2014-05-02 04:02:48 +00:00
|
|
|
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
|
|
|
|
void intel_dp_mst_suspend(struct drm_device *dev);
|
|
|
|
void intel_dp_mst_resume(struct drm_device *dev);
|
2015-03-12 15:10:34 +00:00
|
|
|
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
|
2015-03-12 15:10:36 +00:00
|
|
|
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
|
2014-05-02 04:02:48 +00:00
|
|
|
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
|
2014-09-04 11:54:56 +00:00
|
|
|
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
|
2014-11-14 16:52:28 +00:00
|
|
|
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
|
2014-12-23 18:41:51 +00:00
|
|
|
void intel_plane_destroy(struct drm_plane *plane);
|
2015-01-22 09:47:40 +00:00
|
|
|
void intel_edp_drrs_enable(struct intel_dp *intel_dp);
|
|
|
|
void intel_edp_drrs_disable(struct intel_dp *intel_dp);
|
2015-01-09 20:55:59 +00:00
|
|
|
void intel_edp_drrs_invalidate(struct drm_device *dev,
|
|
|
|
unsigned frontbuffer_bits);
|
|
|
|
void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
|
drm/i915: Check live status before reading edid
The Bspec is very clear that Live status must be checked about before
trying to read EDID over DDC channel. This patch makes sure that HDMI
EDID is read only when live status is up.
The live status doesn't seem to perform very consistent across various
platforms when tested with different monitors. The reason behind that is
some monitors are late to provide right voltage to set live_status up.
So, after getting the interrupt, for a small duration, live status reg
fluctuates, and then settles down showing the correct staus.
This is explained here in, in a rough way:
HPD line ________________
|\ T1 = Monitor Hotplug causing IRQ
| \______________________________________
| |
| |
| | T2 = Live status is stable
| | _____________________________________
| | /|
Live status _____________|_|/ |
| | |
| | |
| | |
T0 T1 T2
(Between T1 and T2 Live status fluctuates or can be even low, depending on
the monitor)
After several experiments, we have concluded that a max delay
of 30ms is enough to allow the live status to settle down with
most of the monitors. This total delay of 30ms has been split into
a resolution of 3 retries of 10ms each, for the better cases.
This delay is kept at 30ms, keeping in consideration that, HDCP compliance
expect the HPD handler to respond a plug out in 100ms, by disabling port.
v2: Adding checks for VLV/CHV as well. Reusing old ibx and g4x functions
to check digital port status. Adding a separate function to get bxt live
status (Daniel)
v3: Using intel_encoder->hpd_pin to check the live status (Siva)
Moving the live status read to intel_hdmi_probe and passing parameter
to read/not to read the edid. (me)
v4:
* Added live status check for all platforms using
intel_digital_port_connected.
* Rebased on top of Jani's DP cleanup series
* Some monitors take time in setting the live status. So retry for few
times if this is a connect HPD
v5: Removed extra "drm/i915" from commit message. Adding Shashank's sob
which was missed.
v6: Drop the (!detect_edid && !live_status check) check because for DDI
ports which are enumerated as hdmi as well as DP, we don't have a
mechanism to differentiate between DP and hdmi inside the encoder's
hot_plug. This leads to call to the hdmi's hot_plug hook for DP as well
as hdmi which leads to issues during unplug because of the above check.
v7: Make intel_digital_port_connected global in this patch, some
reformatting of while loop, adding a print when live status is not
up. (Rodrigo)
v8: Rebase it on nightly which involved skipping the hot_plug hook for now
and letting the live_status check happen in detect until the hpd handling
part is finalized (Daniel)
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-09-15 04:14:20 +00:00
|
|
|
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
|
|
|
|
struct intel_digital_port *port);
|
2015-08-31 08:23:28 +00:00
|
|
|
void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
|
2014-11-14 16:52:28 +00:00
|
|
|
|
2014-05-02 04:02:48 +00:00
|
|
|
/* intel_dp_mst.c */
|
|
|
|
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
|
|
|
|
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
|
2013-09-24 16:52:53 +00:00
|
|
|
/* intel_dsi.c */
|
2014-05-28 11:30:56 +00:00
|
|
|
void intel_dsi_init(struct drm_device *dev);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_dvo.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_dvo_init(struct drm_device *dev);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
|
2013-10-08 15:44:49 +00:00
|
|
|
/* legacy fbdev emulation in intel_fbdev.c */
|
2015-08-10 11:34:08 +00:00
|
|
|
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
2013-10-09 07:18:51 +00:00
|
|
|
extern int intel_fbdev_init(struct drm_device *dev);
|
2014-05-28 21:39:03 +00:00
|
|
|
extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
|
2013-10-09 07:18:51 +00:00
|
|
|
extern void intel_fbdev_fini(struct drm_device *dev);
|
2014-08-13 12:09:46 +00:00
|
|
|
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
|
2013-10-08 15:44:49 +00:00
|
|
|
extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
|
|
|
|
extern void intel_fbdev_restore_mode(struct drm_device *dev);
|
2013-10-09 07:18:51 +00:00
|
|
|
#else
|
|
|
|
static inline int intel_fbdev_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2013-09-24 16:52:53 +00:00
|
|
|
|
2014-05-28 21:39:03 +00:00
|
|
|
static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
|
2013-10-09 07:18:51 +00:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void intel_fbdev_fini(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2014-08-13 12:09:46 +00:00
|
|
|
static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
|
2013-10-09 07:18:51 +00:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2013-10-08 15:44:49 +00:00
|
|
|
static inline void intel_fbdev_restore_mode(struct drm_device *dev)
|
2013-10-09 07:18:51 +00:00
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
2013-09-24 16:52:53 +00:00
|
|
|
|
2014-12-08 16:09:10 +00:00
|
|
|
/* intel_fbc.c */
|
2015-07-07 18:26:04 +00:00
|
|
|
bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_fbc_update(struct drm_i915_private *dev_priv);
|
2014-12-08 16:09:10 +00:00
|
|
|
void intel_fbc_init(struct drm_i915_private *dev_priv);
|
2015-07-07 18:26:04 +00:00
|
|
|
void intel_fbc_disable(struct drm_i915_private *dev_priv);
|
2015-07-02 22:25:10 +00:00
|
|
|
void intel_fbc_disable_crtc(struct intel_crtc *crtc);
|
2015-02-13 19:23:46 +00:00
|
|
|
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
|
|
|
|
unsigned int frontbuffer_bits,
|
|
|
|
enum fb_op_origin origin);
|
|
|
|
void intel_fbc_flush(struct drm_i915_private *dev_priv,
|
2015-07-14 19:29:10 +00:00
|
|
|
unsigned int frontbuffer_bits, enum fb_op_origin origin);
|
2015-06-12 17:36:20 +00:00
|
|
|
const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
|
2015-07-07 18:26:04 +00:00
|
|
|
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
|
2014-12-08 16:09:10 +00:00
|
|
|
|
2013-09-24 16:52:53 +00:00
|
|
|
/* intel_hdmi.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
|
|
|
|
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector);
|
|
|
|
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
|
|
|
|
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_lvds.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_lvds_init(struct drm_device *dev);
|
|
|
|
bool intel_is_dual_link_lvds(struct drm_device *dev);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_modes.c */
|
|
|
|
int intel_connector_update_modes(struct drm_connector *connector,
|
2013-09-24 18:48:31 +00:00
|
|
|
struct edid *edid);
|
2013-09-24 16:52:53 +00:00
|
|
|
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_attach_force_audio_property(struct drm_connector *connector);
|
|
|
|
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
|
2015-09-25 13:39:30 +00:00
|
|
|
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_overlay.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_setup_overlay(struct drm_device *dev);
|
|
|
|
void intel_cleanup_overlay(struct drm_device *dev);
|
|
|
|
int intel_overlay_switch_off(struct intel_overlay *overlay);
|
|
|
|
int intel_overlay_put_image(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
|
|
|
int intel_overlay_attrs(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
2014-11-26 15:07:29 +00:00
|
|
|
void intel_overlay_reset(struct drm_i915_private *dev_priv);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
|
|
|
|
/* intel_panel.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
int intel_panel_init(struct intel_panel *panel,
|
2014-02-11 08:56:36 +00:00
|
|
|
struct drm_display_mode *fixed_mode,
|
|
|
|
struct drm_display_mode *downclock_mode);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_panel_fini(struct intel_panel *panel);
|
|
|
|
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
|
|
|
|
struct drm_display_mode *adjusted_mode);
|
|
|
|
void intel_pch_panel_fitting(struct intel_crtc *crtc,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config,
|
2013-09-24 18:48:31 +00:00
|
|
|
int fitting_mode);
|
|
|
|
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
|
2015-01-15 12:55:21 +00:00
|
|
|
struct intel_crtc_state *pipe_config,
|
2013-09-24 18:48:31 +00:00
|
|
|
int fitting_mode);
|
2014-06-24 15:27:40 +00:00
|
|
|
void intel_panel_set_backlight_acpi(struct intel_connector *connector,
|
|
|
|
u32 level, u32 max);
|
2014-11-07 09:16:02 +00:00
|
|
|
int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
|
2013-10-31 16:55:49 +00:00
|
|
|
void intel_panel_enable_backlight(struct intel_connector *connector);
|
|
|
|
void intel_panel_disable_backlight(struct intel_connector *connector);
|
2013-11-08 14:48:53 +00:00
|
|
|
void intel_panel_destroy_backlight(struct drm_connector *connector);
|
2013-09-24 18:48:31 +00:00
|
|
|
enum drm_connector_status intel_panel_detect(struct drm_device *dev);
|
2013-12-10 08:07:36 +00:00
|
|
|
extern struct drm_display_mode *intel_find_panel_downclock(
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|
|
|
struct drm_device *dev,
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|
|
|
struct drm_display_mode *fixed_mode,
|
|
|
|
struct drm_connector *connector);
|
2014-11-07 13:19:46 +00:00
|
|
|
void intel_backlight_register(struct drm_device *dev);
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|
|
void intel_backlight_unregister(struct drm_device *dev);
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|
2013-09-24 16:52:53 +00:00
|
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|
|
2014-11-14 16:52:28 +00:00
|
|
|
/* intel_psr.c */
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void intel_psr_enable(struct intel_dp *intel_dp);
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|
|
void intel_psr_disable(struct intel_dp *intel_dp);
|
|
|
|
void intel_psr_invalidate(struct drm_device *dev,
|
2015-06-18 08:30:27 +00:00
|
|
|
unsigned frontbuffer_bits);
|
2014-11-14 16:52:28 +00:00
|
|
|
void intel_psr_flush(struct drm_device *dev,
|
2015-07-08 23:21:31 +00:00
|
|
|
unsigned frontbuffer_bits,
|
|
|
|
enum fb_op_origin origin);
|
2014-11-14 16:52:28 +00:00
|
|
|
void intel_psr_init(struct drm_device *dev);
|
2015-06-18 08:30:27 +00:00
|
|
|
void intel_psr_single_frame_update(struct drm_device *dev,
|
|
|
|
unsigned frontbuffer_bits);
|
2014-11-14 16:52:28 +00:00
|
|
|
|
2014-09-30 08:56:38 +00:00
|
|
|
/* intel_runtime_pm.c */
|
|
|
|
int intel_power_domains_init(struct drm_i915_private *);
|
2014-09-30 08:56:39 +00:00
|
|
|
void intel_power_domains_fini(struct drm_i915_private *);
|
2014-09-30 08:56:38 +00:00
|
|
|
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
|
2014-09-30 08:56:39 +00:00
|
|
|
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
|
2014-09-30 08:56:38 +00:00
|
|
|
|
2014-09-30 08:56:39 +00:00
|
|
|
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
|
|
|
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
2014-09-30 08:56:38 +00:00
|
|
|
void intel_display_power_get(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
|
|
|
void intel_display_power_put(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain);
|
|
|
|
void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
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|
|
void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
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|
|
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
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|
|
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
|
|
|
|
|
2014-09-30 08:56:40 +00:00
|
|
|
void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
|
|
|
|
|
2015-07-08 20:45:54 +00:00
|
|
|
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
|
|
|
|
bool override, unsigned int mask);
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-08 20:45:55 +00:00
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|
|
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
|
|
|
|
enum dpio_channel ch, bool override);
|
2015-07-08 20:45:54 +00:00
|
|
|
|
|
|
|
|
2013-09-24 16:52:53 +00:00
|
|
|
/* intel_pm.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_init_clock_gating(struct drm_device *dev);
|
|
|
|
void intel_suspend_hw(struct drm_device *dev);
|
2014-05-13 14:30:26 +00:00
|
|
|
int ilk_wm_max_level(const struct drm_device *dev);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_update_watermarks(struct drm_crtc *crtc);
|
|
|
|
void intel_init_pm(struct drm_device *dev);
|
2013-12-06 09:17:53 +00:00
|
|
|
void intel_pm_setup(struct drm_device *dev);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
|
|
|
|
void intel_gpu_ips_teardown(void);
|
2014-03-31 12:10:44 +00:00
|
|
|
void intel_init_gt_powersave(struct drm_device *dev);
|
|
|
|
void intel_cleanup_gt_powersave(struct drm_device *dev);
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_enable_gt_powersave(struct drm_device *dev);
|
|
|
|
void intel_disable_gt_powersave(struct drm_device *dev);
|
2014-06-12 15:35:45 +00:00
|
|
|
void intel_suspend_gt_powersave(struct drm_device *dev);
|
2014-04-14 17:24:29 +00:00
|
|
|
void intel_reset_gt_powersave(struct drm_device *dev);
|
2013-08-19 16:18:09 +00:00
|
|
|
void gen6_update_ring_freq(struct drm_device *dev);
|
2015-03-18 09:48:22 +00:00
|
|
|
void gen6_rps_busy(struct drm_i915_private *dev_priv);
|
|
|
|
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
|
2013-10-08 17:39:29 +00:00
|
|
|
void gen6_rps_idle(struct drm_i915_private *dev_priv);
|
2015-04-07 15:20:32 +00:00
|
|
|
void gen6_rps_boost(struct drm_i915_private *dev_priv,
|
2015-04-27 12:41:24 +00:00
|
|
|
struct intel_rps_client *rps,
|
|
|
|
unsigned long submitted);
|
2015-04-07 15:20:31 +00:00
|
|
|
void intel_queue_rps_boost_for_request(struct drm_device *dev,
|
2015-05-21 12:21:25 +00:00
|
|
|
struct drm_i915_gem_request *req);
|
2015-06-24 19:00:03 +00:00
|
|
|
void vlv_wm_get_hw_state(struct drm_device *dev);
|
2013-10-14 11:55:24 +00:00
|
|
|
void ilk_wm_get_hw_state(struct drm_device *dev);
|
2014-11-04 17:06:45 +00:00
|
|
|
void skl_wm_get_hw_state(struct drm_device *dev);
|
2014-11-04 17:06:52 +00:00
|
|
|
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct skl_ddb_allocation *ddb /* out */);
|
2015-06-03 12:45:11 +00:00
|
|
|
uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
|
2012-05-09 18:37:31 +00:00
|
|
|
|
2013-09-24 16:52:53 +00:00
|
|
|
/* intel_sdvo.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
|
2013-02-18 17:08:49 +00:00
|
|
|
|
2013-07-11 21:44:58 +00:00
|
|
|
|
2013-09-24 16:52:53 +00:00
|
|
|
/* intel_sprite.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
|
|
|
|
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv);
|
2015-08-31 11:04:25 +00:00
|
|
|
void intel_pipe_update_start(struct intel_crtc *crtc);
|
|
|
|
void intel_pipe_update_end(struct intel_crtc *crtc);
|
2013-09-24 16:52:53 +00:00
|
|
|
|
|
|
|
/* intel_tv.c */
|
2013-09-24 18:48:31 +00:00
|
|
|
void intel_tv_init(struct drm_device *dev);
|
2013-09-04 15:25:25 +00:00
|
|
|
|
2014-12-23 18:41:52 +00:00
|
|
|
/* intel_atomic.c */
|
2015-01-23 00:51:27 +00:00
|
|
|
int intel_connector_atomic_get_property(struct drm_connector *connector,
|
|
|
|
const struct drm_connector_state *state,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t *val);
|
2015-01-22 00:35:47 +00:00
|
|
|
struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
|
|
|
|
void intel_crtc_destroy_state(struct drm_crtc *crtc,
|
|
|
|
struct drm_crtc_state *state);
|
2015-06-04 08:21:28 +00:00
|
|
|
struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
|
|
|
|
void intel_atomic_state_clear(struct drm_atomic_state *);
|
|
|
|
struct intel_shared_dpll_config *
|
|
|
|
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
|
|
|
|
|
2015-03-20 14:18:01 +00:00
|
|
|
static inline struct intel_crtc_state *
|
|
|
|
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
|
|
|
|
struct intel_crtc *crtc)
|
|
|
|
{
|
|
|
|
struct drm_crtc_state *crtc_state;
|
|
|
|
crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
|
|
|
|
if (IS_ERR(crtc_state))
|
2015-04-25 09:34:29 +00:00
|
|
|
return ERR_CAST(crtc_state);
|
2015-03-20 14:18:01 +00:00
|
|
|
|
|
|
|
return to_intel_crtc_state(crtc_state);
|
|
|
|
}
|
2015-04-09 23:42:46 +00:00
|
|
|
int intel_atomic_setup_scalers(struct drm_device *dev,
|
|
|
|
struct intel_crtc *intel_crtc,
|
|
|
|
struct intel_crtc_state *crtc_state);
|
2015-01-22 00:35:44 +00:00
|
|
|
|
|
|
|
/* intel_atomic_plane.c */
|
2015-01-22 00:35:41 +00:00
|
|
|
struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
|
2014-12-23 18:41:52 +00:00
|
|
|
struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
|
|
|
|
void intel_plane_destroy_state(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *state);
|
|
|
|
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
|
|
|
|
|
DRM: i915: add mode setting support
This commit adds i915 driver support for the DRM mode setting APIs.
Currently, VGA, LVDS, SDVO DVI & VGA, TV and DVO LVDS outputs are
supported. HDMI, DisplayPort and additional SDVO output support will
follow.
Support for the mode setting code is controlled by the new 'modeset'
module option. A new config option, CONFIG_DRM_I915_KMS controls the
default behavior, and whether a PCI ID list is built into the module for
use by user level module utilities.
Note that if mode setting is enabled, user level drivers that access
display registers directly or that don't use the kernel graphics memory
manager will likely corrupt kernel graphics memory, disrupt output
configuration (possibly leading to hangs and/or blank displays), and
prevent panic/oops messages from appearing. So use caution when
enabling this code; be sure your user level code supports the new
interfaces.
A new SysRq key, 'g', provides emergency support for switching back to
the kernel's framebuffer console; which is useful for testing.
Co-authors: Dave Airlie <airlied@linux.ie>, Hong Liu <hong.liu@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-11-07 22:24:08 +00:00
|
|
|
#endif /* __INTEL_DRV_H__ */
|