forked from Minki/linux
drm/i915: Don't wait for page flips if there was GPU reset
If a GPU reset occurs while a page flip has been submitted to the ring, the flip will never complete once the ring has been reset. The GPU reset can be detected by sampling the reset_counter before the flip is submitted, and then while waiting for the flip, the sampled counter is compared with the current reset_counter value. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Move the reset_counter assignment to an earlier place in common code as discussed on the mailing list.] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60140 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -2868,10 +2868,12 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned long flags;
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bool pending;
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if (i915_reset_in_progress(&dev_priv->gpu_error))
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if (i915_reset_in_progress(&dev_priv->gpu_error) ||
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intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
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return false;
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spin_lock_irqsave(&dev->event_lock, flags);
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@ -7250,6 +7252,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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work->enable_stall_check = true;
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atomic_inc(&intel_crtc->unpin_work_count);
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intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
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ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
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if (ret)
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@ -235,6 +235,9 @@ struct intel_crtc {
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/* We can share PLLs across outputs if the timings match */
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struct intel_pch_pll *pch_pll;
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uint32_t ddi_pll_sel;
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/* reset counter value when the last flip was submitted */
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unsigned int reset_counter;
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};
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struct intel_plane {
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