Commit Graph

29737 Commits

Author SHA1 Message Date
mlugg
1eaeb4a0a8
Zcu: rework source locations
`LazySrcLoc` now stores a reference to the "base AST node" to which it
is relative. The previous tagged union is `LazySrcLoc.Offset`. To make
working with this structure convenient, `Sema.Block` contains a
convenience `src` method which takes an `Offset` and returns a
`LazySrcLoc`.

The "base node" of a source location is no longer given by a `Decl`, but
rather a `TrackedInst` representing either a `declaration`,
`struct_decl`, `union_decl`, `enum_decl`, or `opaque_decl`. This is a
more appropriate model, and removes an unnecessary responsibility from
`Decl` in preparation for the upcoming refactor which will split it into
`Nav` and `Cau`.

As a part of these `Decl` reworks, the `src_node` field is eliminated.
This change aids incremental compilation, and simplifies `Decl`. In some
cases -- particularly in backends -- the source location of a
declaration is desired. This was previously `Decl.srcLoc` and worked for
any `Decl`. Now, it is `Decl.navSrcLoc` in reference to the upcoming
refactor, since the set of `Decl`s this works for precisely corresponds
to what will in future become a `Nav` -- that is, source-level
declarations and generic function instantiations, but *not* type owner
Decls.

This commit introduces more tags to `LazySrcLoc.Offset` so as to
eliminate the concept of `error.NeededSourceLocation`. Now, `.unneeded`
should only be used to assert that an error path is unreachable. In the
future, uses of `.unneeded` can probably be replaced with `undefined`.

The `src_decl` field of `Sema.Block` no longer has a role in type
resolution. Its main remaining purpose is to handle namespacing of type
names. It will be eliminated entirely in a future commit to remove
another undue responsibility from `Decl`.

It is worth noting that in future, the `Zcu.SrcLoc` type should probably
be eliminated entirely in favour of storing `Zcu.LazySrcLoc` values.
This is because `Zcu.SrcLoc` is not valid across incremental updates,
and we want to be able to reuse error messages from previous updates
even if the source file in question changed. The error reporting logic
should instead simply resolve the location from the `LazySrcLoc` on the
fly.
2024-06-15 00:57:52 +01:00
mlugg
07a24bec9a
compiler: move LazySrcLoc out of std
This is in preparation for some upcoming changes to how we represent
source locations in the compiler. The bulk of the change here is dealing
with the removal of `src()` methods from `Zir` types.
2024-06-15 00:57:52 +01:00
mlugg
e39cc0dff7
Zir: use absolute nodes for declarations and type declarations
The justification for using relative source nodes in ZIR is that it
allows source locations -- which may be serialized across incremental
updates -- to be relative to the source location of their containing
declaration. However, having those "baseline" instructions themselves be
relative to their own parent is counterproductive, since the source
location updating problem is only being moved to `Decl`. Storing the
absolute node here instead makes more sense, since it allows for this
source location update logic to be elided entirely in the future by
storing a `TrackedInst.Index` to resolve a source location relative to
rather than a `Decl.Index`.
2024-06-15 00:57:52 +01:00
Peng Guanwen
82a934bb91 Fix futex2_waitv syscall
The syscall gives immediate compile error in zig 0.12. This fix that.
2024-06-13 16:51:13 -04:00
Ryan Liptak
8e155959ca posix.renameW: Handle DIRECTORY_NOT_EMPTY more generally
Before this commit, the DIRECTORY_NOT_EMPTY/FILE_IS_A_DIRECTORY/NOT_A_DIRECTORY statuses were assumed only to be possible when using `FILE_RENAME_INFORMATION_EX` and `FILE_RENAME_POSIX_SEMANTICS`, but that has empirically been shown to be false; a networked samba share can return the DIRECTORY_NOT_EMPTY status from `FILE_RENAME_INFORMATION` (which doesn't support `FILE_RENAME_POSIX_SEMANTICS`).

`FILE_IS_A_DIRECTORY` and `NOT_A_DIRECTORY` were not proven to be possible, but they were also moved to the outer switch just in case.

Fixes #19785
2024-06-13 10:50:46 -04:00
Krzysztof Wolicki
45c77931c2 Change deprecated b.host to b.graph.host in tests and Zig's build.zig 2024-06-13 10:49:06 -04:00
Ryan Liptak
76fb2b685b std: Convert deprecated aliases to compile errors and fix usages
Deprecated aliases that are now compile errors:

- `std.fs.MAX_PATH_BYTES` (renamed to `std.fs.max_path_bytes`)
- `std.mem.tokenize` (split into `tokenizeAny`, `tokenizeSequence`, `tokenizeScalar`)
- `std.mem.split` (split into `splitSequence`, `splitAny`, `splitScalar`)
- `std.mem.splitBackwards` (split into `splitBackwardsSequence`, `splitBackwardsAny`, `splitBackwardsScalar`)
- `std.unicode`
  + `utf16leToUtf8Alloc`, `utf16leToUtf8AllocZ`, `utf16leToUtf8`, `fmtUtf16le` (all renamed to have capitalized `Le`)
  + `utf8ToUtf16LeWithNull` (renamed to `utf8ToUtf16LeAllocZ`)
- `std.zig.CrossTarget` (moved to `std.Target.Query`)

Deprecated `lib/std/std.zig` decls were deleted instead of made a `@compileError` because the `refAllDecls` in the test block would trigger the `@compileError`. The deleted top-level `std` namespaces are:

- `std.rand` (renamed to `std.Random`)
- `std.TailQueue` (renamed to `std.DoublyLinkedList`)
- `std.ChildProcess` (renamed/moved to `std.process.Child`)

This is not exhaustive. Deprecated aliases that I didn't touch:
  + `std.io.*`
  + `std.Build.*`
  + `std.builtin.Mode`
  + `std.zig.c_translation.CIntLiteralRadix`
  + anything in `src/`
2024-06-13 10:18:59 -04:00
David Rubin
e60c581147
test: disable-enable riscv tests 2024-06-13 04:42:26 -07:00
David Rubin
4ce9bfff19
ZigObject: include all RISCs in minFunctionAlignment 2024-06-13 02:24:40 -07:00
David Rubin
3530308476
test: refactor mainSimple
added some comments to make it easier for future contributors.
2024-06-13 02:24:39 -07:00
David Rubin
3967e00047
riscv: disable failing test 2024-06-13 02:24:39 -07:00
David Rubin
4fd8900337
riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin
a9ef016943
riscv: implement airArrayToSlice 2024-06-13 02:22:34 -07:00
David Rubin
a270c6f8c8
riscv: implement optional logic 2024-06-13 02:22:33 -07:00
David Rubin
d69c48370a
riscv: integer + float @abs 2024-06-13 02:22:06 -07:00
David Rubin
206e66858c
riscv: rename Self to Func
Very similar reasoning to the Wasm backend. I believe that "Self" is
not the most descriptive possible name here and "Func" better explains it.

The generation is happening for a Function, and accessing "Func" is like accessing
the context of that current function.
2024-06-13 02:22:05 -07:00
David Rubin
c10d1c6a75
riscv: implement more arithmetic instructions 2024-06-13 02:22:05 -07:00
David Rubin
083b7b483e
riscv: zero registers when using register-wide operations
what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register.

with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.
2024-06-13 02:22:04 -07:00
David Rubin
b67995689d
riscv: add airAggregateInit for arrays 2024-06-13 02:22:04 -07:00
David Rubin
b2cb090c37
riscv: float args 2024-06-13 02:21:39 -07:00
David Rubin
031d8248e0
riscv: first sign of floats! 2024-06-13 02:21:38 -07:00
David Rubin
7ed2f2156f
riscv: fix register clobber in certain edge cases 2024-06-13 02:21:38 -07:00
David Rubin
381a1043eb
ZigObject: enforce min function alignement on riscv 2024-06-13 02:21:38 -07:00
David Rubin
6603a9c26c
testing: fix test runner 2024-06-13 02:20:48 -07:00
David Rubin
39c95e8930
riscv: switch the test runner to mainSimple 2024-06-13 02:20:47 -07:00
David Rubin
05de6c279b
riscv: std.fmt.format running
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.

- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.

- only generating `.got.zig` entries when not compiling an object or shared library

- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin
55b28c7e44
riscv: PRO member function calls
this is enough progress for us to be able to call `stdout.write`!
2024-06-13 02:19:40 -07:00
David Rubin
c457f35da5
riscv: arbitrary sized arrays 2024-06-13 02:19:40 -07:00
David Rubin
f34dcd067b
riscv: basic libc varargs 2024-06-13 02:19:39 -07:00
David Rubin
fcafaae747
riscv: get basic libc interop 2024-06-13 02:19:39 -07:00
David Rubin
004d0c8978
riscv: switch progress + by-ref return progress 2024-06-13 02:19:38 -07:00
Andrew Kelley
4aa15440c7
Merge pull request #20268 from ziglang/keep-calm-and-continue-panicking 2024-06-13 00:21:12 -04:00
Andrew Kelley
5fc1f8a32b std.Thread.Mutex.Recursive: alternate implementation
This version is simpler. Thanks King!
2024-06-12 18:07:39 -07:00
Andrew Kelley
fad223d92e std.Progress: use a recursive mutex for stderr 2024-06-12 17:43:49 -07:00
Andrew Kelley
506b3f6db6 introduce std.Thread.Mutex.Recursive 2024-06-12 17:43:49 -07:00
Andrew Kelley
55a9ea250c std.debug: lock stderr mutex when panicking
The doc comments for this global said:
"Locked to avoid interleaving panic messages from multiple threads."

Huh? There's already a mutex for that, it's the stderr mutex. Lock that
one instead.
2024-06-12 17:09:07 -07:00
Ryan Liptak
0cef727e59 More precise error message for unencodable \u escapes
The surrogate code points U+D800 to U+DFFF are valid code points but are not Unicode scalar values. This commit makes the error message more accurately reflect what is actually allowed in `\u` escape sequences.

From https://www.unicode.org/versions/Unicode15.0.0/ch03.pdf:

> D71 High-surrogate code point: A Unicode code point in the range U+D800 to U+DBFF.
> D73 Low-surrogate code point: A Unicode code point in the range U+DC00 to U+DFFF.
>
> 3.9 Unicode Encoding Forms
> D76 Unicode scalar value: Any Unicode code point except high-surrogate and low-surrogate code points.

Related: #20270
2024-06-12 16:49:00 -04:00
Andrew Kelley
44f4abf380
Merge pull request #20269 from ziglang/fix-progress-race 2024-06-12 13:20:14 -04:00
Andrew Kelley
727f1fa743 update update_cpu_features tool to latest std.Progress API
closes #20261
2024-06-11 15:24:57 -07:00
Andrew Kelley
4b776ae441 std.Progress: fix race assertion failure
A node may be freed during the execution of this loop, causing there to
be a parent reference to a nonexistent node. Without this assignment,
this would lead to the map entry containing stale data. By assigning
none, the child node with the bad parent pointer will be harmlessly
omitted from the tree.

Closes #20262
2024-06-11 15:24:57 -07:00
Robin Voetter
d9bd34fd05
Merge pull request #20247 from Snektron/spirv-vectors-v3
spirv: vectors v3
2024-06-11 08:21:04 +02:00
Robin Voetter
a567f3871e
spirv: improve shuffle codegen 2024-06-10 20:32:50 +02:00
Robin Voetter
a3b1ba82f5
spirv: new vectorization helper
The old vectorization helper (WipElementWise) was clunky and a bit
annoying to use, and it wasn't really flexible enough.

This introduces a new vectorization helper, which uses Temporary and
Operation types to deduce a Vectorization to perform the operation
in a reasonably efficient manner. It removes the outer loop
required by WipElementWise so that implementations of AIR instructions
are cleaner. This helps with sanity when we start to introduce support
for composite integers.

airShift, convertToDirect, convertToIndirect, and normalize are initially
implemented using this new method.
2024-06-10 20:32:49 +02:00
Robin Voetter
4e7159ae1d
spirv: remove OpCompositeConstruct workarounds
Now that we use POCL to test, we no longer need this 
2024-06-10 20:32:43 +02:00
Robin Voetter
4bd9d9b7e0
spirv: change direct vector child repr to direct
Previously the child type of a vector was always in indirect representation.
Concretely, this meant that vectors of bools are represented by vectors
of u8.

This was undesirable because it introduced a difference between vectorizable
operations with a scalar bool and a vector of bool. This commit changes the
representation to be the same for vectors and scalars everywhere.

Some issues arised with constructing vectors: it seems the previous temporary-
and-pointer approach does not work properly with vectors of bool. To work around
this, simply use OpCompositeConstruct. This is the proper instruction for this,
but it was previously not used because of a now-solved limitation in the
SPIRV-LLVM-Translator. It was not yet applied to Zig because the Intel OpenCL
CPU runtime does not have a recent enough version of the translator yet, but
to solve that we just switch to testing with POCL instead.
2024-06-10 20:32:43 +02:00
Robin Voetter
b9d738a5cf
spirv: disable tests that fail on pocl
Besides the Intel OpenCL CPU runtime, we can now run the
behavior tests using the Portable Computing Language. This
implementation is open-source, so it will be easier for us
to patch in updated versions of spirv-llvm-translator that
have bug fixes etc.
2024-06-10 20:32:34 +02:00
mlugg
d4bc64038c Zir: remove legacy error_set_decl variants
These instructions are not emitted by AstGen. They also would have no
effect even if they did appear in ZIR: the Sema handling for these
instructions creates a Decl which the name strategy is applied to, and
proceeds to never use it. This pointless CPU heater is now gone, saving
2 ZIR tags in the process.
2024-06-10 05:02:34 +01:00
Robin Voetter
44443b833b
build: inherit setExecCmd from test compile steps when creating run steps
This should fix #17756
2024-06-09 01:55:50 +02:00
Robin Voetter
fba6b7e4c2
spirv: fix error code encoding 2024-06-09 01:55:49 +02:00
Shane Peelar
ec337051a9 Fix slight deviation from spec in handling Elf*_Rela relative relocations
`Elf*_Rela` relocations store their argument in `r_addend`, including for `R_*_RELATIVE` relocations.  Unlike `Elf*_Rel` relocations, they are not applied as a delta to the destination virtual address.  Instead, they are computed from `base_address + r_addend` directly.
2024-06-08 16:02:47 -04:00