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1389 Commits

Author SHA1 Message Date
Robin Lambertz
96804c6c2c
[AArch64] Make the system registers volatile. 
Currently, reads and writes to system registers do not show up in the decompilation output. Fix this by marking them as volatile.
 2019-06-05 15:17:00 +02:00
Ryan Kurtz
08dbf35254 Merge remote-tracking branch 'origin/GT-2828_GhidorahRex_PR-346_ahroach_AVR8_add_ISA_manual_index_file' 2019-06-04 12:52:38 -04:00
GhidorahRex
da4b11981d GT-2828: Accepting pull request 
Pulled-from: Austin Roach <ahroach@gmail.com>
 2019-06-04 12:49:44 -04:00
Ryan Kurtz
ba2226a239 Merge remote-tracking branch 'origin/GT-2896_ryanmkurtz_PR-649_bonbom1_update8051' 2019-06-04 12:12:31 -04:00
Philip Pemberton
a4c4b5f7c7 Add noddy definition of the TEQ<cc>P instruction. 
Note that this doesn't take into account the subtleties of what TEQP
does -- for more information on this, see
https://www.heyrick.co.uk/armwiki/The_Status_register#Legacy_processors_.2826_bit.29

It will, however, stop Ghidra from completely freaking out when it sees
this instruction in old RISC OS 26bit-PC code.

TODO, make this behave (in SLEIGH) like a PSR update (MSR CPSR, ...) but
note that the PSR bit order is different to the 26bit ARM PSR so fudging
will be needed.
 2019-06-04 14:20:31 +01:00
Ryan Kurtz
a9d50254d2 GT-2896 (closes #649): Certified. 
Pulled-from: Tommi <tommi.karppa@gmail.com>
 2019-06-04 09:12:43 -04:00
Ryan Kurtz
b8f042da80 GT-2343: New DYLD shared cache loader. 2019-06-04 08:47:51 -04:00
Tommi
981c283a54
Update Update8051.java 2019-06-02 23:39:27 +03:00
Tommi
ad5534a7cb
Update Update8051.java 
flaw in logic
 2019-06-02 23:16:51 +03:00
Marcus Comstedt
45cfc3cfc2 Add processor implementation for 8048 (MCS-48) 2019-05-30 19:34:44 +02:00
GhidorahRex
67301a9013 GT-2876: Updated Z80 slaspec for additional issues. 
Pulled-from: Dennis Brakhane <brakhane@gmail.com>
 2019-05-17 15:20:37 -04:00
Markus Piéton
508c9a7ea0 Updating MIPS Processor Manuals to latest version. 
* MIPS Architecture For Programmers Volume II-A:
      MD00087-2B-MIPS64BIS-AFP-6.06.pdf
  * MIPS Architecture for Programmers Volume II-B: microMIPS64
      MD00594-2B-microMIPS64-AFP-6.05.pdf
  * MIPS Architecture for Programmers Volume II-B: microMIPS32
      MIPS_Architecture_microMIPS32_InstructionSet_AFP_P_MD00582_06.04.pdf

Document Source:

  * https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
  * https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00594-2B-microMIPS64-AFP-6.05.pdf
  * https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MIPS_Architecture_microMIPS32_InstructionSet_AFP_P_MD00582_06.04.pdf
 2019-05-11 11:45:05 +02:00
Ryan Kurtz
79509193dd Merge remote-tracking branch 'origin/GT-2860_ryanmkurtz_PR-415_neutralinsomniac_remove-dup-code' 2019-05-10 13:47:10 -04:00
ghidra1
16a7aa5b85 Merge remote-tracking branch 'origin/GT-2826_GhidorahRex_PR-469_agatti_Correct_6502_index_flag_bit' 2019-05-09 17:51:50 -04:00
ghidra1
0fc0250762 Merge remote-tracking branch 'origin/GT-2781_GhidorahRex_PR-387_aldelaro5_PowerPC_FLOAT_NEG' 2019-05-09 17:51:24 -04:00
ghidra1
7403e884a8 Merge remote-tracking branch 'origin/GT-2744_GhidorahRex_PR-362_ARM_THUMB' 2019-05-09 17:38:41 -04:00
ghidra1
ba4e6218ce Merge remote-tracking branch 'origin/ghidorahrex_GT-2768' 2019-05-09 16:59:56 -04:00
Andrew Cooper
28d473fed9 x86: Support for {RD,WR}{FS,GS}BASE instructions 
This was derived from the existing readPID instruction, whose encoding is very
similar.

Fixes #554
 2019-05-06 19:35:08 +01:00
Dennis Brakhane
416772c426 Z80: fix alternate registers 
The 8-bit alternate registers were swapped, the low part of BC'
was specified as being B' instead of C'
 2019-04-27 03:01:54 +02:00
ghidravore
f1e50fb079 Major refactoring of the gradle build system. 2019-04-23 15:20:26 -04:00
Alessandro Gatti
48150b1870 Use proper bit index for 6502 Interrupt flag. 2019-04-19 17:04:28 +02:00
ghidravore
8f9a8dd1b1 Merge remote-tracking branch 'origin/Ghidra_9.0.3' 2019-04-17 18:49:15 -04:00
ghidravore
aa7ba796fd Merge remote-tracking branch 'origin/emteere_GT-2759' into Ghidra_9.0.3 2019-04-17 18:42:06 -04:00
ghidravore
163da67799 Merge remote-tracking branch 'origin/GT-2807_emteere' into Ghidra_9.0.3 2019-04-17 18:39:55 -04:00
emteere
0859edf517 GT_2807_emteere Semantics for BCD arithmetic instructions in 68K 2019-04-17 12:19:07 -04:00
ghidorahrex
bc6f6ad927 GT-2768: Corrected spelling and index for mips reference manual. 2019-04-16 14:03:16 -04:00
emteere
008cf415b2 GT-2759 Fixed 6502 processor module Zero Page indexed addressing. 2019-04-15 16:42:57 -04:00
caheckman
53d9018f9e GT-2755: certified 
Pulled-from: Markus Piéton <marpie@a12d404.net>
 2019-04-15 11:22:55 -04:00
Markus Piéton
bdcbe2cf3a Callfixup for _guard_dispatch_icall on x86-64-win 
Change goto to call
As pointed out by @caheckman [here](https://github.com/NationalSecurityAgency/ghidra/pull/340#issuecomment-482248465) the `goto` should be a `call`.
 2019-04-15 11:15:12 -04:00
Jeremy O'Brien
8a1a70d7ba Remove duplicated options in MipsAddressAnalyzer 2019-04-12 13:43:25 -04:00
Dan
03258283d2 GT-2744 (closes #362): ARM and THUMB corrections. 
Pulled-from: mumbel <mumbel@localhost.localdomain>
 2019-04-10 12:19:15 -04:00
caheckman
c87adb2115 Fix for invalid UTF, fix for multiple anonymous function definitions 2019-04-09 14:51:37 -04:00
aldelaro5
e51128e46f Processors/PowerPC: Use FLOAT_NEG on fneg and fneg. instructions 
It was causing weird decompilation output.
 2019-04-09 01:09:38 -04:00
Kreeblah
b00852877c Updated x86 manual index 
Updated x86 manual indexes to the following:

Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z, Sep 2016 (325383-060US), available at https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf

AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Rev 3.26 May 2018 (24594), available at https://www.amd.com/system/files/TechDocs/24594.pdf

AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, Rev 3.23 Feb 2019 (26568), available at https://www.amd.com/system/files/TechDocs/26568.pdf

AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions, Rev 3.15 May 2018 (26569), available at https://www.amd.com/system/files/TechDocs/26569_APM_v5.pdf

AMD64 Technology 128-Bit SSE5 Instruction Set, Rev 3.01 August 2007 (43479), which is unchanged from the provided .idx. I can't find a newer version of the publication (or a different publication) that lists the same instructions, so I left it as it was. The only copy of the actual publication that I can find is at http://www.cs.northwestern.edu/~pdinda/icsclass/doc/AMD_ARCH_MANUALS/AMD64_128_Bit_SSE5_Instrs.pdf but it looks to be incomplete, as it stops at ROUNDSS.
 2019-04-06 09:56:12 -07:00
mumbel
5028d3015d ARM and THUMB corrections 
ADD (SP plus register, T32) was incorrectly op11=0x1e (1 1 1 1 0),
but is supposed to be 0x1d (1 1 1 0 1)

ARM's CLREX matches THUMB's BL<c> <label>.  Added AMODE check to
CLREX
 2019-04-05 22:07:30 -05:00
Austin Roach
1aed26b4d3 AVR8: Add ISA manual index file 2019-04-04 20:32:23 -04:00
emteere
8cf5b0f2c6 GT-2722 updates for CMP.W and LSL instruction decodes 2019-04-02 10:45:18 -04:00
ghidra1
7179c6de81 GT-2667 added support for generating sleigh build.xml files 2019-03-29 17:24:31 -04:00
Dan
79d8f164f8 Candidate release of source code. 2019-03-26 13:46:51 -04:00