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GT-2759 Fixed 6502 processor module Zero Page indexed addressing.

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This commit is contained in:
emteere 2019-04-15 16:42:57 -04:00
parent 38edad78f1
commit 008cf415b2
1 changed files with 37 additions and 26 deletions
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63
Ghidra/Processors/6502/data/languages/6502.slaspec
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@ -78,35 +78,46 @@ define pcodeop readIRQ;
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REL: reloc is rel [ reloc = inst_next + rel; ] { export *:2 reloc; }
# Immediate
OP1: "#"imm8 is bbb=2; imm8 { tmp:1 = imm8; export tmp; }
# Zero Page
OP1: imm8 is bbb=1; imm8 { export *:1 imm8; }
# Zero Page Indexed X
OP1: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
# Absolute
OP1: imm16 is bbb=3; imm16 { export *:1 imm16; }
# Absolute Indexed X
OP1: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
# Absolute Indexed Y
OP1: imm16,Y is bbb=6 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
# Indirect X
OP1: (imm8,X) is bbb=0 & X; imm8 { addr:2 = zext(imm8 + X); tmp:2 = *:2 addr; export *:1 tmp; }
# Indirect Y
OP1: (imm8),Y is bbb=4 & Y; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; }
OP1: (imm8,X) is bbb=0 & X; imm8 { addr:2 = imm8 + zext(X); tmp:2 = *:2 addr; export *:1 tmp; }
OP1: imm8 is bbb=1; imm8 { export *:1 imm8; }
OP1: "#"imm8 is bbb=2; imm8 { tmp:1 = imm8; export tmp; }
OP1: imm16 is bbb=3; imm16 { export *:1 imm16; }
OP1: (imm8),Y is bbb=4 & Y; imm8 { addr:2 = imm8; tmp:2 = *:2 addr; tmp = tmp + zext(Y); export *:1 tmp; }
OP1: imm8,X is bbb=5 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; }
OP1: imm16,Y is bbb=6 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
OP1: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
# Immediate
OP2: "#"imm8 is bbb=0; imm8 { tmp:1 = imm8; export tmp; }
# Zero Page
OP2: imm8 is bbb=1; imm8 { export *:1 imm8; }
OP2: A is bbb=2 & A { export A; }
# Absolute
OP2: imm16 is bbb=3; imm16 { export *:1 imm16; }
# Zero Page Indexed X
OP2: imm8,X is bbb=5 & X; imm8 { tmp:2 = zext(imm8 + X); export *:1 tmp; }
# Absolute Indexed X
OP2: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
OP2ST: OP2 is OP2 { export OP2; }
OP2ST: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
OP2LD: OP2 is OP2 { export OP2; }
OP2LD: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = zext(imm8 + Y); export *:1 tmp; }
OP2LD: imm16,Y is bbb=7 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
OP2: "#"imm8 is bbb=0; imm8 { tmp:1 = imm8; export tmp; }
OP2: imm8 is bbb=1; imm8 { export *:1 imm8; }
OP2: A is bbb=2 & A { export A; }
OP2: imm16 is bbb=3; imm16 { export *:1 imm16; }
OP2: imm8,X is bbb=5 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; }
OP2: imm16,X is bbb=7 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
OP2ST: OP2 is OP2 { export OP2; }
OP2ST: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = imm8 + zext(Y); export *:1 tmp; }
OP2LD: OP2 is OP2 { export OP2; }
OP2LD: imm8,Y is bbb=5 & Y; imm8 { tmp:2 = imm8 + zext(Y); export *:1 tmp; }
OP2LD: imm16,Y is bbb=7 & Y; imm16 { tmp:2 = imm16 + zext(Y); export *:1 tmp; }
ADDR8: imm8 is imm8 { export *:1 imm8; }
ADDR16: imm16 is imm16 { export *:1 imm16; }
ADDRI: imm16 is imm16 { tmp:2 = imm16; export *:2 tmp; }
ADDR8: imm8 is imm8 { export *:1 imm8; }
ADDR16: imm16 is imm16 { export *:1 imm16; }
ADDRI: imm16 is imm16 { tmp:2 = imm16; export *:2 tmp; }
# Instructions