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Merge remote-tracking branch 'origin/GT-2807_emteere' into Ghidra_9.0.3
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commit
163da67799
@ -306,6 +306,8 @@ define pcodeop saveFPUStateFrame;
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define pcodeop restoreFPUStateFrame;
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define pcodeop pushInvalidateCaches;
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define pcodeop bcdAdjust;
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define pcodeop sin;
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define pcodeop cos;
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define pcodeop tan;
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@ -638,12 +640,15 @@ macro clearflags_fp() {
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$(NAN_FP) = 0;
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}
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# SCR 10997:
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macro bcdflags(result) {
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XF = CF;
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ZF = (result == 0) * ZF + (result != 0);
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}
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macro getbit(res,in,bitnum) {
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res = ((in >> bitnum) & 1) != 0;
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}
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# SCR 10997:
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macro bitmask(res, width) {
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res = (1 << width) - 1;
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}
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@ -656,7 +661,6 @@ macro getbitfield(res, off, width) {
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res = (res << off) >> (32 - width);
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}
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# SCR 10997:
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macro resbitflags(result, bitnum) {
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NF = ((result >> bitnum) & 1) != 0;
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ZF = result == 0;
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@ -687,7 +691,7 @@ macro extendedResultFlags(result) {
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with : extGUARD=1 {
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:abcd Tyb,Txb is op=12 & op48=16 & Tyb & Txb unimpl
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:abcd Tyb,Txb is op=12 & op48=16 & Tyb & Txb { CF = carry(Tyb,carry(Txb,XF)); Tyb = Tyb + Txb + XF; Tyb = bcdAdjust(Tyb); bcdflags(Tyb); }
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:add.b eab,reg9dnb is (op=13 & reg9dnb & op68=0)... & eab { addflags(eab,reg9dnb); reg9dnb = reg9dnb + eab; resflags(reg9dnb); }
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:add.w eaw,reg9dnw is (op=13 & reg9dnw & op68=1)... & eaw { addflags(eaw,reg9dnw); reg9dnw = reg9dnw + eaw; resflags(reg9dnw); }
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@ -1391,7 +1395,8 @@ submul: regdr-regdq is regdq & divsgn=0 & divsz=1 & regdr { tmp1:8 = zext(glb
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regdr=res(4); resflags(res); CF=0; VF=0; }
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:mul^mulsize e2l,submul is opbig=0x4c & op67=0 & $(DAT_ALTER_ADDR_MODES); submul & mulsize; e2l [ savmod2=savmod1; regtsan=regtfan; ] { glbdenom=e2l; build submul; }
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:nbcd eab is (opbig=0x48 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab unimpl
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:nbcd eab is (opbig=0x48 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab
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{ tmp:1 = eab; CF = (tmp != 0) || (XF == 1); tmp = 0 - tmp - XF; eab = bcdAdjust(tmp); bcdflags(tmp); }
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# NB: For the neg insn the CF carry flag is not set like other insns, from the manual:
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@ -1600,7 +1605,8 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; }
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:rts is opbig=0x4e & op37=14 & op02=5 { PC = *SP; SP = SP+4; return [PC]; }
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:sbcd Tyb,Txb is op=8 & op48=16 & Txb & Tyb unimpl
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:sbcd Tyb,Txb is op=8 & op48=16 & Txb & Tyb
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{ CF = (Tyb < Txb) || ( (XF == 1) && (Tyb == Txb) ); Tyb = Tyb - Txb - XF; Tyb = bcdAdjust(Tyb); bcdflags(Tyb); }
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:s^cc eab is (op=5 & cc & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = -cc; }
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