Dennis Brakhane
416772c426
Z80: fix alternate registers
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The 8-bit alternate registers were swapped, the low part of BC'
was specified as being B' instead of C'
2019-04-27 03:01:54 +02:00
ghidravore
f1e50fb079
Major refactoring of the gradle build system.
2019-04-23 15:20:26 -04:00
Alessandro Gatti
48150b1870
Use proper bit index for 6502 Interrupt flag.
2019-04-19 17:04:28 +02:00
ghidravore
8f9a8dd1b1
Merge remote-tracking branch 'origin/Ghidra_9.0.3'
2019-04-17 18:49:15 -04:00
ghidravore
aa7ba796fd
Merge remote-tracking branch 'origin/emteere_GT-2759' into Ghidra_9.0.3
2019-04-17 18:42:06 -04:00
ghidravore
163da67799
Merge remote-tracking branch 'origin/GT-2807_emteere' into Ghidra_9.0.3
2019-04-17 18:39:55 -04:00
emteere
0859edf517
GT_2807_emteere Semantics for BCD arithmetic instructions in 68K
2019-04-17 12:19:07 -04:00
ghidorahrex
bc6f6ad927
GT-2768: Corrected spelling and index for mips reference manual.
2019-04-16 14:03:16 -04:00
emteere
008cf415b2
GT-2759 Fixed 6502 processor module Zero Page indexed addressing.
2019-04-15 16:42:57 -04:00
caheckman
53d9018f9e
GT-2755: certified
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Pulled-from: Markus Piéton <marpie@a12d404.net>
2019-04-15 11:22:55 -04:00
Markus Piéton
bdcbe2cf3a
Callfixup for _guard_dispatch_icall on x86-64-win
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Change goto to call
As pointed out by @caheckman [here](https://github.com/NationalSecurityAgency/ghidra/pull/340#issuecomment-482248465 ) the `goto` should be a `call`.
2019-04-15 11:15:12 -04:00
Jeremy O'Brien
8a1a70d7ba
Remove duplicated options in MipsAddressAnalyzer
2019-04-12 13:43:25 -04:00
Dan
03258283d2
GT-2744 ( closes #362 ): ARM and THUMB corrections.
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Pulled-from: mumbel <mumbel@localhost.localdomain>
2019-04-10 12:19:15 -04:00
caheckman
c87adb2115
Fix for invalid UTF, fix for multiple anonymous function definitions
2019-04-09 14:51:37 -04:00
aldelaro5
e51128e46f
Processors/PowerPC: Use FLOAT_NEG on fneg and fneg. instructions
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It was causing weird decompilation output.
2019-04-09 01:09:38 -04:00
Kreeblah
b00852877c
Updated x86 manual index
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Updated x86 manual indexes to the following:
Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z, Sep 2016 (325383-060US), available at https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Rev 3.26 May 2018 (24594), available at https://www.amd.com/system/files/TechDocs/24594.pdf
AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, Rev 3.23 Feb 2019 (26568), available at https://www.amd.com/system/files/TechDocs/26568.pdf
AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions, Rev 3.15 May 2018 (26569), available at https://www.amd.com/system/files/TechDocs/26569_APM_v5.pdf
AMD64 Technology 128-Bit SSE5 Instruction Set, Rev 3.01 August 2007 (43479), which is unchanged from the provided .idx. I can't find a newer version of the publication (or a different publication) that lists the same instructions, so I left it as it was. The only copy of the actual publication that I can find is at http://www.cs.northwestern.edu/~pdinda/icsclass/doc/AMD_ARCH_MANUALS/AMD64_128_Bit_SSE5_Instrs.pdf but it looks to be incomplete, as it stops at ROUNDSS.
2019-04-06 09:56:12 -07:00
mumbel
5028d3015d
ARM and THUMB corrections
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ADD (SP plus register, T32) was incorrectly op11=0x1e (1 1 1 1 0),
but is supposed to be 0x1d (1 1 1 0 1)
ARM's CLREX matches THUMB's BL<c> <label>. Added AMODE check to
CLREX
2019-04-05 22:07:30 -05:00
Austin Roach
1aed26b4d3
AVR8: Add ISA manual index file
2019-04-04 20:32:23 -04:00
emteere
8cf5b0f2c6
GT-2722 updates for CMP.W and LSL instruction decodes
2019-04-02 10:45:18 -04:00
ghidra1
7179c6de81
GT-2667 added support for generating sleigh build.xml files
2019-03-29 17:24:31 -04:00
Dan
79d8f164f8
Candidate release of source code.
2019-03-26 13:46:51 -04:00
