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Ampere SoC PMU follows CoreSight PMU architecture. It uses implementation specific registers to filter events rather than PMEVFILTnR registers. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20230913233941.9814-5-ilkka@os.amperecomputing.com [will: Include linux/io.h in ampere_cspmu.c for writel()] Signed-off-by: Will Deacon <will@kernel.org>
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913 B
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30 lines
913 B
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.. SPDX-License-Identifier: GPL-2.0
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============================================
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Ampere SoC Performance Monitoring Unit (PMU)
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============================================
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Ampere SoC PMU is a generic PMU IP that follows Arm CoreSight PMU architecture.
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Therefore, the driver is implemented as a submodule of arm_cspmu driver. At the
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first phase it's used for counting MCU events on AmpereOne.
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MCU PMU events
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--------------
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The PMU driver supports setting filters for "rank", "bank", and "threshold".
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Note, that the filters are per PMU instance rather than per event.
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Example for perf tool use::
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/ # perf list ampere
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ampere_mcu_pmu_0/act_sent/ [Kernel PMU event]
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<...>
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ampere_mcu_pmu_1/rd_sent/ [Kernel PMU event]
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<...>
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/ # perf stat -a -e ampere_mcu_pmu_0/act_sent,bank=5,rank=3,threshold=2/,ampere_mcu_pmu_1/rd_sent/ \
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sleep 1
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