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perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU
Ampere SoC PMU follows CoreSight PMU architecture. It uses implementation specific registers to filter events rather than PMEVFILTnR registers. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Link: https://lore.kernel.org/r/20230913233941.9814-5-ilkka@os.amperecomputing.com [will: Include linux/io.h in ampere_cspmu.c for writel()] Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Ilkka Koskinen
Will Deacon
parent
647d5c5a9e
commit
53a810ad3c
29
Documentation/admin-guide/perf/ampere_cspmu.rst
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29
Documentation/admin-guide/perf/ampere_cspmu.rst
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@ -0,0 +1,29 @@
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.. SPDX-License-Identifier: GPL-2.0
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============================================
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Ampere SoC Performance Monitoring Unit (PMU)
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============================================
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Ampere SoC PMU is a generic PMU IP that follows Arm CoreSight PMU architecture.
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Therefore, the driver is implemented as a submodule of arm_cspmu driver. At the
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first phase it's used for counting MCU events on AmpereOne.
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MCU PMU events
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--------------
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The PMU driver supports setting filters for "rank", "bank", and "threshold".
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Note, that the filters are per PMU instance rather than per event.
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Example for perf tool use::
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/ # perf list ampere
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ampere_mcu_pmu_0/act_sent/ [Kernel PMU event]
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<...>
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ampere_mcu_pmu_1/rd_sent/ [Kernel PMU event]
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<...>
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/ # perf stat -a -e ampere_mcu_pmu_0/act_sent,bank=5,rank=3,threshold=2/,ampere_mcu_pmu_1/rd_sent/ \
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sleep 1
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@ -17,3 +17,13 @@ config NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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help
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Provides NVIDIA specific attributes for performance monitoring unit
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(PMU) devices based on ARM CoreSight PMU architecture.
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config AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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tristate "Ampere Coresight Architecture PMU"
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depends on ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU
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help
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Provides Ampere specific attributes for performance monitoring unit
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(PMU) devices based on ARM CoreSight PMU architecture.
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In the first phase, the driver enables support on MCU PMU used in
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AmpereOne SoC family.
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@ -3,6 +3,8 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += arm_cspmu_module.o
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arm_cspmu_module-y := arm_cspmu.o
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obj-$(CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += nvidia_cspmu.o
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obj-$(CONFIG_AMPERE_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += ampere_cspmu.o
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272
drivers/perf/arm_cspmu/ampere_cspmu.c
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272
drivers/perf/arm_cspmu/ampere_cspmu.c
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@ -0,0 +1,272 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Ampere SoC PMU (Performance Monitor Unit)
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*
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* Copyright (c) 2023, Ampere Computing LLC
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/topology.h>
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#include "arm_cspmu.h"
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#define PMAUXR0 0xD80
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#define PMAUXR1 0xD84
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#define PMAUXR2 0xD88
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#define PMAUXR3 0xD8C
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#define to_ampere_cspmu_ctx(cspmu) ((struct ampere_cspmu_ctx *)(cspmu->impl.ctx))
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struct ampere_cspmu_ctx {
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const char *name;
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struct attribute **event_attr;
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struct attribute **format_attr;
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};
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static DEFINE_IDA(mcu_pmu_ida);
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#define SOC_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) \
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static inline u32 get_##_name(const struct perf_event *event) \
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{ \
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return FIELD_GET(GENMASK_ULL(_end, _start), \
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event->attr._config); \
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} \
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SOC_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 8);
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SOC_PMU_EVENT_ATTR_EXTRACTOR(threshold, config1, 0, 7);
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SOC_PMU_EVENT_ATTR_EXTRACTOR(rank, config1, 8, 23);
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SOC_PMU_EVENT_ATTR_EXTRACTOR(bank, config1, 24, 55);
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static struct attribute *ampereone_mcu_pmu_event_attrs[] = {
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ARM_CSPMU_EVENT_ATTR(cycle_count, 0x00),
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ARM_CSPMU_EVENT_ATTR(act_sent, 0x01),
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ARM_CSPMU_EVENT_ATTR(pre_sent, 0x02),
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ARM_CSPMU_EVENT_ATTR(rd_sent, 0x03),
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ARM_CSPMU_EVENT_ATTR(rda_sent, 0x04),
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ARM_CSPMU_EVENT_ATTR(wr_sent, 0x05),
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ARM_CSPMU_EVENT_ATTR(wra_sent, 0x06),
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ARM_CSPMU_EVENT_ATTR(pd_entry_vld, 0x07),
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ARM_CSPMU_EVENT_ATTR(sref_entry_vld, 0x08),
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ARM_CSPMU_EVENT_ATTR(prea_sent, 0x09),
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ARM_CSPMU_EVENT_ATTR(pre_sb_sent, 0x0a),
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ARM_CSPMU_EVENT_ATTR(ref_sent, 0x0b),
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ARM_CSPMU_EVENT_ATTR(rfm_sent, 0x0c),
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ARM_CSPMU_EVENT_ATTR(ref_sb_sent, 0x0d),
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ARM_CSPMU_EVENT_ATTR(rfm_sb_sent, 0x0e),
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ARM_CSPMU_EVENT_ATTR(rd_rda_sent, 0x0f),
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ARM_CSPMU_EVENT_ATTR(wr_wra_sent, 0x10),
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ARM_CSPMU_EVENT_ATTR(raw_hazard, 0x11),
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ARM_CSPMU_EVENT_ATTR(war_hazard, 0x12),
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ARM_CSPMU_EVENT_ATTR(waw_hazard, 0x13),
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ARM_CSPMU_EVENT_ATTR(rar_hazard, 0x14),
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ARM_CSPMU_EVENT_ATTR(raw_war_waw_hazard, 0x15),
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ARM_CSPMU_EVENT_ATTR(hprd_lprd_wr_req_vld, 0x16),
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ARM_CSPMU_EVENT_ATTR(lprd_req_vld, 0x17),
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ARM_CSPMU_EVENT_ATTR(hprd_req_vld, 0x18),
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ARM_CSPMU_EVENT_ATTR(hprd_lprd_req_vld, 0x19),
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ARM_CSPMU_EVENT_ATTR(prefetch_tgt, 0x1a),
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ARM_CSPMU_EVENT_ATTR(wr_req_vld, 0x1b),
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ARM_CSPMU_EVENT_ATTR(partial_wr_req_vld, 0x1c),
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ARM_CSPMU_EVENT_ATTR(rd_retry, 0x1d),
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ARM_CSPMU_EVENT_ATTR(wr_retry, 0x1e),
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ARM_CSPMU_EVENT_ATTR(retry_gnt, 0x1f),
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ARM_CSPMU_EVENT_ATTR(rank_change, 0x20),
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ARM_CSPMU_EVENT_ATTR(dir_change, 0x21),
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ARM_CSPMU_EVENT_ATTR(rank_dir_change, 0x22),
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ARM_CSPMU_EVENT_ATTR(rank_active, 0x23),
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ARM_CSPMU_EVENT_ATTR(rank_idle, 0x24),
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ARM_CSPMU_EVENT_ATTR(rank_pd, 0x25),
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ARM_CSPMU_EVENT_ATTR(rank_sref, 0x26),
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ARM_CSPMU_EVENT_ATTR(queue_fill_gt_thresh, 0x27),
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ARM_CSPMU_EVENT_ATTR(queue_rds_gt_thresh, 0x28),
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ARM_CSPMU_EVENT_ATTR(queue_wrs_gt_thresh, 0x29),
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ARM_CSPMU_EVENT_ATTR(phy_updt_complt, 0x2a),
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ARM_CSPMU_EVENT_ATTR(tz_fail, 0x2b),
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ARM_CSPMU_EVENT_ATTR(dram_errc, 0x2c),
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ARM_CSPMU_EVENT_ATTR(dram_errd, 0x2d),
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ARM_CSPMU_EVENT_ATTR(read_data_return, 0x32),
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ARM_CSPMU_EVENT_ATTR(chi_wr_data_delta, 0x33),
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ARM_CSPMU_EVENT_ATTR(zq_start, 0x34),
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ARM_CSPMU_EVENT_ATTR(zq_latch, 0x35),
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ARM_CSPMU_EVENT_ATTR(wr_fifo_full, 0x36),
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ARM_CSPMU_EVENT_ATTR(info_fifo_full, 0x37),
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ARM_CSPMU_EVENT_ATTR(cmd_fifo_full, 0x38),
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ARM_CSPMU_EVENT_ATTR(dfi_nop, 0x39),
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ARM_CSPMU_EVENT_ATTR(dfi_cmd, 0x3a),
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ARM_CSPMU_EVENT_ATTR(rd_run_len, 0x3b),
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ARM_CSPMU_EVENT_ATTR(wr_run_len, 0x3c),
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ARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT),
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NULL,
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};
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static struct attribute *ampereone_mcu_format_attrs[] = {
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ARM_CSPMU_FORMAT_EVENT_ATTR,
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ARM_CSPMU_FORMAT_ATTR(threshold, "config1:0-7"),
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ARM_CSPMU_FORMAT_ATTR(rank, "config1:8-23"),
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ARM_CSPMU_FORMAT_ATTR(bank, "config1:24-55"),
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NULL,
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};
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static struct attribute **
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ampere_cspmu_get_event_attrs(const struct arm_cspmu *cspmu)
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{
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const struct ampere_cspmu_ctx *ctx = to_ampere_cspmu_ctx(cspmu);
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return ctx->event_attr;
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}
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static struct attribute **
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ampere_cspmu_get_format_attrs(const struct arm_cspmu *cspmu)
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{
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const struct ampere_cspmu_ctx *ctx = to_ampere_cspmu_ctx(cspmu);
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return ctx->format_attr;
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}
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static const char *
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ampere_cspmu_get_name(const struct arm_cspmu *cspmu)
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{
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const struct ampere_cspmu_ctx *ctx = to_ampere_cspmu_ctx(cspmu);
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return ctx->name;
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}
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static u32 ampere_cspmu_event_filter(const struct perf_event *event)
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{
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/*
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* PMEVFILTR or PMCCFILTR aren't used in Ampere SoC PMU but are marked
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* as RES0. Make sure, PMCCFILTR is written zero.
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*/
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return 0;
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}
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static void ampere_cspmu_set_ev_filter(struct arm_cspmu *cspmu,
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struct hw_perf_event *hwc,
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u32 filter)
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{
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struct perf_event *event;
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unsigned int idx;
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u32 threshold, rank, bank;
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/*
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* At this point, all the events have the same filter settings.
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* Therefore, take the first event and use its configuration.
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*/
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idx = find_first_bit(cspmu->hw_events.used_ctrs,
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cspmu->cycle_counter_logical_idx);
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event = cspmu->hw_events.events[idx];
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threshold = get_threshold(event);
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rank = get_rank(event);
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bank = get_bank(event);
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writel(threshold, cspmu->base0 + PMAUXR0);
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writel(rank, cspmu->base0 + PMAUXR1);
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writel(bank, cspmu->base0 + PMAUXR2);
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}
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static int ampere_cspmu_validate_configs(struct perf_event *event,
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struct perf_event *event2)
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{
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if (get_threshold(event) != get_threshold(event2) ||
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get_rank(event) != get_rank(event2) ||
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get_bank(event) != get_bank(event2))
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return -EINVAL;
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return 0;
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}
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static int ampere_cspmu_validate_event(struct arm_cspmu *cspmu,
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struct perf_event *new)
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{
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struct perf_event *curr, *leader = new->group_leader;
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unsigned int idx;
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int ret;
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ret = ampere_cspmu_validate_configs(new, leader);
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if (ret)
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return ret;
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/* We compare the global filter settings to the existing events */
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idx = find_first_bit(cspmu->hw_events.used_ctrs,
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cspmu->cycle_counter_logical_idx);
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/* This is the first event, thus any configuration is fine */
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if (idx == cspmu->cycle_counter_logical_idx)
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return 0;
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curr = cspmu->hw_events.events[idx];
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return ampere_cspmu_validate_configs(curr, new);
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}
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static char *ampere_cspmu_format_name(const struct arm_cspmu *cspmu,
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const char *name_pattern)
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{
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struct device *dev = cspmu->dev;
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int id;
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id = ida_alloc(&mcu_pmu_ida, GFP_KERNEL);
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if (id < 0)
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return ERR_PTR(id);
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return devm_kasprintf(dev, GFP_KERNEL, name_pattern, id);
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}
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static int ampere_cspmu_init_ops(struct arm_cspmu *cspmu)
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{
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struct device *dev = cspmu->dev;
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struct ampere_cspmu_ctx *ctx;
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struct arm_cspmu_impl_ops *impl_ops = &cspmu->impl.ops;
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ctx = devm_kzalloc(dev, sizeof(struct ampere_cspmu_ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctx->event_attr = ampereone_mcu_pmu_event_attrs;
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ctx->format_attr = ampereone_mcu_format_attrs;
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ctx->name = ampere_cspmu_format_name(cspmu, "ampere_mcu_pmu_%d");
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if (IS_ERR_OR_NULL(ctx->name))
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return ctx->name ? PTR_ERR(ctx->name) : -ENOMEM;
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cspmu->impl.ctx = ctx;
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impl_ops->event_filter = ampere_cspmu_event_filter;
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impl_ops->set_ev_filter = ampere_cspmu_set_ev_filter;
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impl_ops->validate_event = ampere_cspmu_validate_event;
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impl_ops->get_name = ampere_cspmu_get_name;
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impl_ops->get_event_attrs = ampere_cspmu_get_event_attrs;
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impl_ops->get_format_attrs = ampere_cspmu_get_format_attrs;
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return 0;
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}
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/* Match all Ampere Coresight PMU devices */
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static const struct arm_cspmu_impl_match ampere_cspmu_param = {
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.pmiidr_val = ARM_CSPMU_IMPL_ID_AMPERE,
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.module = THIS_MODULE,
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.impl_init_ops = ampere_cspmu_init_ops
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};
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static int __init ampere_cspmu_init(void)
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{
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int ret;
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ret = arm_cspmu_impl_register(&ere_cspmu_param);
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if (ret)
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pr_err("ampere_cspmu backend registration error: %d\n", ret);
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return ret;
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}
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static void __exit ampere_cspmu_exit(void)
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{
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arm_cspmu_impl_unregister(&ere_cspmu_param);
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}
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module_init(ampere_cspmu_init);
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module_exit(ampere_cspmu_exit);
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MODULE_LICENSE("GPL");
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@ -383,6 +383,14 @@ static struct arm_cspmu_impl_match impl_match[] = {
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.module = NULL,
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.impl_init_ops = NULL,
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},
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{
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.module_name = "ampere_cspmu",
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.pmiidr_val = ARM_CSPMU_IMPL_ID_AMPERE,
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.pmiidr_mask = ARM_CSPMU_PMIIDR_IMPLEMENTER,
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.module = NULL,
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.impl_init_ops = NULL,
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},
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{0}
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};
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@ -71,6 +71,7 @@
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/* JEDEC-assigned JEP106 identification code */
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#define ARM_CSPMU_IMPL_ID_NVIDIA 0x36B
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#define ARM_CSPMU_IMPL_ID_AMPERE 0xA16
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struct arm_cspmu;
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