exynos9820(dtsi): minimal dtsi

.azure-pipelines.yml

@@ -2,16 +2,14 @@ variables:
   windows_vm: windows-2019
   ubuntu_vm: ubuntu-18.04
   macos_vm: macOS-10.15
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20211006-14Nov2021
   # Add '-u 0' options for Azure pipelines, otherwise we get "permission
   # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
   # since our $(ci_runner_image) user is not root.
   container_option: -u 0
   work_dir: /u
 
-stages:
-- stage: testsuites
-  jobs:
+jobs:
   - job: tools_only_windows
     displayName: 'Ensure host tools build for Windows'
     pool:
@@ -23,10 +21,9 @@ stages:
       - script: |
           sfx.exe -y -o%CD:~0,2%\
           %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu"
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Su"
         displayName: 'Update MSYS2'
       - script: |
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel"
+          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel"
         displayName: 'Install Toolchain'
       - script: |
           echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
@@ -43,7 +40,7 @@ stages:
     pool:
       vmImage: $(macos_vm)
     steps:
-      - script: brew install make ossp-uuid
+      - script: brew install make
         displayName: Brew install dependencies
       - script: |
           gmake tools-only_config tools-only NO_SDL=1 \
@@ -52,33 +49,6 @@ stages:
             -j$(sysctl -n hw.logicalcpu)
         displayName: 'Perform tools-only build'
 
-  - job: check_for_migrated_symbols_in_board_header
-    displayName: 'Check for migrated symbols in board header'
-    pool:
-      vmImage: $(ubuntu_vm)
-    container:
-      image: $(ci_runner_image)
-      options: $(container_option)
-    steps:
-      - script: |
-          KSYMLST=`mktemp`
-          KUSEDLST=`mktemp`
-          cat `find . -name "Kconfig*"` | \
-             sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-             | sort -u > $KSYMLST
-          for CFG in `find include/configs -name "*.h"`; do
-             grep '#define[[:blank:]]CONFIG_' $CFG | \
-                sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' | \
-                sort -u > ${KUSEDLST} || true
-             NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \
-                cut -d , -f 3`
-             if [[ $NUM -ne 0 ]]; then
-                echo "Unmigrated symbols found in $CFG"
-                exit 1
-             fi
-          done
-
   - job: cppcheck
     displayName: 'Static code analysis with cppcheck'
     pool:
@@ -202,8 +172,6 @@ stages:
           export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH
           test/nokia_rx51_test.sh
 
-- stage: test_py
-  jobs:
   - job: test_py
     displayName: 'test.py'
     pool:
@@ -223,10 +191,6 @@ stages:
           TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
         sandbox_flattree:
           TEST_PY_BD: "sandbox_flattree"
-        coreboot:
-          TEST_PY_BD: "coreboot"
-          TEST_PY_ID: "--id qemu"
-          TEST_PY_TEST_SPEC: "not sleep"
         evb_ast2500:
           TEST_PY_BD: "evb-ast2500"
           TEST_PY_ID: "--id qemu"
@@ -358,12 +322,6 @@ stages:
               genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
               cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
           fi
-          if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-              wget -O - "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-              wget -O - "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >cbfstool;
-              chmod a+x cbfstool;
-              ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-          fi
           virtualenv -p /usr/bin/python3 /tmp/venv
           . /tmp/venv/bin/activate
           pip install -r test/py/requirements.txt
@@ -396,8 +354,6 @@ stages:
           # Some tests using libguestfs-tools need the fuse device to run
           docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
 
-- stage: world_build
-  jobs:
   - job: build_the_world
     displayName: 'Build the World'
     pool:

.gitattributes

@@ -3,4 +3,3 @@
 # Denote all files that are truly binary and should not be modified
 *.bmp binary
 *.ttf binary
-*.gz binary

.gitignore

@@ -95,10 +95,3 @@ GTAGS
 
 # Python cache
 __pycache__
-
-# Python code coverage output (python3-coverage html)
-/htmlcov/
-
-# pylint files
-/pylint.cur
-/pylint.out/

.gitlab-ci.yml

@@ -2,7 +2,7 @@
 
 # Grab our configured image.  The source for this is found at:
 # https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022
+image: trini/u-boot-gitlab-ci-runner:focal-20211006-14Nov2021
 
 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -52,16 +52,6 @@ stages:
         genimage --inputpath . --config board/sifive/unleashed/genimage_spi-nor.cfg;
         cp images/spi-nor.img ${UBOOT_TRAVIS_BUILD_DIR}/;
       fi
-    - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        wget -O -
-          "https://drive.google.com/uc?id=1x6nrtWIyIRPLS2cQBwYTnT2TbOI8UjmM&export=download" |
-          xz -dc >${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom;
-        wget -O -
-          "https://drive.google.com/uc?id=149Cz-5SZXHNKpi9xg6R_5XITWohu348y&export=download" >
-          cbfstool;
-        chmod a+x cbfstool;
-        ./cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
-      fi
     - virtualenv -p /usr/bin/python3 /tmp/venv
     - . /tmp/venv/bin/activate
     - pip install -r test/py/requirements.txt
@@ -71,10 +61,6 @@ stages:
       ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
         ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
         --build-dir "$UBOOT_TRAVIS_BUILD_DIR"
-    # It seems that the files in /tmp go away, so copy out what we need
-    - if [[ "${TEST_PY_BD}" == "coreboot" ]]; then
-        cp -v /tmp/coreboot/*.{html,css} .;
-      fi
 
 build all 32bit ARM platforms:
   stage: world build
@@ -119,27 +105,6 @@ build all other platforms:
         exit $ret;
       fi;
 
-check for migrated symbols in board header:
-  stage: testsuites
-  script:
-    - KSYMLST=`mktemp`;
-      KUSEDLST=`mktemp`;
-      cat `find . -name "Kconfig*"` |
-         sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p'
-         | sort -u > $KSYMLST;
-      for CFG in `find include/configs -name "*.h"`; do
-         grep '#define[[:blank:]]CONFIG_' $CFG |
-            sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |
-            sort -u > ${KUSEDLST} || true;
-         NUM=`comm -12 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} |
-            cut -d , -f 3`;
-         if [[ $NUM -ne 0 ]]; then
-            echo "Unmigrated symbols found in $CFG";
-            exit 1;
-         fi;
-      done
-
 # QA jobs for code analytics
 # static code analysis with cppcheck (we can add --enable=all later)
 cppcheck:
@@ -401,15 +366,3 @@ xtfpga test.py:
     TEST_PY_TEST_SPEC: "not sleep"
     TEST_PY_ID: "--id qemu"
   <<: *buildman_and_testpy_dfn
-
-coreboot test.py:
-  variables:
-    TEST_PY_BD: "coreboot"
-    TEST_PY_TEST_SPEC: "not sleep"
-    TEST_PY_ID: "--id qemu"
-  artifacts:
-    paths:
-      - "*.html"
-      - "*.css"
-    expire_in: 1 week
-  <<: *buildman_and_testpy_dfn

.mailmap

@@ -20,15 +20,11 @@ Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
 Andreas Bießmann <andreas@biessmann.org>
 Aneesh V <aneesh@ti.com>
-Anup Patel <anup@brainfault.org> <anup.patel@wdc.com>
-Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
-Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
 Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
 Dirk Behme <dirk.behme@googlemail.com>
 Fabio Estevam <fabio.estevam@nxp.com>
 Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
-Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
 Jagan Teki <402jagan@gmail.com>
 Jagan Teki <jaganna@gmail.com>
 Jagan Teki <jaganna@xilinx.com>
@@ -37,15 +33,7 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
 Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
-Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com>
-Marek Vasut <marex@denx.de> <marek.vasut@gmail.com>
-Marek Vasut <marex@denx.de> <marex at denx.de>
 Markus Klotzbuecher <mk@denx.de>
-Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com>
-Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org>
-Michal Simek <michal.simek@xilinx.com> <monstr@monstr.eu>
-Michal Simek <michal.simek@xilinx.com> <Monstr@seznam.cz>
-Michal Simek <michal.simek@xilinx.com> <root@monstr.eu>
 Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
 Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
 Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
@@ -57,19 +45,10 @@ Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
 Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com>
 Sandeep Paulraj <s-paulraj@ti.com>
 Shaohui Xie <Shaohui.Xie@freescale.com>
-Stefan Roese <sr@denx.de> <stroese>
+Stefan Roese <stroese>
 Stefano Babic <sbabic@denx.de>
-Tom Rini <trini@konsulko.com> <trini@ti.com>
 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Wolfgang Denk <wd@denx.de> <wdenk>
-Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
-Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@castor.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
-Wolfgang Denk <wd@denx.de> <wd@nyx.(none)>
+Wolfgang Denk <wdenk>
 York Sun <yorksun@freescale.com>
 York Sun <york.sun@nxp.com>
 Łukasz Majewski <l.majewski@samsung.com>

.readthedocs.yml

@@ -5,13 +5,6 @@
 # Required
 version: 2
 
-build:
-  os: "ubuntu-20.04"
-  apt_packages:
-    - python3-six
-  tools:
-    python: "3.9"
-
 # Build documentation in the docs/ directory with Sphinx
 sphinx:
   configuration: doc/conf.py
@@ -19,6 +12,8 @@ sphinx:
 # Optionally build your docs in additional formats such as PDF and ePub
 formats: []
 
-python:
-  install:
-    - requirements: doc/sphinx/requirements.txt
+# Optionally set the version of Python and requirements required to build your docs
+# python:
+#   version: 3.7
+#   install:
+#     - requirements: docs/requirements.txt

Kconfig

@@ -246,10 +246,9 @@ config SYS_MALLOC_F_LEN
 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
 	default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
+	default 0x4020000 if ARCH_SUNXI && !MACH_SUN8I_V3S
 	default 0x200000 if ARCH_BMIPS || X86
-	default 0x120000 if MACH_SUNIV
-	default 0x220000 if MACH_SUN8I_V3S
-	default 0x4020000 if ARCH_SUNXI
+	default 0x220000 if ARCH_SUNXI && MACH_SUN8I_V3S
 	default 0x400000
 	help
 	  This defines memory to be allocated for Dynamic allocation
@@ -353,13 +352,6 @@ config SPL_IMAGE
 	  used to generate a combined image with SPL and main U-Boot
 	  proper as one single image.
 
-config REMAKE_ELF
-	bool "Recreate an ELF image from raw U-Boot binary"
-	help
-	  Enable this to recreate an ELF image (u-boot.elf) from the raw
-	  U-Boot binary (u-boot.bin), which may already have been statically
-	  relocated and may already have a device-tree appended to it.
-
 config BUILD_TARGET
 	string "Build target special images"
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
@@ -399,9 +391,8 @@ config SYS_LOAD_ADDR
 	hex "Address in memory to use by default"
 	default 0x01000000 if ARCH_SOCFPGA
 	default 0x02000000 if PPC || X86
-	default 0x81000000 if MACH_SUNIV
 	default 0x22000000 if MACH_SUN9I
-	default 0x42000000 if ARCH_SUNXI
+	default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
 	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
 	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
@@ -463,12 +454,6 @@ config SYS_SRAM_SIZE
 	default 0x10000 if TARGET_TRICORDER
 	default 0x0
 
-config MP
-	bool "Support for multiprocessor"
-	help
-	  This provides an option to bringup different processors
-	  in multiprocessor cases.
-
 config EXAMPLES
 	bool "Compile API examples"
 	depends on !SANDBOX

MAINTAINERS

@@ -50,12 +50,6 @@ so much easier [Ed]
 Maintainers List (try to look for most precise areas first)
 
 		-----------------------------------
-ACPI:
-M:	Simon Glass <sjg@chromium.org>
-S:	Maintained
-F:	cmd/acpi.c
-F:	lib/acpi/
-
 ANDROID AB
 M:	Igor Opaniuk <igor.opaniuk@gmail.com>
 R:	Sam Protsenko <joe.skb7@gmail.com>
@@ -121,8 +115,6 @@ F:	arch/arm/include/asm/arch-m1/
 F:	arch/arm/mach-apple/
 F:	configs/apple_m1_defconfig
 F:	drivers/iommu/apple_dart.c
-F:	drivers/pinctrl/pinctrl-apple.c
-F:	drivers/watchdog/apple_wdt.c
 F:	include/configs/apple.h
 
 ARM
@@ -278,35 +270,12 @@ T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
 F:	arch/arm/mach-kirkwood/
 F:	arch/arm/mach-mvebu/
 F:	drivers/ata/ahci_mvebu.c
-F:	drivers/clk/mvebu/
 F:	drivers/ddr/marvell/
 F:	drivers/gpio/mvebu_gpio.c
-F:	drivers/i2c/mvtwsi.c
-F:	drivers/mmc/xenon_sdhci.c
-F:	drivers/phy/marvell/
-F:	drivers/pinctrl/mvebu/
-F:	drivers/rtc/armada38x.c
 F:	drivers/spi/kirkwood_spi.c
-F:	drivers/spi/mvebu_a3700_spi.c
-F:	drivers/pci/pcie_dw_mvebu.c
-F:	drivers/watchdog/armada-37xx-wdt.c
-F:	drivers/watchdog/orion_wdt.c
-F:	include/configs/mv-common.h
-
-ARM MARVELL PCIE CONTROLLER DRIVERS
-M:	Pali Rohár <pali@kernel.org>
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
-F:	drivers/pci/pci-aardvark.c
 F:	drivers/pci/pci_mvebu.c
-
-ARM MARVELL SERIAL DRIVERS
-M:	Pali Rohár <pali@kernel.org>
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
-F:	drivers/serial/serial_mvebu_a3700.c
+F:	drivers/pci/pcie_dw_mvebu.c
+F:	drivers/watchdog/orion_wdt.c
 
 ARM MARVELL PXA
 M:	Marek Vasut <marex@denx.de>
@@ -397,9 +366,6 @@ M:	Philipp Tomsich <philipp.tomsich@vrull.eu>
 M:	Kever Yang <kever.yang@rock-chips.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
-F:	arch/arm/dts/rk3*
-F:	arch/arm/dts/rockchip*
-F:	arch/arm/dts/rv1108*
 F:	arch/arm/include/asm/arch-rockchip/
 F:	arch/arm/mach-rockchip/
 F:	board/rockchip/
@@ -417,7 +383,6 @@ F:	tools/rkcommon.h
 F:	tools/rkimage.c
 F:	tools/rksd.c
 F:	tools/rkspi.c
-N:	rockchip
 
 ARM SAMSUNG
 M:	Minkyu Kang <mk7.kang@samsung.com>
@@ -533,8 +498,6 @@ ARM TI
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-ti.git
-F:	arch/arm/dts/am57xx*
-F:	arch/arm/dts/dra7*
 F:	arch/arm/mach-davinci/
 F:	arch/arm/mach-k3/
 F:	arch/arm/mach-keystone/
@@ -554,11 +517,9 @@ F:	drivers/phy/omap-usb2-phy.c
 F:	drivers/phy/phy-ti-am654.c
 F:	drivers/phy/ti-pipe3-phy.c
 F:	drivers/ram/k3*
-F:	drivers/remoteproc/ipu_rproc.c
 F:	drivers/remoteproc/k3_system_controller.c
 F:	drivers/remoteproc/pruc_rpoc.c
 F:	drivers/remoteproc/ti*
-F:	drivers/reset/reset-dra7.c
 F:	drivers/reset/reset-ti-sci.c
 F:	drivers/rtc/davinci.c
 F:	drivers/serial/serial_omap.c
@@ -641,7 +602,6 @@ F:	drivers/clk/clk_zynqmp.c
 F:	driver/firmware/firmware-zynqmp.c
 F:	drivers/fpga/zynqpl.c
 F:	drivers/gpio/zynq_gpio.c
-F:	drivers/gpio/zynqmp_gpio_modepin.c
 F:	drivers/i2c/i2c-cdns.c
 F:	drivers/i2c/muxes/pca954x.c
 F:	drivers/i2c/zynq_i2c.c
@@ -650,8 +610,6 @@ F:	drivers/mmc/zynq_sdhci.c
 F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
 F:	drivers/net/zynq_gem.c
-F:	drivers/phy/phy-zynqmp.c
-F:	drivers/power/domain/zynqmp-power-domain.c
 F:	drivers/serial/serial_zynq.c
 F:	drivers/reset/reset-zynqmp.c
 F:	drivers/rtc/zynqmp_rtc.c
@@ -763,11 +721,11 @@ F:	test/dm/efi_media.c
 
 EFI PAYLOAD
 M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
+R:	Alexander Graf <agraf@csgraf.de>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-efi.git
 F:	doc/api/efi.rst
 F:	doc/develop/uefi/*
-F:	doc/mkeficapsule.1
 F:	doc/usage/bootefi.rst
 F:	drivers/rtc/emul_rtc.c
 F:	include/capitalization.h
@@ -806,13 +764,6 @@ F:	test/env/
 F:	tools/env*
 F:	tools/mkenvimage.c
 
-ENVIRONMENT AS TEXT
-M:	Simon Glass <sjg@chromium.org>
-R:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	doc/usage/environment.rst
-F:	scripts/env2string.awk
-
 FASTBOOT
 S:	Orphaned
 F:	cmd/fastboot.c
@@ -1119,14 +1070,14 @@ F:	drivers/timer/andes_plmt_timer.c
 F:	drivers/timer/sifive_clint_timer.c
 F:	tools/prelink-riscv.c
 
-RISC-V CANAAN KENDRYTE K210
+RISC-V KENDRYTE
 M:	Sean Anderson <seanga2@gmail.com>
 S:	Maintained
-F:	doc/device-tree-bindings/mfd/canaan,k210-sysctl.txt
-F:	doc/device-tree-bindings/pinctrl/canaan,k210-fpioa.txt
-F:	drivers/clk/clk_k210.c
-F:	drivers/pinctrl/pinctrl-k210.c
-F:	include/k210/
+F:	doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
+F:	doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
+F:	drivers/clk/clk_kendryte.c
+F:	drivers/pinctrl/pinctrl-kendryte.c
+F:	include/kendryte/
 
 RNG
 M:	Sughosh Ganu <sughosh.ganu@linaro.org>
@@ -1165,13 +1116,6 @@ S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-sh.git
 F:	arch/sh/
 
-SL28CLPD
-M:	Michael Walle <michael@walle.cc>
-S:	Maintained
-F:	drivers/gpio/sl28cpld-gpio.c
-F:	drivers/misc/sl28cpld.c
-F:	drivers/watchdog/sl28cpld-wdt.c
-
 SPI
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
@@ -1330,14 +1274,6 @@ F:	include/virtio*.h
 F:	test/dm/virtio.c
 F:	doc/develop/driver-model/virtio.rst
 
-WATCHDOG
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-watchdog.git
-F:	cmd/wdt.c
-F:	drivers/watchdog/
-F:	include/watchdog*.h
-
 X86
 M:	Simon Glass <sjg@chromium.org>
 M:	Bin Meng <bmeng.cn@gmail.com>
@@ -1347,7 +1283,7 @@ F:	arch/x86/
 F:	cmd/x86/
 
 XEN
-M:	Anastasiia Lukianenko <vicooodin@gmail.com>
+M:	Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
 M:	Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
 S:	Maintained
 F:	arch/arm/cpu/armv8/xen/

Makefile

@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 VERSION = 2022
-PATCHLEVEL = 04
+PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc3
 NAME =
 
 # *DOCUMENTATION*
@@ -517,11 +517,10 @@ version_h := include/generated/version_autogenerated.h
 timestamp_h := include/generated/timestamp_autogenerated.h
 defaultenv_h := include/generated/defaultenv_autogenerated.h
 dt_h := include/generated/dt.h
-env_h := include/generated/environment.h
 
 no-dot-config-targets := clean clobber mrproper distclean \
 			 help %docs check% coccicheck \
-			 ubootversion backup tests check qcheck tcheck pylint
+			 ubootversion backup tests check qcheck tcheck
 
 config-targets := 0
 mixed-targets  := 0
@@ -944,9 +943,8 @@ INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
 endif
 endif
 INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
-
-# Allow omitting the .dtb output if it is not normally used
-INPUTS-$(CONFIG_OF_SEPARATE) += $(if $(CONFIG_OF_OMIT_DTB),dts/dt.dtb,u-boot.dtb)
+INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
+INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb
 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
 INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
 endif
@@ -1055,10 +1053,6 @@ quiet_cmd_cfgcheck = CFGCHK  $2
 cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
 		$(srctree)/scripts/config_whitelist.txt $(srctree)
 
-quiet_cmd_ofcheck = OFCHK   $2
-cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \
-		$(srctree)/scripts/of_allowlist.txt
-
 # Concat the value of all the CONFIGs (result is 'y' or 'yy', etc. )
 got = $(foreach cfg,$(1),$($(cfg)))
 
@@ -1080,7 +1074,7 @@ define deprecated
 		echo >&2 "for $(2)). Please update the board to use"; \
 		echo >&2 "$(firstword $(1)) before the $(3) release. Failure to"; \
 		echo >&2 "update by the deadline may result in board removal."; \
-		echo >&2 "See doc/develop/driver-model/migration.rst for more info."; \
+		echo >&2 "See doc/driver-model/migration.rst for more info."; \
 		echo >&2 "===================================================="; \
 	fi; fi
 
@@ -1121,27 +1115,17 @@ ifneq ($(CONFIG_DM),y)
 	@echo >&2 "This board does not use CONFIG_DM. CONFIG_DM will be"
 	@echo >&2 "compulsory starting with the v2020.01 release."
 	@echo >&2 "Failure to update may result in board removal."
-	@echo >&2 "See doc/develop/driver-model/migration.rst for more info."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
 	@echo >&2 "===================================================="
 endif
 	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
 		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
 	$(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
 	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
-	$(call deprecated,CONFIG_DM_KEYBOARD,Keyboard drivers,v2022.10,$(CONFIG_KEYBOARD))
-	@# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which
-	@# confuses this rule. Use if() to send just a single character which
-	@# is enable to tell 'deprecated' that one of these symbols exists
-	$(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x))
-	$(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL))
-	$(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI))
 	@# Check that this build does not use CONFIG options that we do not
 	@# know about unless they are in Kconfig. All the existing CONFIG
 	@# options are whitelisted, so new ones should not be added.
 	$(call cmd,cfgcheck,u-boot.cfg)
-	@# Check that this build does not override OF_HAS_PRIOR_STAGE by
-	@# disabling OF_BOARD.
-	$(call cmd,ofcheck,$(KCONFIG_CONFIG))
 
 PHONY += dtbs
 dtbs: dts/dt.dtb
@@ -1195,7 +1179,7 @@ u-boot.bin: u-boot-fit-dtb.bin FORCE
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 	$(call if_changed,cat)
 
-else ifeq ($(CONFIG_OF_SEPARATE).$(CONFIG_OF_OMIT_DTB),y.)
+else ifeq ($(CONFIG_OF_SEPARATE),y)
 u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 	$(call if_changed,cat)
 
@@ -1318,16 +1302,12 @@ default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
 
 quiet_cmd_binman = BINMAN  $@
 cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
-		$(foreach f,$(BINMAN_TOOLPATHS),--toolpath $(f)) \
                 --toolpath $(objtree)/tools \
 		$(if $(BINMAN_VERBOSE),-v$(BINMAN_VERBOSE)) \
 		build -u -d u-boot.dtb -O . -m --allow-missing \
-		--fake-ext-blobs \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-		$(foreach f,$(BINMAN_INDIRS),-I $(f)) \
 		-a atf-bl31-path=${BL31} \
-		-a tee-os-path=${TEE} \
 		-a opensbi-path=${OPENSBI} \
 		-a default-dt=$(default_dt) \
 		-a scp-path=$(SCP) \
@@ -1411,7 +1391,7 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(KWD_CONFIG_FILE) \
 	$(if $(KEYDIR),-k $(KEYDIR))
 
 MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -A $(ARCH) -T pblimage
+		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
 
 ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
 UBOOT_BIN := u-boot-with-dtb.bin
@@ -1431,7 +1411,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE
 
 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
-			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \
+			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
 		,$(UBOOT_BIN)) FORCE
 	$(call if_changed,mkimage)
 	$(BOARD_SIZE_CHECK)
@@ -1537,6 +1517,7 @@ else
 ifeq ($(CONFIG_BINMAN),y)
 flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
 	$(call if_changed,binman)
+	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 else
 flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@@ -1783,9 +1764,9 @@ else
 quiet_cmd_u-boot__ ?= LD      $@
       cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@		\
 		-T u-boot.lds $(u-boot-init)					\
-		--whole-archive							\
+		$(if $(CONFIG_EFI_APP_64BIT),,--whole-archive)			\
 			$(u-boot-main)						\
-		--no-whole-archive						\
+		$(if $(CONFIG_EFI_APP_64BIT),,--no-whole-archive)		\
 		$(PLATFORM_LIBS) -Map u-boot.map;				\
 		$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
 endif
@@ -1813,72 +1794,6 @@ quiet_cmd_sym ?= SYM     $@
 u-boot.sym: u-boot FORCE
 	$(call if_changed,sym)
 
-# Environment processing
-# ---------------------------------------------------------------------------
-
-# Directory where we expect the .env file, if it exists
-ENV_DIR := $(srctree)/board/$(BOARDDIR)
-
-# Basename of .env file, stripping quotes
-ENV_SOURCE_FILE := $(CONFIG_ENV_SOURCE_FILE:"%"=%)
-
-# Filename of .env file
-ENV_FILE_CFG := $(ENV_DIR)/$(ENV_SOURCE_FILE).env
-
-# Default filename, if CONFIG_ENV_SOURCE_FILE is empty
-ENV_FILE_BOARD := $(ENV_DIR)/$(CONFIG_SYS_BOARD:"%"=%).env
-
-# Select between the CONFIG_ENV_SOURCE_FILE and the default one
-ENV_FILE := $(if $(ENV_SOURCE_FILE),$(ENV_FILE_CFG),$(wildcard $(ENV_FILE_BOARD)))
-
-# Run the environment text file through the preprocessor, but only if it is
-# non-empty, to save time and possible build errors if something is wonky with
-# the board.
-# If there is no ENV_FILE, produce an empty output file, to prevent a previous
-# build's file being used in the case of in-tree builds.
-quiet_cmd_gen_envp = ENVP    $@
-      cmd_gen_envp = \
-	if [ -s "$(ENV_FILE)" ]; then \
-		$(CPP) -P $(CFLAGS) -x assembler-with-cpp -D__ASSEMBLY__ \
-			-D__UBOOT_CONFIG__ \
-			-I . -I include -I $(srctree)/include \
-			-include linux/kconfig.h -include include/config.h \
-			-I$(srctree)/arch/$(ARCH)/include \
-			$< -o $@; \
-	else \
-		rm -f $@; \
-		touch $@ ; \
-	fi
-include/generated/env.in: include/generated/env.txt FORCE
-	$(call cmd,gen_envp)
-
-# Regenerate the environment if it changes
-# We use 'wildcard' since the file is not required to exist (at present), in
-# which case we don't want this dependency, but instead should create an empty
-# file
-# This rule is useful since it shows the source file for the environment
-quiet_cmd_envc = ENVC    $@
-      cmd_envc = \
-	if [ -f "$<" ]; then \
-		cat $< > $@; \
-	elif [ -n "$(ENV_SOURCE_FILE)" ]; then \
-		echo "Missing file $(ENV_FILE_CFG)"; \
-	else \
-		touch $@ ; \
-	fi
-
-include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE
-	$(call cmd,envc)
-
-# Write out the resulting environment, converted to a C string
-quiet_cmd_gen_envt = ENVT    $@
-      cmd_gen_envt = \
-	awk -f $(srctree)/scripts/env2string.awk $< >$@
-$(env_h): include/generated/env.in
-	$(call cmd,gen_envt)
-
-# ---------------------------------------------------------------------------
-
 # The actual objects are generated when descending,
 # make sure no implicit rule kicks in
 $(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
@@ -1934,7 +1849,7 @@ endif
 # prepare2 creates a makefile if using a separate output directory
 prepare2: prepare3 outputmakefile cfg
 
-prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) $(env_h) \
+prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) \
                    include/config/auto.conf
 ifeq ($(wildcard $(LDSCRIPT)),)
 	@echo >&2 "  Could not find linker script."
@@ -2189,14 +2104,11 @@ CLEAN_DIRS  += $(MODVERDIR) \
 	       $(foreach d, spl tpl, $(patsubst %,$d/%, \
 			$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
 
-CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
-	       include/generated/env.in drivers/video/u_boot_logo.S \
-	       tools/version.h u-boot* MLO* SPL System.map fit-dtb.blob* \
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
+	       u-boot* MLO* SPL System.map fit-dtb.blob* \
 	       u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
-	       idbloader.img flash.bin flash.log defconfig keep-syms-lto.c \
-	       mkimage-out.spl.mkimage mkimage.spl.mkimage imx-boot.map \
-	       itb.fit.fit itb.fit.itb itb.map spl.map
+	       idbloader.img flash.bin flash.log defconfig keep-syms-lto.c
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl \
@@ -2231,8 +2143,7 @@ clean: $(clean-dirs)
 		-o -name '*.asn1.[ch]' \
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name modules.builtin -o -name '.tmp_*.o.*' \
-		-o -name 'dsdt_generated.aml' -o -name 'dsdt_generated.asl.tmp' \
-		-o -name 'dsdt_generated.c' \
+		-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
 		-o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \
 		-type f -print | xargs rm -f
 
@@ -2264,49 +2175,6 @@ distclean: mrproper
 		-type f -print | xargs rm -f
 	@rm -f boards.cfg CHANGELOG
 
-# See doc/develop/python_cq.rst
-PHONY += pylint
-PYLINT_BASE := scripts/pylint.base
-PYLINT_CUR := pylint.cur
-PYLINT_DIFF := pylint.diff
-pylint:
-	$(Q)echo "Running pylint on all files (summary in $(PYLINT_CUR); output in pylint.out/)"
-	$(Q)mkdir -p pylint.out
-	$(Q)rm -f pylint.out/out*
-	$(Q)find tools test -name "*.py" \
-		| xargs -n1 -P$(shell nproc 2>/dev/null || echo 1) \
-			sh -c 'pylint --reports=y --exit-zero -f parseable --ignore-imports=yes $$@ > pylint.out/$$(echo $$@ | tr / _ | sed s/.py//)' _
-	$(Q)rm -f $(PYLINT_CUR)
-	$(Q)( cd pylint.out; for f in *; do \
-		sed -ne "s/Your code has been rated at \([-0-9.]*\).*/$$f \1/p" $$f; \
-	done ) | sort > $(PYLINT_CUR)
-	$(Q)base=$$(mktemp) cur=$$(mktemp); cut -d' ' -f1 $(PYLINT_BASE) >$$base; \
-		cut -d' ' -f1 $(PYLINT_CUR) >$$cur; \
-		comm -3 $$base $$cur > $(PYLINT_DIFF); \
-		if [ -s $(PYLINT_DIFF) ]; then \
-			echo "Files have been added/removed. Try:\n\tcp $(PYLINT_CUR) $(PYLINT_BASE)"; \
-			echo; \
-			echo "Added files:"; \
-			comm -13 $$base $$cur; \
-			echo; \
-			echo "Removed files:"; \
-			comm -23 $$base $$cur; \
-			false; \
-		else \
-			rm $$base $$cur $(PYLINT_DIFF); \
-		fi
-	$(Q)bad=false; while read base_file base_val <&3 && read cur_file cur_val <&4; do \
-		if awk "BEGIN {exit !($$cur_val < $$base_val)}"; then \
-			echo "$$base_file: Score was $$base_val, now $$cur_val"; \
-			bad=true; fi; \
-		done 3<$(PYLINT_BASE) 4<$(PYLINT_CUR); \
-		if $$bad; then \
-			echo "Some files have regressed, please fix"; \
-			false; \
-		else \
-			echo "No pylint regressions"; \
-		fi
-
 backup:
 	F=`basename $(srctree)` ; cd .. ; \
 	gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
@@ -2325,7 +2193,6 @@ help:
 	@echo  '  check           - Run all automated tests that use sandbox'
 	@echo  '  qcheck          - Run quick automated tests that use sandbox'
 	@echo  '  tcheck          - Run quick automated tests on tools'
-	@echo  '  pylint          - Run pylint on all Python files'
 	@echo  ''
 	@echo  'Other generic targets:'
 	@echo  '  all		  - Build all necessary images depending on configuration'

README

@@ -565,6 +565,11 @@ The following options need to be configured:
 		boards with QUICC Engines require OF_QE to set UCC MAC
 		addresses
 
+		CONFIG_OF_BOARD_SETUP
+
+		Board code has addition modification that it wants to make
+		to the flat device tree before handing it off to the kernel
+
 		CONFIG_OF_SYSTEM_SETUP
 
 		Other code has addition modification that it wants to make
@@ -591,6 +596,9 @@ The following options need to be configured:
 		Note: If a "bootargs" environment is defined, it will override
 		the defaults discussed just above.
 
+- Cache Configuration:
+		CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
+
 - Cache Configuration for ARM:
 		CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
 				      controller
@@ -614,6 +622,19 @@ The following options need to be configured:
 		Define this variable to enable hw flow control in serial driver.
 		Current user of this option is drivers/serial/nsl16550.c driver
 
+- Autoboot Command:
+		CONFIG_BOOTCOMMAND
+		Only needed when CONFIG_BOOTDELAY is enabled;
+		define a command string that is automatically executed
+		when no character is read on the console interface
+		within "Boot Delay" after reset.
+
+		CONFIG_RAMBOOT and CONFIG_NFSBOOT
+		The value of these goes into the environment as
+		"ramboot" and "nfsboot" respectively, and can be used
+		as a convenience, when switching between booting from
+		RAM and NFS.
+
 - Serial Download Echo Mode:
 		CONFIG_LOADS_ECHO
 		If defined to 1, all characters received during a
@@ -638,7 +659,50 @@ The following options need to be configured:
 		which adds regex support to some commands, as for
 		example "env grep" and "setexpr".
 
+- Device tree:
+		CONFIG_OF_CONTROL
+		If this variable is defined, U-Boot will use a device tree
+		to configure its devices, instead of relying on statically
+		compiled #defines in the board file. This option is
+		experimental and only available on a few boards. The device
+		tree is available in the global data as gd->fdt_blob.
+
+		U-Boot needs to get its device tree from somewhere. This can
+		be done using one of the three options below:
+
+		CONFIG_OF_SEPARATE
+		If this variable is defined, U-Boot will build a device tree
+		binary. It will be called u-boot.dtb. Architecture-specific
+		code will locate it at run-time. Generally this works by:
+
+			cat u-boot.bin u-boot.dtb >image.bin
+
+		and in fact, U-Boot does this for you, creating a file called
+		u-boot-dtb.bin which is useful in the common case. You can
+		still use the individual files if you need something more
+		exotic.
+
+		CONFIG_OF_BOARD
+		If this variable is defined, U-Boot will use the device tree
+		provided by the board at runtime instead of embedding one with
+		the image. Only boards defining board_fdt_blob_setup() support
+		this option (see include/fdtdec.h file).
+
 - Watchdog:
+		CONFIG_WATCHDOG
+		If this variable is defined, it enables watchdog
+		support for the SoC. There must be support in the SoC
+		specific code for a watchdog. For the 8xx
+		CPUs, the SIU Watchdog feature is enabled in the SYPCR
+		register.  When supported for a specific SoC is
+		available, then no further board specific code should
+		be needed to use it.
+
+		CONFIG_HW_WATCHDOG
+		When using a watchdog circuitry external to the used
+		SoC, then define this variable and provide board
+		specific code for the "hw_watchdog_reset" function.
+
 		CONFIG_SYS_WATCHDOG_FREQ
 		Some platforms automatically call WATCHDOG_RESET()
 		from the timer interrupt handler every
@@ -720,6 +784,20 @@ The following options need to be configured:
 		CONFIG_SCSI) you must configure support for at
 		least one non-MTD partition type as well.
 
+- IDE Reset method:
+		CONFIG_IDE_RESET_ROUTINE - this is defined in several
+		board configurations files but used nowhere!
+
+		CONFIG_IDE_RESET - is this is defined, IDE Reset will
+		be performed by calling the function
+			ide_set_reset(int reset)
+		which has to be defined in a board specific file
+
+- ATAPI Support:
+		CONFIG_ATAPI
+
+		Set this to enable ATAPI support.
+
 - LBA48 Support
 		CONFIG_LBA48
 
@@ -732,6 +810,16 @@ The following options need to be configured:
 			When enabled, makes the IDE subsystem use 64bit sector addresses.
 			Default is 32bit.
 
+- SCSI Support:
+		CONFIG_SYS_SCSI_MAX_LUN [8], CONFIG_SYS_SCSI_MAX_SCSI_ID [7] and
+		CONFIG_SYS_SCSI_MAX_DEVICE [CONFIG_SYS_SCSI_MAX_SCSI_ID *
+		CONFIG_SYS_SCSI_MAX_LUN] can be adjusted to define the
+		maximum numbers of LUNs, SCSI ID's and target
+		devices.
+
+		The environment variable 'scsidevs' is set to the number of
+		SCSI devices found during the last scan.
+
 - NETWORK Support (PCI):
 		CONFIG_E1000_SPI
 		Utility code for direct access to the SPI bus on Intel 8257x.
@@ -978,6 +1066,9 @@ The following options need to be configured:
 		sending again an USB request to the device.
 
 - Journaling Flash filesystem support:
+		CONFIG_JFFS2_NAND
+		Define these for a default partition on a NAND device
+
 		CONFIG_SYS_JFFS2_FIRST_SECTOR,
 		CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS
 		Define these for a default partition on a NOR device
@@ -985,6 +1076,14 @@ The following options need to be configured:
 - Keyboard Support:
 		See Kconfig help for available keyboard drivers.
 
+		CONFIG_KEYBOARD
+
+		Define this to enable a custom keyboard support.
+		This simply calls drv_keyboard_init() which must be
+		defined in your board-specific files. This option is deprecated
+		and is only used by novena. For new boards, use driver model
+		instead.
+
 - Video support:
 		CONFIG_FSL_DIU_FB
 		Enable the Freescale DIU video driver.	Reference boards for
@@ -996,6 +1095,7 @@ The following options need to be configured:
 			CONFIG_CFB_CONSOLE
 			CONFIG_VIDEO_SW_CURSOR
 			CONFIG_VGA_AS_SINGLE_DEVICE
+			CONFIG_VIDEO_LOGO
 			CONFIG_VIDEO_BMP_LOGO
 
 		The DIU driver will look for the 'video-mode' environment
@@ -1117,6 +1217,11 @@ The following options need to be configured:
 		server to contact when using the "tftboot" command.
 		(Environment variable "serverip")
 
+		CONFIG_KEEP_SERVERADDR
+
+		Keeps the server's MAC address, in the env 'serveraddr'
+		for passing to bootargs (like Linux's netconsole option)
+
 - Gateway IP address:
 		CONFIG_GATEWAYIP
 
@@ -1182,6 +1287,9 @@ The following options need to be configured:
 		CONFIG_BOOTP_VENDOREX
 		CONFIG_BOOTP_MAY_FAIL
 
+		CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
+		environment variable, not the BOOTP server.
+
 		CONFIG_BOOTP_MAY_FAIL - If the DHCP server is not found
 		after the configured retry count, the call will fail
 		instead of starting over.  This can be used to fail over
@@ -1465,6 +1573,16 @@ The following options need to be configured:
 		SPI EEPROM, also an instance works with Crystal A/D and
 		D/As on the SACSng board)
 
+		CONFIG_SOFT_SPI
+
+		Enables a software (bit-bang) SPI driver rather than
+		using hardware support. This is a general purpose
+		driver that only requires three general I/O port pins
+		(two outputs, one input) to function. If this is
+		defined, the board configuration must define several
+		SPI configuration items (port pins to use, etc). For
+		an example, see include/configs/sacsng.h.
+
 		CONFIG_SYS_SPI_MXC_WAIT
 		Timeout for waiting until spi transfer completed.
 		default: (CONFIG_SYS_HZ/100)     /* 10 ms */
@@ -1530,6 +1648,13 @@ The following options need to be configured:
 		Time to wait after FPGA configuration. The default is
 		200 ms.
 
+- Configuration Management:
+
+		CONFIG_IDENT_STRING
+
+		If defined, this string will be added to the U-Boot
+		version information (U_BOOT_VERSION)
+
 - Vendor Parameter Protection:
 
 		U-Boot considers the values of the environment
@@ -1591,6 +1716,14 @@ The following options need to be configured:
 			HERMES, IP860, RPXlite, LWMON,
 			FLAGADM
 
+- Access to physical memory region (> 4GB)
+		Some basic support is provided for operations on memory not
+		normally accessible to U-Boot - e.g. some architectures
+		support access to more than 4GB of memory on 32-bit
+		machines using physical address extension or similar.
+		Define CONFIG_PHYSMEM to access this basic support, which
+		currently only supports clearing the memory.
+
 - Error Recovery:
 		CONFIG_NET_RETRY_COUNT
 
@@ -1850,6 +1983,14 @@ The following options need to be configured:
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 
+		CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+		Partition on the MMC to load U-Boot from when the MMC is being
+		used in raw mode
+
+		CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
+		Sector to load kernel uImage from when MMC is being
+		used in raw mode (for Falcon mode)
+
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
 		CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 		Sector and number of sectors to load kernel argument
@@ -2124,6 +2265,9 @@ Configuration Settings:
 		Enables allocating and saving a kernel copy of the bd_info in
 		space between "bootm_low" and "bootm_low" + BOOTMAPSZ.
 
+- CONFIG_SYS_MAX_FLASH_BANKS:
+		Max number of Flash memory banks
+
 - CONFIG_SYS_MAX_FLASH_SECT:
 		Max number of sectors on a Flash chip
 
@@ -2372,6 +2516,14 @@ Low Level (hardware related) configuration options:
 		If this macro is defined, then CONFIG_SYS_CCSRBAR_PHYS will be
 		forced to a value that ensures that CCSR is not relocated.
 
+- CONFIG_IDE_AHB:
+		Most IDE controllers were designed to be connected with PCI
+		interface. Only few of them were designed for AHB interface.
+		When software is doing ATA command and data transfer to
+		IDE devices through IDE-AHB controller, some additional
+		registers accessing to these kind of IDE-AHB controller
+		is required.
+
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
 		doing! (11-4) [MPC8xx systems only]
@@ -2415,6 +2567,17 @@ Low Level (hardware related) configuration options:
 - CONFIG_SYS_MAMR_PTA:
 		periodic timer for refresh
 
+- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
+  CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
+  CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
+  CONFIG_SYS_BR1_PRELIM:
+		Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
+
+- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
+  CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
+  CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
+		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
+
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not
 
@@ -2803,6 +2966,334 @@ TODO.
 For now: just type "help <command>".
 
 
+Environment Variables:
+======================
+
+U-Boot supports user configuration using Environment Variables which
+can be made persistent by saving to Flash memory.
+
+Environment Variables are set using "setenv", printed using
+"printenv", and saved to Flash using "saveenv". Using "setenv"
+without a value can be used to delete a variable from the
+environment. As long as you don't save the environment you are
+working with an in-memory copy. In case the Flash area containing the
+environment is erased by accident, a default environment is provided.
+
+Some configuration options can be set using Environment Variables.
+
+List of environment variables (most likely not complete):
+
+  baudrate	- see CONFIG_BAUDRATE
+
+  bootdelay	- see CONFIG_BOOTDELAY
+
+  bootcmd	- see CONFIG_BOOTCOMMAND
+
+  bootargs	- Boot arguments when booting an RTOS image
+
+  bootfile	- Name of the image to load with TFTP
+
+  bootm_low	- Memory range available for image processing in the bootm
+		  command can be restricted. This variable is given as
+		  a hexadecimal number and defines lowest address allowed
+		  for use by the bootm command. See also "bootm_size"
+		  environment variable. Address defined by "bootm_low" is
+		  also the base of the initial memory mapping for the Linux
+		  kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and
+		  bootm_mapsize.
+
+  bootm_mapsize - Size of the initial memory mapping for the Linux kernel.
+		  This variable is given as a hexadecimal number and it
+		  defines the size of the memory region starting at base
+		  address bootm_low that is accessible by the Linux kernel
+		  during early boot.  If unset, CONFIG_SYS_BOOTMAPSZ is used
+		  as the default value if it is defined, and bootm_size is
+		  used otherwise.
+
+  bootm_size	- Memory range available for image processing in the bootm
+		  command can be restricted. This variable is given as
+		  a hexadecimal number and defines the size of the region
+		  allowed for use by the bootm command. See also "bootm_low"
+		  environment variable.
+
+  bootstopkeysha256, bootdelaykey, bootstopkey	- See README.autoboot
+
+  updatefile	- Location of the software update file on a TFTP server, used
+		  by the automatic software update feature. Please refer to
+		  documentation in doc/README.update for more details.
+
+  autoload	- if set to "no" (any string beginning with 'n'),
+		  "bootp" will just load perform a lookup of the
+		  configuration from the BOOTP server, but not try to
+		  load any image using TFTP
+
+  autostart	- if set to "yes", an image loaded using the "bootp",
+		  "rarpboot", "tftpboot" or "diskboot" commands will
+		  be automatically started (by internally calling
+		  "bootm")
+
+		  If set to "no", a standalone image passed to the
+		  "bootm" command will be copied to the load address
+		  (and eventually uncompressed), but NOT be started.
+		  This can be used to load and uncompress arbitrary
+		  data.
+
+  fdt_high	- if set this restricts the maximum address that the
+		  flattened device tree will be copied into upon boot.
+		  For example, if you have a system with 1 GB memory
+		  at physical address 0x10000000, while Linux kernel
+		  only recognizes the first 704 MB as low memory, you
+		  may need to set fdt_high as 0x3C000000 to have the
+		  device tree blob be copied to the maximum address
+		  of the 704 MB low memory, so that Linux kernel can
+		  access it during the boot procedure.
+
+		  If this is set to the special value 0xFFFFFFFF then
+		  the fdt will not be copied at all on boot.  For this
+		  to work it must reside in writable memory, have
+		  sufficient padding on the end of it for u-boot to
+		  add the information it needs into it, and the memory
+		  must be accessible by the kernel.
+
+  fdtcontroladdr- if set this is the address of the control flattened
+		  device tree used by U-Boot when CONFIG_OF_CONTROL is
+		  defined.
+
+  i2cfast	- (PPC405GP|PPC405EP only)
+		  if set to 'y' configures Linux I2C driver for fast
+		  mode (400kHZ). This environment variable is used in
+		  initialization code. So, for changes to be effective
+		  it must be saved and board must be reset.
+
+  initrd_high	- restrict positioning of initrd images:
+		  If this variable is not set, initrd images will be
+		  copied to the highest possible address in RAM; this
+		  is usually what you want since it allows for
+		  maximum initrd size. If for some reason you want to
+		  make sure that the initrd image is loaded below the
+		  CONFIG_SYS_BOOTMAPSZ limit, you can set this environment
+		  variable to a value of "no" or "off" or "0".
+		  Alternatively, you can set it to a maximum upper
+		  address to use (U-Boot will still check that it
+		  does not overwrite the U-Boot stack and data).
+
+		  For instance, when you have a system with 16 MB
+		  RAM, and want to reserve 4 MB from use by Linux,
+		  you can do this by adding "mem=12M" to the value of
+		  the "bootargs" variable. However, now you must make
+		  sure that the initrd image is placed in the first
+		  12 MB as well - this can be done with
+
+		  setenv initrd_high 00c00000
+
+		  If you set initrd_high to 0xFFFFFFFF, this is an
+		  indication to U-Boot that all addresses are legal
+		  for the Linux kernel, including addresses in flash
+		  memory. In this case U-Boot will NOT COPY the
+		  ramdisk at all. This may be useful to reduce the
+		  boot time on your system, but requires that this
+		  feature is supported by your Linux kernel.
+
+  ipaddr	- IP address; needed for tftpboot command
+
+  loadaddr	- Default load address for commands like "bootp",
+		  "rarpboot", "tftpboot", "loadb" or "diskboot"
+
+  loads_echo	- see CONFIG_LOADS_ECHO
+
+  serverip	- TFTP server IP address; needed for tftpboot command
+
+  bootretry	- see CONFIG_BOOT_RETRY_TIME
+
+  bootdelaykey	- see CONFIG_AUTOBOOT_DELAY_STR
+
+  bootstopkey	- see CONFIG_AUTOBOOT_STOP_STR
+
+  ethprime	- controls which interface is used first.
+
+  ethact	- controls which interface is currently active.
+		  For example you can do the following
+
+		  => setenv ethact FEC
+		  => ping 192.168.0.1 # traffic sent on FEC
+		  => setenv ethact SCC
+		  => ping 10.0.0.1 # traffic sent on SCC
+
+  ethrotate	- When set to "no" U-Boot does not go through all
+		  available network interfaces.
+		  It just stays at the currently selected interface.
+
+  netretry	- When set to "no" each network operation will
+		  either succeed or fail without retrying.
+		  When set to "once" the network operation will
+		  fail when all the available network interfaces
+		  are tried once without success.
+		  Useful on scripts which control the retry operation
+		  themselves.
+
+  npe_ucode	- set load address for the NPE microcode
+
+  silent_linux  - If set then Linux will be told to boot silently, by
+		  changing the console to be empty. If "yes" it will be
+		  made silent. If "no" it will not be made silent. If
+		  unset, then it will be made silent if the U-Boot console
+		  is silent.
+
+  tftpsrcp	- If this is set, the value is used for TFTP's
+		  UDP source port.
+
+  tftpdstp	- If this is set, the value is used for TFTP's UDP
+		  destination port instead of the Well Know Port 69.
+
+  tftpblocksize - Block size to use for TFTP transfers; if not set,
+		  we use the TFTP server's default block size
+
+  tftptimeout	- Retransmission timeout for TFTP packets (in milli-
+		  seconds, minimum value is 1000 = 1 second). Defines
+		  when a packet is considered to be lost so it has to
+		  be retransmitted. The default is 5000 = 5 seconds.
+		  Lowering this value may make downloads succeed
+		  faster in networks with high packet loss rates or
+		  with unreliable TFTP servers.
+
+  tftptimeoutcountmax	- maximum count of TFTP timeouts (no
+		  unit, minimum value = 0). Defines how many timeouts
+		  can happen during a single file transfer before that
+		  transfer is aborted. The default is 10, and 0 means
+		  'no timeouts allowed'. Increasing this value may help
+		  downloads succeed with high packet loss rates, or with
+		  unreliable TFTP servers or client hardware.
+
+  tftpwindowsize	- if this is set, the value is used for TFTP's
+		  window size as described by RFC 7440.
+		  This means the count of blocks we can receive before
+		  sending ack to server.
+
+  vlan		- When set to a value < 4095 the traffic over
+		  Ethernet is encapsulated/received over 802.1q
+		  VLAN tagged frames.
+
+  bootpretryperiod	- Period during which BOOTP/DHCP sends retries.
+		  Unsigned value, in milliseconds. If not set, the period will
+		  be either the default (28000), or a value based on
+		  CONFIG_NET_RETRY_COUNT, if defined. This value has
+		  precedence over the valu based on CONFIG_NET_RETRY_COUNT.
+
+  memmatches	- Number of matches found by the last 'ms' command, in hex
+
+  memaddr	- Address of the last match found by the 'ms' command, in hex,
+		  or 0 if none
+
+  mempos	- Index position of the last match found by the 'ms' command,
+		  in units of the size (.b, .w, .l) of the search
+
+  zbootbase	- (x86 only) Base address of the bzImage 'setup' block
+
+  zbootaddr	- (x86 only) Address of the loaded bzImage, typically
+		  BZIMAGE_LOAD_ADDR which is 0x100000
+
+The following image location variables contain the location of images
+used in booting. The "Image" column gives the role of the image and is
+not an environment variable name. The other columns are environment
+variable names. "File Name" gives the name of the file on a TFTP
+server, "RAM Address" gives the location in RAM the image will be
+loaded to, and "Flash Location" gives the image's address in NOR
+flash or offset in NAND flash.
+
+*Note* - these variables don't have to be defined for all boards, some
+boards currently use other variables for these purposes, and some
+boards use these variables for other purposes.
+
+Image		    File Name	     RAM Address       Flash Location
+-----		    ---------	     -----------       --------------
+u-boot		    u-boot	     u-boot_addr_r     u-boot_addr
+Linux kernel	    bootfile	     kernel_addr_r     kernel_addr
+device tree blob    fdtfile	     fdt_addr_r	       fdt_addr
+ramdisk		    ramdiskfile	     ramdisk_addr_r    ramdisk_addr
+
+The following environment variables may be used and automatically
+updated by the network boot commands ("bootp" and "rarpboot"),
+depending the information provided by your boot server:
+
+  bootfile	- see above
+  dnsip		- IP address of your Domain Name Server
+  dnsip2	- IP address of your secondary Domain Name Server
+  gatewayip	- IP address of the Gateway (Router) to use
+  hostname	- Target hostname
+  ipaddr	- see above
+  netmask	- Subnet Mask
+  rootpath	- Pathname of the root filesystem on the NFS server
+  serverip	- see above
+
+
+There are two special Environment Variables:
+
+  serial#	- contains hardware identification information such
+		  as type string and/or serial number
+  ethaddr	- Ethernet address
+
+These variables can be set only once (usually during manufacturing of
+the board). U-Boot refuses to delete or overwrite these variables
+once they have been set once.
+
+
+Further special Environment Variables:
+
+  ver		- Contains the U-Boot version string as printed
+		  with the "version" command. This variable is
+		  readonly (see CONFIG_VERSION_VARIABLE).
+
+
+Please note that changes to some configuration parameters may take
+only effect after the next boot (yes, that's just like Windoze :-).
+
+
+Callback functions for environment variables:
+---------------------------------------------
+
+For some environment variables, the behavior of u-boot needs to change
+when their values are changed.  This functionality allows functions to
+be associated with arbitrary variables.  On creation, overwrite, or
+deletion, the callback will provide the opportunity for some side
+effect to happen or for the change to be rejected.
+
+The callbacks are named and associated with a function using the
+U_BOOT_ENV_CALLBACK macro in your board or driver code.
+
+These callbacks are associated with variables in one of two ways.  The
+static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+in the board configuration to a string that defines a list of
+associations.  The list must be in the following format:
+
+	entry = variable_name[:callback_name]
+	list = entry[,list]
+
+If the callback name is not specified, then the callback is deleted.
+Spaces are also allowed anywhere in the list.
+
+Callbacks can also be associated by defining the ".callbacks" variable
+with the same list format above.  Any association in ".callbacks" will
+override any association in the static list. You can define
+CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
+".callbacks" environment variable in the default or embedded environment.
+
+If CONFIG_REGEX is defined, the variable_name above is evaluated as a
+regular expression. This allows multiple variables to be connected to
+the same callback without explicitly listing them all out.
+
+The signature of the callback functions is:
+
+    int callback(const char *name, const char *value, enum env_op op, int flags)
+
+* name - changed environment variable
+* value - new value of the environment variable
+* op - operation (create, overwrite, or delete)
+* flags - attributes of the environment variable change, see flags H_* in
+  include/search.h
+
+The return value is 0 if the variable change is accepted and 1 otherwise.
+
+
 Note for Redundant Ethernet Interfaces:
 =======================================
 
@@ -2868,7 +3359,8 @@ details; basically, the header defines the following image properties:
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
-  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, INTEGRITY).
+  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
+  INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).

api/api_storage.c

@@ -9,7 +9,6 @@
 #include <common.h>
 #include <api_public.h>
 #include <part.h>
-#include <scsi.h>
 
 #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE)
 #include <usb.h>
@@ -72,7 +71,7 @@ void dev_stor_init(void)
 	specs[ENUM_SATA].name = "sata";
 #endif
 #if defined(CONFIG_SCSI)
-	specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE;
+	specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
 	specs[ENUM_SCSI].enum_started = 0;
 	specs[ENUM_SCSI].enum_ended = 0;
 	specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;

arch/Kconfig

@@ -1,7 +1,3 @@
-config ARCH_MAP_SYSMEM
-	depends on SANDBOX || NDS32
-	def_bool y
-
 config CREATE_ARCH_SYMLINK
 	bool
 
@@ -62,7 +58,6 @@ config ARM
 	select ARCH_SUPPORTS_LTO
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
-	select SUPPORT_ACPI
 	select SUPPORT_OF_CONTROL
 
 config M68K
@@ -153,7 +148,6 @@ config SANDBOX
 	select SYS_CACHE_SHIFT_4
 	select IRQ
 	select SUPPORT_EXTENSION_SCAN
-	select SUPPORT_ACPI
 	imply BITREVERSE
 	select BLOBLIST
 	imply LTO
@@ -172,11 +166,11 @@ config SANDBOX
 	imply FIRMWARE
 	imply HASH_VERIFY
 	imply LZMA
+	imply SCSI
 	imply TEE
 	imply AVB_VERIFY
 	imply LIBAVB
 	imply CMD_AVB
-	imply PARTITION_TYPE_GUID
 	imply SCP03
 	imply CMD_SCP03
 	imply UDP_FUNCTION_FASTBOOT
@@ -200,9 +194,6 @@ config SANDBOX
 	imply PHY_FIXED
 	imply DM_DSA
 	imply CMD_EXTENSION
-	imply KEYBOARD
-	imply PHYSMEM
-	imply GENERATE_ACPI_TABLE
 
 config SH
 	bool "SuperH architecture"
@@ -219,7 +210,6 @@ config X86
 	select HAVE_PRIVATE_LIBGCC
 	select OF_CONTROL
 	select PCI
-	select SUPPORT_ACPI
 	select SUPPORT_OF_CONTROL
 	select SYS_CACHE_SHIFT_6
 	select TIMER
@@ -255,12 +245,10 @@ config X86
 	imply USB_ETHER_SMSC95XX
 	imply USB_HOST_ETHER
 	imply PCH
-	imply PHYSMEM
 	imply RTC_MC146818
-	imply ACPIGEN if !QEMU && !EFI_APP
+	imply ACPIGEN if !QEMU
 	imply SYSINFO if GENERATE_SMBIOS_TABLE
 	imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
-	imply TIMESTAMP
 
 	# Thing to enable for when SPL/TPL are enabled: SPL
 	imply SPL_DM
@@ -362,18 +350,6 @@ config SYS_DISABLE_DCACHE_OPS
 	 Note that, its up to the individual architectures to implement
 	 this functionality.
 
-config SYS_IMMR
-	hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
-	depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
-	default 0xFF000000 if MPC8xx
-	default 0xF0000000 if ARCH_MPC8313
-	default 0xE0000000 if MPC83xx && !ARCH_MPC8313
-	default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
-	default SYS_CCSRBAR_DEFAULT
-	help
-	  Address for the Internal Memory-Mapped Registers (IMMR) window used
-	  to configure the features of many Freescale / NXP SoCs.
-
 config SKIP_LOWLEVEL_INIT
 	bool "Skip the calls to certain low level initialization functions"
 	depends on ARM || NDS32 || MIPS || RISCV

arch/arc/dts/Makefile

@@ -8,8 +8,6 @@ dtb-$(CONFIG_TARGET_EMSDP) +=  emsdp.dtb
 dtb-$(CONFIG_TARGET_HSDK) +=  hsdk.dtb hsdk-4xd.dtb
 dtb-$(CONFIG_TARGET_IOT_DEVKIT) +=  iot_devkit.dtb
 
-include $(srctree)/scripts/Makefile.dts
-
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000

arch/arc/lib/cpu.c

@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <init.h>
 #include <malloc.h>
 #include <vsprintf.h>
@@ -19,7 +18,7 @@ int arch_cpu_init(void)
 {
 	timer_init();
 
-	gd->cpu_clk = get_board_sys_clk();
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
 	cache_init();

arch/arm/Kconfig

@@ -311,10 +311,6 @@ config CPU_PXA
 	select SYS_CACHE_SHIFT_5
 	imply SYS_ARM_MMU
 
-config CPU_PXA27X
-	bool
-	select CPU_PXA
-
 config CPU_SA1100
 	bool
 	select SYS_CACHE_SHIFT_5
@@ -452,6 +448,9 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
 	  values, then choose this option, and create a file included as
 	  <asm/arch/boot0.h> which contains the required assembler code.
 
+config ARM_CORTEX_CPU_IS_UP
+	bool
+
 config USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy"
 	default y if !ARM64
@@ -636,7 +635,6 @@ config ARCH_BCMSTB
 	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	imply CMD_DM
-	imply OF_HAS_PRIOR_STAGE
 	help
 	  This enables support for Broadcom ARM-based set-top box
 	  chipsets, including the 7445 family of chips.
@@ -709,12 +707,12 @@ config ARCH_HIGHBANK
 	select DM
 	select DM_SERIAL
 	select OF_CONTROL
+	select OF_BOARD
 	select CLK
 	select CLK_CCF
 	select AHCI
 	select DM_ETH
 	select PHYS_64BIT
-	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
@@ -929,31 +927,19 @@ config ARCH_APPLE
 	select CLK
 	select CMD_USB
 	select DM
-	select DM_GPIO
 	select DM_KEYBOARD
-	select DM_MAILBOX
-	select DM_RESET
 	select DM_SERIAL
-	select DM_SPI
 	select DM_USB
 	select DM_VIDEO
 	select IOMMU
 	select LINUX_KERNEL_IMAGE_HEADER
 	select OF_CONTROL
-	select PINCTRL
+	select OF_BOARD
 	select POSITION_INDEPENDENT
-	select POWER_DOMAIN
-	select REGMAP
-	select SPI
-	select SYSCON
-	select SYSRESET
-	select SYSRESET_WATCHDOG
-	select SYSRESET_WATCHDOG_AUTO
 	select USB
 	imply CMD_DM
 	imply CMD_GPT
 	imply DISTRO_DEFAULTS
-	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
@@ -978,7 +964,6 @@ config ARCH_QEMU
 	imply DM_RNG
 	imply DM_RTC
 	imply RTC_PL031
-	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
@@ -1062,8 +1047,6 @@ config ARCH_SUNXI
 	select DM_ETH
 	select DM_GPIO
 	select DM_I2C if I2C
-	select DM_SPI if SPI
-	select DM_SPI_FLASH if SPI
 	select DM_KEYBOARD
 	select DM_MMC if MMC
 	select DM_SCSI if SCSI
@@ -1141,6 +1124,7 @@ config ARCH_VERSAL
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select GICV3
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SOC_DEVICE
 	imply BOARD_LATE_INIT
@@ -1160,13 +1144,13 @@ config ARCH_ZYNQ
 	select CLK
 	select CLK_ZYNQ
 	select CPU_V7A
-	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
 	select DM
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPI
 	select SPL_BOARD_INIT if SPL
@@ -1193,6 +1177,7 @@ config ARCH_ZYNQMP_R5
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	imply CMD_DM
 	imply DM_USB_GADGET
@@ -1202,15 +1187,15 @@ config ARCH_ZYNQMP
 	select ARM64
 	select CLK
 	select DM
-	select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
 	select DM_ETH if NET
 	select DM_MAILBOX
 	select DM_MMC if MMC
 	select DM_SERIAL
 	select DM_SPI if SPI
 	select DM_SPI_FLASH if DM_SPI
-	imply FIRMWARE
+	select FIRMWARE
 	select GICV2
+	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
 	select SPL_CLK if SPL
@@ -1218,7 +1203,7 @@ config ARCH_ZYNQMP
 	select SPL_DM_SPI if SPI && SPL_DM
 	select SPL_DM_SPI_FLASH if SPL_DM_SPI
 	select SPL_DM_MAILBOX if SPL
-	imply SPL_FIRMWARE if SPL
+	select SPL_FIRMWARE if SPL
 	select SPL_SEPARATE_BSS if SPL
 	select SUPPORT_SPL
 	select ZYNQMP_IPI
@@ -1229,7 +1214,6 @@ config ARCH_ZYNQMP
 	imply FAT_WRITE
 	imply MP
 	imply DM_USB_GADGET
-	imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
 
 config ARCH_TEGRA
 	bool "NVIDIA Tegra"
@@ -1257,6 +1241,7 @@ config TARGET_VEXPRESS64_JUNO
 	select PL01X_SERIAL
 	select DM
 	select OF_CONTROL
+	select OF_BOARD
 	select CLK
 	select DM_SERIAL
 	select ARM_PSCI_FW
@@ -1264,7 +1249,6 @@ config TARGET_VEXPRESS64_JUNO
 	select DM_ETH
 	select BLK
 	select USB
-	imply OF_HAS_PRIOR_STAGE
 
 config TARGET_TOTAL_COMPUTE
 	bool "Support Total Compute Platform"
@@ -1777,24 +1761,9 @@ config TARGET_SL28
 	help
 	  Support for Kontron SMARC-sAL28 board.
 
-config TARGET_TEN64
-	bool "Support ten64"
-	select ARCH_LS1088A
-	select ARCH_MISC_INIT
-	select ARM64
-	select ARMV8_MULTIENTRY
-	select ARCH_SUPPORT_TFABOOT
-	select BOARD_LATE_INIT
-	select SUPPORT_SPL
-	select FSL_DDR_INTERACTIVE if !SD_BOOT
-	select GPIO_EXTRA_HEADER
-	help
-	  Support for Traverse Technologies Ten64 board, based
-	  on NXP LS1088A.
-
 config TARGET_COLIBRI_PXA270
 	bool "Support colibri_pxa270"
-	select CPU_PXA27X
+	select CPU_PXA
 	select GPIO_EXTRA_HEADER
 
 config ARCH_UNIPHIER
@@ -1885,7 +1854,6 @@ config ARCH_STM32MP
 	imply OF_LIBFDT_OVERLAY
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
 	imply USE_PREBOOT
-	imply TIMESTAMP
 	help
 	  Support for STM32MP SoC family developed by STMicroelectronics,
 	  MPUs based on ARM cortex A core
@@ -1937,8 +1905,6 @@ config ARCH_OCTEONTX
 	select OF_LIVE
 	select BOARD_LATE_INIT
 	select SYS_CACHE_SHIFT_7
-	select SYS_PCI_64BIT if PCI
-	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_OCTEONTX2
 	bool "Support OcteonTX2 SoCs"
@@ -1950,8 +1916,6 @@ config ARCH_OCTEONTX2
 	select OF_LIVE
 	select BOARD_LATE_INIT
 	select SYS_CACHE_SHIFT_7
-	select SYS_PCI_64BIT if PCI
-	imply OF_HAS_PRIOR_STAGE
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
@@ -1988,8 +1952,6 @@ config TARGET_XENGUEST_ARM64
 	select LINUX_KERNEL_IMAGE_HEADER
 	select XEN_SERIAL
 	select SSCANF
-	imply OF_HAS_PRIOR_STAGE
-
 endchoice
 
 config SUPPORT_PASSING_ATAGS
@@ -2076,14 +2038,6 @@ config ISW_ENTRY_ADDR
 	  image headers.
 endif
 
-config SYS_KWD_CONFIG
-	string "kwbimage config file path"
-	depends on ARCH_KIRKWOOD || ARCH_MVEBU
-	default "arch/arm/mach-mvebu/kwbimage.cfg"
-	help
-	  Path within the source directory to the kwbimage.cfg file to use
-	  when packaging the U-Boot image for use.
-
 source "arch/arm/mach-apple/Kconfig"
 
 source "arch/arm/mach-aspeed/Kconfig"
@@ -2241,7 +2195,6 @@ source "board/socionext/developerbox/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/tcl/sl50/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
-source "board/traverse/ten64/Kconfig"
 source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/phytium/durian/Kconfig"

arch/arm/cpu/arm920t/ep93xx/speed.c

@@ -6,13 +6,12 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <asm/arch/ep93xx.h>
 #include <asm/io.h>
 #include <div64.h>
 
 /*
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  *
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -21,14 +20,14 @@
 /*
  * return the PLL output frequency
  *
- * PLL rate = get_board_sys_clk() * (X1FBD + 1) * (X2FBD + 1)
+ * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
  * / (X2IPD + 1) / 2^PS
  */
 static ulong get_PLLCLK(uint32_t *pllreg)
 {
 	uint8_t i;
 	const uint32_t clkset = readl(pllreg);
-	uint64_t rate = get_board_sys_clk();
+	uint64_t rate = CONFIG_SYS_CLK_FREQ;
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
 	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
 	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
@@ -88,9 +87,9 @@ ulong get_UCLK(void)
 
 	const uint32_t value = readl(&syscon->pwrcnt);
 	if (value & SYSCON_PWRCNT_UART_BAUD)
-		uclk_rate = get_board_sys_clk();
+		uclk_rate = CONFIG_SYS_CLK_FREQ;
 	else
-		uclk_rate = get_board_sys_clk() / 2;
+		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
 
 	return uclk_rate;
 }

arch/arm/cpu/arm920t/imx/speed.c

@@ -7,14 +7,13 @@
 
 #include <common.h>
 #if defined (CONFIG_IMX)
-#include <clock_legacy.h>
 
 #include <asm/arch/imx-regs.h>
 
 /* ------------------------------------------------------------------------- */
 /* NOTE: This describes the proper use of this file.
  *
- * get_board_sys_clk() should be defined as the input frequency of the PLL.
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
  * SH FIXME: 16780000 in our case
  * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
  * the specified bus in HZ.
@@ -46,7 +45,7 @@ ulong get_mcuPLLCLK(void)
 
 	mfi = mfi<=5 ? 5 : mfi;
 
-	return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
+	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
 }
 
 ulong get_FCLK(void)

arch/arm/cpu/arm926ejs/Makefile

@@ -15,7 +15,6 @@ endif
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/
-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 
 # some files can only build in ARM or THUMB2, not THUMB1
 

arch/arm/cpu/arm926ejs/cpu.c

@@ -21,19 +21,6 @@
 
 static void cache_flush(void);
 
-/************************************************************
- * sdelay() - simple spin loop.  Will be constant time as
- *  its generally used in bypass conditions only.  This
- *  is necessary until timers are accessible.
- *
- *  not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0"(loops));
-}
-
 int cleanup_before_linux (void)
 {
 	/*

arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg

@@ -2,5 +2,5 @@ DISPLAYPROGRESS
 SECTION 0x0 BOOTABLE
  TAG LAST
  LOAD     0x1000     spl/u-boot-spl.bin
- LOAD IVT 0xE000     0x1000
- CALL HAB 0xE000     0x0
+ LOAD IVT 0x8000     0x1000
+ CALL HAB 0x8000     0x0

arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

@@ -2,8 +2,8 @@ DISPLAYPROGRESS
 SECTION 0x0 BOOTABLE
  TAG LAST
  LOAD     0x1000     spl/u-boot-spl.bin
- LOAD IVT 0xE000     0x1000
- CALL HAB 0xE000     0x0
+ LOAD IVT 0x8000     0x1000
+ CALL HAB 0x8000     0x0
  LOAD     0x40002000 u-boot.bin
- LOAD IVT 0xE000     0x40002000
- CALL HAB 0xE000     0x0
+ LOAD IVT 0x8000     0x40002000
+ CALL HAB 0x8000     0x0

arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

@@ -627,11 +627,11 @@ static void mxs_power_enable_4p2(void)
 
 	mxs_power_init_dcdc_4p2_source();
 
-	writel(vddioctrl, &power_regs->hw_power_vddioctrl);
+	writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 	early_delay(20);
 	writel(vddactrl, &power_regs->hw_power_vddactrl);
 	early_delay(20);
-	writel(vdddctrl, &power_regs->hw_power_vdddctrl);
+	writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 
 	/*
 	 * Check if FET is enabled on either powerout and if so,

arch/arm/cpu/arm926ejs/start.S

@@ -17,7 +17,6 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <common.h>
-#include <linux/linkage.h>
 
 /*
  *************************************************************************
@@ -33,13 +32,8 @@
  */
 
 	.globl	reset
-	.globl	save_boot_params_ret
-	.type   save_boot_params_ret,%function
 
 reset:
-	/* Allow the board to save important registers */
-	b	save_boot_params
-save_boot_params_ret:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
@@ -116,16 +110,3 @@ flush_dcache:
 #endif
 	mov	pc, lr		/* back to my caller */
 #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
-
-/*************************************************************************
- *
- * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
- *	__attribute__((weak));
- *
- * Stack pointer is not yet initialized at this moment
- * Don't save anything to stack even if compiled with -O0
- *
- *************************************************************************/
-WEAK(save_boot_params)
-	b	save_boot_params_ret	/* back to my caller */
-ENDPROC(save_boot_params)

arch/arm/cpu/arm926ejs/sunxi/Makefile

@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
-
-obj-y	+= fel_utils.o
-CFLAGS_fel_utils.o := -marm

arch/arm/cpu/arm926ejs/sunxi/config.mk

@@ -1,6 +0,0 @@
-# Build a combined spl + u-boot image
-ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot-sunxi-with-spl.bin
-endif
-endif

arch/arm/cpu/arm926ejs/sunxi/fel_utils.S

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Utility functions for FEL mode.
- *
- * Copyright (c) 2015 Google, Inc
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/system.h>
-#include <linux/linkage.h>
-
-ENTRY(save_boot_params)
-	ldr	r0, =fel_stash
-	str	sp, [r0, #0]
-	str	lr, [r0, #4]
-	mrs	lr, cpsr		@ Read CPSR
-	str	lr, [r0, #8]
-	mrc	p15, 0, lr, c1, c0, 0	@ Read CP15 SCTLR Register
-	str	lr, [r0, #12]
-	b	save_boot_params_ret
-ENDPROC(save_boot_params)
-
-ENTRY(return_to_fel)
-	mov	sp, r0
-	mov	lr, r1
-	ldr	r0, =fel_stash
-	ldr	r1, [r0, #12]
-	mcr	p15, 0, r1, c1, c0, 0	@ Write CP15 SCTLR register
-	ldr	r1, [r0, #8]
-	msr	cpsr, r1		@ Write CPSR
-	bx	lr
-ENDPROC(return_to_fel)

arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds

@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2018
- * Icenowy Zheng <icenowy@aosc.io>
- *
- * Based on arch/arm/cpu/armv7/sunxi/u-boot-spl.lds:
- */
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
-		LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
-		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	.text      :
-	{
-		__start = .;
-		*(.vectors)
-		*(.text*)
-	} > .sram
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
-	. = ALIGN(4);
-	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	} > .sram
-
-	. = ALIGN(4);
-	__image_copy_end = .;
-	_end = .;
-
-	.bss :
-	{
-		. = ALIGN(4);
-		__bss_start = .;
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_end = .;
-	} > .sdram
-}

arch/arm/cpu/armv7/Kconfig

@@ -76,9 +76,4 @@ config ARMV7_LPAE
 	Say Y here to use the long descriptor page table format. This is
 	required if U-Boot runs in HYP mode.
 
-config SPL_ARMV7_SET_CORTEX_SMPEN
-	bool
-	help
-	  Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
-
 endif

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -1,6 +1,5 @@
 config ARCH_LS1021A
 	bool
-	select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR
 	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
 	select SYS_FSL_ERRATUM_A008378

arch/arm/cpu/armv7/ls102xa/clock.c

@@ -39,7 +39,7 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = get_board_sys_clk();
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 
 	sys_info->freq_systembus = sysclk;
 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)

arch/arm/cpu/armv7/ls102xa/fdt.c

@@ -131,9 +131,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	sysclk_path = fdt_get_alias(blob, "sysclk");
 	if (sysclk_path)
 		do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
-				     get_board_sys_clk(), 1);
+				     CONFIG_SYS_CLK_FREQ, 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
-			       "clock-frequency", get_board_sys_clk(), 1);
+			       "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 
 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 #define UBOOT_HEAD_LEN	0x1000
@@ -184,13 +184,13 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 	off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 					    CONFIG_SYS_IFC_ADDR);
-	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
+	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 #else
 	off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
 					    QSPI0_BASE_ADDR);
-	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
+	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 	off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
 					    DSPI1_BASE_ADDR);
-	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
+	fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 #endif
 }

arch/arm/cpu/armv7/s5p-common/timer.c

@@ -37,7 +37,7 @@ static inline struct s5p_timer *s5p_get_base_timer(void)
  * This operates at 1MHz and counts downwards. It will wrap about every
  * hour (2^32 microseconds).
  *
- * Return: current value of timer
+ * @return current value of timer
  */
 static unsigned long timer_get_us_down(void)
 {

arch/arm/cpu/armv7/start.S

@@ -173,17 +173,6 @@ ENDPROC(switch_to_hypervisor)
  *
  *************************************************************************/
 ENTRY(cpu_init_cp15)
-
-#if CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN)
-	/*
-	 * The Arm Cortex-A7 TRM says this bit must be enabled before
-	 * "any cache or TLB maintenance operations are performed".
-	 */
-	mrc	p15, 0, r0, c1, c0, 1	@ read auxilary control register
-	orr	r0, r0, #1 << 6		@ set SMP bit to enable coherency
-	mcr	p15, 0, r0, c1, c0, 1	@ write auxilary control register
-#endif
-
 	/*
 	 * Invalidate L1 I/D
 	 */

arch/arm/cpu/armv7/sunxi/Makefile

@@ -5,13 +5,11 @@
 # Based on some other Makefile
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+obj-y	+= timer.o
 
 obj-$(CONFIG_MACH_SUN6I)	+= tzpc.o
 obj-$(CONFIG_MACH_SUN8I_H3)	+= tzpc.o
 
-obj-$(CONFIG_MACH_SUN6I)	+= sram.o
-obj-$(CONFIG_MACH_SUN8I)	+= sram.o
-
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
 endif

arch/arm/cpu/armv7/sunxi/sram.c

@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * SRAM init for older sunxi SoCs.
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-
-void sunxi_sram_init(void)
-{
-	/*
-	 * Undocumented magic taken from boot0, without this DRAM
-	 * access gets messed up (seems cache related).
-	 * The boot0 sources describe this as: "config ema for cache sram"
-	 * Newer SoCs (A83T, H3 and anything beyond) don't need this anymore.
-	 */
-	if (IS_ENABLED(CONFIG_MACH_SUN6I))
-		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-
-	if (IS_ENABLED(CONFIG_MACH_SUN8I)) {
-		uint version = sunxi_get_sram_id();
-
-		if (IS_ENABLED(CONFIG_MACH_SUN8I_A23)) {
-			if (version == 0x1650)
-				setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-			else /* 0x1661 ? */
-				setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-		} else if (IS_ENABLED(CONFIG_MACH_SUN8I_A33)) {
-			if (version != 0x1667)
-				setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-		}
-	}
-}

arch/arm/cpu/armv7/sunxi/timer.c

@@ -51,7 +51,6 @@ int timer_init(void)
 	struct sunxi_timer_reg *timers =
 		(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
 	struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
-
 	writel(TIMER_LOAD_VAL, &timer->inter);
 	writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
 	       &timer->ctl);
@@ -59,14 +58,15 @@ int timer_init(void)
 	return 0;
 }
 
+/* timer without interrupts */
 static ulong get_timer_masked(void)
 {
 	/* current tick value */
 	ulong now = TICKS_TO_HZ(read_timer());
 
-	if (now >= gd->arch.lastinc) {	/* normal (non rollover) */
+	if (now >= gd->arch.lastinc)	/* normal (non rollover) */
 		gd->arch.tbl += (now - gd->arch.lastinc);
-	} else {
+	else {
 		/* rollover */
 		gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
 				- gd->arch.lastinc) + now;
@@ -76,7 +76,6 @@ static ulong get_timer_masked(void)
 	return gd->arch.tbl;
 }
 
-/* timer without interrupts */
 ulong get_timer(ulong base)
 {
 	return get_timer_masked() - base;

arch/arm/cpu/armv7m/cpu.c

@@ -12,7 +12,6 @@
 #include <irq_func.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
-#include <spl.h>
 
 /*
  * This is called right before passing control to
@@ -57,8 +56,3 @@ void reset_cpu(void)
 		| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
 		| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
 }
-
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
-	spl_image->entry_point |= 0x1;
-}

arch/arm/cpu/armv8/Kconfig

@@ -102,7 +102,7 @@ config PSCI_RESET
 	bool "Use PSCI for reset and shutdown"
 	default y
 	select ARM_SMCCC if OF_CONTROL
-	depends on !ARCH_APPLE && !ARCH_BCM283X && !ARCH_EXYNOS7 && \
+	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
 		   !TARGET_LS2080AQDS && \
 		   !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
 		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \

arch/arm/cpu/armv8/Makefile

@@ -42,5 +42,6 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
 obj-$(CONFIG_S32V234) += s32v234/
 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
 obj-$(CONFIG_ARMV8_PSCI) += psci.o
+obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
 obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
 obj-$(CONFIG_XEN) += xen/

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -21,7 +21,6 @@ config ARCH_LS1012A
 	select SYS_I2C_MXC_I2C1 if !DM_I2C
 	select SYS_I2C_MXC_I2C2 if !DM_I2C
 	imply PANIC_HANG
-	imply TIMESTAMP
 
 config ARCH_LS1028A
 	bool
@@ -42,7 +41,6 @@ config ARCH_LS1028A
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
 	select FSL_TZASC_1
-	select FSL_TZPC_BP147
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
@@ -61,7 +59,6 @@ config ARCH_LS1043A
 	bool
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873 if !TFABOOT
-	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
 	select GICV2
@@ -97,7 +94,6 @@ config ARCH_LS1043A
 config ARCH_LS1046A
 	bool
 	select ARMV8_SET_SMPEN
-	select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
 	select GICV2
@@ -138,7 +134,6 @@ config ARCH_LS1088A
 	bool
 	select ARMV8_SET_SMPEN
 	select ARM_ERRATA_855873 if !TFABOOT
-	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
@@ -187,7 +182,6 @@ config ARCH_LS2080A
 	select ARM_ERRATA_828024
 	select ARM_ERRATA_829520
 	select ARM_ERRATA_833471
-	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
 	select GICV3
@@ -239,11 +233,8 @@ config ARCH_LS2080A
 config ARCH_LX2162A
 	bool
 	select ARMV8_SET_SMPEN
-	select FSL_DDR_BIST
-	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select FSL_TZPC_BP147
 	select GICV3
 	select NXP_LSCH3_2
 	select SYS_HAS_SERDES
@@ -263,7 +254,6 @@ config ARCH_LX2162A
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
-	select SYS_PCI_64BIT if PCI
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
@@ -277,11 +267,8 @@ config ARCH_LX2162A
 config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
-	select FSL_DDR_BIST
-	select FSL_DDR_INTERACTIVE
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
-	select FSL_TZPC_BP147
 	select GICV3
 	select HAS_FSL_XHCI_USB if USB_HOST
 	select NXP_LSCH3_2
@@ -303,7 +290,6 @@ config ARCH_LX2160A
 	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
-	select SYS_PCI_64BIT if PCI
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
@@ -531,6 +517,10 @@ endmenu
 menu "Layerscape clock tree configuration"
 	depends on FSL_LSCH2 || FSL_LSCH3
 
+config SYS_FSL_CLK
+	bool "Enable clock tree initialization"
+	default y
+
 config CLUSTER_CLK_FREQ
 	int "Reference clock of core cluster"
 	depends on ARCH_LS1012A

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <env.h>
 #include <fsl_ddr_sdram.h>

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -161,9 +161,14 @@ void fsl_fdt_disable_usb(void *blob)
 	 * controller is used, SYSCLK must meet the additional requirement
 	 * of 100 MHz.
 	 */
-	if (get_board_sys_clk() != 100000000)
-		fdt_for_each_node_by_compatible(off, blob, -1, "snps,dwc3")
+	if (CONFIG_SYS_CLK_FREQ != 100000000) {
+		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
+		while (off != -FDT_ERR_NOTFOUND) {
 			fdt_status_disabled(blob, off);
+			off = fdt_node_offset_by_compatible(blob, off,
+							    "snps,dwc3");
+		}
+	}
 }
 
 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
@@ -650,7 +655,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #endif
 
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
-			     get_board_sys_clk(), 1);
+			     CONFIG_SYS_CLK_FREQ, 1);
 
 #ifdef CONFIG_GIC_V3_ITS
 	ls_gic_rd_tables_init(blob);

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c

@@ -249,7 +249,7 @@ int setup_serdes_volt(u32 svdd)
 
 	/*
 	 * If SVDD set failed, will not return directly, so that the
-	 * serdes lanes can complete resetting.
+	 * serdes lanes can complete reseting.
 	 */
 	ret = set_serdes_volt(svdd_tar);
 	if (ret)

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -52,12 +52,12 @@ void get_sys_info(struct sys_info *sys_info)
 	uint i, cluster;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = get_board_sys_clk();
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	unsigned long cluster_clk;
 
 	sys_info->freq_systembus = sysclk;
 #ifndef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_CLUSTER_CLK_FREQ	CONFIG_SYS_CLK_FREQ
 #endif
 	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
 

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -72,7 +72,7 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
-	unsigned long sysclk = get_board_sys_clk();
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
 	u32 c_pll_sel, cplx_pll;
 	void *offset;

arch/arm/cpu/armv8/fsl-layerscape/icid.c

@@ -116,7 +116,8 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
 	int noff, len, icid;
 	const u32 *prop;
 
-	fdt_for_each_node_by_compatible(noff, blob, -1, compat) {
+	noff = fdt_node_offset_by_compatible(blob, -1, compat);
+	while (noff > 0) {
 		prop = fdt_getprop(blob, noff, "cell-index", &len);
 		if (!prop) {
 			printf("WARNING missing cell-index for fman port\n");
@@ -136,6 +137,8 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
 		}
 
 		fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
+
+		noff = fdt_node_offset_by_compatible(blob, noff, compat);
 	}
 }
 

arch/arm/cpu/armv8/fsl-layerscape/mp.c

@@ -4,7 +4,6 @@
  */
 
 #include <common.h>
-#include <clock_legacy.h>
 #include <cpu_func.h>
 #include <image.h>
 #include <log.h>

arch/arm/cpu/armv8/fsl-layerscape/spl.c

@@ -93,9 +93,7 @@ void board_init_f(ulong dummy)
 	i2c_init_all();
 #endif
 #endif
-#if defined(CONFIG_VID) && (defined(CONFIG_ARCH_LS1088A) || \
-			    defined(CONFIG_ARCH_LX2160A) || \
-			    defined(CONFIG_ARCH_LX2162A))
+#ifdef CONFIG_VID
 	init_func_vid();
 #endif
 	dram_init();

arch/arm/cpu/armv8/lowlevel_init.S

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * A lowlevel_init function that sets up the stack to call a C function to
+ * perform further init.
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	/*
+	 * Setup a temporary stack. Global data is not available yet.
+	 */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	ldr	w0, =CONFIG_SPL_STACK
+#else
+	ldr	w0, =CONFIG_SYS_INIT_SP_ADDR
+#endif
+	bic	sp, x0, #0xf	/* 16-byte alignment for ABI compliance */
+
+	/*
+	 * Save the old LR(passed in x29) and the current LR to stack
+	 */
+	stp	x29, x30, [sp, #-16]!
+
+	/*
+	 * Call the very early init function. This should do only the
+	 * absolute bare minimum to get started. It should not:
+	 *
+	 * - set up DRAM
+	 * - use global_data
+	 * - clear BSS
+	 * - try to start a console
+	 *
+	 * For boards with SPL this should be empty since SPL can do all of
+	 * this init in the SPL board_init_f() function which is called
+	 * immediately after this.
+	 */
+	bl	s_init
+	ldp	x29, x30, [sp]
+	ret
+ENDPROC(lowlevel_init)

arch/arm/cpu/armv8/start.S

@@ -104,6 +104,10 @@ pie_skip_reloc:
 pie_fixup_done:
 #endif
 
+#ifdef CONFIG_SYS_RESET_SCTRL
+	bl reset_sctrl
+#endif
+
 #if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
 .macro	set_vbar, regname, reg
 	msr	\regname, \reg
@@ -191,6 +195,39 @@ slave_cpu:
 master_cpu:
 	bl	_main
 
+#ifdef CONFIG_SYS_RESET_SCTRL
+reset_sctrl:
+	switch_el x1, 3f, 2f, 1f
+3:
+	mrs	x0, sctlr_el3
+	b	0f
+2:
+	mrs	x0, sctlr_el2
+	b	0f
+1:
+	mrs	x0, sctlr_el1
+
+0:
+	ldr	x1, =0xfdfffffa
+	and	x0, x0, x1
+
+	switch_el x1, 6f, 5f, 4f
+6:
+	msr	sctlr_el3, x0
+	b	7f
+5:
+	msr	sctlr_el2, x0
+	b	7f
+4:
+	msr	sctlr_el1, x0
+
+7:
+	dsb	sy
+	isb
+	b	__asm_invalidate_tlb_all
+	ret
+#endif
+
 /*-----------------------------------------------------------------------*/
 
 WEAK(apply_core_errata)

arch/arm/cpu/armv8/u-boot-spl.lds

@@ -84,8 +84,4 @@ SECTIONS
 	/DISCARD/ : { *(.plt*) }
 	/DISCARD/ : { *(.interp*) }
 	/DISCARD/ : { *(.gnu*) }
-
-#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER
-#include "linux-kernel-image-header-vars.h"
-#endif
 }

arch/arm/dts/Makefile

@@ -34,10 +34,9 @@ dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
 
 dtb-$(CONFIG_ARCH_APPLE) += \
 	t8103-j274.dtb \
-	t8103-j293.dtb \
-	t8103-j313.dtb \
-	t8103-j456.dtb \
-	t8103-j457.dtb
+	t8103-j293.dtb
+
+dtb-$(CONFIG_EXYNOS9820) += exynos9820-beyond1lte.dtb
 
 dtb-$(CONFIG_ARCH_DAVINCI) += \
 	da850-evm.dtb \
@@ -71,7 +70,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \
 	kirkwood-openrd-client.dtb \
 	kirkwood-openrd-ultimate.dtb \
 	kirkwood-pogo_e02.dtb \
-	kirkwood-pogoplug-series-4.dtb \
 	kirkwood-sheevaplug.dtb
 
 dtb-$(CONFIG_MACH_S900) += \
@@ -82,9 +80,8 @@ dtb-$(CONFIG_MACH_S700) += \
 dtb-$(CONFIG_ROCKCHIP_PX30) += \
 	px30-evb.dtb \
 	px30-firefly.dtb \
-	px30-engicam-px30-core-ctouch2.dtb \
-	px30-engicam-px30-core-ctouch2-of10.dtb \
-	px30-engicam-px30-core-edimm2.2.dtb \
+	px30-px30-core-ctouch2.dtb \
+	px30-px30-core-edimm2.2.dtb \
 	rk3326-odroid-go2.dtb
 
 dtb-$(CONFIG_ROCKCHIP_RK3036) += \
@@ -137,7 +134,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-ficus.dtb \
 	rk3399-firefly.dtb \
 	rk3399-gru-bob.dtb \
-	rk3399-gru-kevin.dtb \
 	rk3399-khadas-edge.dtb \
 	rk3399-khadas-edge-captain.dtb \
 	rk3399-khadas-edge-v.dtb \
@@ -366,8 +362,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 dtb-$(CONFIG_ARCH_VERSAL) += \
 	versal-mini.dtb \
 	versal-mini-emmc0.dtb \
-	versal-mini-emmc1.dtb \
-	xilinx-versal-virt.dtb
+	versal-mini-emmc1.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
 	zynqmp-r5.dtb
 dtb-$(CONFIG_AM33XX) += \
@@ -486,8 +481,6 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
 	fsl-ls1028a-kontron-sl28-var3.dtb \
 	fsl-ls1028a-kontron-sl28-var4.dtb \
 
-dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
-
 dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
 dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
@@ -505,8 +498,6 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
 	stm32h743i-eval.dtb \
 	stm32h750i-art-pi.dtb
 
-dtb-$(CONFIG_MACH_SUNIV) += \
-	suniv-f1c100s-licheepi-nano.dtb
 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \
 	sun4i-a10-ba10-tvbox.dtb \
@@ -881,8 +872,6 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
 	imx7ulp-evk.dtb
 
-dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
-
 dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-apalis.dtb \
 	fsl-imx8qm-mek.dtb \
@@ -915,19 +904,13 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mn-ddr4-evk.dtb \
 	imx8mq-cm.dtb \
 	imx8mn-evk.dtb \
-	imx8mn-var-som-symphony.dtb \
-	imx8mn-venice.dtb \
-	imx8mn-venice-gw7902.dtb \
 	imx8mq-evk.dtb \
 	imx8mm-beacon-kit.dtb \
 	imx8mn-beacon-kit.dtb \
-	imx8mq-mnt-reform2.dtb \
 	imx8mq-phanbell.dtb \
 	imx8mp-evk.dtb \
 	imx8mp-phyboard-pollux-rdk.dtb \
-	imx8mp-verdin.dtb \
-	imx8mq-pico-pi.dtb \
-	imx8mq-kontron-pitx-imx8m.dtb
+	imx8mq-pico-pi.dtb
 
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
 	imxrt1020-evk.dtb
@@ -1096,8 +1079,7 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
 	bcm2837-rpi-3-a-plus.dtb \
 	bcm2837-rpi-3-b.dtb \
 	bcm2837-rpi-3-b-plus.dtb \
-	bcm2837-rpi-cm3-io3.dtb \
-	bcm2711-rpi-4-b.dtb
+	bcm2837-rpi-cm3-io3.dtb
 
 dtb-$(CONFIG_ARCH_BCM63158) += \
 	bcm963158.dtb
@@ -1110,8 +1092,6 @@ dtb-$(CONFIG_ARCH_BCM6858) += \
 
 dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
 
-dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
-
 dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
 dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
 
@@ -1119,6 +1099,7 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 
 dtb-$(CONFIG_STM32MP15x) += \
 	stm32mp157a-dk1.dtb \
+	stm32mp157a-avenger96.dtb \
 	stm32mp157a-icore-stm32mp1-ctouch2.dtb \
 	stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
 	stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
@@ -1143,11 +1124,7 @@ dtb-$(CONFIG_SOC_K3_AM6) += \
 dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
 			      k3-j721e-r5-common-proc-board.dtb \
 			      k3-j7200-common-proc-board.dtb \
-			      k3-j7200-r5-common-proc-board.dtb \
-			      k3-j721e-sk.dtb \
-			      k3-j721e-r5-sk.dtb
-dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
-			       k3-j721s2-r5-common-proc-board.dtb
+			      k3-j7200-r5-common-proc-board.dtb
 dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
 			      k3-am642-r5-evm.dtb \
 			      k3-am642-sk.dtb \
@@ -1164,11 +1141,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt8516-pumpkin.dtb \
 	mt8518-ap1-emmc.dtb
 
-dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
-
-dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb
-dtb-$(CONFIG_ARCH_OCTEONTX2) += octeontx.dtb
-
 dtb-$(CONFIG_TARGET_GE_BX50V3) += \
 	imx6q-bx50v3.dtb \
 	imx6q-b850v3.dtb \
@@ -1178,10 +1150,7 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
 dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
 dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
 
-# TODO(Linus Walleij <linus.walleij@linaro.org>): Should us a single vexpress
-# Kconfig option to build all of these. See examples above.
 dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
-dtb-$(CONFIG_TARGET_VEXPRESS64_JUNO) += juno-r2.dtb
 
 dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
 
@@ -1189,34 +1158,12 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
 
 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
 
-dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
-					imx8mm-cl-iot-gate-ied.dtbo \
-					imx8mm-cl-iot-gate-ied-adc0.dtbo \
-					imx8mm-cl-iot-gate-ied-adc1.dtbo \
-					imx8mm-cl-iot-gate-ied-can0.dtbo \
-					imx8mm-cl-iot-gate-ied-can1.dtbo \
-					imx8mm-cl-iot-gate-ied-tpm0.dtbo \
-					imx8mm-cl-iot-gate-ied-tpm1.dtbo
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
 
-dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \
-					imx8mm-cl-iot-gate-ied.dtbo \
-					imx8mm-cl-iot-gate-ied-adc0.dtbo \
-					imx8mm-cl-iot-gate-ied-adc1.dtbo \
-					imx8mm-cl-iot-gate-ied-can0.dtbo \
-					imx8mm-cl-iot-gate-ied-can1.dtbo \
-					imx8mm-cl-iot-gate-ied-tpm0.dtbo \
-					imx8mm-cl-iot-gate-ied-tpm1.dtbo
-
-ifneq ($(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)$(CONFIG_TARGET_IMX8MP_RSB3720A1_6G),)
-dtb-y += imx8mp-rsb3720-a1.dtb
-endif
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
 
 dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
 
-dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
-
-include $(srctree)/scripts/Makefile.dts
-
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here

arch/arm/dts/am335x-pdu001-u-boot.dtsi

@@ -5,25 +5,17 @@
 
 #include "am33xx-u-boot.dtsi"
 
-&l4_wkup {
-	u-boot,dm-pre-reloc;
-	segment@200000 {
-
-		target-module@10000 {
-			u-boot,dm-pre-reloc;
-		};
+/ {
+	ocp {
+		u-boot,dm-pre-reloc;
 	};
 };
 
-&l4_per {
+&l4_wkup {
 	u-boot,dm-pre-reloc;
-	segment@100000 {
-		u-boot,dm-pre-reloc;
+};
 
-		target-module@a6000 {
-			u-boot,dm-pre-reloc;
-		};
-	};
+&l4_per {
 
 	segment@300000 {
 

arch/arm/dts/am57xx-beagle-x15-revb1-u-boot.dtsi

@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"

arch/arm/dts/am57xx-beagle-x15-revc-u-boot.dtsi

@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"

arch/arm/dts/am57xx-beagle-x15-u-boot.dtsi

@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"

arch/arm/dts/am57xx-cl-som-am57x-u-boot.dtsi

@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"

arch/arm/dts/am57xx-idk-common-u-boot.dtsi

@@ -3,7 +3,6 @@
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  */
 #include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"
 
 / {
 	xtal25mhz: xtal25mhz {

arch/arm/dts/am57xx-sbc-am57x-u-boot.dtsi

@@ -1,7 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "omap5-u-boot.dtsi"
-#include "dra7-ipu-common-early-boot.dtsi"

arch/arm/dts/armada-371x.dtsi

@@ -1,4 +1,3 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada 371x family of SoCs
  * (also named 88F3710)
@@ -7,6 +6,43 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "armada-37xx.dtsi"

arch/arm/dts/armada-3720-db.dts

@@ -1,4 +1,3 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree file for Marvell Armada 3720 development board
  * (DB-88F3720-DDR3)
@@ -6,14 +5,47 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
- * This file is compatible with the version 1.4 and the version 2.0 of
- * the board, however the CON numbers are different between the 2
- * version
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
 #include "armada-372x.dtsi"
 
 / {
@@ -24,114 +56,41 @@
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory@0 {
+	aliases {
+		ethernet0 = &eth0;
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
 		device_type = "memory";
 		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
 	};
+};
 
-	exp_usb3_vbus: usb3-vbus {
-		compatible = "regulator-fixed";
-		regulator-name = "usb3-vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		enable-active-high;
-		regulator-always-on;
-		gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
+&comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_USB3_HOST0>;
+		phy-speed = <COMPHY_SPEED_5G>;
 	};
 
-	usb3_phy: usb3-phy {
-		compatible = "usb-nop-xceiv";
-		vcc-supply = <&exp_usb3_vbus>;
-	};
-
-	vcc_sd_reg1: regulator {
-		compatible = "regulator-gpio";
-		regulator-name = "vcc_sd1";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-
-		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
-		gpios-states = <0>;
-		states = <1800000 0x1
-			  3300000 0x0>;
-		enable-active-high;
-	};
-
-	vcc_sd_reg2: regulator-vmcc {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_sd2";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		enable-active-high;
-		gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
+	phy1 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+		phy-speed = <COMPHY_SPEED_2_5G>;
 	};
 };
 
-/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
 &eth0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>;
-	phy-mode = "rgmii-id";
-	phy = <&phy0>;
-	status = "okay";
-};
-
-/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
-&eth1 {
-	phy-mode = "sgmii";
-	phy = <&phy1>;
+	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
 	status = "okay";
+	phy-mode = "rgmii";
 };
 
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
 	status = "okay";
-
-	gpio_exp: pca9555@22 {
-		compatible = "nxp,pca9555";
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		reg = <0x22>;
-		/*
-		 * IO0_0: PWR_EN_USB2	IO1_0: PWR_EN_VTT
-		 * IO0_1: PWR_EN_USB23	IO1_1: MPCIE_WDISABLE
-		 * IO0_2: PWR_EN_SATA	IO1_2: RGMII_DEV_RSTN
-		 * IO0_3: PWR_EN_PCIE	IO1_3: SGMII_DEV_RSTN
-		 * IO0_4: PWR_EN_SD
-		 * IO0_5: PWR_EN_EMMC
-		 * IO0_6: PWR_EN_RGMII	IO1_6: SATA_USB3.0_SEL
-		 * IO0_7: PWR_EN_SGMII	IO1_7: PWR_MCI_PS
-		 */
-	};
-
-	rtc@68  {
-		/* PT7C4337A from pericom fully compatible with the ds1337 */
-		compatible = "dallas,ds1337";
-		reg = <0x68>;
-	};
-};
-
-&mdio {
-	status = "okay";
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-	};
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
-};
-
-/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
-&pcie0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
-	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
-	status = "okay";
 };
 
 /* CON3 */
@@ -140,23 +99,28 @@
 };
 
 &sdhci0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio_pins>;
+	status = "okay";
+};
+
+&sdhci1 {
 	non-removable;
 	bus-width = <8>;
 	mmc-ddr-1_8v;
 	mmc-hs400-1_8v;
 	marvell,pad-type = "fixed-1-8v";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc_pins>;
 	status = "okay";
-};
 
-/* SD slot module on CON14(V2.0)/CON15(V1.4) */
-&sdhci1 {
-	wp-inverted;
-	cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
-	bus-width = <4>;
-	marvell,pad-type = "sd";
-	vqmmc-supply = <&vcc_sd_reg1>;
-	vmmc-supply = <&vcc_sd_reg2>;
-	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+	};
 };
 
 &spi0 {
@@ -164,57 +128,37 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_quad_pins>;
 
-	m25p80@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <108000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			partition@0 {
-				label = "bootloader";
-				reg = <0x0 0x200000>;
-			};
-			partition@200000 {
-				label = "U-boot Env";
-				reg = <0x200000 0x10000>;
-			};
-			partition@210000 {
-				label = "Linux";
-				reg = <0x210000 0xDF0000>;
-			};
-		};
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p128", "jedec,spi-nor";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
 	};
 };
 
-/*
- * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
- * an FTDI (also on CON24(V2.0)/CON26(V1.4)).
- */
+/* Exported on the micro USB connector CON32 through an FTDI */
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart1_pins>;
 	status = "okay";
 };
 
-/* CON26(V2.0)/CON28(V1.4) */
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-/* CON27(V2.0)/CON29(V1.4) */
+/* CON29 */
 &usb2 {
 	status = "okay";
 };
 
-/* CON29(V2.0)/CON31(V1.4) */
+/* CON31 */
 &usb3 {
 	status = "okay";
-	usb-phy = <&usb3_phy>;
+};
+
+/* CON17 */
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+	status = "okay";
 };

arch/arm/dts/armada-3720-espressobin-u-boot.dtsi

@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-
-&spi0 {
-	flash@0 {
-		/*
-		 * For some unknown reason U-Boot SPI driver cannot access
-		 * SPI-NOR with higher frequency. Linux kernel SPI driver
-		 * does not have this problem.
-		 */
-		spi-max-frequency = <50000000>;
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@firmware {
-				reg = <0 CONFIG_ENV_OFFSET>;
-				label = "firmware";
-			};
-
-			partition@u-boot-env {
-				reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
-				label = "u-boot-env";
-			};
-		};
-#endif
-	};
-};
-
-/*
- * U-Boot requires to have this eMMC node by default in "okay" status. U-Boot
- * at runtime changes status to "disabled" if eMMC is not present on the board.
- */
-&sdhci0 {
-	status = "okay";
-};

arch/arm/dts/armada-3720-espressobin.dts

@@ -1,20 +1,210 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Device Tree file for Globalscale Marvell ESPRESSOBin Board
+ * Device Tree file for Marvell Armada 3720 community board
+ * (ESPRESSOBin)
  * Copyright (C) 2016 Marvell
  *
- * Romain Perier <romain.perier@free-electrons.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Konstantin Porotchkin <kostap@marvell.com>
  *
- */
-/*
- * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
 
-#include "armada-3720-espressobin.dtsi"
+#include "armada-372x.dtsi"
 
 / {
 	model = "Globalscale Marvell ESPRESSOBin Board";
 	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+	};
+
+	vcc_sd_reg0: regulator@0 {
+		compatible = "regulator-gpio";
+		regulator-name = "vcc_sd0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-type = "voltage";
+		states = <1800000 0x1
+			  3300000 0x0>;
+		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&comphy {
+	max-lanes = <3>;
+	phy0 {
+		phy-type = <COMPHY_TYPE_USB3_HOST0>;
+		phy-speed = <COMPHY_SPEED_5G>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+		phy-speed = <COMPHY_SPEED_2_5G>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_SATA0>;
+		phy-speed = <COMPHY_SPEED_5G>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+	phy-mode = "rgmii";
+	phy_addr = <0x1>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+/* CON3 */
+&sata {
+	status = "okay";
+};
+
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio_pins>;
+	bus-width = <4>;
+	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
+	vqmmc-supply = <&vcc_sd_reg0>;
+	status = "okay";
+};
+
+/* U11 */
+&sdhci1 {
+	non-removable;
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	marvell,xenon-emmc;
+	marvell,xenon-tun-count = <9>;
+	marvell,pad-type = "fixed-1-8v";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc_pins>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_quad_pins>;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p128", "jedec,spi-nor";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@firmware {
+				reg = <0 CONFIG_ENV_OFFSET>;
+				label = "firmware";
+			};
+
+			partition@u-boot-env {
+				reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
+				label = "u-boot-env";
+			};
+		};
+#endif
+	};
+};
+
+/* Exported on the micro USB connector CON32 through an FTDI */
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+/* CON29 */
+&usb2 {
+	status = "okay";
+};
+
+/* CON31 */
+&usb3 {
+	status = "okay";
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+	status = "okay";
 };

arch/arm/dts/armada-3720-espressobin.dtsi

@@ -1,218 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree file for Globalscale Marvell ESPRESSOBin Board
- * Copyright (C) 2016 Marvell
- *
- * Romain Perier <romain.perier@free-electrons.com>
- *
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-372x.dtsi"
-
-/ {
-	aliases {
-		ethernet0 = &eth0;
-		/* for dsa slave device */
-		ethernet1 = &switch0port1;
-		ethernet2 = &switch0port2;
-		ethernet3 = &switch0port3;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@0 {
-		device_type = "memory";
-		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
-	};
-
-	vcc_sd_reg1: regulator {
-		compatible = "regulator-gpio";
-		regulator-name = "vcc_sd1";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-
-		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
-		gpios-states = <0>;
-		states = <1800000 0x1
-			  3300000 0x0>;
-		enable-active-high;
-	};
-
-	led2: gpio-led2 {
-		/* led2 is working only on v7 board */
-		status = "disabled";
-
-		compatible = "gpio-leds";
-
-		led2 {
-			label = "led2";
-			gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
-			default-state = "off";
-		};
-	};
-};
-
-/* J9 */
-&pcie0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
-	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
-};
-
-/* J6 */
-&sata {
-	status = "okay";
-};
-
-/* U11 */
-&sdhci0 {
-	/* Main DTS file for Espressobin is without eMMC */
-	status = "disabled";
-
-	non-removable;
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	marvell,xenon-emmc;
-	marvell,xenon-tun-count = <9>;
-	marvell,pad-type = "fixed-1-8v";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc_pins>;
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	mmccard: mmccard@0 {
-		compatible = "mmc-card";
-		reg = <0>;
-	};
-};
-
-/* J1 */
-&sdhci1 {
-	wp-inverted;
-	bus-width = <4>;
-	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
-	marvell,pad-type = "sd";
-	vqmmc-supply = <&vcc_sd_reg1>;
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdio_pins>;
-	status = "okay";
-};
-
-&spi0 {
-	status = "okay";
-
-	flash@0 {
-		reg = <0>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <104000000>;
-		m25p,fast-read;
-	};
-};
-
-/* Exported on the micro USB connector J5 through an FTDI */
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_pins>;
-	status = "okay";
-};
-
-/*
- * Connector J17 and J18 expose a number of different features. Some pins are
- * multiplexed. This is the case for instance for the following features:
- * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
- *   how to enable it. Beware that the signals are 1.8V TTL.
- * - I2C
- * - SPI
- * - MMC
- */
-
-/* J7 */
-&usb3 {
-	status = "okay";
-};
-
-/* J8 */
-&usb2 {
-	status = "okay";
-};
-
-&mdio {
-	switch0: switch0@1 {
-		compatible = "marvell,mv88e6085";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <1>;
-
-		dsa,member = <0 0>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch0port0: port@0 {
-				reg = <0>;
-				label = "cpu";
-				ethernet = <&eth0>;
-				phy-mode = "rgmii-id";
-				fixed-link {
-					speed = <1000>;
-					full-duplex;
-				};
-			};
-
-			switch0port1: port@1 {
-				reg = <1>;
-				label = "wan";
-				phy-handle = <&switch0phy0>;
-			};
-
-			switch0port2: port@2 {
-				reg = <2>;
-				label = "lan0";
-				phy-handle = <&switch0phy1>;
-			};
-
-			switch0port3: port@3 {
-				reg = <3>;
-				label = "lan1";
-				phy-handle = <&switch0phy2>;
-			};
-
-		};
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch0phy0: switch0phy0@11 {
-				reg = <0x11>;
-			};
-			switch0phy1: switch0phy1@12 {
-				reg = <0x12>;
-			};
-			switch0phy2: switch0phy2@13 {
-				reg = <0x13>;
-			};
-		};
-	};
-};
-
-&eth0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
-	phy-mode = "rgmii-id";
-	status = "okay";
-
-	fixed-link {
-		speed = <1000>;
-		full-duplex;
-	};
-};

arch/arm/dts/armada-3720-turris-mox-u-boot.dtsi

@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * 2022 by Marek Behún <kabel@kernel.org>
- */
-
-/ {
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		old_binding_phy1: ethernet-phy@1 {
-			reg = <1>;
-		};
-	};
-};
-
-&eth0 {
-	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
-	/delete-property/ phy-handle;
-	phy = <&old_binding_phy1>;
-};
-
-/delete-node/ &mdio;
-
-&usb3 {
-	vbus-supply = <&exp_usb3_vbus>;
-};

arch/arm/dts/armada-3720-turris-mox.dts

@@ -1,14 +1,18 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// SPDX-License-Identifier: GPL-2.0+ or X11
 /*
  * Device Tree file for CZ.NIC Turris Mox Board
- * 2019 by Marek Behún <kabel@kernel.org>
+ * 2018 by Marek Behun <marek.behun@nic.cz>
+ *
+ * Based on armada-3720-espressobin.dts by:
+ *   Gregory CLEMENT <gregory.clement@free-electrons.com>
+ *   Konstantin Porotchkin <kostap@marvell.com>
  */
 
 /dts-v1/;
 
-#include <dt-bindings/bus/moxtet.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 #include "armada-372x.dtsi"
 
 / {
@@ -16,29 +20,29 @@
 	compatible = "cznic,turris-mox", "marvell,armada3720",
 		     "marvell,armada3710";
 
-	aliases {
-		spi0 = &spi0;
-		ethernet0 = &eth0;
-		ethernet1 = &eth1;
-		mmc0 = &sdhci0;
-		mmc1 = &sdhci1;
-	};
-
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	memory@0 {
+	aliases {
+		ethernet0 = &eth0;
+		ethernet1 = &eth1;
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
 		device_type = "memory";
 		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
 	};
 
 	leds {
 		compatible = "gpio-leds";
-		red {
-			label = "mox:red:activity";
+
+		led {
 			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "default-on";
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_ACTIVITY;
 		};
 	};
 
@@ -46,6 +50,7 @@
 		compatible = "gpio-keys";
 
 		reset {
+			compatible = "gpio-keys";
 			label = "reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
@@ -53,14 +58,16 @@
 		};
 	};
 
-	exp_usb3_vbus: usb3-vbus {
+	reg_usb3_vbus: usb3_vbus@0 {
 		compatible = "regulator-fixed";
 		regulator-name = "usb3-vbus";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		enable-active-high;
-		regulator-always-on;
+		startup-delay-us = <2000000>;
+		shutdown-delay-us = <1000000>;
 		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
 	};
 
 	vsdc_reg: vsdc-reg {
@@ -77,111 +84,56 @@
 		enable-active-high;
 	};
 
-	vsdio_reg: vsdio-reg {
-		compatible = "regulator-gpio";
-		regulator-name = "vsdio";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
-		gpios-states = <0>;
-		states = <1800000 0x1
-			  3300000 0x0>;
-		enable-active-high;
-	};
-
-	sdhci1_pwrseq: sdhci1-pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
-		status = "okay";
-	};
-
-	sfp: sfp {
-		compatible = "sff,sfp";
-		i2c-bus = <&i2c0>;
-		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
-		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
-		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
-		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
-		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
-
-		/* enabled by U-Boot if SFP module is present */
-		status = "disabled";
-	};
-
-	firmware {
-		armada-3700-rwtm {
-			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
+		eth_phy1: ethernet-phy@1 {
+			reg = <1>;
 		};
 	};
 };
 
+&comphy {
+	max-lanes = <3>;
+	phy0 {
+		phy-type = <COMPHY_TYPE_SGMII1>;
+		phy-speed = <COMPHY_SPEED_3_125G>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_PEX0>;
+		phy-speed = <COMPHY_SPEED_5G>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_USB3_HOST0>;
+		phy-speed = <COMPHY_SPEED_5G>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+	phy-mode = "rgmii";
+	phy = <&eth_phy1>;
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
-	clock-frequency = <100000>;
-	/delete-property/ mrvl,i2c-fast-mode;
 	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
 
 	rtc@6f {
-		compatible = "microchip,mcp7940x";
+		compatible = "microchip,mcp7941x";
 		reg = <0x6f>;
 	};
 };
 
-&pcie0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
-	status = "okay";
-	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
-	/*
-	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
-	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
-	 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
-	 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
-	 * no remapping) and that this address is the lowest from all specified ranges. If these
-	 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
-	 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
-	 * for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping.
-	 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
-	 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
-	 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
-	 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
-	 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
-	 * Bug related to requirement of same child and parent addresses for first range is fixed
-	 * in U-Boot version 2022.04 by following commit:
-	 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
-	 */
-	#address-cells = <3>;
-	#size-cells = <2>;
-	ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */
-		  0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */
-
-	/* enabled by U-Boot if PCIe module is present */
-	status = "disabled";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&eth0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>;
-	phy-mode = "rgmii-id";
-	phy-handle = <&phy1>;
-	status = "okay";
-};
-
-&eth1 {
-	phy-mode = "2500base-x";
-	managed = "in-band-status";
-	phys = <&comphy0 1>;
-};
-
-&sdhci0 {
+&sdhci1 {
 	wp-inverted;
 	bus-width = <4>;
 	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
@@ -190,23 +142,17 @@
 	status = "okay";
 };
 
-&sdhci1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdio_pins>;
-	non-removable;
-	bus-width = <4>;
-	marvell,pad-type = "sd";
-	vqmmc-supply = <&vsdio_reg>;
-	mmc-pwrseq = <&sdhci1_pwrseq>;
-	/* forbid SDR104 for FCC purposes */
-	sdhci-caps-mask = <0x2 0x0>;
-	status = "okay";
+&pinctrl_nb {
+	spi_cs1_pins: spi-cs1-pins {
+		groups = "spi_cs1";
+		function = "spi";
+	};
 };
 
 &spi0 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
+	pinctrl-0 = <&spi_cs1_pins>;
 	assigned-clocks = <&nb_periph_clk 7>;
 	assigned-clock-parents = <&tbg 1>;
 	assigned-clock-rates = <20000000>;
@@ -214,9 +160,10 @@
 	spi-flash@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
+		compatible = "st,s25fl064l", "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <20000000>;
+		m25p,fast-read;
 
 		partitions {
 			compatible = "fixed-partitions";
@@ -250,621 +197,36 @@
 		};
 	};
 
-	moxtet: moxtet@1 {
+	moxtet@1 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "cznic,moxtet";
 		reg = <1>;
 		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
-		spi-max-frequency = <10000000>;
+		spi-max-frequency = <1000000>;
 		spi-cpol;
 		spi-cpha;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		interrupt-parent = <&gpiosb>;
-		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
-		status = "okay";
-
-		moxtet_sfp: gpio@0 {
-			compatible = "cznic,moxtet-gpio";
-			gpio-controller;
-			#gpio-cells = <2>;
-			reg = <0>;
-			status = "disabled";
-		};
 	};
 };
 
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
 &usb2 {
 	status = "okay";
 };
 
-&comphy2 {
-	connector {
-		compatible = "usb-a-connector";
-		phy-supply = <&exp_usb3_vbus>;
-	};
-};
-
 &usb3 {
+	vbus-supply = <&reg_usb3_vbus>;
 	status = "okay";
-	phys = <&comphy2 0>;
 };
 
-&mdio {
+&pcie0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&smi_pins>;
-	status = "okay";
-
-	phy1: ethernet-phy@1 {
-		reg = <1>;
-	};
-
-	/* switch nodes are enabled by U-Boot if modules are present */
-	switch0@10 {
-		compatible = "marvell,mv88e6190";
-		reg = <0x10 0>;
-		dsa,member = <0 0>;
-		interrupt-parent = <&moxtet>;
-		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
-		status = "disabled";
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch0phy1: switch0phy1@1 {
-				reg = <0x1>;
-			};
-
-			switch0phy2: switch0phy2@2 {
-				reg = <0x2>;
-			};
-
-			switch0phy3: switch0phy3@3 {
-				reg = <0x3>;
-			};
-
-			switch0phy4: switch0phy4@4 {
-				reg = <0x4>;
-			};
-
-			switch0phy5: switch0phy5@5 {
-				reg = <0x5>;
-			};
-
-			switch0phy6: switch0phy6@6 {
-				reg = <0x6>;
-			};
-
-			switch0phy7: switch0phy7@7 {
-				reg = <0x7>;
-			};
-
-			switch0phy8: switch0phy8@8 {
-				reg = <0x8>;
-			};
-		};
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@1 {
-				reg = <0x1>;
-				label = "lan1";
-				phy-handle = <&switch0phy1>;
-			};
-
-			port@2 {
-				reg = <0x2>;
-				label = "lan2";
-				phy-handle = <&switch0phy2>;
-			};
-
-			port@3 {
-				reg = <0x3>;
-				label = "lan3";
-				phy-handle = <&switch0phy3>;
-			};
-
-			port@4 {
-				reg = <0x4>;
-				label = "lan4";
-				phy-handle = <&switch0phy4>;
-			};
-
-			port@5 {
-				reg = <0x5>;
-				label = "lan5";
-				phy-handle = <&switch0phy5>;
-			};
-
-			port@6 {
-				reg = <0x6>;
-				label = "lan6";
-				phy-handle = <&switch0phy6>;
-			};
-
-			port@7 {
-				reg = <0x7>;
-				label = "lan7";
-				phy-handle = <&switch0phy7>;
-			};
-
-			port@8 {
-				reg = <0x8>;
-				label = "lan8";
-				phy-handle = <&switch0phy8>;
-			};
-
-			port@9 {
-				reg = <0x9>;
-				label = "cpu";
-				ethernet = <&eth1>;
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-			};
-
-			switch0port10: port@a {
-				reg = <0xa>;
-				label = "dsa";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				link = <&switch1port9 &switch2port9>;
-				status = "disabled";
-			};
-
-			port-sfp@a {
-				reg = <0xa>;
-				label = "sfp";
-				sfp = <&sfp>;
-				phy-mode = "sgmii";
-				managed = "in-band-status";
-				status = "disabled";
-			};
-		};
-	};
-
-	switch0@2 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x2 0>;
-		dsa,member = <0 0>;
-		interrupt-parent = <&moxtet>;
-		interrupts = <MOXTET_IRQ_TOPAZ>;
-		status = "disabled";
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch0phy1_topaz: switch0phy1@11 {
-				reg = <0x11>;
-			};
-
-			switch0phy2_topaz: switch0phy2@12 {
-				reg = <0x12>;
-			};
-
-			switch0phy3_topaz: switch0phy3@13 {
-				reg = <0x13>;
-			};
-
-			switch0phy4_topaz: switch0phy4@14 {
-				reg = <0x14>;
-			};
-		};
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@1 {
-				reg = <0x1>;
-				label = "lan1";
-				phy-handle = <&switch0phy1_topaz>;
-			};
-
-			port@2 {
-				reg = <0x2>;
-				label = "lan2";
-				phy-handle = <&switch0phy2_topaz>;
-			};
-
-			port@3 {
-				reg = <0x3>;
-				label = "lan3";
-				phy-handle = <&switch0phy3_topaz>;
-			};
-
-			port@4 {
-				reg = <0x4>;
-				label = "lan4";
-				phy-handle = <&switch0phy4_topaz>;
-			};
-
-			port@5 {
-				reg = <0x5>;
-				label = "cpu";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				ethernet = <&eth1>;
-			};
-		};
-	};
-
-	switch1@11 {
-		compatible = "marvell,mv88e6190";
-		reg = <0x11 0>;
-		dsa,member = <0 1>;
-		interrupt-parent = <&moxtet>;
-		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
-		status = "disabled";
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch1phy1: switch1phy1@1 {
-				reg = <0x1>;
-			};
-
-			switch1phy2: switch1phy2@2 {
-				reg = <0x2>;
-			};
-
-			switch1phy3: switch1phy3@3 {
-				reg = <0x3>;
-			};
-
-			switch1phy4: switch1phy4@4 {
-				reg = <0x4>;
-			};
-
-			switch1phy5: switch1phy5@5 {
-				reg = <0x5>;
-			};
-
-			switch1phy6: switch1phy6@6 {
-				reg = <0x6>;
-			};
-
-			switch1phy7: switch1phy7@7 {
-				reg = <0x7>;
-			};
-
-			switch1phy8: switch1phy8@8 {
-				reg = <0x8>;
-			};
-		};
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@1 {
-				reg = <0x1>;
-				label = "lan9";
-				phy-handle = <&switch1phy1>;
-			};
-
-			port@2 {
-				reg = <0x2>;
-				label = "lan10";
-				phy-handle = <&switch1phy2>;
-			};
-
-			port@3 {
-				reg = <0x3>;
-				label = "lan11";
-				phy-handle = <&switch1phy3>;
-			};
-
-			port@4 {
-				reg = <0x4>;
-				label = "lan12";
-				phy-handle = <&switch1phy4>;
-			};
-
-			port@5 {
-				reg = <0x5>;
-				label = "lan13";
-				phy-handle = <&switch1phy5>;
-			};
-
-			port@6 {
-				reg = <0x6>;
-				label = "lan14";
-				phy-handle = <&switch1phy6>;
-			};
-
-			port@7 {
-				reg = <0x7>;
-				label = "lan15";
-				phy-handle = <&switch1phy7>;
-			};
-
-			port@8 {
-				reg = <0x8>;
-				label = "lan16";
-				phy-handle = <&switch1phy8>;
-			};
-
-			switch1port9: port@9 {
-				reg = <0x9>;
-				label = "dsa";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				link = <&switch0port10>;
-			};
-
-			switch1port10: port@a {
-				reg = <0xa>;
-				label = "dsa";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				link = <&switch2port9>;
-				status = "disabled";
-			};
-
-			port-sfp@a {
-				reg = <0xa>;
-				label = "sfp";
-				sfp = <&sfp>;
-				phy-mode = "sgmii";
-				managed = "in-band-status";
-				status = "disabled";
-			};
-		};
-	};
-
-	switch1@2 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x2 0>;
-		dsa,member = <0 1>;
-		interrupt-parent = <&moxtet>;
-		interrupts = <MOXTET_IRQ_TOPAZ>;
-		status = "disabled";
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch1phy1_topaz: switch1phy1@11 {
-				reg = <0x11>;
-			};
-
-			switch1phy2_topaz: switch1phy2@12 {
-				reg = <0x12>;
-			};
-
-			switch1phy3_topaz: switch1phy3@13 {
-				reg = <0x13>;
-			};
-
-			switch1phy4_topaz: switch1phy4@14 {
-				reg = <0x14>;
-			};
-		};
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@1 {
-				reg = <0x1>;
-				label = "lan9";
-				phy-handle = <&switch1phy1_topaz>;
-			};
-
-			port@2 {
-				reg = <0x2>;
-				label = "lan10";
-				phy-handle = <&switch1phy2_topaz>;
-			};
-
-			port@3 {
-				reg = <0x3>;
-				label = "lan11";
-				phy-handle = <&switch1phy3_topaz>;
-			};
-
-			port@4 {
-				reg = <0x4>;
-				label = "lan12";
-				phy-handle = <&switch1phy4_topaz>;
-			};
-
-			port@5 {
-				reg = <0x5>;
-				label = "dsa";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				link = <&switch0port10>;
-			};
-		};
-	};
-
-	switch2@12 {
-		compatible = "marvell,mv88e6190";
-		reg = <0x12 0>;
-		dsa,member = <0 2>;
-		interrupt-parent = <&moxtet>;
-		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
-		status = "disabled";
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch2phy1: switch2phy1@1 {
-				reg = <0x1>;
-			};
-
-			switch2phy2: switch2phy2@2 {
-				reg = <0x2>;
-			};
-
-			switch2phy3: switch2phy3@3 {
-				reg = <0x3>;
-			};
-
-			switch2phy4: switch2phy4@4 {
-				reg = <0x4>;
-			};
-
-			switch2phy5: switch2phy5@5 {
-				reg = <0x5>;
-			};
-
-			switch2phy6: switch2phy6@6 {
-				reg = <0x6>;
-			};
-
-			switch2phy7: switch2phy7@7 {
-				reg = <0x7>;
-			};
-
-			switch2phy8: switch2phy8@8 {
-				reg = <0x8>;
-			};
-		};
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@1 {
-				reg = <0x1>;
-				label = "lan17";
-				phy-handle = <&switch2phy1>;
-			};
-
-			port@2 {
-				reg = <0x2>;
-				label = "lan18";
-				phy-handle = <&switch2phy2>;
-			};
-
-			port@3 {
-				reg = <0x3>;
-				label = "lan19";
-				phy-handle = <&switch2phy3>;
-			};
-
-			port@4 {
-				reg = <0x4>;
-				label = "lan20";
-				phy-handle = <&switch2phy4>;
-			};
-
-			port@5 {
-				reg = <0x5>;
-				label = "lan21";
-				phy-handle = <&switch2phy5>;
-			};
-
-			port@6 {
-				reg = <0x6>;
-				label = "lan22";
-				phy-handle = <&switch2phy6>;
-			};
-
-			port@7 {
-				reg = <0x7>;
-				label = "lan23";
-				phy-handle = <&switch2phy7>;
-			};
-
-			port@8 {
-				reg = <0x8>;
-				label = "lan24";
-				phy-handle = <&switch2phy8>;
-			};
-
-			switch2port9: port@9 {
-				reg = <0x9>;
-				label = "dsa";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				link = <&switch1port10 &switch0port10>;
-			};
-
-			port-sfp@a {
-				reg = <0xa>;
-				label = "sfp";
-				sfp = <&sfp>;
-				phy-mode = "sgmii";
-				managed = "in-band-status";
-				status = "disabled";
-			};
-		};
-	};
-
-	switch2@2 {
-		compatible = "marvell,mv88e6085";
-		reg = <0x2 0>;
-		dsa,member = <0 2>;
-		interrupt-parent = <&moxtet>;
-		interrupts = <MOXTET_IRQ_TOPAZ>;
-		status = "disabled";
-
-		mdio {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			switch2phy1_topaz: switch2phy1@11 {
-				reg = <0x11>;
-			};
-
-			switch2phy2_topaz: switch2phy2@12 {
-				reg = <0x12>;
-			};
-
-			switch2phy3_topaz: switch2phy3@13 {
-				reg = <0x13>;
-			};
-
-			switch2phy4_topaz: switch2phy4@14 {
-				reg = <0x14>;
-			};
-		};
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@1 {
-				reg = <0x1>;
-				label = "lan17";
-				phy-handle = <&switch2phy1_topaz>;
-			};
-
-			port@2 {
-				reg = <0x2>;
-				label = "lan18";
-				phy-handle = <&switch2phy2_topaz>;
-			};
-
-			port@3 {
-				reg = <0x3>;
-				label = "lan19";
-				phy-handle = <&switch2phy3_topaz>;
-			};
-
-			port@4 {
-				reg = <0x4>;
-				label = "lan20";
-				phy-handle = <&switch2phy4_topaz>;
-			};
-
-			port@5 {
-				reg = <0x5>;
-				label = "dsa";
-				phy-mode = "2500base-x";
-				managed = "in-band-status";
-				link = <&switch1port10 &switch0port10>;
-			};
-		};
-	};
+	pinctrl-0 = <&pcie_pins>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+	status = "disabled";
 };

arch/arm/dts/armada-3720-uDPU-u-boot.dtsi

@@ -28,6 +28,6 @@
 	};
 };
 
-&sdhci0 {
+&sdhci1 {
 	u-boot,dm-pre-reloc;
 };

arch/arm/dts/armada-3720-uDPU.dts

@@ -3,23 +3,30 @@
  * Device tree for the uDPU board.
  * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
  * Copyright (C) 2016 Marvell
- * Copyright (C) 2019 Methode Electronics
- * Copyright (C) 2019 Telus
+ * Copyright (C) 2018 Methode
+ * Copyright (C) 2018 Telus
  *
  * Vladimir Vid <vladimir.vid@sartura.hr>
  */
 
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include "armada-372x.dtsi"
+#include "armada-37xx.dtsi"
+#include "armada-3720-uDPU-u-boot.dtsi"
 
 / {
 	model = "Methode uDPU Board";
-	compatible = "methode,udpu", "marvell,armada3720";
+	compatible = "methode,udpu";
 
 	chosen {
 		stdout-path = "serial0:115200n8";
+		bootargs = "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000";
+	};
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		spi0 = &spi0;
 	};
 
 	memory@0 {
@@ -27,39 +34,56 @@
 		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
 	};
 
-	leds {
+	mdio: mdio@32004 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ethphy0: ethernet-phy@0 {
+			 reg = <0>;
+		};
+		ethphy1: ethernet-phy@1 {
+			reg = <1>;
+		};
+	};
+
+	scsi: scsi {
+		compatible = "marvell,mvebu-scsi";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		max-id = <1>;
+		max-lun = <1>;
+		status = "okay";
+	};
+
+	i2c1: i2c@11080 {
+		compatible = "marvell,armada-3700-i2c", "simple-bus";
+		reg = <0x0 0x11080 0x0 0x80>;
 		pinctrl-names = "default";
-		compatible = "gpio-leds";
+		pinctrl-0 = <&i2c2_pins>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		status = "okay";
+	};
 
-		power1 {
-			label = "udpu:green:power";
-			gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
-		};
+	uart1: serial@12200 {
+		compatible = "marvell,armada-3700-uart-ext";
+		reg = <0x0 0x12200 0x0 0x30>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2_pins>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		status = "okay";
+		#address-cells = <2>;
+		#size-cells = <2>;
+	};
 
-		power2 {
-			label = "udpu:red:power";
-			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
-		};
-
-		network1 {
-			label = "udpu:green:network";
-			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
-		};
-
-		network2 {
-			label = "udpu:red:network";
-			gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
-		};
-
-		alarm1 {
-			label = "udpu:green:alarm";
-			gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
-		};
-
-		alarm2 {
-			label = "udpu:red:alarm";
-			gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
-		};
+	vcc_sd_reg0: regulator@0 {
+		compatible = "regulator-gpio";
+		regulator-name = "vcc_sd0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-type = "voltage";
+		states = <1800000 0x1
+			3300000 0x0>;
+		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
 	};
 
 	sfp_eth0: sfp-eth0 {
@@ -69,29 +93,55 @@
 		mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 		tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
 		tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
 	};
 
 	sfp_eth1: sfp-eth1 {
 		compatible = "sff,sfp";
 		i2c-bus = <&i2c1>;
+		sfp,ethernet = <&eth1>;
 		los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
 		mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
 		tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
 		tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
-		maximum-power-milliwatt = <3000>;
 	};
 };
 
-&sdhci0 {
+&comphy {
+	phy0 {
+		phy-type = <COMPHY_TYPE_SGMII1>;
+		phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy1 {
+		phy-type = <COMPHY_TYPE_SGMII0>;
+		phy-speed = <COMPHY_SPEED_1_25G>;
+	};
+
+	phy2 {
+		phy-type = <COMPHY_TYPE_USB3_HOST1>;
+		phy-speed = <COMPHY_SPEED_5G>;
+	};
+};
+
+&eth0 {
+	pinctrl-0 = <&pcie_pins>;
 	status = "okay";
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	marvell,pad-type = "fixed-1-8v";
-	non-removable;
-	no-sd;
-	no-sdio;
+	phy-mode = "2500base-x";
+	managed = "in-band-status";
+	phy = <&ethphy0>;
+};
+
+&eth1 {
+	status = "okay";
+	phy-mode = "2500base-x";
+	managed = "in-band-status";
+	phy = <&ethphy1>;
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        status = "okay";
 };
 
 &spi0 {
@@ -99,90 +149,47 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_quad_pins>;
 
-	m25p80@0 {
-		compatible = "jedec,spi-nor";
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q1024a","n25q512a";
 		reg = <0>;
-		spi-max-frequency = <54000000>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		m25p,fast-read;
 
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			/* only bootloader is located on the SPI */
-			partition@0 {
-				label = "uboot";
-				reg = <0 0x400000>;
-			};
+		partition@0 {
+			label = "uboot";
+			reg = <0 0x400000>;
 		};
 	};
 };
 
-&pinctrl_nb {
-	i2c1_recovery_pins: i2c1-recovery-pins {
-		groups = "i2c1";
-		function = "gpio";
-	};
+&sdhci1 {
+	non-removable;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	bus-width = <4>;
+	vqmmc-supply = <&vcc_sd_reg0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio_pins>;
+	status = "okay";
 
-	i2c2_recovery_pins: i2c2-recovery-pins {
-		groups = "i2c2";
-		function = "gpio";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard@0 {
+		compatible = "mmc-card";
+		reg = <0>;
 	};
 };
 
-&i2c0 {
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
 	status = "okay";
-	pinctrl-names = "default", "recovery";
-	pinctrl-0 = <&i2c1_pins>;
-	pinctrl-1 = <&i2c1_recovery_pins>;
-	/delete-property/mrvl,i2c-fast-mode;
-	scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&i2c1 {
-	status = "okay";
-	pinctrl-names = "default", "recovery";
-	pinctrl-0 = <&i2c2_pins>;
-	pinctrl-1 = <&i2c2_recovery_pins>;
-	/delete-property/mrvl,i2c-fast-mode;
-	scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-	sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
-	lm75@48 {
-		status = "okay";
-		compatible = "lm75";
-		reg = <0x48>;
-	};
-
-	lm75@49 {
-		status = "okay";
-		compatible = "lm75";
-		reg = <0x49>;
-	};
-};
-
-&eth0 {
-	phy-mode = "sgmii";
-	status = "okay";
-	managed = "in-band-status";
-	phys = <&comphy1 0>;
-	sfp = <&sfp_eth0>;
-};
-
-&eth1 {
-	phy-mode = "sgmii";
-	status = "okay";
-	managed = "in-band-status";
-	phys = <&comphy0 1>;
-	sfp = <&sfp_eth1>;
 };
 
 &usb3 {
 	status = "okay";
-	phys = <&usb2_utmi_otg_phy>;
-	phy-names = "usb2-utmi-otg-phy";
-};
-
-&uart0 {
-	status = "okay";
 };

arch/arm/dts/armada-372x.dtsi

@@ -1,4 +1,3 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada 372x family of SoCs
  * (also named 88F3720)
@@ -7,6 +6,43 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include "armada-37xx.dtsi"
@@ -16,11 +52,10 @@
 	compatible = "marvell,armada3720", "marvell,armada3710";
 
 	cpus {
-		cpu1: cpu@1 {
+		cpu@1 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53";
+			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x1>;
-			clocks = <&nb_periph_clk 16>;
 			enable-method = "psci";
 		};
 	};

arch/arm/dts/armada-375.dtsi

@@ -384,10 +384,9 @@
 				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			systemc: system-controller@18200 {
+			system-controller@18200 {
 				compatible = "marvell,armada-375-system-controller";
 				reg = <0x18200 0x100>;
-				#reset-cells = <2>;
 			};
 
 			gateclk: clock-gating-control@18220 {
@@ -617,7 +616,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -636,7 +634,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 6>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 

arch/arm/dts/armada-37xx.dtsi

@@ -1,4 +1,3 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Device Tree Include file for Marvell Armada 37xx family of SoCs.
  *
@@ -6,9 +5,48 @@
  *
  * Gregory CLEMENT <gregory.clement@free-electrons.com>
  *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/comphy/comphy_data.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Marvell Armada 37xx SoC";
@@ -19,32 +57,15 @@
 
 	aliases {
 		serial0 = &uart0;
-		serial1 = &uart1;
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		/*
-		 * The PSCI firmware region depicted below is the default one
-		 * and should be updated by the bootloader.
-		 */
-		psci-area@4000000 {
-			reg = <0 0x4000000 0 0x200000>;
-			no-map;
-		};
 	};
 
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		cpu0: cpu@0 {
+		cpu@0 {
 			device_type = "cpu";
-			compatible = "arm,cortex-a53";
+			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0>;
-			clocks = <&nb_periph_clk 16>;
 			enable-method = "psci";
 		};
 	};
@@ -56,15 +77,14 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
 	soc {
@@ -73,123 +93,54 @@
 		#size-cells = <2>;
 		ranges;
 
-		internal-regs@d0000000 {
+		internal-regs {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "simple-bus";
 			/* 32M internal register @ 0xd000_0000 */
 			ranges = <0x0 0x0 0xd0000000 0x2000000>;
 
-			wdt: watchdog@8300 {
-				compatible = "marvell,armada-3700-wdt";
-				reg = <0x8300 0x40>;
-				marvell,system-controller = <&cpu_misc>;
-				clocks = <&xtalclk>;
-			};
-
-			cpu_misc: system-controller@d000 {
-				compatible = "marvell,armada-3700-cpu-misc",
-					     "syscon";
-				reg = <0xd000 0x1000>;
-			};
-
-			spi0: spi@10600 {
-				compatible = "marvell,armada-3700-spi";
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x10600 0xA00>;
-				clocks = <&nb_periph_clk 7>;
-				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-				num-cs = <4>;
-				status = "disabled";
-			};
-
-			i2c0: i2c@11000 {
-				compatible = "marvell,armada-3700-i2c";
-				reg = <0x11000 0x24>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&nb_periph_clk 10>;
-				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-				mrvl,i2c-fast-mode;
-				status = "disabled";
-			};
-
-			i2c1: i2c@11080 {
-				compatible = "marvell,armada-3700-i2c";
-				reg = <0x11080 0x24>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&nb_periph_clk 9>;
-				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-				mrvl,i2c-fast-mode;
-				status = "disabled";
-			};
-
-			avs: avs@11500 {
-				compatible = "marvell,armada-3700-avs",
-					     "syscon";
-				reg = <0x11500 0x40>;
-			};
-
 			uart0: serial@12000 {
 				compatible = "marvell,armada-3700-uart";
-				reg = <0x12000 0x18>;
-				clocks = <&xtalclk>;
-				interrupts =
-				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
+				reg = <0x12000 0x400>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
-			uart1: serial@12200 {
-				compatible = "marvell,armada-3700-uart-ext";
-				reg = <0x12200 0x30>;
-				clocks = <&xtalclk>;
-				interrupts =
-				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
-				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
-				interrupt-names = "uart-tx", "uart-rx";
-				status = "disabled";
+			wdt: watchdog-timer@8300 {
+				compatible = "marvell,armada-3700-wdt";
+				reg = <0xd064 0x4>,
+				      <0x8300 0x40>;
 			};
 
 			nb_periph_clk: nb-periph-clk@13000 {
-				compatible = "marvell,armada-3700-periph-clock-nb",
-					     "syscon";
+				compatible = "marvell,armada-3700-periph-clock-nb";
 				reg = <0x13000 0x100>;
-				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
-				<&tbg 3>, <&xtalclk>;
+				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
 				#clock-cells = <1>;
 			};
 
 			sb_periph_clk: sb-periph-clk@18000 {
 				compatible = "marvell,armada-3700-periph-clock-sb";
 				reg = <0x18000 0x100>;
-				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
-				<&tbg 3>, <&xtalclk>;
+				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
 				#clock-cells = <1>;
 			};
 
 			tbg: tbg@13200 {
 				compatible = "marvell,armada-3700-tbg-clock";
 				reg = <0x13200 0x100>;
-				clocks = <&xtalclk>;
 				#clock-cells = <1>;
 			};
 
-			pinctrl_nb: pinctrl@13800 {
+			pinctrl_nb: pinctrl-nb@13800 {
 				compatible = "marvell,armada3710-nb-pinctrl",
-					     "syscon", "simple-mfd";
+				"syscon", "simple-mfd";
 				reg = <0x13800 0x100>, <0x13C00 0x20>;
-				/* MPP1[19:0] */
-				gpionb: gpio {
+				gpionb: gpionb {
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_nb 0 0 36>;
 					gpio-controller;
-					interrupt-controller;
-					#interrupt-cells = <2>;
 					interrupts =
 					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
@@ -203,12 +154,7 @@
 					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
-				};
 
-				xtalclk: xtal-clk {
-					compatible = "marvell,armada-3700-xtal-clock";
-					clock-output-names = "xtal";
-					#clock-cells = <0>;
 				};
 
 				spi_quad_pins: spi-quad-pins {
@@ -216,11 +162,6 @@
 					function = "spi";
 				};
 
-				spi_cs1_pins: spi-cs1-pins {
-					groups = "spi_cs1";
-					function = "spi";
-				};
-
 				i2c1_pins: i2c1-pins {
 					groups = "i2c1";
 					function = "i2c";
@@ -247,54 +188,14 @@
 				};
 			};
 
-			nb_pm: syscon@14000 {
-				compatible = "marvell,armada-3700-nb-pm",
-					     "syscon";
-				reg = <0x14000 0x60>;
-			};
-
-			comphy: phy@18300 {
-				compatible = "marvell,comphy-a3700";
-				reg = <0x18300 0x300>,
-				      <0x1F000 0x400>,
-				      <0x5C000 0x400>,
-				      <0xe0178 0x8>;
-				reg-names = "comphy",
-					    "lane1_pcie_gbe",
-					    "lane0_usb3_gbe",
-					    "lane2_sata_usb3";
-				#address-cells = <1>;
-				#size-cells = <0>;
-				clocks = <&xtalclk>;
-				clock-names = "xtal";
-
-				comphy0: phy@0 {
-					reg = <0>;
-					#phy-cells = <1>;
-				};
-
-				comphy1: phy@1 {
-					reg = <1>;
-					#phy-cells = <1>;
-				};
-
-				comphy2: phy@2 {
-					reg = <2>;
-					#phy-cells = <1>;
-				};
-			};
-
-			pinctrl_sb: pinctrl@18800 {
+			pinctrl_sb: pinctrl-sb@18800 {
 				compatible = "marvell,armada3710-sb-pinctrl",
-					     "syscon", "simple-mfd";
+				"syscon", "simple-mfd";
 				reg = <0x18800 0x100>, <0x18C00 0x20>;
-				/* MPP2[23:0] */
-				gpiosb: gpio {
+				gpiosb: gpiosb {
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_sb 0 0 30>;
 					gpio-controller;
-					interrupt-controller;
-					#interrupt-cells = <2>;
 					interrupts =
 					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
@@ -318,92 +219,30 @@
 					function = "sdio";
 				};
 
-				pcie_reset_pins: pcie-reset-pins {
-					groups = "pcie1"; /* this actually controls "pcie1_reset" */
+				pcie_pins: pcie-pins {
+					groups = "pcie1";
 					function = "gpio";
 				};
-
-				pcie_clkreq_pins: pcie-clkreq-pins {
-					groups = "pcie1_clkreq";
-					function = "pcie";
-				};
-			};
-
-			eth0: ethernet@30000 {
-				   compatible = "marvell,armada-3700-neta";
-				   reg = <0x30000 0x4000>;
-				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-				   clocks = <&sb_periph_clk 8>;
-				   status = "disabled";
-			};
-
-			mdio: mdio@32004 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "marvell,orion-mdio";
-				reg = <0x32004 0x4>;
-			};
-
-			eth1: ethernet@40000 {
-				compatible = "marvell,armada-3700-neta";
-				reg = <0x40000 0x4000>;
-				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&sb_periph_clk 7>;
-				status = "disabled";
 			};
 
 			usb3: usb@58000 {
 				compatible = "marvell,armada3700-xhci",
 				"generic-xhci";
 				reg = <0x58000 0x4000>;
-				marvell,usb-misc-reg = <&usb32_syscon>;
-				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&sb_periph_clk 12>;
-				phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
-				phy-names = "usb3-phy", "usb2-utmi-otg-phy";
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 				status = "disabled";
 			};
 
-			usb2_utmi_otg_phy: phy@5d000 {
-				compatible = "marvell,a3700-utmi-otg-phy";
-				reg = <0x5d000 0x800>;
-				marvell,usb-misc-reg = <&usb32_syscon>;
-				#phy-cells = <0>;
-			};
-
-			usb32_syscon: system-controller@5d800 {
-				compatible = "marvell,armada-3700-usb2-host-device-misc",
-				"syscon";
-				reg = <0x5d800 0x800>;
-			};
-
 			usb2: usb@5e000 {
-				compatible = "marvell,armada-3700-ehci";
-				reg = <0x5e000 0x1000>;
-				marvell,usb-misc-reg = <&usb2_syscon>;
-				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb2_utmi_host_phy>;
-				phy-names = "usb2-utmi-host-phy";
+				compatible = "marvell,armada3700-ehci";
+				reg = <0x5e000 0x450>;
 				status = "disabled";
 			};
 
-			usb2_utmi_host_phy: phy@5f000 {
-				compatible = "marvell,a3700-utmi-host-phy";
-				reg = <0x5f000 0x800>;
-				marvell,usb-misc-reg = <&usb2_syscon>;
-				#phy-cells = <0>;
-			};
-
-			usb2_syscon: system-controller@5f800 {
-				compatible = "marvell,armada-3700-usb2-host-misc",
-				"syscon";
-				reg = <0x5f800 0x800>;
-			};
-
 			xor@60900 {
 				compatible = "marvell,armada-3700-xor";
-				reg = <0x60900 0x100>,
-				      <0x60b00 0x100>;
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
 
 				xor10 {
 					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
@@ -413,56 +252,26 @@
 				};
 			};
 
-			crypto: crypto@90000 {
-				compatible = "inside-secure,safexcel-eip97ies";
-				reg = <0x90000 0x20000>;
-				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "mem", "ring0", "ring1",
-						  "ring2", "ring3", "eip";
-				clocks = <&nb_periph_clk 15>;
-			};
-
-			rwtm: mailbox@b0000 {
-				compatible = "marvell,armada-3700-rwtm-mailbox";
-				reg = <0xb0000 0x100>;
-				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-				#mbox-cells = <1>;
-			};
-
-			sdhci1: sdhci@d0000 {
+			sdhci0: sdhci@d0000 {
 				compatible = "marvell,armada-3700-sdhci",
-					     "marvell,sdhci-xenon";
-				reg = <0xd0000 0x300>,
-				      <0x1e808 0x4>;
-				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&nb_periph_clk 0>;
-				clock-names = "core";
+				"marvell,sdhci-xenon";
+				reg = <0xd0000 0x300
+				       0x1e808 0x4>;
 				status = "disabled";
 			};
 
-			sdhci0: sdhci@d8000 {
+			sdhci1: sdhci@d8000 {
 				compatible = "marvell,armada-3700-sdhci",
-					     "marvell,sdhci-xenon";
-				reg = <0xd8000 0x300>,
-				      <0x17808 0x4>;
-				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&nb_periph_clk 0>;
-				clock-names = "core";
+				"marvell,sdhci-xenon";
+				reg = <0xd8000 0x300
+				       0x17808 0x4>;
 				status = "disabled";
 			};
 
 			sata: sata@e0000 {
 				compatible = "marvell,armada-3700-ahci";
-				reg = <0xe0000 0x178>;
+				reg = <0xe0000 0x2000>;
 				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&nb_periph_clk 1>;
-				phys = <&comphy2 0>;
-				phy-names = "sata-phy";
 				status = "disabled";
 			};
 
@@ -471,26 +280,58 @@
 				#interrupt-cells = <3>;
 				interrupt-controller;
 				reg = <0x1d00000 0x10000>, /* GICD */
-				      <0x1d40000 0x40000>, /* GICR */
-				      <0x1d80000 0x2000>,  /* GICC */
-				      <0x1d90000 0x2000>,  /* GICH */
-				      <0x1da0000 0x20000>; /* GICV */
-				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				      <0x1d40000 0x40000>; /* GICR */
+			};
+
+			eth0: neta@30000 {
+				compatible = "marvell,armada-3700-neta";
+				reg = <0x30000 0x20>;
+				status = "disabled";
+			};
+
+			eth1: neta@40000 {
+				compatible = "marvell,armada-3700-neta";
+				reg = <0x40000 0x20>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@11000 {
+				compatible = "marvell,armada-3700-i2c";
+				reg = <0x11000 0x100>;
+				status = "disabled";
+			};
+
+			spi0: spi@10600 {
+				compatible = "marvell,armada-3700-spi";
+				reg = <0x10600 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <0>;
+				spi-max-frequency = <50000000>;
+				clocks = <&nb_periph_clk 7>;
+				status = "disabled";
+			};
+
+			comphy: comphy@18300 {
+				compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
+				reg = <0x18300 0x28>,
+				      <0x1f300 0x3d000>;
+				mux-bitcount = <4>;
+				mux-lane-order = <1 0 2>;
+				max-lanes = <3>;
 			};
 		};
 
 		pcie0: pcie@d0070000 {
 			compatible = "marvell,armada-3700-pcie";
-			device_type = "pci";
-			status = "disabled";
 			reg = <0 0xd0070000 0 0x20000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-			bus-range = <0x00 0xff>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			#interrupt-cells = <1>;
-			msi-parent = <&pcie0>;
-			msi-controller;
+			device_type = "pci";
+			num-lanes = <1>;
+			status = "disabled";
+
+			bus-range = <0 0xff>;
 			/*
 			 * The 128 MiB address range [0xe8000000-0xf0000000] is
 			 * dedicated for PCIe and can be assigned to 8 windows
@@ -498,27 +339,10 @@
 			 * IO at the end and the remaining seven windows
 			 * (totaling 127 MiB) for MEM.
 			 */
-			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
-				  0x81000000 0 0x00000000   0 0xeff00000   0 0x00100000>; /* Port 0 IO */
-			interrupt-map-mask = <0 0 0 7>;
-			interrupt-map = <0 0 0 1 &pcie_intc 0>,
-					<0 0 0 2 &pcie_intc 1>,
-					<0 0 0 3 &pcie_intc 2>,
-					<0 0 0 4 &pcie_intc 3>;
-			max-link-speed = <2>;
-			phys = <&comphy1 0>;
-			pcie_intc: interrupt-controller {
-				interrupt-controller;
-				#interrupt-cells = <1>;
-			};
-		};
-	};
-
-	firmware {
-		armada-3700-rwtm {
-			compatible = "marvell,armada-3700-rwtm-firmware";
-			mboxes = <&rwtm 0>;
-			status = "okay";
+			ranges = <0x82000000 0 0xe8000000
+				 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
+				 0x81000000 0 0xeff00000
+				 0 0xeff00000 0 0x100000>; /* Port 0 IO*/
 		};
 	};
 };

arch/arm/dts/armada-380.dtsi

@@ -73,7 +73,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 8>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -93,7 +92,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -113,7 +111,6 @@
 				marvell,pcie-port = <2>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 6>;
-				resets = <&systemc 0 2>;
 				status = "disabled";
 			};
 		};

arch/arm/dts/armada-385.dtsi

@@ -78,7 +78,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 8>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -98,7 +97,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -118,7 +116,6 @@
 				marvell,pcie-port = <2>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 6>;
-				resets = <&systemc 0 2>;
 				status = "disabled";
 			};
 
@@ -141,7 +138,6 @@
 				marvell,pcie-port = <3>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 7>;
-				resets = <&systemc 0 3>;
 				status = "disabled";
 			};
 		};

arch/arm/dts/armada-38x.dtsi

@@ -328,7 +328,6 @@
 				compatible = "marvell,armada-380-system-controller",
 					     "marvell,armada-370-xp-system-controller";
 				reg = <0x18200 0x100>;
-				#reset-cells = <2>;
 			};
 
 			gateclk: clock-gating-control@18220 {

arch/arm/dts/armada-cp110.dtsi

@@ -231,7 +231,7 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				clocks = <&CP110_LABEL(syscon0) 1 2>;
-				marvell,nand-enable-arbiter;
+				nand-enable-arbiter;
 				num-cs = <1>;
 				nand-ecc-strength = <8>;
 				nand-ecc-step-size = <512>;

arch/arm/dts/armada-xp-98dx3236.dtsi

@@ -85,7 +85,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 		};
@@ -137,7 +136,6 @@
 			systemc: system-controller@18200 {
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0x18200 0x500>;
-				#reset-cells = <2>;
 			};
 
 			gateclk: clock-gating-control@18220 {

arch/arm/dts/armada-xp-mv78230.dtsi

@@ -92,7 +92,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -111,7 +110,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 6>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -130,7 +128,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <2>;
 				clocks = <&gateclk 7>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -149,7 +146,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <3>;
 				clocks = <&gateclk 8>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -168,7 +164,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 9>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 		};

arch/arm/dts/armada-xp-mv78260.dtsi

@@ -107,7 +107,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -126,7 +125,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 6>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -145,7 +143,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <2>;
 				clocks = <&gateclk 7>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -164,7 +161,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <3>;
 				clocks = <&gateclk 8>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -183,7 +179,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 9>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -202,7 +197,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 10>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -221,7 +215,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <2>;
 				clocks = <&gateclk 11>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -240,7 +233,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <3>;
 				clocks = <&gateclk 12>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -259,7 +251,6 @@
 				marvell,pcie-port = <2>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 26>;
-				resets = <&systemc 0 2>;
 				status = "disabled";
 			};
 		};

arch/arm/dts/armada-xp-mv78460.dtsi

@@ -128,7 +128,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 5>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -147,7 +146,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 6>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -166,7 +164,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <2>;
 				clocks = <&gateclk 7>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -185,7 +182,6 @@
 				marvell,pcie-port = <0>;
 				marvell,pcie-lane = <3>;
 				clocks = <&gateclk 8>;
-				resets = <&systemc 0 0>;
 				status = "disabled";
 			};
 
@@ -204,7 +200,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 9>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -223,7 +218,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <1>;
 				clocks = <&gateclk 10>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -242,7 +236,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <2>;
 				clocks = <&gateclk 11>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -261,7 +254,6 @@
 				marvell,pcie-port = <1>;
 				marvell,pcie-lane = <3>;
 				clocks = <&gateclk 12>;
-				resets = <&systemc 0 1>;
 				status = "disabled";
 			};
 
@@ -280,7 +272,6 @@
 				marvell,pcie-port = <2>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 26>;
-				resets = <&systemc 0 2>;
 				status = "disabled";
 			};
 
@@ -299,7 +290,6 @@
 				marvell,pcie-port = <3>;
 				marvell,pcie-lane = <0>;
 				clocks = <&gateclk 27>;
-				resets = <&systemc 0 3>;
 				status = "disabled";
 			};
 		};

arch/arm/dts/armada-xp-synology-ds414.dts

@@ -187,7 +187,6 @@
 	pcie@1,0 {
 		/* Port 0, Lane 0 */
 		status = "okay";
-		num-lanes = <4>;
 	};
 
 	/*

arch/arm/dts/armada-xp-theadorable.dts

@@ -71,8 +71,6 @@
 		spi0 = &spi0;
 		spi1 = &spi1;
 		ethernet0 = &eth0;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
 	};
 
 	memory {
@@ -158,16 +156,6 @@
 	};
 };
 
-&i2c0 {
-	status = "okay";
-	clock-frequency = <100000>;
-};
-
-&i2c1 {
-	status = "okay";
-	clock-frequency = <100000>;
-};
-
 &spi0 {
 	status = "okay";
 	u-boot,dm-pre-reloc;
@@ -214,6 +202,5 @@
 	pcie@9,0 {
 		/* Port 2, Lane 0 */
 		status = "okay";
-		num-lanes = <4>;
 	};
 };

arch/arm/dts/armada-xp.dtsi

@@ -78,7 +78,6 @@
 			systemc: system-controller@18200 {
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0x18200 0x500>;
-				#reset-cells = <2>;
 			};
 
 			gateclk: clock-gating-control@18220 {

arch/arm/dts/ast2600-evb.dts

@@ -163,74 +163,6 @@
 	pinctrl-0 = <&pinctrl_i2c9_default>;
 };
 
-&mdio0 {
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
-};
-
-&mdio1 {
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	ethphy1: ethernet-phy@0 {
-		reg = <0>;
-	};
-};
-
-&mdio2 {
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	ethphy2: ethernet-phy@0 {
-		reg = <0>;
-	};
-};
-
-&mdio3 {
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	ethphy3: ethernet-phy@0 {
-		reg = <0>;
-	};
-};
-
-&mac0 {
-	status = "okay";
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&ethphy0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rgmii1_default>;
-};
-
-&mac1 {
-	status = "okay";
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&ethphy1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rgmii2_default>;
-};
-
-&mac2 {
-	status = "okay";
-	phy-mode = "rgmii";
-	phy-handle = <&ethphy2>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rgmii3_default>;
-};
-
-&mac3 {
-	status = "okay";
-	phy-mode = "rgmii";
-	phy-handle = <&ethphy3>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rgmii4_default>;
-};
-
 &scu {
 	mac0-clk-delay = <0x1d 0x1c
 			  0x10 0x17
@@ -245,13 +177,3 @@
 			  0x08 0x04
 			  0x08 0x04>;
 };
-
-&hace {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};
-
-&acry {
-	u-boot,dm-pre-reloc;
-	status = "okay";
-};

arch/arm/dts/ast2600.dtsi

@@ -187,70 +187,17 @@
 			};
 		};
 
-		hace: hace@1e6d0000 {
-			compatible = "aspeed,ast2600-hace";
-			reg = <0x1e6d0000 0x200>;
-			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&scu ASPEED_CLK_GATE_YCLK>;
-			status = "disabled";
-		};
-
-		acry: acry@1e6fa000 {
-			compatible = "aspeed,ast2600-acry";
-			reg = <0x1e6fa000 0x1000>,
-			      <0x1e710000 0x10000>;
-			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
-			status = "disabled";
-		};
-
 		edac: sdram@1e6e0000 {
 			compatible = "aspeed,ast2600-sdram-edac";
 			reg = <0x1e6e0000 0x174>;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		mdio: bus@1e650000 {
-			compatible = "simple-bus";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x1e650000 0x100>;
-
-			mdio0: mdio@0 {
-				compatible = "aspeed,ast2600-mdio";
-				reg = <0 0x8>;
-				resets = <&rst ASPEED_RESET_MII>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_mdio1_default>;
-				status = "disabled";
-			};
-
-			mdio1: mdio@8 {
-				compatible = "aspeed,ast2600-mdio";
-				reg = <0x8 0x8>;
-				resets = <&rst ASPEED_RESET_MII>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_mdio2_default>;
-				status = "disabled";
-			};
-
-			mdio2: mdio@10 {
-				compatible = "aspeed,ast2600-mdio";
-				reg = <0x10 0x8>;
-				resets = <&rst ASPEED_RESET_MII>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_mdio3_default>;
-				status = "disabled";
-			};
-
-			mdio3: mdio@18 {
-				compatible = "aspeed,ast2600-mdio";
-				reg = <0x18 0x8>;
-				resets = <&rst ASPEED_RESET_MII>;
-				pinctrl-names = "default";
-				pinctrl-0 = <&pinctrl_mdio4_default>;
-				status = "disabled";
-			};
+		mdio: ethernet@1e650000 {
+			compatible = "aspeed,aspeed-mdio";
+			reg = <0x1e650000 0x40>;
+			resets = <&rst ASPEED_RESET_MII>;
+			status = "disabled";
 		};
 
 		mac0: ftgmac@1e660000 {

arch/arm/dts/bcm2711-rpi-4-b.dts

@@ -1,262 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
-#include "bcm2711.dtsi"
-#include "bcm2711-rpi.dtsi"
-#include "bcm283x-rpi-usb-peripheral.dtsi"
-
-/ {
-	compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
-	model = "Raspberry Pi 4 Model B";
-
-	chosen {
-		/* 8250 auxiliary UART instead of pl011 */
-		stdout-path = "serial1:115200n8";
-	};
-
-	leds {
-		led-act {
-			gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
-		};
-
-		led-pwr {
-			label = "PWR";
-			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
-			default-state = "keep";
-			linux,default-trigger = "default-on";
-		};
-	};
-
-	wifi_pwrseq: wifi-pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
-	};
-
-	sd_io_1v8_reg: sd_io_1v8_reg {
-		compatible = "regulator-gpio";
-		regulator-name = "vdd-sd-io";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		regulator-always-on;
-		regulator-settling-time-us = <5000>;
-		gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
-		states = <1800000 0x1>,
-			 <3300000 0x0>;
-		status = "okay";
-	};
-
-	sd_vcc_reg: sd_vcc_reg {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc-sd";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-boot-on;
-		enable-active-high;
-		gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-&ddc0 {
-	status = "okay";
-};
-
-&ddc1 {
-	status = "okay";
-};
-
-&expgpio {
-	gpio-line-names = "BT_ON",
-			  "WL_ON",
-			  "PWR_LED_OFF",
-			  "GLOBAL_RESET",
-			  "VDD_SD_IO_SEL",
-			  "CAM_GPIO",
-			  "SD_PWR_ON",
-			  "";
-};
-
-&gpio {
-	/*
-	 * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
-	 * the official GPU firmware DT blob.
-	 *
-	 * Legend:
-	 * "FOO" = GPIO line named "FOO" on the schematic
-	 * "FOO_N" = GPIO line named "FOO" on schematic, active low
-	 */
-	gpio-line-names = "ID_SDA",
-			  "ID_SCL",
-			  "SDA1",
-			  "SCL1",
-			  "GPIO_GCLK",
-			  "GPIO5",
-			  "GPIO6",
-			  "SPI_CE1_N",
-			  "SPI_CE0_N",
-			  "SPI_MISO",
-			  "SPI_MOSI",
-			  "SPI_SCLK",
-			  "GPIO12",
-			  "GPIO13",
-			  /* Serial port */
-			  "TXD1",
-			  "RXD1",
-			  "GPIO16",
-			  "GPIO17",
-			  "GPIO18",
-			  "GPIO19",
-			  "GPIO20",
-			  "GPIO21",
-			  "GPIO22",
-			  "GPIO23",
-			  "GPIO24",
-			  "GPIO25",
-			  "GPIO26",
-			  "GPIO27",
-			  "RGMII_MDIO",
-			  "RGMIO_MDC",
-			  /* Used by BT module */
-			  "CTS0",
-			  "RTS0",
-			  "TXD0",
-			  "RXD0",
-			  /* Used by Wifi */
-			  "SD1_CLK",
-			  "SD1_CMD",
-			  "SD1_DATA0",
-			  "SD1_DATA1",
-			  "SD1_DATA2",
-			  "SD1_DATA3",
-			  /* Shared with SPI flash */
-			  "PWM0_MISO",
-			  "PWM1_MOSI",
-			  "STATUS_LED_G_CLK",
-			  "SPIFLASH_CE_N",
-			  "SDA0",
-			  "SCL0",
-			  "RGMII_RXCLK",
-			  "RGMII_RXCTL",
-			  "RGMII_RXD0",
-			  "RGMII_RXD1",
-			  "RGMII_RXD2",
-			  "RGMII_RXD3",
-			  "RGMII_TXCLK",
-			  "RGMII_TXCTL",
-			  "RGMII_TXD0",
-			  "RGMII_TXD1",
-			  "RGMII_TXD2",
-			  "RGMII_TXD3";
-};
-
-&hdmi0 {
-	status = "okay";
-};
-
-&hdmi1 {
-	status = "okay";
-};
-
-&pixelvalve0 {
-	status = "okay";
-};
-
-&pixelvalve1 {
-	status = "okay";
-};
-
-&pixelvalve2 {
-	status = "okay";
-};
-
-&pixelvalve4 {
-	status = "okay";
-};
-
-&pwm1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
-	status = "okay";
-};
-
-/* SDHCI is used to control the SDIO for wireless */
-&sdhci {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_gpio34>;
-	bus-width = <4>;
-	non-removable;
-	mmc-pwrseq = <&wifi_pwrseq>;
-	status = "okay";
-
-	brcmf: wifi@1 {
-		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
-	};
-};
-
-/* EMMC2 is used to drive the SD card */
-&emmc2 {
-	vqmmc-supply = <&sd_io_1v8_reg>;
-	vmmc-supply = <&sd_vcc_reg>;
-	broken-cd;
-	status = "okay";
-};
-
-&genet {
-	phy-handle = <&phy1>;
-	phy-mode = "rgmii-rxid";
-	status = "okay";
-};
-
-&genet_mdio {
-	phy1: ethernet-phy@1 {
-		/* No PHY interrupt */
-		reg = <0x1>;
-	};
-};
-
-&pcie0 {
-	pci@0,0 {
-		device_type = "pci";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		ranges;
-
-		reg = <0 0 0 0 0>;
-
-		usb@0,0 {
-			reg = <0 0 0 0 0>;
-			resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
-		};
-	};
-};
-
-/* uart0 communicates with the BT module */
-&uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
-	uart-has-rtscts;
-	status = "okay";
-
-	bluetooth {
-		compatible = "brcm,bcm43438-bt";
-		max-speed = <2000000>;
-		shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
-	};
-};
-
-/* uart1 is mapped to the pin header */
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart1_gpio14>;
-	status = "okay";
-};
-
-&vc4 {
-	status = "okay";
-};
-
-&vec {
-	status = "disabled";
-};

arch/arm/dts/bcm2711-rpi.dtsi

@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include "bcm2835-rpi.dtsi"
-
-#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
-
-/ {
-	/* Will be filled by the bootloader */
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0 0>;
-	};
-
-	aliases {
-		emmc2bus = &emmc2bus;
-		ethernet0 = &genet;
-		pcie0 = &pcie0;
-		blconfig = &blconfig;
-	};
-};
-
-&firmware {
-	firmware_clocks: clocks {
-		compatible = "raspberrypi,firmware-clocks";
-		#clock-cells = <1>;
-	};
-
-	expgpio: gpio {
-		compatible = "raspberrypi,firmware-gpio";
-		gpio-controller;
-		#gpio-cells = <2>;
-		status = "okay";
-	};
-
-	reset: reset {
-		compatible = "raspberrypi,firmware-reset";
-		#reset-cells = <1>;
-	};
-};
-
-&hdmi0 {
-	clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
-	clock-names = "hdmi", "bvb", "audio", "cec";
-	wifi-2.4ghz-coexistence;
-};
-
-&hdmi1 {
-	clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
-	clock-names = "hdmi", "bvb", "audio", "cec";
-	wifi-2.4ghz-coexistence;
-};
-
-&hvs {
-	clocks = <&firmware_clocks 4>;
-};
-
-&rmem {
-	/*
-	 * RPi4's co-processor will copy the board's bootloader configuration
-	 * into memory for the OS to consume. It'll also update this node with
-	 * its placement information.
-	 */
-	blconfig: nvram@0 {
-		compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0x0 0x0 0x0>;
-		no-map;
-		status = "disabled";
-	};
-};
-
-&vchiq {
-	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-};

arch/arm/dts/bcm2835-common.dtsi

@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-/* This include file covers the common peripherals and configuration between
- * bcm2835, bcm2836 and bcm2837 implementations.
- */
-
-/ {
-	interrupt-parent = <&intc>;
-
-	soc {
-		dma: dma@7e007000 {
-			compatible = "brcm,bcm2835-dma";
-			reg = <0x7e007000 0xf00>;
-			interrupts = <1 16>,
-				     <1 17>,
-				     <1 18>,
-				     <1 19>,
-				     <1 20>,
-				     <1 21>,
-				     <1 22>,
-				     <1 23>,
-				     <1 24>,
-				     <1 25>,
-				     <1 26>,
-				     /* dma channel 11-14 share one irq */
-				     <1 27>,
-				     <1 27>,
-				     <1 27>,
-				     <1 27>,
-				     /* unused shared irq for all channels */
-				     <1 28>;
-			interrupt-names = "dma0",
-					  "dma1",
-					  "dma2",
-					  "dma3",
-					  "dma4",
-					  "dma5",
-					  "dma6",
-					  "dma7",
-					  "dma8",
-					  "dma9",
-					  "dma10",
-					  "dma11",
-					  "dma12",
-					  "dma13",
-					  "dma14",
-					  "dma-shared-all";
-			#dma-cells = <1>;
-			brcm,dma-channel-mask = <0x7f35>;
-		};
-
-		intc: interrupt-controller@7e00b200 {
-			compatible = "brcm,bcm2835-armctrl-ic";
-			reg = <0x7e00b200 0x200>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		pm: watchdog@7e100000 {
-			compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
-			#power-domain-cells = <1>;
-			#reset-cells = <1>;
-			reg = <0x7e100000 0x114>,
-			      <0x7e00a000 0x24>;
-			clocks = <&clocks BCM2835_CLOCK_V3D>,
-				 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
-				 <&clocks BCM2835_CLOCK_H264>,
-				 <&clocks BCM2835_CLOCK_ISP>;
-			clock-names = "v3d", "peri_image", "h264", "isp";
-			system-power-controller;
-		};
-
-		rng@7e104000 {
-			compatible = "brcm,bcm2835-rng";
-			reg = <0x7e104000 0x10>;
-			interrupts = <2 29>;
-		};
-
-		pixelvalve@7e206000 {
-			compatible = "brcm,bcm2835-pixelvalve0";
-			reg = <0x7e206000 0x100>;
-			interrupts = <2 13>; /* pwa0 */
-		};
-
-		pixelvalve@7e207000 {
-			compatible = "brcm,bcm2835-pixelvalve1";
-			reg = <0x7e207000 0x100>;
-			interrupts = <2 14>; /* pwa1 */
-		};
-
-		thermal: thermal@7e212000 {
-			compatible = "brcm,bcm2835-thermal";
-			reg = <0x7e212000 0x8>;
-			clocks = <&clocks BCM2835_CLOCK_TSENS>;
-			#thermal-sensor-cells = <0>;
-			status = "disabled";
-		};
-
-		i2c2: i2c@7e805000 {
-			compatible = "brcm,bcm2835-i2c";
-			reg = <0x7e805000 0x1000>;
-			interrupts = <2 21>;
-			clocks = <&clocks BCM2835_CLOCK_VPU>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "okay";
-		};
-
-		vec: vec@7e806000 {
-			compatible = "brcm,bcm2835-vec";
-			reg = <0x7e806000 0x1000>;
-			clocks = <&clocks BCM2835_CLOCK_VEC>;
-			interrupts = <2 27>;
-			status = "disabled";
-		};
-
-		pixelvalve@7e807000 {
-			compatible = "brcm,bcm2835-pixelvalve2";
-			reg = <0x7e807000 0x100>;
-			interrupts = <2 10>; /* pixelvalve */
-		};
-
-		hdmi: hdmi@7e902000 {
-			compatible = "brcm,bcm2835-hdmi";
-			reg = <0x7e902000 0x600>,
-			      <0x7e808000 0x100>;
-			interrupts = <2 8>, <2 9>;
-			ddc = <&i2c2>;
-			clocks = <&clocks BCM2835_PLLH_PIX>,
-				 <&clocks BCM2835_CLOCK_HSM>;
-			clock-names = "pixel", "hdmi";
-			dmas = <&dma 17>;
-			dma-names = "audio-rx";
-			status = "disabled";
-		};
-
-		v3d: v3d@7ec00000 {
-			compatible = "brcm,bcm2835-v3d";
-			reg = <0x7ec00000 0x1000>;
-			interrupts = <1 10>;
-		};
-
-		vc4: gpu {
-			compatible = "brcm,bcm2835-vc4";
-		};
-	};
-};
-
-&cpu_thermal {
-	thermal-sensors = <&thermal>;
-};
-
-&gpio {
-	i2c_slave_gpio18: i2c_slave_gpio18 {
-		brcm,pins = <18 19 20 21>;
-		brcm,function = <BCM2835_FSEL_ALT3>;
-	};
-
-	jtag_gpio4: jtag_gpio4 {
-		brcm,pins = <4 5 6 12 13>;
-		brcm,function = <BCM2835_FSEL_ALT5>;
-	};
-
-	pwm0_gpio12: pwm0_gpio12 {
-		brcm,pins = <12>;
-		brcm,function = <BCM2835_FSEL_ALT0>;
-	};
-	pwm0_gpio18: pwm0_gpio18 {
-		brcm,pins = <18>;
-		brcm,function = <BCM2835_FSEL_ALT5>;
-	};
-	pwm0_gpio40: pwm0_gpio40 {
-		brcm,pins = <40>;
-		brcm,function = <BCM2835_FSEL_ALT0>;
-	};
-	pwm1_gpio13: pwm1_gpio13 {
-		brcm,pins = <13>;
-		brcm,function = <BCM2835_FSEL_ALT0>;
-	};
-	pwm1_gpio19: pwm1_gpio19 {
-		brcm,pins = <19>;
-		brcm,function = <BCM2835_FSEL_ALT5>;
-	};
-	pwm1_gpio41: pwm1_gpio41 {
-		brcm,pins = <41>;
-		brcm,function = <BCM2835_FSEL_ALT0>;
-	};
-	pwm1_gpio45: pwm1_gpio45 {
-		brcm,pins = <45>;
-		brcm,function = <BCM2835_FSEL_ALT0>;
-	};
-};
-
-&i2s {
-	dmas = <&dma 2>, <&dma 3>;
-	dma-names = "tx", "rx";
-};
-
-&sdhost {
-	dmas = <&dma 13>;
-	dma-names = "rx-tx";
-};
-
-&spi {
-	dmas = <&dma 6>, <&dma 7>;
-	dma-names = "tx", "rx";
-};

arch/arm/dts/bcm2835-rpi-a-plus.dts

@@ -8,17 +8,12 @@
 	compatible = "raspberrypi,model-a-plus", "brcm,bcm2835";
 	model = "Raspberry Pi Model A+";
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x10000000>;
-	};
-
 	leds {
-		led-act {
+		act {
 			gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
 		};
 
-		led-pwr {
+		pwr {
 			label = "PWR";
 			gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
@@ -104,8 +99,6 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
 };
 
 &pwm {
@@ -114,13 +107,6 @@
 	status = "okay";
 };
 
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
-};
-
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_gpio14>;

arch/arm/dts/bcm2835-rpi-a.dts

@@ -8,13 +8,8 @@
 	compatible = "raspberrypi,model-a", "brcm,bcm2835";
 	model = "Raspberry Pi Model A";
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x10000000>;
-	};
-
 	leds {
-		led-act {
+		act {
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -99,8 +94,6 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
 };
 
 &pwm {
@@ -109,13 +102,6 @@
 	status = "okay";
 };
 
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
-};
-
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_gpio14>;

arch/arm/dts/bcm2835-rpi-b-plus.dts

@@ -9,17 +9,12 @@
 	compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
 	model = "Raspberry Pi Model B+";
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x20000000>;
-	};
-
 	leds {
-		led-act {
+		act {
 			gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
 		};
 
-		led-pwr {
+		pwr {
 			label = "PWR";
 			gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
 			default-state = "keep";
@@ -106,8 +101,6 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
 };
 
 &pwm {
@@ -116,13 +109,6 @@
 	status = "okay";
 };
 
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
-};
-
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_gpio14>;

arch/arm/dts/bcm2835-rpi-b-rev2.dts

@@ -9,13 +9,8 @@
 	compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
 	model = "Raspberry Pi Model B rev2";
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x10000000>;
-	};
-
 	leds {
-		led-act {
+		act {
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -99,8 +94,6 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
 };
 
 &pwm {
@@ -109,13 +102,6 @@
 	status = "okay";
 };
 
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
-};
-
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_gpio14>;

arch/arm/dts/bcm2835-rpi-b.dts

@@ -9,13 +9,8 @@
 	compatible = "raspberrypi,model-b", "brcm,bcm2835";
 	model = "Raspberry Pi Model B";
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x10000000>;
-	};
-
 	leds {
-		led-act {
+		act {
 			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
 		};
 	};
@@ -94,8 +89,6 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
 };
 
 &pwm {
@@ -104,13 +97,6 @@
 	status = "okay";
 };
 
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
-};
-
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_gpio14>;

arch/arm/dts/bcm2835-rpi-cm1-io1.dts

@@ -79,15 +79,6 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
-};
-
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
 };
 
 &uart0 {

arch/arm/dts/bcm2835-rpi-cm1.dtsi

@@ -5,16 +5,11 @@
 
 / {
 	leds {
-		led-act {
+		act {
 			gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
 		};
 	};
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x20000000>;
-	};
-
 	reg_3v3: fixed-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "3V3";

arch/arm/dts/bcm2835-rpi-common.dtsi

@@ -1,12 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * This include file covers the common peripherals and configuration between
- * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's
- * firmware interface.
- */
-
-#include <dt-bindings/power/raspberrypi-power.h>
-
-&v3d {
-	power-domains = <&power RPI_POWER_DOMAIN_V3D>;
-};

arch/arm/dts/bcm2835-rpi-zero-w.dts

@@ -12,19 +12,14 @@
 	compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
 	model = "Raspberry Pi Zero W";
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x20000000>;
-	};
-
 	chosen {
 		/* 8250 auxiliary UART instead of pl011 */
 		stdout-path = "serial1:115200n8";
 	};
 
 	leds {
-		led-act {
-			gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
+		act {
+			gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -105,16 +100,12 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
 };
 
 &sdhci {
 	#address-cells = <1>;
 	#size-cells = <0>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
-	bus-width = <4>;
 	mmc-pwrseq = <&wifi_pwrseq>;
 	non-removable;
 	status = "okay";
@@ -125,13 +116,6 @@
 	};
 };
 
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
-};
-
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;

arch/arm/dts/bcm2835-rpi-zero.dts

@@ -12,13 +12,8 @@
 	compatible = "raspberrypi,model-zero", "brcm,bcm2835";
 	model = "Raspberry Pi Zero";
 
-	memory@0 {
-		device_type = "memory";
-		reg = <0 0x20000000>;
-	};
-
 	leds {
-		led-act {
+		act {
 			gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
 		};
 	};
@@ -101,15 +96,6 @@
 
 &hdmi {
 	hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
-	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
-	status = "okay";
-};
-
-&sdhost {
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdhost_gpio48>;
-	bus-width = <4>;
-	status = "okay";
 };
 
 &uart0 {

arch/arm/dts/bcm2835-rpi.dtsi

@@ -1,10 +1,15 @@
 #include <dt-bindings/power/raspberrypi-power.h>
 
 / {
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0x10000000>;
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
-		led-act {
+		act {
 			label = "ACT";
 			default-state = "keep";
 			linux,default-trigger = "heartbeat";
@@ -13,12 +18,8 @@
 
 	soc {
 		firmware: firmware {
-			compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
+			compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
 			mboxes = <&mailbox>;
-			dma-ranges;
 		};
 
 		power: power {
@@ -63,10 +64,32 @@
 	clock-frequency = <100000>;
 };
 
+&i2c2 {
+	status = "okay";
+};
+
+&sdhci {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_gpio48>;
+	bus-width = <4>;
+};
+
+&sdhost {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdhost_gpio48>;
+	status = "okay";
+	bus-width = <4>;
+};
+
 &usb {
 	power-domains = <&power RPI_POWER_DOMAIN_USB>;
 };
 
+&hdmi {
+	power-domains = <&power RPI_POWER_DOMAIN_HDMI>;
+	status = "okay";
+};
+
 &vec {
 	power-domains = <&power RPI_POWER_DOMAIN_VEC>;
 	status = "okay";

arch/arm/dts/bcm2835.dtsi

@@ -1,7 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
 #include "bcm283x.dtsi"
-#include "bcm2835-common.dtsi"
-#include "bcm2835-rpi-common.dtsi"
 
 / {
 	compatible = "brcm,bcm2835";