pytest: Fix squashfs tests not checking for directory exists

It is possible that we will have our "sqfs_src" directory already existing, and not be in an error condition. Don't try and make the directory again. Signed-off-by: Tom Rini <trini@konsulko.com>
Azure/GitLab: Ensure we use requirements.txt for testsuites
2021-02-25 14:28:10 -05:00 · 2021-02-25 13:47:36 -05:00 · 2021-02-25 13:22:43 -05:00 · 2021-02-25 13:20:07 -05:00
5896 changed files with 178855 additions and 412652 deletions
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -2,7 +2,7 @@ variables:
  windows_vm: vs2017-win2016
  ubuntu_vm: ubuntu-18.04
  macos_vm: macOS-10.15
-  ci_runner_image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
+  ci_runner_image: trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020
  # Add '-u 0' options for Azure pipelines, otherwise we get "permission
  # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
  # since our $(ci_runner_image) user is not root.
@@ -16,14 +16,14 @@ jobs:
      vmImage: $(windows_vm)
    steps:
      - powershell: |
-          (New-Object Net.WebClient).DownloadFile("https://github.com/msys2/msys2-installer/releases/download/2021-06-04/msys2-base-x86_64-20210604.sfx.exe", "sfx.exe")
+          (New-Object Net.WebClient).DownloadFile("https://github.com/msys2/msys2-installer/releases/download/2020-07-20/msys2-base-x86_64-20200720.sfx.exe", "sfx.exe")
        displayName: 'Install MSYS2'
      - script: |
          sfx.exe -y -o%CD:~0,2%\
          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu"
        displayName: 'Update MSYS2'
      - script: |
-          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel"
+          %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -S make gcc bison flex diffutils openssl-devel"
        displayName: 'Install Toolchain'
      - script: |
          echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh
@@ -148,7 +148,7 @@ jobs:
          export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
          export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
          export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
-          ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board sandbox_spl
+          ./tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl
          ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
          ./tools/buildman/buildman -t
          ./tools/dtoc/dtoc -t
@@ -183,18 +183,21 @@ jobs:
          TEST_PY_BD: "sandbox"
        sandbox_clang:
          TEST_PY_BD: "sandbox"
-          OVERRIDE: "-O clang-12"
+          OVERRIDE: "-O clang-10"
        sandbox_spl:
          TEST_PY_BD: "sandbox_spl"
          TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-        sandbox_noinst:
-          TEST_PY_BD: "sandbox_noinst"
-          TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
        sandbox_flattree:
          TEST_PY_BD: "sandbox_flattree"
        evb_ast2500:
          TEST_PY_BD: "evb-ast2500"
          TEST_PY_ID: "--id qemu"
+        vexpress_ca15_tc2:
+          TEST_PY_BD: "vexpress_ca15_tc2"
+          TEST_PY_ID: "--id qemu"
+        vexpress_ca9x4:
+          TEST_PY_BD: "vexpress_ca9x4"
+          TEST_PY_ID: "--id qemu"
        integratorcp_cm926ejs:
          TEST_PY_BD: "integratorcp_cm926ejs"
          TEST_PY_ID: "--id qemu"
@@ -205,6 +208,18 @@ jobs:
        qemu_arm64:
          TEST_PY_BD: "qemu_arm64"
          TEST_PY_TEST_SPEC: "not sleep"
+        qemu_mips:
+          TEST_PY_BD: "qemu_mips"
+          TEST_PY_TEST_SPEC: "not sleep"
+        qemu_mipsel:
+          TEST_PY_BD: "qemu_mipsel"
+          TEST_PY_TEST_SPEC: "not sleep"
+        qemu_mips64:
+          TEST_PY_BD: "qemu_mips64"
+          TEST_PY_TEST_SPEC: "not sleep"
+        qemu_mips64el:
+          TEST_PY_BD: "qemu_mips64el"
+          TEST_PY_TEST_SPEC: "not sleep"
        qemu_malta:
          TEST_PY_BD: "malta"
          TEST_PY_ID: "--id qemu"
@@ -280,18 +295,18 @@ jobs:
          cat << "EOF" >> test.sh
          # the below corresponds to .gitlab-ci.yml "before_script"
          cd ${WORK_DIR}
-          git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+          git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
          ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
          ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
          grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
          grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
          if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+              wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ;
+              export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
          fi
          if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
-              wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-              export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+              wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ;
+              export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
          fi
          # the below corresponds to .gitlab-ci.yml "script"
          cd ${WORK_DIR}
@@ -300,6 +315,7 @@ jobs:
          cp ~/grub_x86.efi ${UBOOT_TRAVIS_BUILD_DIR}/
          cp ~/grub_x64.efi ${UBOOT_TRAVIS_BUILD_DIR}/
          cp /opt/grub/grubriscv64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
+          cp /opt/grub/grubriscv32.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv32.efi
          cp /opt/grub/grubaa64.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
          cp /opt/grub/grubarm.efi ${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
          virtualenv -p /usr/bin/python3 /tmp/venv
@@ -317,22 +333,7 @@ jobs:
          # as sandbox testing need create files like spi flash images, etc.
          # (TODO: clean up this in the future)
          chmod 777 .
-          # Filesystem tests need extra docker args to run
-          set --
-          if [[ "${TEST_PY_BD}" == "sandbox" ]]; then
-              # mount -o loop needs the loop devices
-              if modprobe loop; then
-                  for d in $(find /dev -maxdepth 1 -name 'loop*'); do
-                      set -- "$@" --device $d:$d
-                  done
-              fi
-              # Needed for mount syscall (for guestmount as well)
-              set -- "$@" --cap-add SYS_ADMIN
-              # Default apparmor profile denies mounts
-              set -- "$@" --security-opt apparmor=unconfined
-          fi
-          # Some tests using libguestfs-tools need the fuse device to run
-          docker run "$@" --device /dev/fuse:/dev/fuse -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh
+          docker run -v $PWD:$(work_dir) $(ci_runner_image) /bin/bash $(work_dir)/test.sh

  - job: build_the_world
    displayName: 'Build the World'
@@ -347,7 +348,7 @@ jobs:
        arm11_arm7_arm920t_arm946es:
          BUILDMAN: "arm11 arm7 arm920t arm946es"
        arm926ejs:
-          BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,omap"
+          BUILDMAN: "arm926ejs -x freescale,siemens,at91,kirkwood,spear,omap"
        at91_non_armv7:
          BUILDMAN: "at91 -x armv7"
        at91_non_arm926ejs:
@@ -374,12 +375,12 @@ jobs:
          BUILDMAN: "mx6 -x boundary,engicam,freescale,technexion,toradex"
        imx:
          BUILDMAN: "mx -x mx6,freescale,technexion,toradex"
-        imx8:
-          BUILDMAN: "imx8"
        keystone2_keystone3:
          BUILDMAN: "k2 k3"
        samsung_socfpga:
          BUILDMAN: "samsung socfpga"
+        spear:
+          BUILDMAN: "spear"
        sun4i:
          BUILDMAN: "sun4i"
        sun5i:
@@ -397,7 +398,7 @@ jobs:
        sun50i:
          BUILDMAN: "sun50i"
        arm_catch_all:
-          BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,renesas,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
+          BUILDMAN: "arm -x arm11,arm7,arm9,aarch64,at91,bcm,freescale,kirkwood,mvebu,siemens,tegra,uniphier,mx,samsung,sunxi,am33xx,omap,rk,toradex,socfpga,k2,k3,zynq"
        sandbox_x86:
          BUILDMAN: "sandbox x86"
        technexion:
@@ -413,11 +414,11 @@ jobs:
        non_fsl_ppc:
          BUILDMAN: "powerpc -x freescale"
        mpc85xx_freescale:
-          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*"
+          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
        t208xrdb_corenet_ds:
          BUILDMAN: "t208xrdb corenet_ds"
        fsl_ppc:
-          BUILDMAN: "mpc83xx&freescale"
+          BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale"
        t102x:
          BUILDMAN: "t102*"
        p1_p2_rdb_pc:
@@ -435,11 +436,11 @@ jobs:
        uniphier:
          BUILDMAN: "uniphier"
        aarch64_catch_all:
-          BUILDMAN: "aarch64 -x bcm,imx8,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,renesas,sunxi,samsung,socfpga,rk,versal,zynq"
+          BUILDMAN: "aarch64 -x bcm,k3,tegra,ls1,ls2,lx216,mvebu,uniphier,sunxi,samsung,socfpga,rk,versal,zynq"
        rockchip:
          BUILDMAN: "rk"
-        renesas:
-          BUILDMAN: "renesas"
+        sh:
+          BUILDMAN: "sh -x arm"
        zynq:
          BUILDMAN: "zynq&armv7"
        zynqmp_versal:
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -26,9 +26,6 @@
 # addresses are __aligned(2)".
 --ignore PREFER_ETHER_ADDR_COPY

-# ENOSYS is a conventionally used error, even though U-Boot lacks system calls.
--ignore ENOSYS
-
 # A bit shorter of a description is OK with us.
 --min-conf-desc-length=2

--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0+

 # Grab our configured image.  The source for this is found at:
-# https://source.denx.de/u-boot/gitlab-ci-runner
-image: trini/u-boot-gitlab-ci-runner:focal-20210723-30Sep2021
+# https://gitlab.denx.de/u-boot/gitlab-ci-runner
+image: trini/u-boot-gitlab-ci-runner:bionic-20200807-02Sep2020

 # We run some tests in different order, to catch some failures quicker.
 stages:
@@ -14,18 +14,18 @@ stages:
  stage: test.py
  before_script:
    # Clone uboot-test-hooks
-    - git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
+    - git clone --depth=1 git://github.com/swarren/uboot-test-hooks.git /tmp/uboot-test-hooks
    - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
    - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
    - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
    - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal  echo lsefimmap lsefi lsefisystab efinet tftp minicmd
    - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
-        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
+        wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
      fi
    - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then
-        wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ;
-        export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
+        wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.tar.xz | tar -C /tmp -xJ;
+        export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
      fi

  after_script:
@@ -38,6 +38,7 @@ stages:
    - cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
    - cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
    - cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
+    - cp /opt/grub/grubriscv32.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv32.efi
    - cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
    - cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
    - virtualenv -p /usr/bin/python3 /tmp/venv
@@ -154,8 +155,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
      export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
      export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
      export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
-      ./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
-        --board sandbox_spl;
+      ./tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w sandbox_spl;
      ./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
      ./tools/buildman/buildman -t;
      ./tools/dtoc/dtoc -t;
@@ -178,7 +178,7 @@ sandbox test.py:
 sandbox with clang test.py:
  variables:
    TEST_PY_BD: "sandbox"
-    OVERRIDE: "-O clang-12"
+    OVERRIDE: "-O clang-10"
  <<: *buildman_and_testpy_dfn

 sandbox_spl test.py:
@@ -187,12 +187,6 @@ sandbox_spl test.py:
    TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
  <<: *buildman_and_testpy_dfn

-sandbox_noinst_test.py:
-  variables:
-    TEST_PY_BD: "sandbox_noinst"
-    TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
-  <<: *buildman_and_testpy_dfn
-
 evb-ast2500 test.py:
  variables:
    TEST_PY_BD: "evb-ast2500"
@@ -204,6 +198,18 @@ sandbox_flattree test.py:
    TEST_PY_BD: "sandbox_flattree"
  <<: *buildman_and_testpy_dfn

+vexpress_ca15_tc2 test.py:
+  variables:
+    TEST_PY_BD: "vexpress_ca15_tc2"
+    TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
+vexpress_ca9x4 test.py:
+  variables:
+    TEST_PY_BD: "vexpress_ca9x4"
+    TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
 integratorcp_cm926ejs test.py:
  variables:
    TEST_PY_BD: "integratorcp_cm926ejs"
@@ -223,6 +229,30 @@ qemu_arm64 test.py:
    TEST_PY_TEST_SPEC: "not sleep"
  <<: *buildman_and_testpy_dfn

+qemu_mips test.py:
+  variables:
+    TEST_PY_BD: "qemu_mips"
+    TEST_PY_TEST_SPEC: "not sleep"
+  <<: *buildman_and_testpy_dfn
+
+qemu_mipsel test.py:
+  variables:
+    TEST_PY_BD: "qemu_mipsel"
+    TEST_PY_TEST_SPEC: "not sleep"
+  <<: *buildman_and_testpy_dfn
+
+qemu_mips64 test.py:
+  variables:
+    TEST_PY_BD: "qemu_mips64"
+    TEST_PY_TEST_SPEC: "not sleep"
+  <<: *buildman_and_testpy_dfn
+
+qemu_mips64el test.py:
+  variables:
+    TEST_PY_BD: "qemu_mips64el"
+    TEST_PY_TEST_SPEC: "not sleep"
+  <<: *buildman_and_testpy_dfn
+
 qemu_malta test.py:
  variables:
    TEST_PY_BD: "malta"
--- a/.mailmap
+++ b/.mailmap
@@ -32,7 +32,6 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
 Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
 Markus Klotzbuecher <mk@denx.de>
-Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
 Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
 Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
 Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
--- a/2
+++ b/2
@@ -10,8 +10,6 @@ generic-offsets-file := include/generated/generic-asm-offsets.h
 always  := $(generic-offsets-file)
 targets := lib/asm-offsets.s

-CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
-
 $(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
 	$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)

--- a/60
+++ b/60
@@ -57,21 +57,6 @@ config LOCALVERSION_AUTO

 	  which is done within the script "scripts/setlocalversion".)

-config CC_IS_GCC
-	def_bool $(success,$(CC) --version | head -n 1 | grep -q gcc)
-
-config GCC_VERSION
-	int
-	default $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed 's/^0*//') if CC_IS_GCC
-	default 0
-
-config CC_IS_CLANG
-	def_bool $(success,$(CC) --version | head -n 1 | grep -q clang)
-
-config CLANG_VERSION
-	int
-	default $(shell,$(srctree)/scripts/clang-version.sh $(CC))
-
 config CC_OPTIMIZE_FOR_SIZE
 	bool "Optimize for size"
 	default y
@@ -100,30 +85,6 @@ config SPL_OPTIMIZE_INLINING
 	  do what it thinks is best, which is desirable in some cases for size
 	  reasons.

-config ARCH_SUPPORTS_LTO
-	bool
-
-config LTO
-	bool "Enable Link Time Optimizations"
-	depends on ARCH_SUPPORTS_LTO
-	default n
-	help
-	  This option enables Link Time Optimization (LTO), a mechanism which
-	  allows the compiler to optimize between different compilation units.
-
-	  This can optimize away dead code paths, resulting in smaller binary
-	  size (if CC_OPTIMIZE_FOR_SIZE is enabled).
-
-	  This option is not available for every architecture and may
-	  introduce bugs.
-
-	  Currently, when compiling with GCC, due to a weird bug regarding
-	  jobserver, the final linking will not respect make's --jobs argument.
-	  Instead all available processors will be used (as reported by the
-	  nproc command).
-
-	  If unsure, say n.
-
 config TPL_OPTIMIZE_INLINING
 	bool "Allow compiler to uninline functions marked 'inline' in TPL"
 	depends on TPL
@@ -343,6 +304,27 @@ config HAS_ROM
 	  Enables building of a u-boot.rom target. This collects U-Boot and
 	  any necessary binary blobs.

+config ROM_NEEDS_BLOBS
+	bool
+	depends on HAS_ROM
+	help
+	  Enable this if building the u-boot.rom target needs binary blobs, and
+	  so cannot be done normally. In this case, U-Boot will only build the
+	  ROM if the required blobs exist. If not, you will see an warning like:
+
+	    Image 'main-section' is missing external blobs and is non-functional:
+	      intel-descriptor intel-me intel-refcode intel-vga intel-mrc
+
+config BUILD_ROM
+	bool "Build U-Boot as BIOS replacement"
+	depends on HAS_ROM
+	default y if !ROM_NEEDS_BLOBS
+	help
+	  This option allows to build a ROM version of U-Boot.
+	  The build process generally requires several binary blobs
+	  which are not shipped in the U-Boot source tree.
+	  Please, see doc/arch/x86.rst for details.
+
 config SPL_IMAGE
 	string "SPL image used in the combined SPL+U-Boot image"
 	default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
--- a/203
+++ b/203
@@ -75,7 +75,7 @@ M:	Alexey Brodkin <alexey.brodkin@synopsys.com>
 M:	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
 S:	Maintained
 L:	uboot-snps-arc@synopsys.com
-T:	git https://source.denx.de/u-boot/custodians/u-boot-arc.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-arc.git
 F:	arch/arc/
 F:	board/synopsys/

@@ -111,16 +111,16 @@ F:	drivers/mmc/snps_dw_mmc.c
 ARM
 M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-arm.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-arm.git
 F:	arch/arm/
 F:	cmd/arm/

 ARM ALTERA SOCFPGA
 M:	Marek Vasut <marex@denx.de>
 M:	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
-M:	Tien Fong Chee <tien.fong.chee@intel.com>
-S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
+M:	Ley Foon Tan <ley.foon.tan@intel.com>
+S:	Maintainted
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga.git
 F:	arch/arm/mach-socfpga/
 F:	drivers/sysreset/sysreset_socfpga*

@@ -128,7 +128,7 @@ ARM AMLOGIC SOC SUPPORT
 M:	Neil Armstrong <narmstrong@baylibre.com>
 S:	Maintained
 L:	u-boot-amlogic@groups.io
-T:	git https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git
 F:	arch/arm/mach-meson/
 F:	arch/arm/include/asm/arch-meson/
 F:	drivers/clk/meson/
@@ -160,7 +160,7 @@ F:	drivers/clk/aspeed/
 F:	drivers/pinctrl/aspeed/
 N:	aspeed

-ARM BROADCOM BCM283X / BCM27XX
+ARM BROADCOM BCM283X
 M:	Matthias Brugger <mbrugger@suse.com>
 S:	Maintained
 F:	arch/arm/dts/bcm283*
@@ -175,8 +175,6 @@ F:	drivers/video/bcm2835.c
 F:	include/dm/platform_data/serial_bcm283x_mu.h
 F:	include/dt-bindings/pinctrl/bcm2835.h
 F:	drivers/pinctrl/broadcom/
-F:	configs/rpi_*
-T:	git https://source.denx.de/u-boot/custodians/u-boot-arm.git

 ARM BROADCOM BCMSTB
 M:	Thomas Fitzsimmons <fitzsim@fitzsim.org>
@@ -220,7 +218,7 @@ M:	Stefano Babic <sbabic@denx.de>
 M:	Fabio Estevam <festevam@gmail.com>
 R:	NXP i.MX U-Boot Team <uboot-imx@nxp.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-imx.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
 F:	arch/arm/cpu/arm1136/mx*/
 F:	arch/arm/cpu/arm926ejs/mx*/
 F:	arch/arm/cpu/armv7/vf610/
@@ -257,7 +255,7 @@ F:	drivers/rng/msm_rng.c
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-marvell.git
 F:	arch/arm/mach-kirkwood/
 F:	arch/arm/mach-mvebu/
 F:	drivers/ata/ahci_mvebu.c
@@ -271,7 +269,7 @@ F:	drivers/watchdog/orion_wdt.c
 ARM MARVELL PXA
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-pxa.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-pxa.git
 F:	arch/arm/cpu/pxa/
 F:	arch/arm/include/asm/arch-pxa/

@@ -307,7 +305,7 @@ N:	mediatek
 ARM MICROCHIP/ATMEL AT91
 M:	Eugen Hristev <eugen.hristev@microchip.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-atmel.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 F:	board/atmel/
 F:	drivers/cpu/at91_cpu.c
@@ -347,15 +345,15 @@ ARM RENESAS RMOBILE/R-CAR
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 M:	Marek Vasut <marek.vasut+renesas@gmail.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-sh.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git
 F:	arch/arm/mach-rmobile/

 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
-M:	Philipp Tomsich <philipp.tomsich@vrull.eu>
+M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
 M:	Kever Yang <kever.yang@rock-chips.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git
 F:	arch/arm/include/asm/arch-rockchip/
 F:	arch/arm/mach-rockchip/
 F:	board/rockchip/
@@ -377,7 +375,7 @@ F:	tools/rkspi.c
 ARM SAMSUNG
 M:	Minkyu Kang <mk7.kang@samsung.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-samsung.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.git
 F:	arch/arm/mach-exynos/
 F:	arch/arm/mach-s5pc1xx/
 F:	arch/arm/cpu/armv7/s5p-common/
@@ -396,7 +394,7 @@ F:	drivers/usb/host/ehci-msm.c
 ARM STI
 M:	Patrice Chotard <patrice.chotard@foss.st.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-stm.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
 F:	arch/arm/mach-sti/
 F:	arch/arm/include/asm/arch-sti*/
 F:	drivers/phy/sti_usb_phy.c
@@ -412,11 +410,18 @@ F:	include/dt-bindings/clock/stih407-clks.h
 F:	include/dt-bindings/clock/stih410-clks.h
 F:	include/dt-bindings/reset/stih407-resets.h

+ARM STM SPEAR
+#M:	Vipin Kumar <vipin.kumar@st.com>
+S:	Orphaned (Since 2016-02)
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
+F:	arch/arm/cpu/arm926ejs/spear/
+F:	arch/arm/include/asm/arch-spear/
+
 ARM STM STM32MP
 M:	Patrick Delaunay <patrick.delaunay@foss.st.com>
 M:	Patrice Chotard <patrice.chotard@foss.st.com>
 L:	uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
-T:	git https://source.denx.de/u-boot/custodians/u-boot-stm.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
 S:	Maintained
 F:	arch/arm/mach-stm32mp/
 F:	doc/board/st/
@@ -466,26 +471,23 @@ ARM SUNXI
 M:	Jagan Teki <jagan@amarulasolutions.com>
 M:	Andre Przywara <andre.przywara@arm.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-sunxi.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi.git
 F:	arch/arm/cpu/armv7/sunxi/
 F:	arch/arm/include/asm/arch-sunxi/
 F:	arch/arm/mach-sunxi/
 F:	board/sunxi/
-F:	drivers/clk/sunxi/
-F:	drivers/phy/allwinner/
-F:	drivers/video/sunxi/

 ARM TEGRA
 M:	Tom Warren <twarren@nvidia.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-tegra.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-tegra.git
 F:	arch/arm/mach-tegra/
 F:	arch/arm/include/asm/arch-tegra*/

 ARM TI
-M:	Tom Rini <trini@konsulko.com>
+M:	Lokesh Vutla <lokeshvutla@ti.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-ti.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-ti.git
 F:	arch/arm/mach-davinci/
 F:	arch/arm/mach-k3/
 F:	arch/arm/mach-keystone/
@@ -506,7 +508,6 @@ F:	drivers/phy/phy-ti-am654.c
 F:	drivers/phy/ti-pipe3-phy.c
 F:	drivers/ram/k3*
 F:	drivers/remoteproc/k3_system_controller.c
-F:	drivers/remoteproc/pruc_rpoc.c
 F:	drivers/remoteproc/ti*
 F:	drivers/reset/reset-ti-sci.c
 F:	drivers/rtc/davinci.c
@@ -516,7 +517,6 @@ F:	drivers/sysreset/sysreset-ti-sci.c
 F:	drivers/thermal/ti-bandgap.c
 F:	drivers/timer/omap-timer.c
 F:	drivers/watchdog/omap_wdt.c
-F:	include/linux/pruss_driver.h
 F:	include/linux/soc/ti/

 ARM U8500
@@ -536,10 +536,8 @@ N:	uniphier
 ARM VERSAL
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-versal/
-F:	drivers/net/xilinx_axi_mrmac.*
-F:	drivers/soc/soc_xilinx_versal.c
 F:	drivers/watchdog/xilinx_wwdt.c
 N:	(?<!uni)versal

@@ -553,7 +551,7 @@ N:	vexpress
 ARM ZYNQ
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynq/
 F:	doc/board/xilinx/
 F:	doc/device-tree-bindings/video/syncoam,seps525.txt
@@ -579,7 +577,7 @@ N:	zynq
 ARM ZYNQMP
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp/
 F:	drivers/clk/clk_zynqmp.c
 F:	driver/firmware/firmware-zynqmp.c
@@ -594,9 +592,6 @@ F:	drivers/mtd/nand/raw/zynq_nand.c
 F:	drivers/net/phy/xilinx_phy.c
 F:	drivers/net/zynq_gem.c
 F:	drivers/serial/serial_zynq.c
-F:	drivers/reset/reset-zynqmp.c
-F:	drivers/rtc/zynqmp_rtc.c
-F:	drivers/soc/soc_xilinx_zynqmp.c
 F:	drivers/spi/zynq_qspi.c
 F:	drivers/spi/zynq_spi.c
 F:	drivers/timer/cadence-ttc.c
@@ -612,7 +607,7 @@ N:	zynqmp
 ARM ZYNQMP R5
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-zynqmp-r5/

 ARM PHYTIUM
@@ -644,14 +639,14 @@ F:	tools/buildman/
 CFI FLASH
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-cfi-flash.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-cfi-flash.git
 F:	drivers/mtd/cfi_flash.c
 F:	drivers/mtd/jedec_flash.c

 CLOCK
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-clk.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-clk.git
 F:	drivers/clk/
 F:	drivers/clk/imx/

@@ -659,21 +654,20 @@ COLDFIRE
 M:	Huan Wang <alison.wang@nxp.com>
 M:	Angelo Dureghello <angelo@sysam.it>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-coldfire.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-coldfire.git
 F:	arch/m68k/
 F:	doc/arch/m68k.rst

 DFU
 M:	Lukasz Majewski <lukma@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-dfu.git
 F:	cmd/dfu.c
 F:	cmd/usb_*.c
 F:	common/dfu.c
 F:	common/update.c
 F:	common/usb_storage.c
 F:	doc/api/dfu.rst
-F:	doc/usage/dfu.rst
 F:	drivers/dfu/
 F:	drivers/usb/gadget/
 F:	include/dfu.h
@@ -681,7 +675,7 @@ F:	include/dfu.h
 DRIVER MODEL
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-dm.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-dm.git
 F:	doc/driver-model/
 F:	drivers/core/
 F:	include/dm/
@@ -691,9 +685,9 @@ EFI PAYLOAD
 M:	Heinrich Schuchardt <xypron.glpk@gmx.de>
 R:	Alexander Graf <agraf@csgraf.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-efi.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
 F:	doc/api/efi.rst
-F:	doc/develop/uefi/*
+F:	doc/uefi/*
 F:	doc/usage/bootefi.rst
 F:	drivers/rtc/emul_rtc.c
 F:	include/capitalization.h
@@ -714,7 +708,6 @@ F:	cmd/efidebug.c
 F:	cmd/nvedit_efi.c
 F:	tools/efivar.py
 F:	tools/file2include.c
-F:	tools/mkeficapsule.c

 EFI VARIABLES VIA OP-TEE
 M:	Ilias Apalodimas <ilias.apalodimas@linaro.org>
@@ -735,7 +728,7 @@ F:	tools/mkenvimage.c
 FPGA
 M:	Michal Simek <michal.simek@xilinx.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	drivers/fpga/
 F:	cmd/fpga.c
 F:	include/fpga.h
@@ -743,7 +736,7 @@ F:	include/fpga.h
 FLATTENED DEVICE TREE
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-fdt.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-fdt.git
 F:	lib/fdtdec*
 F:	lib/libfdt/
 F:	include/fdt*
@@ -754,25 +747,25 @@ F:	common/fdt_support.c
 FREEBSD
 M:	Rafal Jaworowski <raj@semihalf.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-freebsd.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-freebsd.git

 FREESCALE QORIQ
 M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
 F:	drivers/watchdog/sp805_wdt.c
 F:	drivers/watchdog/sbsa_gwdt.c

 I2C
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-i2c.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-i2c.git
 F:	drivers/i2c/

 LOGGING
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/u-boot.git
+T:	git https://gitlab.denx.de/u-boot/u-boot.git
 F:	common/log*
 F:	cmd/log.c
 F:	doc/develop/logging.rst
@@ -791,7 +784,7 @@ F:	drivers/i2c/i2c-versatile.c
 MICROBLAZE
 M:	Michal Simek <monstr@monstr.eu>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/microblaze/
 F:	cmd/mfsl.c
 F:	drivers/gpio/xilinx_gpio.c
@@ -806,7 +799,7 @@ N:	xilinx
 MIPS
 M:	Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-mips.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git
 F:	arch/mips/

 MIPS CORTINA ACCESS CAxxxx
@@ -882,28 +875,27 @@ F:	arch/mips/dts/mrvl,cn73xx.dtsi

 MMC
 M:	Peng Fan <peng.fan@nxp.com>
-M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git
 F:	drivers/mmc/

 NAND FLASH
 #M:	Scott Wood <oss@buserror.net>
 S:	Orphaned (Since 2018-07)
-T:	git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash.git
 F:	drivers/mtd/nand/raw/

 NDS32
 M:	Rick Chen <rick@andestech.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-nds32.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-nds32.git
 F:	arch/nds32/

 NETWORK
 M:	Joe Hershberger <joe.hershberger@ni.com>
 M:	Ramon Fried <rfried.dev@gmail.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-net.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-net.git
 F:	drivers/net/
 F:	include/net.h
 F:	net/
@@ -911,40 +903,15 @@ F:	net/
 NIOS
 M:	Thomas Chou <thomas@wytron.com.tw>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-nios.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-nios.git
 F:	arch/nios2/

-NVMe
-M:	Bin Meng <bmeng.cn@gmail.com>
-S:	Maintained
-F:	drivers/nvme/
-F:	cmd/nvme.c
-F:	include/nvme.h
-F:	doc/develop/driver-model/nvme.rst
-
-NXP C45 TJA11XX PHY DRIVER
-M:	Radu Pirea <radu-nicolae.pirea@oss.nxp.com>
-S:	Maintained
-F:	drivers/net/phy/nxp-c45-tja11xx.c
-
 ONENAND
 #M:	Lukasz Majewski <l.majewski@majess.pl>
 S:	Orphaned (Since 2017-01)
-T:	git https://source.denx.de/u-boot/custodians/u-boot-onenand.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-onenand.git
 F:	drivers/mtd/onenand/

-OUT4-IMX6ULL-NANO BOARD
-M:	Oleh Kravchenko <oleg@kaa.org.ua>
-S:	Maintained
-T:	git https://github.com/Oleh-Kravchenko/u-boot-out4.git
-F:	arch/arm/dts/ev-imx280-nano-x-mb.dts
-F:	arch/arm/dts/o4-imx-nano.dts
-F:	arch/arm/dts/o4-imx6ull-nano.dtsi
-F:	board/out4
-F:	configs/ev-imx280-nano-x-mb_defconfig
-F:	configs/o4-imx6ull-nano_defconfig
-F:	include/configs/o4-imx6ull-nano.h
-
 PATMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -964,7 +931,7 @@ F:	drivers/pci/pci_mpc85xx.c
 POWER
 M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-pmic.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-pmic.git
 F:	drivers/power/

 POWERPC
@@ -973,15 +940,15 @@ S:	Maintained
 F:	arch/powerpc/

 POWERPC MPC8XX
-M:	Christophe Leroy <christophe.leroy@csgroup.eu>
+M:	Christophe Leroy <christophe.leroy@c-s.fr>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-mpc8xx.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc8xx.git
 F:	arch/powerpc/cpu/mpc8xx/

 POWERPC MPC83XX
 M:	Mario Six <mario.six@gdsys.cc>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-mpc83xx.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc83xx.git
 F:	drivers/ram/mpc83xx_sdram.c
 F:	include/dt-bindings/memory/mpc83xx-sdram.h
 F:	drivers/sysreset/sysreset_mpc83xx.c
@@ -999,14 +966,19 @@ F:	arch/powerpc/include/asm/arch-mpc83xx/
 POWERPC MPC85XX
 M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx.git
 F:	arch/powerpc/cpu/mpc85xx/

+POWERPC MPC86XX
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-mpc86xx.git
+F:	arch/powerpc/cpu/mpc86xx/
+
 RISC-V
 M:	Rick Chen <rick@andestech.com>
-M:	Leo <ycliang@andestech.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
 F:	arch/riscv/
 F:	cmd/riscv/
 F:	doc/usage/sbi.rst
@@ -1019,8 +991,8 @@ M:	Sean Anderson <seanga2@gmail.com>
 S:	Maintained
 F:	doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
 F:	doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
-F:	drivers/clk/clk_kendryte.c
-F:	drivers/pinctrl/pinctrl-kendryte.c
+F:	drivers/clk/kendryte/
+F:	drivers/pinctrl/kendryte/
 F:	include/kendryte/

 RNG
@@ -1047,23 +1019,17 @@ F:	arch/sandbox/
 F:	doc/arch/sandbox.rst
 F:	include/dt-bindings/*/sandbox*.h

-SETEXPR
-M:	Roland Gaudig <roland.gaudig@weidmueller.com>
-S:	Maintained
-F:	cmd/printf.c
-F:	doc/usage/setexpr.rst
-
 SH
 M:	Marek Vasut <marek.vasut+renesas@gmail.com>
 M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-sh.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-sh.git
 F:	arch/sh/

 SPI
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-spi.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-spi.git
 F:	drivers/spi/
 F:	include/spi*

@@ -1092,13 +1058,6 @@ F:	include/sqfs.h
 F:	cmd/sqfs.c
 F:	test/py/tests/test_fs/test_squashfs/

-STACKPROTECTOR
-M:	Joel Peshkin <joel.peshkin@broadcom.com>
-S:	Maintained
-F:	common/stackprot.c
-F:	cmd/stackprot_test.c
-F:	test/py/tests/test_stackprotector.py
-
 TARGET_BCMNS3
 M:	Bharat Gooty <bharat.gooty@broadcom.com>
 M:	Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
@@ -1168,7 +1127,7 @@ UBI
 M:	Kyungmin Park <kmpark@infradead.org>
 M:	Heiko Schocher <hs@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-ubi.git
 F:	drivers/mtd/ubi/

 UFS
@@ -1179,7 +1138,7 @@ F:	drivers/ufs/
 USB
 M:	Marek Vasut <marex@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-usb.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git
 F:	drivers/usb/
 F:	common/usb.c
 F:	common/usb_kbd.c
@@ -1188,36 +1147,24 @@ F:	include/usb.h
 USB xHCI
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci
 F:	drivers/usb/host/xhci*
 F:	include/usb/xhci.h

 VIDEO
 M:	Anatolij Gustschin <agust@denx.de>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-video.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-video.git
 F:	drivers/video/
 F:	common/lcd*.c
 F:	include/lcd*.h
 F:	include/video*.h

-VirtIO
-M:	Bin Meng <bmeng.cn@gmail.com>
-S:	Maintained
-F:	drivers/virtio/
-F:	cmd/virtio.c
-F:	include/config/virtio/
-F:	include/config/virtio.h
-F:	include/config/cmd/virtio.h
-F:	include/virtio*.h
-F:	test/dm/virtio.c
-F:	doc/develop/driver-model/virtio.rst
-
 X86
 M:	Simon Glass <sjg@chromium.org>
 M:	Bin Meng <bmeng.cn@gmail.com>
 S:	Maintained
-T:	git https://source.denx.de/u-boot/custodians/u-boot-x86.git
+T:	git https://gitlab.denx.de/u-boot/custodians/u-boot-x86.git
 F:	arch/x86/
 F:	cmd/x86/

@@ -1247,7 +1194,7 @@ M:	Tom Rini <trini@konsulko.com>
 L:	u-boot@lists.denx.de
 Q:	http://patchwork.ozlabs.org/project/uboot/list/
 S:	Maintained
-T:	git https://source.denx.de/u-boot/u-boot.git
+T:	git https://gitlab.denx.de/u-boot/u-boot.git
 F:	configs/tools-only_defconfig
 F:	*
 F:	*/
--- a/414
+++ b/414
@@ -1,9 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0+

 VERSION = 2021
-PATCHLEVEL = 10
+PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc2
 NAME =

 # *DOCUMENTATION*
@@ -12,17 +12,14 @@ NAME =
 # Comments in this file are targeted only to the developer, do not
 # expect to learn how to build the kernel reading this file.

-# Do not use make's built-in rules and variables
-# (this increases performance and avoids hard-to-debug behaviour)
-MAKEFLAGS += -rR
+# o Do not use make's built-in rules and variables
+#   (this increases performance and avoids hard-to-debug behaviour);
+# o Look for make include files relative to root of kernel src
+MAKEFLAGS += -rR --include-dir=$(CURDIR)

-# Determine target architecture for the sandbox
+# Determine host architecture
 include include/host_arch.h
-ifeq ("", "$(CROSS_COMPILE)")
-  MK_ARCH="${shell uname -m}"
-else
-  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\s*\([^\/]*\/\)*\([^-]*\)-\S*/\2/p'}"
-endif
+MK_ARCH="${shell uname -m}"
 unexport HOST_ARCH
 ifeq ("x86_64", $(MK_ARCH))
  export HOST_ARCH=$(HOST_ARCH_X86_64)
@@ -30,7 +27,7 @@ else ifneq (,$(findstring $(MK_ARCH), "i386" "i486" "i586" "i686"))
  export HOST_ARCH=$(HOST_ARCH_X86)
 else ifneq (,$(findstring $(MK_ARCH), "aarch64" "armv8l"))
  export HOST_ARCH=$(HOST_ARCH_AARCH64)
-else ifneq (,$(findstring $(MK_ARCH), "arm" "armv7" "armv7l"))
+else ifeq ("armv7l", $(MK_ARCH))
  export HOST_ARCH=$(HOST_ARCH_ARM)
 else ifeq ("riscv32", $(MK_ARCH))
  export HOST_ARCH=$(HOST_ARCH_RISCV32)
@@ -161,13 +158,6 @@ KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \
 $(if $(KBUILD_OUTPUT),, \
     $(error failed to create output directory "$(saved-output)"))

-# Look for make include files relative to root of kernel src
-#
-# This does not become effective immediately because MAKEFLAGS is re-parsed
-# once after the Makefile is read.  It is OK since we are going to invoke
-# 'sub-make' below.
-MAKEFLAGS += --include-dir=$(CURDIR)
-
 PHONY += $(MAKECMDGOALS) sub-make

 $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make
@@ -334,6 +324,11 @@ HOSTCC       = $(call os_x_before, 10, 5, "cc", "gcc")
 KBUILD_HOSTCFLAGS  += $(call os_x_before, 10, 4, "-traditional-cpp")
 KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")

+# since Lion (10.7) ASLR is on by default, but we use linker generated lists
+# in some host tools which is a problem then ... so disable ASLR for these
+# tools
+KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 7, "", "-Xlinker -no_pie")
+
 # macOS Mojave (10.14.X) 
 # Undefined symbols for architecture x86_64: "_PyArg_ParseTuple"
 KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "")
@@ -414,7 +409,7 @@ AWK		= awk
 PERL		= perl
 PYTHON		?= python
 PYTHON2		= python2
-PYTHON3		?= python3
+PYTHON3		= python3
 DTC		?= $(objtree)/scripts/dtc/dtc
 CHECK		= sparse

@@ -498,7 +493,8 @@ PHONY += outputmakefile
 outputmakefile:
 ifneq ($(KBUILD_SRC),)
 	$(Q)ln -fsn $(srctree) source
-	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile $(srctree)
+	$(Q)$(CONFIG_SHELL) $(srctree)/scripts/mkmakefile \
+	    $(srctree) $(objtree) $(VERSION) $(PATCHLEVEL)
 endif

 # To make sure we do not include .config for any of the *config targets
@@ -577,7 +573,7 @@ else
 # Carefully list dependencies so we do not try to build scripts twice
 # in parallel
 PHONY += scripts
-scripts: scripts_basic scripts_dtc include/config/auto.conf
+scripts: scripts_basic include/config/auto.conf
 	$(Q)$(MAKE) $(build)=$(@)

 ifeq ($(dot-config),1)
@@ -681,49 +677,12 @@ else
 KBUILD_CFLAGS	+= -O2
 endif

-LTO_CFLAGS :=
-LTO_FINAL_LDFLAGS :=
-export LTO_CFLAGS LTO_FINAL_LDFLAGS
-ifdef CONFIG_LTO
-	ifeq ($(cc-name),clang)
-		LTO_CFLAGS		+= -flto
-		LTO_FINAL_LDFLAGS	+= -flto
-
-		AR			= $(shell $(CC) -print-prog-name=llvm-ar)
-		NM			= $(shell $(CC) -print-prog-name=llvm-nm)
-	else
-		NPROC			:= $(shell nproc 2>/dev/null || echo 1)
-		LTO_CFLAGS		+= -flto=$(NPROC)
-		LTO_FINAL_LDFLAGS	+= -fuse-linker-plugin -flto=$(NPROC)
-
-		# use plugin aware tools
-		AR			= $(CROSS_COMPILE)gcc-ar
-		NM			= $(CROSS_COMPILE)gcc-nm
-	endif
-
-	CFLAGS_NON_EFI			+= $(LTO_CFLAGS)
-
-	KBUILD_CFLAGS			+= $(LTO_CFLAGS)
-endif
-
-ifeq ($(CONFIG_STACKPROTECTOR),y)
-KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
-CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
-else
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
-endif
 KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)

-# disable pointer signed / unsigned warnings in gcc 4.0
-KBUILD_CFLAGS += -Wno-pointer-sign
-
 # disable stringop warnings in gcc 8+
 KBUILD_CFLAGS += $(call cc-disable-warning, stringop-truncation)

-KBUILD_CFLAGS += $(call cc-disable-warning, zero-length-bounds)
-KBUILD_CFLAGS += $(call cc-disable-warning, array-bounds)
-KBUILD_CFLAGS += $(call cc-disable-warning, stringop-overflow)
-
 # Enabled with W=2, disabled by default as noisy
 KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)

@@ -747,7 +706,7 @@ endif
 KBUILD_CFLAGS += $(call cc-option,-Wno-format-nonliteral)
 KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member)

-ifdef CONFIG_CC_IS_CLANG
+ifeq ($(cc-name),clang)
 KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
 KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
 KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
@@ -759,11 +718,12 @@ KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
 # See modpost pattern 2
 KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
 KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior)
-endif
+else

 # These warnings generated too much noise in a regular build.
 # Use make W=1 to enable them (see scripts/Makefile.extrawarn)
 KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
+endif

 # Prohibit date/time macros, which would make the build non-deterministic
 KBUILD_CFLAGS   += $(call cc-option,-Werror=date-time)
@@ -802,19 +762,16 @@ c_flags := $(KBUILD_CFLAGS) $(cpp_flags)

 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n)

-libs-$(CONFIG_API) += api/
-libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
-libs-y += cmd/
-libs-y += common/
-libs-$(CONFIG_OF_EMBED) += dts/
-libs-y += env/
 libs-y += lib/
+libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+libs-$(CONFIG_OF_EMBED) += dts/
 libs-y += fs/
 libs-y += net/
 libs-y += disk/
 libs-y += drivers/
 libs-y += drivers/dma/
 libs-y += drivers/gpio/
+libs-y += drivers/i2c/
 libs-y += drivers/net/
 libs-y += drivers/net/phy/
 libs-y += drivers/power/ \
@@ -835,7 +792,6 @@ libs-y += drivers/usb/dwc3/
 libs-y += drivers/usb/common/
 libs-y += drivers/usb/emul/
 libs-y += drivers/usb/eth/
-libs-$(CONFIG_USB_DEVICE) += drivers/usb/gadget/
 libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/
 libs-$(CONFIG_USB_GADGET) += drivers/usb/gadget/udc/
 libs-y += drivers/usb/host/
@@ -844,6 +800,10 @@ libs-y += drivers/usb/musb/
 libs-y += drivers/usb/musb-new/
 libs-y += drivers/usb/phy/
 libs-y += drivers/usb/ulpi/
+libs-y += cmd/
+libs-y += common/
+libs-y += env/
+libs-$(CONFIG_API) += api/
 ifdef CONFIG_POST
 libs-y += post/
 endif
@@ -953,7 +913,6 @@ endif
 endif
 INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
 INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
-INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb
 ifeq ($(CONFIG_SPL_FRAMEWORK),y)
 INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
 endif
@@ -1007,8 +966,6 @@ LDFLAGS_u-boot += $(LDFLAGS_FINAL)
 # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
 LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)

-LDFLAGS_u-boot += --build-id=none
-
 ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
 LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
 endif
@@ -1059,33 +1016,6 @@ quiet_cmd_cfgcheck = CFGCHK  $2
 cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \
 		$(srctree)/scripts/config_whitelist.txt $(srctree)

-# Concat the value of all the CONFIGs (result is 'y' or 'yy', etc. )
-got = $(foreach cfg,$(1),$($(cfg)))
-
-# expected value 'y for each one
-expect = $(foreach cfg,$(1),y)
-
-# Show a deprecation message
-# Args:
-# 1: List of CONFIG_DM_... to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK")
-# 2: Name of component (e.g . "Ethernet drivers")
-# 3: Release deadline (e.g. "v202.07")
-# 4: Condition to require before checking (e.g. "$(CONFIG_NET)")
-# Note: Script avoids bash construct, hence the strange double 'if'
-# (patches welcome!)
-define deprecated
-	@if [ -n "$(strip $(4))" ]; then if [ "$(got)" != "$(expect)" ]; then \
-		echo >&2 "===================== WARNING ======================"; \
-		echo >&2 "This board does not use $(firstword $(1)) (Driver Model"; \
-		echo >&2 "for $(2)). Please update the board to use"; \
-		echo >&2 "$(firstword $(1)) before the $(3) release. Failure to"; \
-		echo >&2 "update by the deadline may result in board removal."; \
-		echo >&2 "See doc/driver-model/migration.rst for more info."; \
-		echo >&2 "===================================================="; \
-	fi; fi
-
-endef
-
 PHONY += inputs
 inputs: $(INPUTS-y)

@@ -1100,21 +1030,11 @@ endif

 ifeq ($(CONFIG_DEPRECATED),y)
 	$(warning "You have deprecated configuration options enabled in your .config! Please check your configuration.")
+ifeq ($(CONFIG_SPI),y)
+ifneq ($(CONFIG_DM_SPI)$(CONFIG_OF_CONTROL),yy)
+	$(warning "The relevant config item with associated code will remove in v2019.07 release.")
 endif
-ifeq ($(CONFIG_OF_EMBED),y)
-	@echo >&2 "===================== WARNING ======================"
-	@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
-	@echo >&2 "be used for debugging purposes. Please use"
-	@echo >&2 "CONFIG_OF_SEPARATE for boards in mainline."
-	@echo >&2 "See doc/README.fdt-control for more info."
-	@echo >&2 "===================================================="
 endif
-ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
-	@echo >&2 "===================== WARNING ======================"
-	@echo >&2 "This board uses CONFIG_SPL_FIT_GENERATOR. Please migrate"
-	@echo >&2 "to binman instead, to avoid the proliferation of"
-	@echo >&2 "arch-specific scripts with no tests."
-	@echo >&2 "===================================================="
 endif
 ifneq ($(CONFIG_DM),y)
 	@echo >&2 "===================== WARNING ======================"
@@ -1124,10 +1044,114 @@ ifneq ($(CONFIG_DM),y)
 	@echo >&2 "See doc/driver-model/migration.rst for more info."
 	@echo >&2 "===================================================="
 endif
-	$(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\
-		$(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG))
-	$(call deprecated,CONFIG_DM_ETH,Ethernet drivers,v2020.07,$(CONFIG_NET))
-	$(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY))
+ifeq ($(CONFIG_MMC),y)
+ifneq ($(CONFIG_DM_MMC)$(CONFIG_BLK),yy)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_MMC. Please update"
+	@echo >&2 "the board to use CONFIG_DM_MMC before the v2019.04 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_USB),y)
+ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_USB. Please update"
+	@echo >&2 "the board to use CONFIG_DM_USB before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_MVSATA_IDE),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does use CONFIG_MVSATA_IDE which is not"
+	@echo >&2 "ported to driver-model (DM) yet. Please update the storage"
+	@echo >&2 "controller driver to use CONFIG_AHCI before the v2019.07"
+	@echo >&2 "release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+ifeq ($(CONFIG_LIBATA),y)
+ifneq ($(CONFIG_AHCI),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
+	@echo >&2 "enabled. Please update the storage controller driver to use"
+	@echo >&2 "CONFIG_AHCI before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_PCI),y)
+ifneq ($(CONFIG_DM_PCI),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_PCI Please update"
+	@echo >&2 "the board to use CONFIG_DM_PCI before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifneq ($(CONFIG_LCD)$(CONFIG_VIDEO),)
+ifneq ($(CONFIG_DM_VIDEO),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_VIDEO Please update"
+	@echo >&2 "the board to use CONFIG_DM_VIDEO before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifeq ($(CONFIG_OF_EMBED),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "CONFIG_OF_EMBED is enabled. This option should only"
+	@echo >&2 "be used for debugging purposes. Please use"
+	@echo >&2 "CONFIG_OF_SEPARATE for boards in mainline."
+	@echo >&2 "See doc/README.fdt-control for more info."
+	@echo >&2 "===================================================="
+endif
+ifeq ($(CONFIG_SPI_FLASH),y)
+ifneq ($(CONFIG_DM_SPI_FLASH)$(CONFIG_OF_CONTROL),yy)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_SPI_FLASH. Please update"
+	@echo >&2 "the board to use CONFIG_SPI_FLASH before the v2019.07 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifneq ($(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG),)
+ifneq ($(CONFIG_WDT),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_WDT (DM watchdog support)."
+	@echo >&2 "Please update the board to use CONFIG_WDT before the"
+	@echo >&2 "v2019.10 release."
+	@echo >&2 "Failure to update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifneq ($(CONFIG_NET),)
+ifneq ($(CONFIG_DM_ETH),y)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board does not use CONFIG_DM_ETH (Driver Model"
+	@echo >&2 "for Ethernet drivers). Please update the board to use"
+	@echo >&2 "CONFIG_DM_ETH before the v2020.07 release. Failure to"
+	@echo >&2 "update by the deadline may result in board removal."
+	@echo >&2 "See doc/driver-model/migration.rst for more info."
+	@echo >&2 "===================================================="
+endif
+endif
+ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
+	@echo >&2 "===================== WARNING ======================"
+	@echo >&2 "This board uses CONFIG_SPL_FIT_GENERATOR. Please migrate"
+	@echo >&2 "to binman instead, to avoid the proliferation of"
+	@echo >&2 "arch-specific scripts with no tests."
+	@echo >&2 "===================================================="
+endif
 	@# Check that this build does not use CONFIG options that we do not
 	@# know about unless they are in Kconfig. All the existing CONFIG
 	@# options are whitelisted, so new ones should not be added.
@@ -1169,8 +1193,6 @@ MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
 	-a 0 -e 0 -E \
 	$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null

-MKIMAGEFLAGS_fit-dtb.blob += -B 0x8
-
 ifneq ($(EXT_DTB),)
 u-boot-fit-dtb.bin: u-boot-nodtb.bin $(EXT_DTB)
 		$(call if_changed,cat)
@@ -1241,6 +1263,11 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
 		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
 		$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)

+OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
+
+spl/u-boot-spl.hex: spl/u-boot-spl FORCE
+	$(call if_changed,objcopy)
+
 binary_size_check: u-boot-nodtb.bin FORCE
 	@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
 	map_size=$(shell cat u-boot.map | \
@@ -1303,13 +1330,7 @@ u-boot.ldr:	u-boot
 # binman
 # ---------------------------------------------------------------------------
 # Use 'make BINMAN_DEBUG=1' to enable debugging
-# Use 'make BINMAN_VERBOSE=3' to set vebosity level
 default_dt := $(if $(DEVICE_TREE),$(DEVICE_TREE),$(CONFIG_DEFAULT_DEVICE_TREE))
-
-# Tell binman whether we have a devicetree for SPL and TPL
-have_spl_dt := $(if $(CONFIG_SPL_OF_PLATDATA),,$(CONFIG_SPL_OF_CONTROL))
-have_tpl_dt := $(if $(CONFIG_TPL_OF_PLATDATA),,$(CONFIG_TPL_OF_CONTROL))
-
 quiet_cmd_binman = BINMAN  $@
 cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
                --toolpath $(objtree)/tools \
@@ -1318,12 +1339,8 @@ cmd_binman = $(srctree)/tools/binman/binman $(if $(BINMAN_DEBUG),-D) \
 		-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
 		-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
 		-a atf-bl31-path=${BL31} \
-		-a opensbi-path=${OPENSBI} \
 		-a default-dt=$(default_dt) \
 		-a scp-path=$(SCP) \
-		-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
-		-a tpl-bss-pad=$(if $(CONFIG_TPL_SEPARATE_BSS),,1) \
-		-a spl-dtb=$(have_spl_dt) -a tpl-dtb=$(have_tpl_dt) \
 		$(BINMAN_$(@F))

 OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
@@ -1423,7 +1440,7 @@ u-boot-lzma.img: u-boot.bin.lzma FORCE

 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
 		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
-			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
+			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
 		,$(UBOOT_BIN)) FORCE
 	$(call if_changed,mkimage)
 	$(BOARD_SIZE_CHECK)
@@ -1433,7 +1450,6 @@ MKIMAGEFLAGS_u-boot.itb =
 else
 MKIMAGEFLAGS_u-boot.itb = -E
 endif
-MKIMAGEFLAGS_u-boot.itb += -B 0x8

 ifdef U_BOOT_ITS
 u-boot.itb: u-boot-nodtb.bin \
@@ -1443,7 +1459,7 @@ u-boot.itb: u-boot-nodtb.bin \
 	$(BOARD_SIZE_CHECK)
 endif

-u-boot-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE
+u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)

 u-boot.sha1:	u-boot.bin
@@ -1526,21 +1542,12 @@ u-boot.cnt: u-boot.bin FORCE
 flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 else
-ifeq ($(CONFIG_BINMAN),y)
-flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
-	$(call if_changed,binman)
-	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
-else
 flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
 endif
 endif
-endif

-u-boot.uim: u-boot.bin FORCE
-	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
-
-u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
+u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
 	$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@

 MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)
@@ -1563,11 +1570,22 @@ u-boot-signed.sb: u-boot.bin spl/u-boot-spl.bin
 u-boot.sb: u-boot.bin spl/u-boot-spl.bin
 	$(Q)$(MAKE) $(build)=arch/arm/cpu/arm926ejs/mxs u-boot.sb

+# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
+# Both images are created using mkimage (crc etc), so that the ROM
+# bootloader can check its integrity. Padding needs to be done to the
+# SPL image (with mkimage header) and not the binary. Otherwise the resulting image
+# which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
+# The resulting image containing both U-Boot images is called u-boot.spr
 MKIMAGEFLAGS_u-boot-spl.img = -A $(ARCH) -T firmware -C none \
 	-a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER
 spl/u-boot-spl.img: spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)

+OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+			  --gap-fill=0xff
+u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
+	$(call if_changed,pad_cat)
+
 ifneq ($(CONFIG_ARCH_SOCFPGA),)
 quiet_cmd_gensplx4 = GENSPLX4 $@
 cmd_gensplx4 = $(OBJCOPY) -I binary -O binary --gap-fill=0x0		\
@@ -1710,9 +1728,6 @@ u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE

 ifeq ($(CONFIG_SPL),y)
 spl/u-boot-spl-mtk.bin: spl/u-boot-spl
-
-u-boot-mtk.bin: u-boot-with-spl.bin
-	$(call if_changed,copy)
 else
 MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
@@ -1730,54 +1745,14 @@ u-boot-swap.bin: u-boot.bin FORCE

 ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)

-# Generate linker list symbols references to force compiler to not optimize
-# them away when compiling with LTO
-ifdef CONFIG_LTO
-u-boot-keep-syms-lto := keep-syms-lto.o
-u-boot-keep-syms-lto_c := $(patsubst %.o,%.c,$(u-boot-keep-syms-lto))
-
-quiet_cmd_keep_syms_lto = KSL     $@
-      cmd_keep_syms_lto = \
-	$(srctree)/scripts/gen_ll_addressable_symbols.sh $(NM) $^ > $@
-
-quiet_cmd_keep_syms_lto_cc = KSLCC   $@
-      cmd_keep_syms_lto_cc = \
-	$(CC) $(filter-out $(LTO_CFLAGS),$(c_flags)) -c -o $@ $<
-
-$(u-boot-keep-syms-lto_c): $(u-boot-main)
-	$(call if_changed,keep_syms_lto)
-$(u-boot-keep-syms-lto): $(u-boot-keep-syms-lto_c)
-	$(call if_changed,keep_syms_lto_cc)
-else
-u-boot-keep-syms-lto :=
-endif
-
 # Rule to link u-boot
 # May be overridden by arch/$(ARCH)/config.mk
-ifdef CONFIG_LTO
-quiet_cmd_u-boot__ ?= LTO     $@
-      cmd_u-boot__ ?= 								\
-		$(CC) -nostdlib -nostartfiles					\
-		$(LTO_FINAL_LDFLAGS) $(c_flags)					\
-		$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@	\
-		-T u-boot.lds $(u-boot-init)					\
-		-Wl,--whole-archive						\
-			$(u-boot-main)						\
-			$(u-boot-keep-syms-lto)					\
-			$(PLATFORM_LIBS)					\
-		-Wl,--no-whole-archive						\
-		-Wl,-Map,u-boot.map;						\
-		$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
-else
 quiet_cmd_u-boot__ ?= LD      $@
-      cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@		\
-		-T u-boot.lds $(u-boot-init)					\
-		--whole-archive							\
-			$(u-boot-main)						\
-		--no-whole-archive						\
-		$(PLATFORM_LIBS) -Map u-boot.map;				\
-		$(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
-endif
+      cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
+      -T u-boot.lds $(u-boot-init)                             \
+      --start-group $(u-boot-main) --end-group                 \
+      $(PLATFORM_LIBS) -Map u-boot.map;                        \
+      $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)

 quiet_cmd_smap = GEN     common/system_map.o
 cmd_smap = \
@@ -1786,7 +1761,7 @@ cmd_smap = \
 	$(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
 		-c $(srctree)/common/system_map.c -o common/system_map.o

-u-boot:	$(u-boot-init) $(u-boot-main) $(u-boot-keep-syms-lto) u-boot.lds FORCE
+u-boot:	$(u-boot-init) $(u-boot-main) u-boot.lds FORCE
 	+$(call if_changed,u-boot__)
 ifeq ($(CONFIG_KALLSYMS),y)
 	$(call cmd,smap)
@@ -1866,8 +1841,6 @@ endif

 ifeq ($(CONFIG_USE_DEFAULT_ENV_FILE),y)
 prepare1: $(defaultenv_h)
-
-envtools: $(defaultenv_h)
 endif

 archprepare: prepare1 scripts_basic
@@ -1907,6 +1880,7 @@ define filechk_timestamp.h
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE "%b %d %C%y"'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TIME "%T"'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
+			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
 			LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_EPOCH %s'; \
 		else \
@@ -1916,16 +1890,18 @@ define filechk_timestamp.h
 		LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"'; \
 		LC_ALL=C date +'#define U_BOOT_TIME "%T"'; \
 		LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
+		LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
 		LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
 		LC_ALL=C date +'#define U_BOOT_EPOCH %s'; \
 	fi)
 endef

 define filechk_defaultenv.h
-	( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
+	(grep -v '^#' | \
+	 grep -v '^$$' | \
 	 tr '\n' '\0' | \
 	 sed -e 's/\\\x0\s*//g' | \
-	 xxd -i ; )
+	 xxd -i ; echo ", 0x00" ; )
 endef

 define filechk_dt.h
@@ -1948,35 +1924,6 @@ $(dt_h): $(srctree)/Makefile FORCE
 $(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE
 	$(call filechk,defaultenv.h)

-# ---------------------------------------------------------------------------
-# Devicetree files
-
-ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/boot/dts/),)
-dtstree := arch/$(SRCARCH)/boot/dts
-endif
-
-ifneq ($(dtstree),)
-
-%.dtb: prepare3 scripts_dtc
-	$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@
-
-PHONY += dtbs dtbs_install
-dtbs: prepare3 scripts_dtc
-	$(Q)$(MAKE) $(build)=$(dtstree)
-
-dtbs_install:
-	$(Q)$(MAKE) $(dtbinst)=$(dtstree)
-
-ifdef CONFIG_OF_EARLY_FLATTREE
-all: dtbs
-endif
-
-endif
-
-PHONY += scripts_dtc
-scripts_dtc: scripts_basic
-	$(Q)$(MAKE) $(build)=scripts/dtc
-
 # ---------------------------------------------------------------------------
 quiet_cmd_cpp_lds = LDS     $@
 cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) \
@@ -1989,12 +1936,6 @@ spl/u-boot-spl.bin: spl/u-boot-spl
 	@:
 	$(SPL_SIZE_CHECK)

-spl/u-boot-spl-dtb.bin: spl/u-boot-spl
-	@:
-
-spl/u-boot-spl-dtb.hex: spl/u-boot-spl
-	@:
-
 spl/u-boot-spl: tools prepare \
 		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
 		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
@@ -2098,16 +2039,14 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h tools/version.h \
 	       boot* u-boot* MLO* SPL System.map fit-dtb.blob* \
 	       u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
 	       lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
-	       idbloader.img flash.bin flash.log defconfig keep-syms-lto.c
+	       idbloader.img flash.bin flash.log defconfig

 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl \
-		  .tmp_objdiff doc/output include/asm
-
-# Remove include/asm symlink created by U-Boot before v2014.01
+		  .tmp_objdiff doc/output
 MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
 		  ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
-		  drivers/video/fonts/*.S include/asm
+		  drivers/video/fonts/*.S

 # clean - Delete most, but leave enough to build external modules
 #
@@ -2239,6 +2178,9 @@ PHONY += $(DOC_TARGETS)
 $(DOC_TARGETS): scripts_basic FORCE
 	$(Q)$(MAKE) $(build)=doc $@

+endif #ifeq ($(config-targets),1)
+endif #ifeq ($(mixed-targets),1)
+
 PHONY += checkstack ubootrelease ubootversion

 checkstack:
@@ -2300,7 +2242,7 @@ endif
 	$(build)=$(build-dir) $(@:.ko=.o)
 	$(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost

-quiet_cmd_genenv = GENENV  $@
+quiet_cmd_genenv = GENENV $@
 cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \
 	sed --in-place -e 's/\x00/\x0A/g' $@

@@ -2326,15 +2268,13 @@ quiet_cmd_rmfiles = $(if $(wildcard $(rm-files)),CLEAN   $(wildcard $(rm-files))

 # read all saved command lines

-cmd_files := $(wildcard .*.cmd)
+cmd_files := $(wildcard .*.cmd $(foreach f,$(sort $(targets)),$(dir $(f)).$(notdir $(f)).cmd))

 ifneq ($(cmd_files),)
  $(cmd_files): ;	# Do not try to update included dependency files
  include $(cmd_files)
 endif

-endif    #ifeq ($(config-targets),1)
-endif    #ifeq ($(mixed-targets),1)
 endif	# skip-makefile

 PHONY += FORCE
--- a/89
+++ b/89
@@ -58,8 +58,8 @@ Where to get source code:
 =========================

 The U-Boot source code is maintained in the Git repository at
-https://source.denx.de/u-boot/u-boot.git ; you can browse it online at
-https://source.denx.de/u-boot/u-boot
+https://gitlab.denx.de/u-boot/u-boot.git ; you can browse it online at
+https://gitlab.denx.de/u-boot/u-boot

 The "Tags" links on this page allow you to download tarballs of
 any version you might be interested in. Official releases are also
@@ -128,7 +128,7 @@ Examples:
 Directory Hierarchy:
 ====================

-/arch			Architecture-specific files
+/arch			Architecture specific files
  /arc			Files generic to ARC architecture
  /arm			Files generic to ARM architecture
  /m68k			Files generic to m68k architecture
@@ -142,16 +142,16 @@ Directory Hierarchy:
  /sh			Files generic to SH architecture
  /x86			Files generic to x86 architecture
  /xtensa		Files generic to Xtensa architecture
-/api			Machine/arch-independent API for external apps
-/board			Board-dependent files
+/api			Machine/arch independent API for external apps
+/board			Board dependent files
 /cmd			U-Boot commands functions
-/common			Misc architecture-independent functions
+/common			Misc architecture independent functions
 /configs		Board default configuration files
 /disk			Code for disk drive partition handling
-/doc			Documentation (a mix of ReST and READMEs)
-/drivers		Device drivers
-/dts			Makefile for building internal U-Boot fdt.
-/env			Environment support
+/doc			Documentation (don't expect too much)
+/drivers		Commonly used device drivers
+/dts			Contains Makefile for building internal U-Boot fdt.
+/env			Environment files
 /examples		Example code for standalone applications, etc.
 /fs			Filesystem code (cramfs, ext2, jffs2, etc.)
 /include		Header Files
@@ -161,7 +161,7 @@ Directory Hierarchy:
 /post			Power On Self Test
 /scripts		Various build scripts and Makefiles
 /test			Various unit test files
-/tools			Tools to build and sign FIT images, etc.
+/tools			Tools to build S-Record or U-Boot images, etc.

 Software Configuration:
 =======================
@@ -423,7 +423,8 @@ The following options need to be configured:

 		CONFIG_SYS_FSL_DDR
 		Freescale DDR driver in use. This type of DDR controller is
-		found in mpc83xx, mpc85xx as well as some ARM core SoCs.
+		found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+		SoCs.

 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
@@ -629,6 +630,10 @@ The following options need to be configured:
 					controller register space

 - Serial Ports:
+		CONFIG_PL010_SERIAL
+
+		Define this if you want support for Amba PrimeCell PL010 UARTs.
+
 		CONFIG_PL011_SERIAL

 		Define this if you want support for Amba PrimeCell PL011 UARTs.
@@ -742,15 +747,6 @@ The following options need to be configured:
 		SoC, then define this variable and provide board
 		specific code for the "hw_watchdog_reset" function.

-		CONFIG_SYS_WATCHDOG_FREQ
-		Some platforms automatically call WATCHDOG_RESET()
-		from the timer interrupt handler every
-		CONFIG_SYS_WATCHDOG_FREQ interrupts. If not set by the
-		board configuration file, a default of CONFIG_SYS_HZ/2
-		(i.e. 500) is used. Setting CONFIG_SYS_WATCHDOG_FREQ
-		to 0 disables calling WATCHDOG_RESET() from the timer
-		interrupt.
-
 - Real-Time Clock:

 		When CONFIG_CMD_DATE is selected, the type of the RTC
@@ -1461,12 +1457,9 @@ The following options need to be configured:
 		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.

- I2C Support:	CONFIG_SYS_I2C_LEGACY
+- I2C Support:	CONFIG_SYS_I2C

-		Note: This is deprecated in favour of driver model. Use
-		CONFIG_DM_I2C instead.
-
-		This enable the legacy i2c subsystem, and will allow you to use
+		This enable the NEW i2c subsystem, and will allow you to use
 		i2c commands at the u-boot command line (as long as you set
 		    CONFIG_SYS_I2C_SOFT_SPEED and CONFIG_SYS_I2C_SOFT_SLAVE
 		    for defining speed and slave address
@@ -2776,6 +2769,9 @@ Low Level (hardware related) configuration options:
  CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
 		Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)

+- CONFIG_PCI_INDIRECT_BRIDGE:
+		Enable support for indirect PCI bridges.
+
 - CONFIG_SYS_SRIO:
 		Chip has SRIO or not

@@ -3507,6 +3503,47 @@ The signature of the callback functions is:

 The return value is 0 if the variable change is accepted and 1 otherwise.

+Command Line Parsing:
+=====================
+
+There are two different command line parsers available with U-Boot:
+the old "simple" one, and the much more powerful "hush" shell:
+
+Old, simple command line parser:
+--------------------------------
+
+- supports environment variables (through setenv / saveenv commands)
+- several commands on one line, separated by ';'
+- variable substitution using "... ${name} ..." syntax
+- special characters ('$', ';') can be escaped by prefixing with '\',
+  for example:
+	setenv bootcmd bootm \${address}
+- You can also escape text by enclosing in single apostrophes, for example:
+	setenv addip 'setenv bootargs $bootargs ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off'
+
+Hush shell:
+-----------
+
+- similar to Bourne shell, with control structures like
+  if...then...else...fi, for...do...done; while...do...done,
+  until...do...done, ...
+- supports environment ("global") variables (through setenv / saveenv
+  commands) and local shell variables (through standard shell syntax
+  "name=value"); only environment variables can be used with "run"
+  command
+
+General rules:
+--------------
+
+(1) If a command line (or an environment variable executed by a "run"
+    command) contains several commands separated by semicolon, and
+    one of these commands fails, then the remaining commands will be
+    executed anyway.
+
+(2) If you execute several variables with one call to run (i. e.
+    calling run with a list of variables as arguments), any failing
+    command will cause "run" to terminate, i. e. the remaining
+    variables are not executed.

 Note for Redundant Ethernet Interfaces:
 =======================================
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -33,7 +33,6 @@ config ARC

 config ARM
 	bool "ARM architecture"
-	select ARCH_SUPPORTS_LTO
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
 	select SUPPORT_OF_CONTROL
@@ -102,7 +101,6 @@ config RISCV

 config SANDBOX
 	bool "Sandbox"
-	select ARCH_SUPPORTS_LTO
 	select BOARD_LATE_INIT
 	select BZIP2
 	select CMD_POWEROFF
@@ -122,11 +120,8 @@ config SANDBOX
 	select SPI
 	select SUPPORT_OF_CONTROL
 	select SYSRESET_CMD_POWEROFF
-	select IRQ
-	select SUPPORT_EXTENSION_SCAN
 	imply BITREVERSE
 	select BLOBLIST
-	imply LTO
 	imply CMD_DM
 	imply CMD_EXCEPTION
 	imply CMD_GETTIME
@@ -147,8 +142,6 @@ config SANDBOX
 	imply AVB_VERIFY
 	imply LIBAVB
 	imply CMD_AVB
-	imply SCP03
-	imply CMD_SCP03
 	imply UDP_FUNCTION_FASTBOOT
 	imply VIRTIO_MMIO
 	imply VIRTIO_PCI
@@ -167,9 +160,6 @@ config SANDBOX
 	imply CMD_CLONE
 	imply SILENT_CONSOLE
 	imply BOOTARGS_SUBST
-	imply PHY_FIXED
-	imply DM_DSA
-	imply CMD_EXTENSION

 config SH
 	bool "SuperH architecture"
@@ -182,6 +172,7 @@ config X86
 	select SUPPORT_TPL
 	select CREATE_ARCH_SYMLINK
 	select DM
+	select DM_PCI
 	select HAVE_ARCH_IOMAP
 	select HAVE_PRIVATE_LIBGCC
 	select OF_CONTROL
@@ -190,7 +181,6 @@ config X86
 	select TIMER
 	select USE_PRIVATE_LIBGCC
 	select X86_TSC_TIMER
-	select IRQ
 	imply HAS_ROM if X86_RESET_VECTOR
 	imply BLK
 	imply CMD_DM
@@ -221,6 +211,7 @@ config X86
 	imply USB_HOST_ETHER
 	imply PCH
 	imply RTC_MC146818
+	imply IRQ
 	imply ACPIGEN if !QEMU
 	imply SYSINFO if GENERATE_SMBIOS_TABLE
 	imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
@@ -228,8 +219,8 @@ config X86
 	# Thing to enable for when SPL/TPL are enabled: SPL
 	imply SPL_DM
 	imply SPL_OF_LIBFDT
-	imply SPL_DRIVERS_MISC
-	imply SPL_GPIO
+	imply SPL_DRIVERS_MISC_SUPPORT
+	imply SPL_GPIO_SUPPORT
 	imply SPL_PINCTRL
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
@@ -242,8 +233,8 @@ config X86
 	imply SPL_SYSCON
 	# TPL
 	imply TPL_DM
-	imply TPL_DRIVERS_MISC
-	imply TPL_GPIO
+	imply TPL_DRIVERS_MISC_SUPPORT
+	imply TPL_GPIO_SUPPORT
 	imply TPL_PINCTRL
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
--- a/arch/arc/dts/iot_devkit.dts
+++ b/arch/arc/dts/iot_devkit.dts
@@ -39,7 +39,7 @@
 	};

 	usbphy: phy {
-		compatible = "usb-nop-xceiv";
+		compatible = "nop-phy";
 		#phy-cells = <0>;
 	};

--- a/arch/arc/include/asm/config.h
+++ b/arch/arc/include/asm/config.h
@@ -8,4 +8,6 @@

 #define CONFIG_SYS_BOOT_RAMDISK_HIGH

+#define CONFIG_LMB
+
 #endif /*__ASM_ARC_CONFIG_H_ */
--- a/arch/arc/include/asm/global_data.h
+++ b/arch/arc/include/asm/global_data.h
@@ -6,6 +6,8 @@
 #ifndef	__ASM_ARC_GLOBAL_DATA_H
 #define __ASM_ARC_GLOBAL_DATA_H

+#include <config.h>
+
 #ifndef __ASSEMBLY__
 /* Architecture-specific global data */
 struct arch_global_data {
--- a/arch/arc/lib/reset.c
+++ b/arch/arc/lib/reset.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <cpu_func.h>

-__weak void reset_cpu(void)
+__weak void reset_cpu(ulong addr)
 {
 	/* Stop debug session here */
 	__builtin_arc_brk();
@@ -17,7 +17,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	printf("Resetting the board...\n");

-	reset_cpu();
+	reset_cpu(0);

 	return 0;
 }
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -67,7 +67,6 @@ config GIC_V3_ITS
 	bool "ARM GICV3 ITS"
 	select REGMAP
 	select SYSCON
-	select IRQ
 	help
 	  ARM GICV3 Interrupt translation service (ITS).
 	  Basic support for programming locality specific peripheral
@@ -90,9 +89,6 @@ config HAS_VBAR
 config HAS_THUMB2
 	bool

-config GPIO_EXTRA_HEADER
-	bool
-
 # Used for compatibility with asm files copied from the kernel
 config ARM_ASM_UNIFIED
 	bool
@@ -350,7 +346,7 @@ config SYS_CACHELINE_SIZE
 choice
 	prompt "Select the ARM data write cache policy"
 	default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
-					      CPU_PXA || RZA1
+					      TARGET_BCMNSP || CPU_PXA || RZA1
 	default SYS_ARM_CACHE_WRITEBACK

 config SYS_ARM_CACHE_WRITEBACK
@@ -521,19 +517,25 @@ choice

 config ARCH_AT91
 	bool "Atmel AT91"
-	select GPIO_EXTRA_HEADER
 	select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
 	select SPL_SEPARATE_BSS if SPL

+config TARGET_EDB93XX
+	bool "Support edb93xx"
+	select CPU_ARM920T
+	select PL010_SERIAL
+
 config TARGET_ASPENITE
 	bool "Support aspenite"
 	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
+
+config TARGET_GPLUGD
+	bool "Support gplugd"
+	select CPU_ARM926EJS

 config ARCH_DAVINCI
 	bool "TI DaVinci"
 	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
 	select SPL_DM_SPI if SPL
 	imply CMD_SAVES
 	help
@@ -544,7 +546,6 @@ config ARCH_KIRKWOOD
 	select ARCH_MISC_INIT
 	select BOARD_EARLY_INIT_F
 	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER

 config ARCH_MVEBU
 	bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
@@ -553,7 +554,6 @@ config ARCH_MVEBU
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select GPIO_EXTRA_HEADER
 	select SPL_DM_SPI if SPL
 	select SPL_DM_SPI_FLASH if SPL
 	select OF_CONTROL
@@ -561,10 +561,42 @@ config ARCH_MVEBU
 	select SPI
 	imply CMD_DM

+config TARGET_APF27
+	bool "Support apf27"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
+
 config ARCH_ORION5X
 	bool "Marvell Orion"
 	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
+
+config TARGET_SPEAR300
+	bool "Support spear300"
+	select BOARD_EARLY_INIT_F
+	select CPU_ARM926EJS
+	select PL011_SERIAL
+	imply CMD_SAVES
+
+config TARGET_SPEAR310
+	bool "Support spear310"
+	select BOARD_EARLY_INIT_F
+	select CPU_ARM926EJS
+	select PL011_SERIAL
+	imply CMD_SAVES
+
+config TARGET_SPEAR320
+	bool "Support spear320"
+	select BOARD_EARLY_INIT_F
+	select CPU_ARM926EJS
+	select PL011_SERIAL
+	imply CMD_SAVES
+
+config TARGET_SPEAR600
+	bool "Support spear600"
+	select BOARD_EARLY_INIT_F
+	select CPU_ARM926EJS
+	select PL011_SERIAL
+	imply CMD_SAVES

 config TARGET_STV0991
 	bool "Support stv0991"
@@ -573,23 +605,27 @@ config TARGET_STV0991
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	select SPI
 	select SPI_FLASH
 	imply CMD_DM

+config TARGET_X600
+	bool "Support x600"
+	select BOARD_LATE_INIT
+	select CPU_ARM926EJS
+	select PL011_SERIAL
+	select SUPPORT_SPL
+
 config TARGET_FLEA3
 	bool "Support flea3"
 	select CPU_ARM1136
-	select GPIO_EXTRA_HEADER

 config ARCH_BCM283X
 	bool "Broadcom BCM283X family"
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	select SERIAL_SEARCH_ALL
@@ -614,11 +650,17 @@ config ARCH_BCM6858
 	select OF_CONTROL
 	imply CMD_DM

+config TARGET_VEXPRESS_CA15_TC2
+	bool "Support vexpress_ca15_tc2"
+	select CPU_V7A
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
+	select PL011_SERIAL
+
 config ARCH_BCMSTB
 	bool "Broadcom BCM7XXX family"
 	select CPU_V7A
 	select DM
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select OF_PRIOR_STAGE
 	imply CMD_DM
@@ -626,10 +668,31 @@ config ARCH_BCMSTB
 	  This enables support for Broadcom ARM-based set-top box
 	  chipsets, including the 7445 family of chips.

+config TARGET_VEXPRESS_CA5X2
+	bool "Support vexpress_ca5x2"
+	select CPU_V7A
+	select PL011_SERIAL
+
+config TARGET_VEXPRESS_CA9X4
+	bool "Support vexpress_ca9x4"
+	select CPU_V7A
+	select PL011_SERIAL
+
+config TARGET_BCM23550_W1D
+	bool "Support bcm23550_w1d"
+	select CPU_V7A
+	imply CRC32_VERIFY
+	imply FAT_WRITE
+
+config TARGET_BCM28155_AP
+	bool "Support bcm28155_ap"
+	select CPU_V7A
+	imply CRC32_VERIFY
+	imply FAT_WRITE
+
 config TARGET_BCMCYGNUS
 	bool "Support bcmcygnus"
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
 	imply BCM_SF2_ETH
 	imply BCM_SF2_ETH_GMAC
 	imply CMD_HASH
@@ -638,10 +701,13 @@ config TARGET_BCMCYGNUS
 	imply HASH_VERIFY
 	imply NETDEVICES

+config TARGET_BCMNSP
+	bool "Support bcmnsp"
+	select CPU_V7A
+
 config TARGET_BCMNS2
 	bool "Support Broadcom Northstar2"
 	select ARM64
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for Broadcom Northstar 2 SoCs.  NS2 is a quad-core 64-bit
 	  ARMv8 Cortex-A57 processors targeting a broad range of networking
@@ -661,13 +727,11 @@ config ARCH_EXYNOS
 	select DM
 	select DM_GPIO
 	select DM_I2C
-	select DM_ETH
 	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
 	select SPI
-	select GPIO_EXTRA_HEADER
 	imply SYS_THUMB_BUILD
 	imply CMD_DM
 	imply FAT_WRITE
@@ -679,28 +743,17 @@ config ARCH_S5PC1XX
 	select DM_GPIO
 	select DM_I2C
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	imply CMD_DM

 config ARCH_HIGHBANK
 	bool "Calxeda Highbank"
 	select CPU_V7A
-	select PL01X_SERIAL
-	select DM
-	select DM_SERIAL
-	select OF_CONTROL
-	select OF_BOARD
-	select CLK
-	select CLK_CCF
-	select AHCI
-	select DM_ETH
-	select PHYS_64BIT
+	select PL011_SERIAL

 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
 	select DM
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	imply CMD_DM

@@ -711,7 +764,6 @@ config ARCH_IPQ40XX
 	select DM_GPIO
 	select DM_SERIAL
 	select DM_RESET
-	select GPIO_EXTRA_HEADER
 	select MSM_SMEM
 	select PINCTRL
 	select CLK
@@ -723,7 +775,6 @@ config ARCH_KEYSTONE
 	bool "TI Keystone"
 	select CMD_POWEROFF
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	select SYS_ARCH_TIMER
 	select SYS_THUMB_BUILD
@@ -740,7 +791,6 @@ config ARCH_K3
 config ARCH_OMAP2PLUS
 	bool "TI OMAP2+"
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
 	select SPL_BOARD_INIT if SPL
 	select SPL_STACK_R if SPL
 	select SUPPORT_SPL
@@ -749,7 +799,6 @@ config ARCH_OMAP2PLUS

 config ARCH_MESON
 	bool "Amlogic Meson"
-	select GPIO_EXTRA_HEADER
 	imply DISTRO_DEFAULTS
 	imply DM_RNG
 	help
@@ -760,7 +809,6 @@ config ARCH_MESON
 config ARCH_MEDIATEK
 	bool "MediaTek SoCs"
 	select DM
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_DM if SPL
 	select SPL_LIBCOMMON_SUPPORT if SPL
@@ -777,7 +825,6 @@ config ARCH_LPC32XX
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select SPL_DM if SPL
 	select SUPPORT_SPL
 	imply CMD_DM
@@ -786,71 +833,48 @@ config ARCH_IMX8
 	bool "NXP i.MX8 platform"
 	select ARM64
 	select DM
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select ENABLE_ARM_SOC_BOOT0_HOOK

 config ARCH_IMX8M
 	bool "NXP i.MX8M platform"
 	select ARM64
-	select GPIO_EXTRA_HEADER
-	select SYS_FSL_HAS_SEC if IMX_HAB
-	select SYS_FSL_SEC_COMPAT_4
-	select SYS_FSL_SEC_LE
 	select DM
 	select SUPPORT_SPL
 	imply CMD_DM

-config ARCH_IMX8ULP
-	bool "NXP i.MX8ULP platform"
-	select ARM64
-	select DM
-	select OF_CONTROL
-	select SUPPORT_SPL
-	select GPIO_EXTRA_HEADER
-	imply CMD_DM
-
 config ARCH_IMXRT
 	bool "NXP i.MXRT platform"
 	select CPU_V7M
 	select DM
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	imply CMD_DM

 config ARCH_MX23
 	bool "NXP i.MX23 family"
 	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	select SUPPORT_SPL

 config ARCH_MX25
 	bool "NXP MX25"
 	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
 	imply MXC_GPIO

 config ARCH_MX28
 	bool "NXP i.MX28 family"
 	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
 	select PL011_SERIAL
 	select SUPPORT_SPL

 config ARCH_MX31
 	bool "NXP i.MX31 family"
 	select CPU_ARM1136
-	select GPIO_EXTRA_HEADER

 config ARCH_MX7ULP
 	bool "NXP MX7ULP"
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
-	select SYS_FSL_HAS_SEC if IMX_HAB
-	select SYS_FSL_SEC_COMPAT_4
-	select SYS_FSL_SEC_LE
 	select ROM_UNIFIED_SECTIONS
 	imply MXC_GPIO
 	imply SYS_THUMB_BUILD
@@ -859,7 +883,6 @@ config ARCH_MX7
 	bool "Freescale MX7"
 	select ARCH_MISC_INIT
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
 	select SYS_FSL_HAS_SEC if IMX_HAB
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -870,7 +893,6 @@ config ARCH_MX7
 config ARCH_MX6
 	bool "Freescale MX6"
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
@@ -886,21 +908,18 @@ config ARCH_MX5
 	bool "Freescale MX5"
 	select BOARD_EARLY_INIT_F
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
 	imply MXC_GPIO

 config ARCH_NEXELL
 	bool "Nexell S5P4418/S5P6818 SoC"
 	select ENABLE_ARM_SOC_BOOT0_HOOK
 	select DM
-	select GPIO_EXTRA_HEADER

 config ARCH_OWL
 	bool "Actions Semi OWL SoCs"
 	select DM
 	select DM_ETH
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OWL_SERIAL
 	select CLK
 	select CLK_OWL
@@ -923,20 +942,23 @@ config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
 	select DM
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	imply BOARD_EARLY_INIT_F
 	imply CMD_DM
 	imply FAT_WRITE
 	imply SYS_THUMB_BUILD
 	imply ARCH_MISC_INIT if DISPLAY_CPUINFO

+config TARGET_S32V234EVB
+	bool "Support s32v234evb"
+	select ARM64
+	select SYS_FSL_ERRATUM_ESDHC111
+
 config ARCH_SNAPDRAGON
 	bool "Qualcomm Snapdragon SoCs"
 	select ARM64
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select MSM_SMEM
 	select OF_CONTROL
 	select OF_SEPARATE
@@ -948,11 +970,10 @@ config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select ARCH_EARLY_INIT_R
 	select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
-	select ARM64 if TARGET_SOCFPGA_SOC64
+	select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select OF_CONTROL
 	select SPL_DM_RESET if DM_RESET
@@ -961,16 +982,16 @@ config ARCH_SOCFPGA
 	select SPL_LIBGENERIC_SUPPORT
 	select SPL_NAND_SUPPORT if SPL_NAND_DENALI
 	select SPL_OF_CONTROL
-	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
+	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	select SPL_SERIAL_SUPPORT
 	select SPL_SYSRESET
-	select SPL_WATCHDOG
+	select SPL_WATCHDOG_SUPPORT
 	select SUPPORT_SPL
 	select SYS_NS16550
 	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select SYSRESET
 	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
-	select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
+	select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
@@ -994,7 +1015,7 @@ config ARCH_SUNXI
 	select BINMAN
 	select CMD_GPIO
 	select CMD_MMC if MMC
-	select CMD_USB if DISTRO_DEFAULTS && USB_HOST
+	select CMD_USB if DISTRO_DEFAULTS
 	select CLK
 	select DM
 	select DM_ETH
@@ -1003,7 +1024,7 @@ config ARCH_SUNXI
 	select DM_MMC if MMC
 	select DM_SCSI if SCSI
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
+	select DM_USB if DISTRO_DEFAULTS
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
@@ -1015,8 +1036,8 @@ config ARCH_SUNXI
 	select SYS_NS16550
 	select SYS_THUMB_BUILD if !ARM64
 	select USB if DISTRO_DEFAULTS
-	select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
-	select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
+	select USB_KEYBOARD if DISTRO_DEFAULTS
+	select USB_STORAGE if DISTRO_DEFAULTS
 	select SPL_USE_TINY_PRINTF
 	select USE_PREBOOT
 	select SYS_RELOC_GD_ENV_ADDR
@@ -1029,11 +1050,11 @@ config ARCH_SUNXI
 	imply FIT
 	imply OF_LIBFDT_OVERLAY
 	imply PRE_CONSOLE_BUFFER
-	imply SPL_GPIO
+	imply SPL_GPIO_SUPPORT
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
 	imply SPL_MMC_SUPPORT if MMC
-	imply SPL_POWER
+	imply SPL_POWER_SUPPORT
 	imply SPL_SERIAL_SUPPORT
 	imply USB_GADGET

@@ -1044,6 +1065,7 @@ config ARCH_U8500
 	select DM_GPIO
 	select DM_MMC if MMC
 	select DM_SERIAL
+	select DM_USB if USB
 	select OF_CONTROL
 	select SYSRESET
 	select TIMER
@@ -1062,16 +1084,13 @@ config ARCH_VERSAL
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
-	select SOC_DEVICE
 	imply BOARD_LATE_INIT
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG

 config ARCH_VF610
 	bool "Freescale Vybrid"
 	select CPU_V7A
-	select GPIO_EXTRA_HEADER
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_MTDPARTS
 	imply MTD_RAW_NAND
@@ -1087,7 +1106,7 @@ config ARCH_ZYNQ
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
-	select GPIO_EXTRA_HEADER
+	select DM_USB if USB
 	select OF_CONTROL
 	select SPI
 	select SPL_BOARD_INIT if SPL
@@ -1114,7 +1133,6 @@ config ARCH_ZYNQMP_R5
 	select DM_ETH if NET
 	select DM_MMC if MMC
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	imply CMD_DM
 	imply DM_USB_GADGET
@@ -1130,8 +1148,8 @@ config ARCH_ZYNQMP
 	select DM_SERIAL
 	select DM_SPI if SPI
 	select DM_SPI_FLASH if DM_SPI
+	select DM_USB if USB
 	select FIRMWARE
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select SPL_BOARD_INIT if SPL
 	select SPL_CLK if SPL
@@ -1143,7 +1161,6 @@ config ARCH_ZYNQMP
 	select SPL_SEPARATE_BSS if SPL
 	select SUPPORT_SPL
 	select ZYNQMP_IPI
-	select SOC_DEVICE
 	imply BOARD_LATE_INIT
 	imply CMD_DM
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -1153,27 +1170,23 @@ config ARCH_ZYNQMP

 config ARCH_TEGRA
 	bool "NVIDIA Tegra"
-	select GPIO_EXTRA_HEADER
 	imply DISTRO_DEFAULTS
 	imply FAT_WRITE

 config TARGET_VEXPRESS64_AEMV8A
 	bool "Support vexpress_aemv8a"
 	select ARM64
-	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL

 config TARGET_VEXPRESS64_BASE_FVP
 	bool "Support Versatile Express ARMv8a FVP BASE model"
 	select ARM64
-	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	select SEMIHOSTING

 config TARGET_VEXPRESS64_JUNO
 	bool "Support Versatile Express Juno Development Platform"
 	select ARM64
-	select GPIO_EXTRA_HEADER
 	select PL01X_SERIAL
 	select DM
 	select OF_CONTROL
@@ -1185,6 +1198,7 @@ config TARGET_VEXPRESS64_JUNO
 	select DM_ETH
 	select BLK
 	select USB
+	select DM_USB

 config TARGET_TOTAL_COMPUTE
 	bool "Support Total Compute Platform"
@@ -1201,7 +1215,6 @@ config TARGET_LS2080A_EMU
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select FSL_DDR_SYNC_REFRESH
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS2080A_EMU platform.
 	  The LS2080A Development System (EMULATOR) is a pre-silicon
@@ -1215,7 +1228,6 @@ config TARGET_LS1088AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	select FSL_DDR_INTERACTIVE if !SD_BOOT
 	help
@@ -1231,7 +1243,6 @@ config TARGET_LS2080AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	imply SCSI
 	imply SCSI_AHCI
@@ -1253,7 +1264,6 @@ config TARGET_LS2080ARDB
 	select SUPPORT_SPL
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE if !SPL
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1268,7 +1278,6 @@ config TARGET_LS2081ARDB
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	select SUPPORT_SPL
 	help
 	  Support for Freescale LS2081ARDB platform.
@@ -1283,7 +1292,6 @@ config TARGET_LX2160ARDB
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LX2160ARDB platform.
 	  The lx2160ardb (LX2160A Reference design board (RDB)
@@ -1297,7 +1305,6 @@ config TARGET_LX2160AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LX2160AQDS platform.
 	  The lx2160aqds (LX2160A QorIQ Development System (QDS)
@@ -1312,7 +1319,6 @@ config TARGET_LX2162AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LX2162AQDS platform.
 	  The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
@@ -1323,7 +1329,6 @@ config TARGET_HIKEY
 	select DM
 	select DM_GPIO
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	select SPECIFY_CONSOLE_INDEX
@@ -1337,7 +1342,6 @@ config TARGET_HIKEY960
 	select ARM64
 	select DM
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	imply CMD_DM
@@ -1350,7 +1354,7 @@ config TARGET_POPLAR
 	select ARM64
 	select DM
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
+	select DM_USB
 	select OF_CONTROL
 	select PL01X_SERIAL
 	imply CMD_DM
@@ -1366,7 +1370,6 @@ config TARGET_LS1012AQDS
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1012AQDS platform.
 	  The LS1012A Development System (QDS) is a high-performance
@@ -1379,7 +1382,6 @@ config TARGET_LS1012ARDB
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1394,7 +1396,6 @@ config TARGET_LS1012A2G5RDB
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1012A2G5RDB platform.
@@ -1408,7 +1409,6 @@ config TARGET_LS1012AFRWY
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1422,7 +1422,6 @@ config TARGET_LS1012AFRDM
 	select ARCH_LS1012A
 	select ARM64
 	select ARCH_SUPPORT_TFABOOT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1012AFRDM platform.
 	  The LS1012A Freedom  board (FRDM) is a high-performance
@@ -1436,7 +1435,6 @@ config TARGET_LS1028AQDS
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1028AQDS platform
 	  The LS1028A Development System (QDS) is a high-performance
@@ -1450,7 +1448,6 @@ config TARGET_LS1028ARDB
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
 	select BOARD_LATE_INIT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1028ARDB platform
 	  The LS1028A Development System (RDB) is a high-performance
@@ -1466,7 +1463,6 @@ config TARGET_LS1088ARDB
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 	select FSL_DDR_INTERACTIVE if !SD_BOOT
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for NXP LS1088ARDB platform.
 	  The LS1088A Reference design board (RDB) is a high-performance
@@ -1487,7 +1483,6 @@ config TARGET_LS1021AQDS
 	select SYS_FSL_DDR
 	select FSL_DDR_INTERACTIVE
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
-	select GPIO_EXTRA_HEADER
 	select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
 	imply SCSI

@@ -1503,46 +1498,8 @@ config TARGET_LS1021ATWR
 	select LS1_DEEP_SLEEP
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
-	select GPIO_EXTRA_HEADER
 	imply SCSI

-config TARGET_PG_WCOM_SELI8
-	bool "Support Hitachi-Powergrids SELI8 service unit card"
-	select ARCH_LS1021A
-	select ARCH_SUPPORT_PSCI
-	select BOARD_EARLY_INIT_F
-	select BOARD_LATE_INIT
-	select CPU_V7A
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select SYS_FSL_DDR
-	select FSL_DDR_INTERACTIVE
-	select GPIO_EXTRA_HEADER
-	select VENDOR_KM
-	imply SCSI
-	help
-	 Support for Hitachi-Powergrids SELI8 service unit card.
-	 SELI8 is a QorIQ LS1021a based service unit card used
-	 in XMC20 and FOX615 product families.
-
-config TARGET_PG_WCOM_EXPU1
-	bool "Support Hitachi-Powergrids EXPU1 service unit card"
-	select ARCH_LS1021A
-	select ARCH_SUPPORT_PSCI
-	select BOARD_EARLY_INIT_F
-	select BOARD_LATE_INIT
-	select CPU_V7A
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select SYS_FSL_DDR
-	select FSL_DDR_INTERACTIVE
-	select VENDOR_KM
-	imply SCSI
-	help
-	 Support for Hitachi-Powergrids EXPU1 service unit card.
-	 EXPU1 is a QorIQ LS1021a based service unit card used
-	 in XMC20 and FOX615 product families.
-
 config TARGET_LS1021ATSN
 	bool "Support ls1021atsn"
 	select ARCH_LS1021A
@@ -1554,7 +1511,6 @@ config TARGET_LS1021ATSN
 	select CPU_V7_HAS_VIRT
 	select LS1_DEEP_SLEEP
 	select SUPPORT_SPL
-	select GPIO_EXTRA_HEADER
 	imply SCSI

 config TARGET_LS1021AIOT
@@ -1567,7 +1523,6 @@ config TARGET_LS1021AIOT
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
 	select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1021AIOT platform.
@@ -1587,7 +1542,6 @@ config TARGET_LS1043AQDS
 	select FSL_DDR_INTERACTIVE if !SPL
 	select FSL_DSPI if !SPL_NO_DSPI
 	select DM_SPI_FLASH if FSL_DSPI
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	imply SCSI_AHCI
 	help
@@ -1604,7 +1558,6 @@ config TARGET_LS1043ARDB
 	select SUPPORT_SPL
 	select FSL_DSPI if !SPL_NO_DSPI
 	select DM_SPI_FLASH if FSL_DSPI
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for Freescale LS1043ARDB platform.

@@ -1621,7 +1574,6 @@ config TARGET_LS1046AQDS
 	select FSL_DDR_BIST if !SPL
 	select FSL_DDR_INTERACTIVE  if !SPL
 	select FSL_DDR_INTERACTIVE if !SPL
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1046AQDS platform.
@@ -1642,7 +1594,6 @@ config TARGET_LS1046ARDB
 	select SUPPORT_SPL
 	select FSL_DDR_BIST
 	select FSL_DDR_INTERACTIVE if !SPL
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1046ARDB platform.
@@ -1659,7 +1610,6 @@ config TARGET_LS1046AFRWY
 	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 	select DM_SPI_FLASH if DM_SPI
-	select GPIO_EXTRA_HEADER
 	imply SCSI
 	help
 	  Support for Freescale LS1046AFRWY platform.
@@ -1674,33 +1624,12 @@ config TARGET_SL28
 	select ARMV8_MULTIENTRY
 	select SUPPORT_SPL
 	select BINMAN
-	select DM
-	select DM_GPIO
-	select DM_I2C
-	select DM_MMC
-	select DM_SPI_FLASH
-	select DM_ETH
-	select DM_MDIO
-	select PCI
-	select DM_RNG
-	select DM_RTC
-	select DM_SCSI
-	select DM_SERIAL
-	select DM_SPI
-	select GPIO_EXTRA_HEADER
-	select SPL_DM if SPL
-	select SPL_DM_SPI if SPL
-	select SPL_DM_SPI_FLASH if SPL
-	select SPL_DM_I2C if SPL
-	select SPL_DM_MMC if SPL
-	select SPL_DM_SERIAL if SPL
 	help
 	  Support for Kontron SMARC-sAL28 board.

 config TARGET_COLIBRI_PXA270
 	bool "Support colibri_pxa270"
 	select CPU_PXA
-	select GPIO_EXTRA_HEADER

 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
@@ -1713,6 +1642,7 @@ config ARCH_UNIPHIER
 	select DM_MTD
 	select DM_RESET
 	select DM_SERIAL
+	select DM_USB
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_LIBFDT
@@ -1731,25 +1661,11 @@ config ARCH_UNIPHIER
 	  Support for UniPhier SoC family developed by Socionext Inc.
 	  (formerly, System LSI Business Division of Panasonic Corporation)

-config ARCH_SYNQUACER
-	bool "Socionext SynQuacer SoCs"
-	select ARM64
-	select DM
-	select GIC_V3
-	select PSCI_RESET
-	select SYSRESET
-	select SYSRESET_PSCI
-	select OF_CONTROL
-	help
-	  Support for SynQuacer SoC family developed by Socionext Inc.
-	  This SoC is used on 96boards EE DeveloperBox.
-
 config ARCH_STM32
 	bool "Support STMicroelectronics STM32 MCU with cortex M"
 	select CPU_V7M
 	select DM
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	imply CMD_DM

 config ARCH_STI
@@ -1775,7 +1691,6 @@ config ARCH_STM32MP
 	select DM_GPIO
 	select DM_RESET
 	select DM_SERIAL
-	select GPIO_EXTRA_HEADER
 	select MISC
 	select OF_CONTROL
 	select OF_LIBFDT
@@ -1803,7 +1718,7 @@ config ARCH_STM32MP
 config ARCH_ROCKCHIP
 	bool "Support Rockchip SoCs"
 	select BLK
-	select BINMAN if SPL_OPTEE || (SPL && !ARM64)
+	select BINMAN if SPL_OPTEE
 	select DM
 	select DM_GPIO
 	select DM_I2C
@@ -1813,6 +1728,7 @@ config ARCH_ROCKCHIP
 	select DM_SERIAL
 	select DM_SPI
 	select DM_SPI_FLASH
+	select DM_USB if USB
 	select ENABLE_ARM_SOC_BOOT0_HOOK
 	select OF_CONTROL
 	select SPI
@@ -1837,7 +1753,6 @@ config ARCH_OCTEONTX
 	bool "Support OcteonTX SoCs"
 	select CLK
 	select DM
-	select GPIO_EXTRA_HEADER
 	select ARM64
 	select OF_CONTROL
 	select OF_LIVE
@@ -1848,7 +1763,6 @@ config ARCH_OCTEONTX2
 	bool "Support OcteonTX2 SoCs"
 	select CLK
 	select DM
-	select GPIO_EXTRA_HEADER
 	select ARM64
 	select OF_CONTROL
 	select OF_LIVE
@@ -1858,7 +1772,6 @@ config ARCH_OCTEONTX2
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
 	select ARM64
-	select GPIO_EXTRA_HEADER
 	select OF_CONTROL
 	select PL01X_SERIAL
 	select SYS_CACHE_SHIFT_7
@@ -1872,7 +1785,6 @@ config ARCH_ASPEED
 config TARGET_DURIAN
 	bool "Support Phytium Durian Platform"
 	select ARM64
-	select GPIO_EXTRA_HEADER
 	help
 	  Support for durian platform.
 	  It has 2GB Sdram, uart and pcie.
@@ -1982,8 +1894,6 @@ source "arch/arm/mach-imx/imx8/Kconfig"

 source "arch/arm/mach-imx/imx8m/Kconfig"

-source "arch/arm/mach-imx/imx8ulp/Kconfig"
-
 source "arch/arm/mach-imx/imxrt/Kconfig"

 source "arch/arm/mach-imx/mxs/Kconfig"
@@ -2050,15 +1960,24 @@ source "board/bosch/shc/Kconfig"
 source "board/bosch/guardian/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/gplugd/Kconfig"
 source "board/Marvell/octeontx/Kconfig"
 source "board/Marvell/octeontx2/Kconfig"
+source "board/armadeus/apf27/Kconfig"
+source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/cortina/presidio-asic/Kconfig"
+source "board/broadcom/bcm23550_w1d/Kconfig"
+source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcm963158/Kconfig"
 source "board/broadcom/bcm968360bg/Kconfig"
 source "board/broadcom/bcm968580xref/Kconfig"
+source "board/broadcom/bcmcygnus/Kconfig"
+source "board/broadcom/bcmnsp/Kconfig"
+source "board/broadcom/bcmns2/Kconfig"
 source "board/broadcom/bcmns3/Kconfig"
 source "board/cavium/thunderx/Kconfig"
+source "board/cirrus/edb93xx/Kconfig"
 source "board/eets/pdu001/Kconfig"
 source "board/emulation/qemu-arm/Kconfig"
 source "board/freescale/ls2080aqds/Kconfig"
@@ -2078,6 +1997,7 @@ source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/lx2160a/Kconfig"
+source "board/freescale/s32v234evb/Kconfig"
 source "board/grinn/chiliboard/Kconfig"
 source "board/hisilicon/hikey/Kconfig"
 source "board/hisilicon/hikey960/Kconfig"
@@ -2085,8 +2005,11 @@ source "board/hisilicon/poplar/Kconfig"
 source "board/isee/igep003x/Kconfig"
 source "board/kontron/sl28/Kconfig"
 source "board/myir/mys_6ulx/Kconfig"
-source "board/seeed/npi_imx6ull/Kconfig"
-source "board/socionext/developerbox/Kconfig"
+source "board/spear/spear300/Kconfig"
+source "board/spear/spear310/Kconfig"
+source "board/spear/spear320/Kconfig"
+source "board/spear/spear600/Kconfig"
+source "board/spear/x600/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/tcl/sl50/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
@@ -2094,7 +2017,6 @@ source "board/variscite/dart_6ul/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/phytium/durian/Kconfig"
 source "board/xen/xenguest_arm64/Kconfig"
-source "board/keymile/Kconfig"

 source "arch/arm/Kconfig.debug"

--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -107,11 +107,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/

 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imxrt))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imxrt vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -11,19 +11,12 @@ CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
 endif
 endif

-CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-		  -fstack-protector-strong
+CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
 CFLAGS_EFI := -fpic -fshort-wchar

-ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
 LDFLAGS_FINAL += --gc-sections
-endif
-
-ifndef CONFIG_LTO
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-endif
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r9
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
+		     -fno-common -ffixed-r9
 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
      $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))

--- a/arch/arm/cpu/arm920t/ep93xx/cpu.c
+++ b/arch/arm/cpu/arm920t/ep93xx/cpu.c
@@ -14,7 +14,7 @@
 #include <asm/io.h>

 /* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(void)
+extern void reset_cpu(ulong addr)
 {
 	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
 	uint32_t value;
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ b/arch/arm/cpu/arm920t/imx/timer.c
@@ -81,7 +81,7 @@ ulong get_tbclk(void)
 /*
 * Reset the cpu by setting up the watchdog timer and let him time out
 */
-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	/* Disable watchdog and set Time-Out field to 0 */
 	WCR = 0x00000000;
--- a/arch/arm/cpu/arm920t/start.S
+++ b/arch/arm/cpu/arm920t/start.S
@@ -35,7 +35,7 @@ reset:
 	orr	r0, r0, #0xd3
 	msr	cpsr, r0

-#if	defined(CONFIG_AT91RM9200DK)
+#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
 	/*
 	 * relocate exception table
 	 */
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -25,8 +25,6 @@ ifndef CONFIG_HAS_THUMB2

 CFLAGS_cpu.o := -marm
 CFLAGS_cache.o := -marm
-CFLAGS_REMOVE_cpu.o := $(LTO_CFLAGS)
-CFLAGS_REMOVE_cache.o := $(LTO_CFLAGS)

 endif
 endif
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -142,7 +142,7 @@ int timer_init(void)
 * 2. Write key value to TMP_WSAR reg.
 * 3. Perform write operation.
 */
-void reset_cpu(void)
+void reset_cpu(unsigned long ignored)
 {
 	struct armd1mpmu_registers *mpmu =
 		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
--- a/arch/arm/cpu/arm926ejs/mx25/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx25/reset.c
@@ -23,7 +23,7 @@
 /*
 * Reset the cpu by setting up the watchdog timer and let it time out
 */
-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */
--- a/arch/arm/cpu/arm926ejs/mx27/reset.c
+++ b/arch/arm/cpu/arm926ejs/mx27/reset.c
@@ -23,7 +23,7 @@
 /*
 * Reset the cpu by setting up the watchdog timer and let it time out
 */
-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
 	/* Disable watchdog and set Time-Out field to 0 */
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -25,7 +25,6 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/sections.h>
 #include <linux/compiler.h>

 DECLARE_GLOBAL_DATA_PTR;
@@ -33,9 +32,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 __weak void lowlevel_init(void) {}

-void reset_cpu(void) __attribute__((noreturn));
+void reset_cpu(ulong ignored) __attribute__((noreturn));

-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	struct mxs_rtc_regs *rtc_regs =
 		(struct mxs_rtc_regs *)MXS_RTC_BASE;
@@ -99,6 +98,7 @@ int arch_cpu_init(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
 		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	extern uint32_t _start;

 	mx28_fixup_vt((uint32_t)&_start);

--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -16,7 +16,6 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/sections.h>
 #include <linux/compiler.h>

 #include "mxs_init.h"
@@ -101,6 +100,7 @@ static void mxs_spl_fixup_vectors(void)
 	 * thus this fixup. Our vectoring table is PIC, so copying is
 	 * fine.
 	 */
+	extern uint32_t _start;

 	/* cppcheck-suppress nullPointer */
 	memcpy(0x0, &_start, 0x60);
@@ -122,7 +122,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
 {
 	struct mxs_spl_data *data = MXS_SPL_DATA;
 	uint8_t bootmode = mxs_get_bootmode_index();
-	set_gd(&gdata);
+	gd = &gdata;

 	mxs_spl_fixup_vectors();

--- a/arch/arm/cpu/arm926ejs/spear/Makefile
+++ b/arch/arm/cpu/arm926ejs/spear/Makefile
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y	:= cpu.o \
+	   reset.o \
+	   timer.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+obj-$(CONFIG_SPEAR600) += spear600.o
+obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
+obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
+obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
+obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+else
+obj-y += spr_misc.o spr_lowlevel_init.o
+endif
+
+extra-$(CONFIG_SPL_BUILD) := start.o
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+
+int arch_cpu_init(void)
+{
+	struct misc_regs *const misc_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 periph1_clken, periph_clk_cfg;
+
+	periph1_clken = readl(&misc_p->periph1_clken);
+
+#if defined(CONFIG_SPEAR3XX)
+	periph1_clken |= MISC_GPT2ENB;
+#elif defined(CONFIG_SPEAR600)
+	periph1_clken |= MISC_GPT3ENB;
+#endif
+
+#if defined(CONFIG_PL011_SERIAL)
+	periph1_clken |= MISC_UART0ENB;
+
+	periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+	periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
+#endif
+#if defined(CONFIG_ETH_DESIGNWARE)
+	periph1_clken |= MISC_ETHENB;
+#endif
+#if defined(CONFIG_DW_UDC)
+	periph1_clken |= MISC_USBDENB;
+#endif
+#if defined(CONFIG_SYS_I2C_DW)
+	periph1_clken |= MISC_I2CENB;
+#endif
+#if defined(CONFIG_ST_SMI)
+	periph1_clken |= MISC_SMIENB;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+	periph1_clken |= MISC_FSMCENB;
+#endif
+#if defined(CONFIG_USB_EHCI_SPEAR)
+	periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
+#endif
+#if defined(CONFIG_SPEAR_GPIO)
+	periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
+#endif
+#if defined(CONFIG_PL022_SPI)
+	periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
+#endif
+
+	writel(periph1_clken, &misc_p->periph1_clken);
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+#ifdef CONFIG_SPEAR300
+	printf("CPU:   SPEAr300\n");
+#elif defined(CONFIG_SPEAR310)
+	printf("CPU:   SPEAr310\n");
+#elif defined(CONFIG_SPEAR320)
+	printf("CPU:   SPEAr320\n");
+#elif defined(CONFIG_SPEAR600)
+	printf("CPU:   SPEAr600\n");
+#else
+#error CPU not supported in spear platform
+#endif
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
+static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	if (argc != 2)
+		goto usage;
+
+	if (strncmp(argv[1], "hw", 2) == 0) {
+		/* 1-bit HW ECC */
+		printf("Switching to 1-bit HW ECC\n");
+		fsmc_nand_switch_ecc(1);
+	} else if (strncmp(argv[1], "bch4", 2) == 0) {
+		/* 4-bit SW ECC BCH4 */
+		printf("Switching to 4-bit SW ECC (BCH4)\n");
+		fsmc_nand_switch_ecc(4);
+	} else {
+		goto usage;
+	}
+
+	return 0;
+
+usage:
+	printf("Usage: nandecc %s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	nandecc, 2, 0,	do_switch_ecc,
+	"switch NAND ECC calculation algorithm",
+	"hw|bch4 - Switch between NAND hardware 1-bit HW and"
+	" 4-bit SW BCH\n"
+);
+#endif
--- a/arch/arm/cpu/arm926ejs/spear/reset.c
+++ b/arch/arm/cpu/arm926ejs/spear/reset.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_syscntl.h>
+#include <linux/delay.h>
+
+void reset_cpu(ulong ignored)
+{
+	struct syscntl_regs *syscntl_regs_p =
+	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+	printf("System is going to reboot ...\n");
+
+	/*
+	 * This 1 second delay will allow the above message
+	 * to be printed before reset
+	 */
+	udelay((1000 * 1000));
+
+	/* Going into slow mode before resetting SOC */
+	writel(0x02, &syscntl_regs_p->scctrl);
+
+	/*
+	 * Writing any value to the system status register will
+	 * reset the SoC
+	 */
+	writel(0x00, &syscntl_regs_p->scsysstat);
+
+	/* system will restart */
+	while (1)
+		;
+}
--- a/arch/arm/cpu/arm926ejs/spear/spear600.c
+++ b/arch/arm/cpu/arm926ejs/spear/spear600.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2009
+ * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_defs.h>
+
+void spear_late_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(0x80000007, &misc_p->arb_icm_ml1);
+	writel(0x80000007, &misc_p->arb_icm_ml2);
+	writel(0x80000007, &misc_p->arb_icm_ml3);
+	writel(0x80000007, &misc_p->arb_icm_ml4);
+	writel(0x80000007, &misc_p->arb_icm_ml5);
+	writel(0x80000007, &misc_p->arb_icm_ml6);
+	writel(0x80000007, &misc_p->arb_icm_ml7);
+	writel(0x80000007, &misc_p->arb_icm_ml8);
+	writel(0x80000007, &misc_p->arb_icm_ml9);
+}
+
+static void sel_1v8(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000003;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000010;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+static void sel_2v5(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddr1v8, ddr2v5;
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000003;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000010;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
+		;
+}
+
+/*
+ * plat_ddr_init:
+ */
+void plat_ddr_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 ddrpad;
+	u32 core3v3, ddr1v8, ddr2v5;
+
+	/* DDR pad register configurations */
+	ddrpad = readl(&misc_p->ddr_pad);
+	ddrpad &= ~DDR_PAD_CNF_MSK;
+
+#if (CONFIG_DDR_HCLK)
+	ddrpad |= 0xEAAB;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpad |= 0xEAAD;
+#elif (CONFIG_DDR_PLL2)
+	ddrpad |= 0xEAAD;
+#endif
+	writel(ddrpad, &misc_p->ddr_pad);
+
+	/* Compensation register configurations */
+	core3v3 = readl(&misc_p->core_3v3_compensation);
+	core3v3 &= 0x8080ffe0;
+	core3v3 |= 0x78000002;
+	writel(core3v3, &misc_p->core_3v3_compensation);
+
+	ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+	ddr1v8 &= 0x8080ffc0;
+	ddr1v8 |= 0x78000004;
+	writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+	ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+	ddr2v5 &= 0x8080ffc0;
+	ddr2v5 |= 0x78000004;
+	writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+	if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
+		/* Software memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
+			sel_1v8();
+		else
+			sel_2v5();
+	} else {
+		/* Hardware memory configuration */
+		if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
+			sel_1v8();
+		else
+			sel_2v5();
+	}
+}
+
+/*
+ * xxx_boot_selected:
+ *
+ * return true if the particular booting option is selected
+ * return false otherwise
+ */
+static u32 read_bootstrap(void)
+{
+	return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
+		& CONFIG_SPEAR_BOOTSTRAPMASK;
+}
+
+int snor_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (SNOR_BOOT_SUPPORTED) {
+		/* Check whether SNOR boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
+			CONFIG_SPEAR_ONLYSNORBOOT)
+			return true;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return true;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return true;
+	}
+
+	return false;
+}
+
+int nand_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (NAND_BOOT_SUPPORTED) {
+		/* Check whether NAND boot is selected */
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND8BOOT)
+			return true;
+
+		if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+			CONFIG_SPEAR_NORNAND16BOOT)
+			return true;
+	}
+
+	return false;
+}
+
+int pnor_boot_selected(void)
+{
+	/* Parallel NOR boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int usb_boot_selected(void)
+{
+	u32 bootstrap = read_bootstrap();
+
+	if (USB_BOOT_SUPPORTED) {
+		/* Check whether USB boot is selected */
+		if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
+			return true;
+	}
+
+	return false;
+}
+
+int tftp_boot_selected(void)
+{
+	/* TFTP boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int uart_boot_selected(void)
+{
+	/* UART boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int spi_boot_selected(void)
+{
+	/* SPI boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int i2c_boot_selected(void)
+{
+	/* I2C boot is not selected in any SPEAr600 revision */
+	return false;
+}
+
+int mmc_boot_selected(void)
+{
+	return false;
+}
+
+void plat_late_init(void)
+{
+	spear_late_init();
+}
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/ptrace.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_syscntl.h>
+#include <linux/mtd/st_smi.h>
+
+/* Reserve some space to store the BootROM's stack pointer during SPL operation.
+ * The BSS cannot be used for this purpose because it will be zeroed after
+ * having stored the pointer, so force the location to the data section.
+ */
+u32 bootrom_stash_sp __attribute__((section(".data")));
+
+static void ddr_clock_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 clkenb, ddrpll;
+
+	clkenb = readl(&misc_p->periph1_clken);
+	clkenb &= ~PERIPH_MPMCMSK;
+	clkenb |= PERIPH_MPMC_WE;
+
+	/* Intentionally done twice */
+	writel(clkenb, &misc_p->periph1_clken);
+	writel(clkenb, &misc_p->periph1_clken);
+
+	ddrpll = readl(&misc_p->pll_ctr_reg);
+	ddrpll &= ~MEM_CLK_SEL_MSK;
+#if (CONFIG_DDR_HCLK)
+	ddrpll |= MEM_CLK_HCLK;
+#elif (CONFIG_DDR_2HCLK)
+	ddrpll |= MEM_CLK_2HCLK;
+#elif (CONFIG_DDR_PLL2)
+	ddrpll |= MEM_CLK_PLL2;
+#else
+#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
+#endif
+	writel(ddrpll, &misc_p->pll_ctr_reg);
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
+			&misc_p->periph1_clken);
+}
+
+static void mpmc_init_values(void)
+{
+	u32 i;
+	u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+	u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+	for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
+		writel(*mpmc_val_p, mpmc_reg_p);
+
+	mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+
+	/*
+	 * MPMC controller start
+	 * MPMC waiting for DLLLOCKREG high
+	 */
+	writel(0x01000100, &mpmc_reg_p[7]);
+
+	while (!(readl(&mpmc_reg_p[3]) & 0x10000))
+		;
+}
+
+static void mpmc_init(void)
+{
+	/* Clock related settings for DDR */
+	ddr_clock_init();
+
+	/*
+	 * DDR pad register bits are different for different SoCs
+	 * Compensation values are also handled separately
+	 */
+	plat_ddr_init();
+
+	/* Initialize mpmc register values */
+	mpmc_init_values();
+}
+
+static void pll_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	/* Initialize PLLs */
+	writel(FREQ_332, &misc_p->pll1_frq);
+	writel(0x1C0A, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+	writel(0x1C06, &misc_p->pll1_cntl);
+	writel(0x1C0E, &misc_p->pll1_cntl);
+
+	writel(FREQ_332, &misc_p->pll2_frq);
+	writel(0x1C0A, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+	writel(0x1C06, &misc_p->pll2_cntl);
+	writel(0x1C0E, &misc_p->pll2_cntl);
+
+	/* wait for pll locks */
+	while (!(readl(&misc_p->pll1_cntl) & 0x1))
+		;
+	while (!(readl(&misc_p->pll2_cntl) & 0x1))
+		;
+}
+
+static void mac_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
+			&misc_p->periph1_clken);
+
+	writel(SYNTH23, &misc_p->gmac_synth_clk);
+
+	switch (get_socrev()) {
+	case SOC_SPEAR600_AA:
+	case SOC_SPEAR600_AB:
+	case SOC_SPEAR600_BA:
+	case SOC_SPEAR600_BB:
+	case SOC_SPEAR600_BC:
+	case SOC_SPEAR600_BD:
+		writel(0x0, &misc_p->gmac_ctr_reg);
+		break;
+
+	case SOC_SPEAR300:
+	case SOC_SPEAR310:
+	case SOC_SPEAR320:
+		writel(0x4, &misc_p->gmac_ctr_reg);
+		break;
+	}
+
+	writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
+			&misc_p->periph1_clken);
+
+	writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
+			&misc_p->periph1_rst);
+	writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
+			&misc_p->periph1_rst);
+}
+
+static void sys_init(void)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct syscntl_regs *syscntl_p =
+		(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+	/* Set system state to SLOW */
+	writel(SLOW, &syscntl_p->scctrl);
+	writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
+
+	/* Initialize PLLs */
+	pll_init();
+
+	/*
+	 * Ethernet configuration
+	 * To be done only if the tftp boot is not selected already
+	 * Boot code ensures the correct configuration in tftp booting
+	 */
+	if (!tftp_boot_selected())
+		mac_init();
+
+	writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
+	writel(0x555, &misc_p->amba_clk_cfg);
+
+	writel(NORMAL, &syscntl_p->scctrl);
+
+	/* Wait for system to switch to normal mode */
+	while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
+		!= NORMAL)
+		;
+}
+
+/*
+ * get_socrev
+ *
+ * Get SoC Revision.
+ * @return SOC_SPEARXXX
+ */
+int get_socrev(void)
+{
+#if defined(CONFIG_SPEAR600)
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	u32 soc_id = readl(&misc_p->soc_core_id);
+	u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
+	u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
+
+	if ((pri_socid == 'B') && (sec_socid == 'B'))
+		return SOC_SPEAR600_BB;
+	else if ((pri_socid == 'B') && (sec_socid == 'C'))
+		return SOC_SPEAR600_BC;
+	else if ((pri_socid == 'B') && (sec_socid == 'D'))
+		return SOC_SPEAR600_BD;
+	else if (soc_id == 0)
+		return SOC_SPEAR600_BA;
+	else
+		return SOC_SPEAR_NA;
+#elif defined(CONFIG_SPEAR300)
+	return SOC_SPEAR300;
+#elif defined(CONFIG_SPEAR310)
+	return SOC_SPEAR310;
+#elif defined(CONFIG_SPEAR320)
+	return SOC_SPEAR320;
+#endif
+}
+
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+static void snor_init(void)
+{
+	struct smi_regs *const smicntl =
+		(struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+	/* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+	       &smicntl->smi_cr1);
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode = 0;
+
+	if (usb_boot_selected()) {
+		mode = BOOT_DEVICE_BOOTROM;
+	} else if (snor_boot_selected()) {
+		/* SNOR-SMI initialization */
+		snor_init();
+
+		mode = BOOT_DEVICE_NOR;
+	}
+
+	return mode;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	/*
+	 * If the main boot device (eg. NOR) is empty, try to jump back into the
+	 * BootROM for USB boot process.
+	 */
+	if (USB_BOOT_SUPPORTED)
+		spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
+}
+
+void board_init_f(ulong dummy)
+{
+	struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	/* Initialize PLLs */
+	sys_init();
+
+	preloader_console_init();
+	arch_cpu_init();
+
+	/* Enable IPs (release reset) */
+	writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
+
+	/* Initialize MPMC */
+	puts("Configure DDR\n");
+	mpmc_init();
+	spear_late_init();
+}
+
+/*
+ * In a few cases (Ethernet, UART or USB boot, we might want to go back into the
+ * BootROM code right after having initialized a few components like the DRAM).
+ * The following function is called from SPL common code (board_init_r).
+ */
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+			    struct spl_boot_device *bootdev)
+{
+	/*
+	 * Retrieve the BootROM's stack pointer and jump back to the start of
+	 * the SPL, where we can easily branch back into the BootROM. Don't do
+	 * it right here because SPL might be compiled in Thumb mode while the
+	 * BootROM expects ARM mode.
+	 */
+	asm volatile ("ldr r0, =bootrom_stash_sp;"
+		      "ldr r0, [r0];"
+		      "mov sp, r0;"
+#if defined(CONFIG_SPL_SYS_THUMB_BUILD)
+		      "blx back_to_bootrom;"
+#else
+		      "bl back_to_bootrom;"
+#endif
+		      );
+
+	return 0;
+}
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x00000001,
+	0x00000000,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02030202,
+	0x03000204,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00040800,
+	0x00000000,
+	0x00000f02,
+	0x00001b1b,
+	0x7f000000,
+	0x005f0000,
+	0x1c040b6a,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x000007ff,
+	0x00000000,
+	0x47ec00c8,
+	0x00c8001f,
+	0x00000000,
+	0x0000cd98,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00270000,
+	0x00250027,
+	0x00300000,
+	0x008900b7,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+	0x72000000,
+	0x00550000,
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+	0x03030301,
+	0x03030303,
+	0x01000000,
+	0x00000101,
+	0x00000001,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x00010001,
+	0x00000003,
+	0x01000201,
+	0x06000202,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+	0x02010106,
+	0x03000404,
+	0x02020202,
+	0x03000203,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x08080a01,
+	0x0000023f,
+	0x00030600,
+	0x00000000,
+	0x00000a02,
+	0x00001c1c,
+	0x7f000000,
+	0x005f0000,
+	0x12030743,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x0000050e,
+	0x00000000,
+	0x2d8900c8,
+	0x00c80014,
+	0x00000000,
+	0x00008236,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00400000,
+	0x003a0040,
+	0x00680000,
+	0x00d80120,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
--- a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+	0x00000001,
+	0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+	0x02020201,
+	0x02020202,
+#endif
+	0x01000000,
+	0x00000101,
+	0x00000101,
+	0x01000000,
+	0x00010001,
+	0x00000100,
+	0x01010001,
+	0x00000201,
+	0x01000101,
+	0x06000002,
+	0x06060106,
+	0x03050502,
+	0x03040404,
+	0x02020503,
+#ifdef CONFIG_X600
+	0x02030206,
+#else
+	0x02010106,
+#endif
+	0x03000405,
+	0x03040202,
+	0x04000305,
+	0x0707073f,
+	0x07070707,
+	0x06060607,
+	0x06060606,
+	0x05050506,
+	0x05050505,
+	0x04040405,
+	0x04040404,
+	0x03030304,
+	0x03030303,
+	0x02020203,
+	0x02020202,
+	0x01010102,
+	0x01010101,
+	0x0a0a0a01,
+	0x0000023f,
+	0x00050a00,
+	0x11000000,
+	0x00001302,
+	0x00000A0A,
+#ifdef CONFIG_X600
+	0x7f000000,
+	0x005c0000,
+#else
+	0x72000000,
+	0x00550000,
+#endif
+	0x2b050e86,
+	0x00640064,
+	0x00640064,
+	0x00640064,
+	0x00000064,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00200020,
+	0x00000a24,
+	0x43C20000,
+	0x5b1c00c8,
+	0x00c8002e,
+	0x00000000,
+	0x0001046b,
+	0x00000000,
+	0x03030100,
+	0x03030303,
+	0x03030303,
+	0x03030303,
+	0x00210000,
+	0x00010021,
+	0x00200000,
+	0x006c0090,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x003fffff,
+	0x003fffff,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+#endif
--- a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <config.h>
+
+/*
+ * platform specific initializations are already done in Xloader
+ * Initializations already done include
+ * DDR, PLLs, IP's clock enable and reset release etc
+ */
+.globl lowlevel_init
+lowlevel_init:
+	mov	pc, lr
+
+/* void setfreq(unsigned int device, unsigned int frequency) */
+.global setfreq
+setfreq:
+	stmfd 	sp!,{r14}
+	stmfd 	sp!,{r0-r12}
+
+	mov  	r8,sp
+	ldr 	sp,SRAM_STACK_V
+
+	/* Saving the function arguements for later use */
+	mov  	r4,r0
+	mov  	r5,r1
+
+	/* Putting DDR into self refresh */
+	ldr 	r0,DDR_07_V
+	ldr	r1,[r0]
+	ldr	r2,DDR_ACTIVE_V
+	bic	r1, r1, r2
+	str	r1,[r0]
+	ldr 	r0,DDR_57_V
+	ldr	r1,[r0]
+	ldr	r2,CYCLES_MASK_V
+	bic	r1, r1, r2
+	ldr	r2,REFRESH_CYCLES_V
+	orr	r1, r1, r2, lsl #16
+	str	r1,[r0]
+	ldr 	r0,DDR_07_V
+	ldr	r1,[r0]
+	ldr	r2,SREFRESH_MASK_V
+	orr	r1, r1, r2
+	str	r1,[r0]
+
+	/* flush pipeline */
+	b	flush
+	.align 5
+flush:
+	/* Delay to ensure self refresh mode */
+	ldr	r0,SREFRESH_DELAY_V
+delay:
+	sub	r0,r0,#1
+	cmp	r0,#0
+	bne	delay
+
+	/* Putting system in slow mode */
+	ldr	r0,SCCTRL_V
+	mov	r1,#2
+	str	r1,[r0]
+
+	/* Changing PLL(1/2) frequency */
+	mov	r0,r4
+	mov	r1,r5
+
+	cmp	r4,#0
+	beq	pll1_freq
+
+	/* Change PLL2 (DDR frequency) */
+	ldr	r6,PLL2_FREQ_V
+	ldr	r7,PLL2_CNTL_V
+	b	pll2_freq
+
+pll1_freq:
+	/* Change PLL1 (CPU frequency) */
+	ldr	r6,PLL1_FREQ_V
+	ldr	r7,PLL1_CNTL_V
+
+pll2_freq:
+	mov	r0,r6
+	ldr	r1,[r0]
+	ldr	r2,PLLFREQ_MASK_V
+	bic	r1,r1,r2
+	mov	r2,r5,lsr#1
+	orr	r1,r1,r2,lsl#24
+	str	r1,[r0]
+
+	mov	r0,r7
+	ldr	r1,P1C0A_V
+	str	r1,[r0]
+	ldr	r1,P1C0E_V
+	str	r1,[r0]
+	ldr	r1,P1C06_V
+	str	r1,[r0]
+	ldr	r1,P1C0E_V
+	str	r1,[r0]
+
+lock:
+	ldr	r1,[r0]
+	and	r1,r1,#1
+	cmp	r1,#0
+	beq	lock
+
+	/* Putting system back to normal mode */
+	ldr	r0,SCCTRL_V
+	mov	r1,#4
+	str	r1,[r0]
+
+	/* Putting DDR back to normal */
+	ldr	r0,DDR_07_V
+	ldr	r1,[R0]
+	ldr	r2,SREFRESH_MASK_V
+	bic	r1, r1, r2
+	str	r1,[r0]
+	ldr	r2,DDR_ACTIVE_V
+	orr	r1, r1, r2
+	str	r1,[r0]
+
+	/* Delay to ensure self refresh mode */
+	ldr	r0,SREFRESH_DELAY_V
+1:
+	sub	r0,r0,#1
+	cmp	r0,#0
+	bne	1b
+
+	mov	sp,r8
+	/* Resuming back to code */
+	ldmia	sp!,{r0-r12}
+	ldmia	sp!,{pc}
+
+SCCTRL_V:
+	.word 0xfca00000
+PLL1_FREQ_V:
+	.word 0xfca8000C
+PLL1_CNTL_V:
+	.word 0xfca80008
+PLL2_FREQ_V:
+	.word 0xfca80018
+PLL2_CNTL_V:
+	.word 0xfca80014
+PLLFREQ_MASK_V:
+	.word 0xff000000
+P1C0A_V:
+	.word 0x1C0A
+P1C0E_V:
+	.word 0x1C0E
+P1C06_V:
+	.word 0x1C06
+
+SREFRESH_DELAY_V:
+	.word 0x9999
+SRAM_STACK_V:
+	.word 0xD2800600
+DDR_07_V:
+	.word 0xfc60001c
+DDR_ACTIVE_V:
+	.word 0x01000000
+DDR_57_V:
+	.word 0xfc6000e4
+CYCLES_MASK_V:
+	.word 0xffff0000
+REFRESH_CYCLES_V:
+	.word 0xf0f0
+SREFRESH_MASK_V:
+	.word 0x00010000
+
+.global setfreq_sz
+setfreq_sz:
+	.word setfreq_sz - setfreq
--- a/arch/arm/cpu/arm926ejs/spear/spr_misc.c
+++ b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <linux/mtd/st_smi.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_emi.h>
+#include <asm/arch/spr_defs.h>
+
+#define CPU		0
+#define DDR		1
+#define SRAM_REL	0xD2801000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer);
+#endif
+
+int dram_init(void)
+{
+	/* Store complete RAM size and return */
+	gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
+int board_early_init_f()
+{
+#if defined(CONFIG_ST_SMI)
+	smi_init();
+#endif
+	return 0;
+}
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_NET)
+	uchar mac_id[6];
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
+		eth_env_set_enetaddr("ethaddr", mac_id);
+#endif
+	env_set("verify", "n");
+
+#if defined(CONFIG_SPEAR_USBTTY)
+	env_set("stdin", "usbtty");
+	env_set("stdout", "usbtty");
+	env_set("stderr", "usbtty");
+
+#ifndef CONFIG_SYS_NO_DCACHE
+	dcache_enable();
+#endif
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_SPEAR_EMI
+struct cust_emi_para {
+	unsigned int tap;
+	unsigned int tsdp;
+	unsigned int tdpw;
+	unsigned int tdpr;
+	unsigned int tdcs;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+	.tap = 0x10,
+	.tsdp = 0x05,
+	.tdpw = 0x0a,
+	.tdpr = 0x0a,
+	.tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+	.tap = 0xf,
+	.tsdp = 0x0,
+	.tdpw = 0xff,
+	.tdpr = 0x111,
+	.tdcs = 0x02,
+};
+
+void spear_emi_init(void)
+{
+	const struct cust_emi_para *p = &emi_timing_m28w640hc;
+	struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+	unsigned int cs;
+	unsigned int val, tmp;
+
+	val = readl(CONFIG_SPEAR_RASBASE);
+
+	if (val & EMI_ACKMSK)
+		tmp = 0x3f;
+	else
+		tmp = 0x0;
+
+	writel(tmp, &emi_regs_p->ack);
+
+	for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+		writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+		writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+		writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+		writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+		writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+		writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+		       &emi_regs_p->bank_regs[cs].control);
+	}
+}
+#endif
+
+int spear_board_init(ulong mach_type)
+{
+	gd->bd->bi_arch_number = mach_type;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
+
+#ifdef CONFIG_SPEAR_EMI
+	spear_emi_init();
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer)
+{
+	u8 buf[2];
+
+	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+	/* Check if mac in i2c memory is valid */
+	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+		/* Valid mac address is saved in i2c eeprom */
+		i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int write_mac(uchar *mac)
+{
+	u8 buf[2];
+
+	buf[0] = (u8)MAGIC_BYTE0;
+	buf[1] = (u8)MAGIC_BYTE1;
+	i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+	buf[0] = (u8)~MAGIC_BYTE0;
+	buf[1] = (u8)~MAGIC_BYTE1;
+
+	i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+	/* check if valid MAC address is saved in I2C EEPROM or not? */
+	if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+		i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
+		puts("I2C EEPROM written with mac address \n");
+		return 0;
+	}
+
+	puts("I2C EEPROM writing failed\n");
+	return -1;
+}
+#endif
+
+int do_chip_config(struct cmd_tbl *cmdtp, int flag, int argc,
+		   char *const argv[])
+{
+	void (*sram_setfreq) (unsigned int, unsigned int);
+	unsigned int frequency;
+#if defined(CONFIG_CMD_NET)
+	unsigned char mac[6];
+#endif
+
+	if ((argc > 3) || (argc < 2))
+		return cmd_usage(cmdtp);
+
+	if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
+
+		frequency = simple_strtoul(argv[2], NULL, 0);
+
+		if (frequency > 333) {
+			printf("Frequency is limited to 333MHz\n");
+			return 1;
+		}
+
+		sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
+
+		if (!strcmp(argv[1], "cpufreq")) {
+			sram_setfreq(CPU, frequency);
+			printf("CPU frequency changed to %u\n", frequency);
+		} else {
+			sram_setfreq(DDR, frequency);
+			printf("DDR frequency changed to %u\n", frequency);
+		}
+
+		return 0;
+
+#if defined(CONFIG_CMD_NET)
+	} else if (!strcmp(argv[1], "ethaddr")) {
+
+		u32 reg;
+		char *e, *s = argv[2];
+		for (reg = 0; reg < 6; ++reg) {
+			mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		write_mac(mac);
+
+		return 0;
+#endif
+	} else if (!strcmp(argv[1], "print")) {
+#if defined(CONFIG_CMD_NET)
+		if (!i2c_read_mac(mac)) {
+			printf("Ethaddr (from i2c mem) = %pM\n", mac);
+		} else {
+			printf("Ethaddr (from i2c mem) = Not set\n");
+		}
+#endif
+		return 0;
+	}
+
+	return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
+	   "configure chip",
+	   "chip_config cpufreq/ddrfreq frequency\n"
+#if defined(CONFIG_CMD_NET)
+	   "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
+#endif
+	   "chip_config print");
--- a/arch/arm/cpu/arm926ejs/spear/start.S
+++ b/arch/arm/cpu/arm926ejs/spear/start.S
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ */
+
+
+#include <config.h>
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * The BootROM already initialized its own stack in the [0-0xb00] reserved
+ * range of the SRAM. The SPL (in _main) will update the stack pointer to
+ * its own SRAM area (right before the gd section).
+ *
+ *************************************************************************
+ */
+
+	.globl	reset
+	.globl	back_to_bootrom
+
+reset:
+	/*
+	* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
+	* UART boot, USB boot): save registers in BootROM's stack and then the
+	* BootROM's stack pointer in the SPL's data section.
+	*/
+	push	{r0-r12,lr}
+	ldr	r0, =bootrom_stash_sp
+	str	sp, [r0]
+
+	/*
+	 * Flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* Flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* Flush v4 TLB */
+
+	/*
+	 * Enable instruction cache
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 * This call is not supposed to return.
+	 */
+	b	_main	/* _main will call board_init_f */
+
+back_to_bootrom:
+	pop	{r0-r12,pc}
--- a/arch/arm/cpu/arm926ejs/spear/timer.c
+++ b/arch/arm/cpu/arm926ejs/spear/timer.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <time.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_gpt.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/ptrace.h>
+#include <linux/delay.h>
+
+#define GPT_RESOLUTION	(CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
+#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
+
+static struct gpt_regs *const gpt_regs_p =
+    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
+
+static struct misc_regs *const misc_regs_p =
+    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_timer_masked(void);
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+int timer_init(void)
+{
+	u32 synth;
+
+	/* Prescaler setting */
+#if defined(CONFIG_SPEAR3XX)
+	writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
+	synth = MISC_GPT4SYNTH;
+#elif defined(CONFIG_SPEAR600)
+	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
+	synth = MISC_GPT3SYNTH;
+#else
+# error Incorrect config. Can only be SPEAR{600|300|310|320}
+#endif
+
+	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
+	       &misc_regs_p->periph_clk_cfg);
+
+	/* disable timers */
+	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
+
+	/* load value for free running */
+	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
+
+	/* auto reload, start timer */
+	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
+
+	/* Reset the timer */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+ulong get_timer(ulong base)
+{
+	return (get_timer_masked() / GPT_RESOLUTION) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_timer_masked();
+	ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
+	ulong rndoff;
+
+	rndoff = (usec % 10) ? 1 : 0;
+
+	/* tenudelcnt timer tick gives 10 microsecconds delay */
+	tmo = ((usec / 10) + rndoff) * tenudelcnt;
+
+	while ((ulong) (get_timer_masked() - start) < tmo)
+		;
+}
+
+static ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER();
+
+	if (now >= lastdec) {
+		/* normal mode */
+		timestamp += now - lastdec;
+	} else {
+		/* we have an overflow ... */
+		timestamp += now + GPT_FREE_RUNNING - lastdec;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SPEAR_HZ;
+}
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ */
+
+MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\
+		LENGTH = IMAGE_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		*(.vectors)
+		CPUDIR/spear/start.o	(.text*)
+		*(.text*)
+	} > .sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .sram
+}
--- a/arch/arm/cpu/arm946es/cpu.c
+++ b/arch/arm/cpu/arm946es/cpu.c
@@ -56,7 +56,7 @@ static void cache_flush (void)

 #ifndef CONFIG_ARCH_INTEGRATOR

-__attribute__((noreturn)) void reset_cpu(void)
+__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
 {
 	writew(0x0, 0xfffece10);
 	writew(0x8, 0xfffece10);
--- a/arch/arm/cpu/armv7/bcm281xx/reset.c
+++ b/arch/arm/cpu/armv7/bcm281xx/reset.c
@@ -13,7 +13,7 @@
 #define CLKS_SHIFT	20		/* Clock period shift */
 #define LD_SHIFT	0		/* Reload value shift */

-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	/*
 	 * Set WD enable, RST enable,
--- a/arch/arm/cpu/armv7/bcmcygnus/reset.c
+++ b/arch/arm/cpu/armv7/bcmcygnus/reset.c
@@ -10,7 +10,7 @@
 #define CRMU_MAIL_BOX1		0x03024028
 #define CRMU_SOFT_RESET_CMD	0xFFFFFFFF

-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	/* Send soft reset command via Mailbox. */
 	writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);
--- a/arch/arm/cpu/armv7/bcmnsp/reset.c
+++ b/arch/arm/cpu/armv7/bcmnsp/reset.c
@@ -9,7 +9,7 @@

 #define CRU_RESET_OFFSET	0x1803F184

-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	/* Reset the cpu by setting software reset request bit */
 	writel(0x1, CRU_RESET_OFFSET);
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -176,6 +176,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 {
 }

+void arm_init_domains(void)
+{
+}
 #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
--- a/arch/arm/cpu/armv7/iproc-common/armpll.c
+++ b/arch/arm/cpu/armv7/iproc-common/armpll.c
@@ -19,22 +19,19 @@ struct armpll_parameters {
 };

 struct armpll_parameters armpll_clk_tab[] = {
-	{   25,  64,      1, 1, 0},
-	{  100,  64,      1, 1, 2},
-	{  400,  64,      1, 1, 6},
-	{  448,  71, 713050, 1, 6},
-	{  500,  80,      1, 1, 6},
-	{  560,  89, 629145, 1, 6},
-	{  600,  96,      1, 1, 6},
-	{  800,  64,      1, 1, 7},
-	{  896,  71, 713050, 1, 7},
-	{ 1000,  80,      1, 1, 7},
-	{ 1100,  88,      1, 1, 7},
-	{ 1120,  89, 629145, 1, 7},
-	{ 1200,  96,      1, 1, 7},
-	{ 1300, 104,      1, 1, 7},
-	{ 1350, 108,      1, 1, 7},
-	{ 1400, 112,      1, 1, 7},
+	{   25, 64,      1, 1, 0},
+	{  100, 64,      1, 1, 2},
+	{  400, 64,      1, 1, 6},
+	{  448, 71, 713050, 1, 6},
+	{  500, 80,      1, 1, 6},
+	{  560, 89, 629145, 1, 6},
+	{  600, 96,      1, 1, 6},
+	{  800, 64,      1, 1, 7},
+	{  896, 71, 713050, 1, 7},
+	{ 1000, 80,      1, 1, 7},
+	{ 1100, 88,      1, 1, 7},
+	{ 1120, 89, 629145, 1, 7},
+	{ 1200, 96,      1, 1, 7},
 };

 uint32_t armpll_config(uint32_t clkmhz)
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -14,7 +14,7 @@ int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
 	return 0;
 }

-int __weak clk_bsc_enable(void *base)
+int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
 {
 	return 0;
 }
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -375,7 +375,7 @@ void smp_kick_all_cpus(void)
 }
 #endif

-void reset_cpu(void)
+void reset_cpu(ulong addr)
 {
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;

--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -13,7 +13,7 @@
 #include <fsl_immap.h>
 #include "fsl_epu.h"

-#define __secure __section("._secure.text")
+#define __secure __attribute__((section("._secure.text")))

 #define CCSR_GICD_CTLR			0x1000
 #define CCSR_GICC_CTLR			0x2000
--- a/arch/arm/cpu/armv7/s5p4418/cpu.c
+++ b/arch/arm/cpu/armv7/s5p4418/cpu.c
@@ -88,7 +88,7 @@ int print_cpuinfo(void)
 }
 #endif

-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
 	const u32 sw_rst_enb_bitpos = 3;
--- a/arch/arm/cpu/armv7/stv0991/reset.c
+++ b/arch/arm/cpu/armv7/stv0991/reset.c
@@ -9,7 +9,7 @@
 #include <asm/io.h>
 #include <asm/arch/stv0991_wdru.h>
 #include <linux/delay.h>
-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	puts("System is going to reboot ...\n");
 	/*
--- a/arch/arm/cpu/armv7m/cpu.c
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -47,7 +47,7 @@ int cleanup_before_linux(void)
 /*
 * Perform the low-level reset.
 */
-void reset_cpu(void)
+void reset_cpu(ulong addr)
 {
 	/*
 	 * Perform reset but keep priority group unchanged.
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -116,7 +116,7 @@ config PSCI_RESET
 		   !TARGET_LS1046AFRWY && \
 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
 		   !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
-		   !ARCH_UNIPHIER
+		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through
 	  ARM Trusted Firmware or other firmware.
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -188,24 +188,27 @@ ENDPROC(__asm_invalidate_icache_all)
 .popsection

 .pushsection .text.__asm_invalidate_l3_dcache, "ax"
-WEAK(__asm_invalidate_l3_dcache)
+ENTRY(__asm_invalidate_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_invalidate_l3_dcache)
+	.weak	__asm_invalidate_l3_dcache
 .popsection

 .pushsection .text.__asm_flush_l3_dcache, "ax"
-WEAK(__asm_flush_l3_dcache)
+ENTRY(__asm_flush_l3_dcache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_flush_l3_dcache)
+	.weak	__asm_flush_l3_dcache
 .popsection

 .pushsection .text.__asm_invalidate_l3_icache, "ax"
-WEAK(__asm_invalidate_l3_icache)
+ENTRY(__asm_invalidate_l3_icache)
 	mov	x0, #0			/* return status as success */
 	ret
 ENDPROC(__asm_invalidate_l3_icache)
+	.weak	__asm_invalidate_l3_icache
 .popsection

 /*
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -719,11 +719,6 @@ int icache_status(void)
 	return (get_sctlr() & CR_I) != 0;
 }

-int mmu_status(void)
-{
-	return (get_sctlr() & CR_M) != 0;
-}
-
 void invalidate_icache_all(void)
 {
 	__asm_invalidate_icache_all();
@@ -745,11 +740,6 @@ int icache_status(void)
 	return 0;
 }

-int mmu_status(void)
-{
-	return 0;
-}
-
 void invalidate_icache_all(void)
 {
 }
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -47,8 +47,6 @@ config ARCH_LS1028A
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 	select SYS_FSL_ERRATUM_A050382
-	select SYS_FSL_ERRATUM_A011334
-	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
 	select RESV_RAM if GIC_V3_ITS
 	imply PANIC_HANG

@@ -58,7 +56,6 @@ config ARCH_LS1043A
 	select ARM_ERRATA_855873 if !TFABOOT
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
-	select HAS_FSL_XHCI_USB if USB_HOST
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -90,7 +87,6 @@ config ARCH_LS1046A
 	select ARMV8_SET_SMPEN
 	select FSL_LAYERSCAPE
 	select FSL_LSCH2
-	select HAS_FSL_XHCI_USB if USB_HOST
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR
@@ -225,9 +221,7 @@ config ARCH_LX2162A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_EC1
 	select SYS_FSL_EC2
-	select SYS_FSL_ERRATUM_A050204
-	select SYS_FSL_ERRATUM_A011334
-	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
+	select SYS_FSL_ERRATUM_A050106
 	select SYS_FSL_HAS_RGMII
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_HAS_CCN508
@@ -247,7 +241,6 @@ config ARCH_LX2160A
 	bool
 	select ARMV8_SET_SMPEN
 	select FSL_LSCH3
-	select HAS_FSL_XHCI_USB if USB_HOST
 	select NXP_LSCH3_2
 	select SYS_HAS_SERDES
 	select SYS_FSL_SRDS_1
@@ -258,9 +251,7 @@ config ARCH_LX2160A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_EC1
 	select SYS_FSL_EC2
-	select SYS_FSL_ERRATUM_A050204
-	select SYS_FSL_ERRATUM_A011334
-	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
+	select SYS_FSL_ERRATUM_A050106
 	select SYS_FSL_HAS_RGMII
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_HAS_CCN508
@@ -378,8 +369,8 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
 	bool "Workaround for USB PHY erratum A009798"

-config SYS_FSL_ERRATUM_A050204
-	bool "Workaround for USB PHY erratum A050204"
+config SYS_FSL_ERRATUM_A050106
+	bool "Workaround for USB PHY erratum A050106"
 	help
 	  USB3.0 Receiver needs to enable fixed equalization
 	  for each of PHY instances in an SOC. This is similar
@@ -645,16 +636,7 @@ config SPL_LDSCRIPT

 config HAS_FSL_XHCI_USB
 	bool
+	default y if ARCH_LS1043A || ARCH_LS1046A
 	help
-	  For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
+	  For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
 	  pins, select it when the pins are assigned to USB.
-
-config SYS_FSL_BOOTROM_BASE
-	hex
-	depends on FSL_LSCH2
-	default 0
-
-config SYS_FSL_BOOTROM_SIZE
-	hex
-	depends on FSL_LSCH2
-	default 0x1000000
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1063,7 +1063,7 @@ int cpu_eth_init(struct bd_info *bis)
 	return error;
 }

-int check_psci(void)
+static inline int check_psci(void)
 {
 	unsigned int psci_ver;

@@ -1231,7 +1231,7 @@ int timer_init(void)

 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;

-void __efi_runtime reset_cpu(void)
+void __efi_runtime reset_cpu(ulong addr)
 {
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	/* clear the RST_REQ_MSK and SW_RST_REQ */
@@ -1260,7 +1260,7 @@ void __efi_runtime EFIAPI efi_reset_system(
 	case EFI_RESET_COLD:
 	case EFI_RESET_WARM:
 	case EFI_RESET_PLATFORM_SPECIFIC:
-		reset_cpu();
+		reset_cpu(0);
 		break;
 	case EFI_RESET_SHUTDOWN:
 		/* Nothing we can do */
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
@@ -6,4 +6,3 @@
 int fsl_qoriq_core_to_cluster(unsigned int core);
 u32 initiator_type(u32 cluster, int init_id);
 u32 cpu_mask(void);
-int check_psci(void);
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2020-2021 NXP
+ * Copyright 2020 NXP
 */

 #include <common.h>
@@ -478,151 +478,6 @@ static bool crypto_is_disabled(unsigned int svr)
 	return false;
 }

-#ifdef CONFIG_FSL_PFE
-void pfe_set_firmware_in_fdt(void *blob, int pfenode, void *pfw, char *pename,
-			     unsigned int len)
-{
-	int rc, fwnode;
-	unsigned int phandle;
-	char subnode_str[32], prop_str[32], phandle_str[32], s[64];
-
-	sprintf(subnode_str, "pfe-%s-firmware", pename);
-	sprintf(prop_str, "fsl,pfe-%s-firmware", pename);
-	sprintf(phandle_str, "fsl,%s-firmware", pename);
-
-	/*Add PE FW to fdt.*/
-	/* Increase the size of the fdt to make room for the node. */
-	rc = fdt_increase_size(blob, len);
-	if (rc < 0) {
-		printf("Unable to make room for %s firmware: %s\n", pename,
-		       fdt_strerror(rc));
-		return;
-	}
-
-	/* Create the firmware node. */
-	fwnode = fdt_add_subnode(blob, pfenode, subnode_str);
-	if (fwnode < 0) {
-		fdt_get_path(blob, pfenode, s, sizeof(s));
-		printf("Could not add firmware node to %s: %s\n", s,
-		       fdt_strerror(fwnode));
-		return;
-	}
-
-	rc = fdt_setprop_string(blob, fwnode, "compatible", prop_str);
-	if (rc < 0) {
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add compatible property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-
-	rc = fdt_setprop_u32(blob, fwnode, "length", len);
-	if (rc < 0) {
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add compatible property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-
-	/*create phandle and set the property*/
-	phandle = fdt_create_phandle(blob, fwnode);
-	if (!phandle) {
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add phandle property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-
-	rc = fdt_setprop(blob, fwnode, phandle_str, pfw, len);
-	if (rc < 0) {
-		fdt_get_path(blob, fwnode, s, sizeof(s));
-		printf("Could not add firmware property to node %s: %s\n", s,
-		       fdt_strerror(rc));
-		return;
-	}
-}
-
-void fdt_fixup_pfe_firmware(void *blob)
-{
-	int pfenode;
-	unsigned int len_class = 0, len_tmu = 0, len_util = 0;
-	const char *p;
-	void *pclassfw, *ptmufw, *putilfw;
-
-	/* The first PFE we find, will contain the actual firmware. */
-	pfenode = fdt_node_offset_by_compatible(blob, -1, "fsl,pfe");
-	if (pfenode < 0)
-		/* Exit silently if there are no PFE devices */
-		return;
-
-	/* If we already have a firmware node, then also exit silently. */
-	if (fdt_node_offset_by_compatible(blob, -1,
-					  "fsl,pfe-class-firmware") > 0)
-		return;
-
-	/* If the environment variable is not set, then exit silently */
-	p = env_get("class_elf_firmware");
-	if (!p)
-		return;
-
-	pclassfw = (void *)hextoul(p, NULL);
-	if (!pclassfw)
-		return;
-
-	p = env_get("class_elf_size");
-	if (!p)
-		return;
-	len_class = hextoul(p, NULL);
-
-	/* If the environment variable is not set, then exit silently */
-	p = env_get("tmu_elf_firmware");
-	if (!p)
-		return;
-
-	ptmufw = (void *)hextoul(p, NULL);
-	if (!ptmufw)
-		return;
-
-	p = env_get("tmu_elf_size");
-	if (!p)
-		return;
-	len_tmu = hextoul(p, NULL);
-
-	if (len_class == 0 || len_tmu == 0) {
-		printf("PFE FW corrupted. CLASS FW size %d, TMU FW size %d\n",
-		       len_class, len_tmu);
-		return;
-	}
-
-	/*Add CLASS FW to fdt.*/
-	pfe_set_firmware_in_fdt(blob, pfenode, pclassfw, "class", len_class);
-
-	/*Add TMU FW to fdt.*/
-	pfe_set_firmware_in_fdt(blob, pfenode, ptmufw, "tmu", len_tmu);
-
-	/* Util PE firmware is handled separately as it is not a usual case*/
-	p = env_get("util_elf_firmware");
-	if (!p)
-		return;
-
-	putilfw = (void *)hextoul(p, NULL);
-	if (!putilfw)
-		return;
-
-	p = env_get("util_elf_size");
-	if (!p)
-		return;
-	len_util = hextoul(p, NULL);
-
-	if (len_util) {
-		printf("PFE Util PE firmware is not added to FDT.\n");
-		return;
-	}
-
-	pfe_set_firmware_in_fdt(blob, pfenode, putilfw, "util", len_util);
-}
-#endif
-
 void ft_cpu_setup(void *blob, struct bd_info *bd)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -679,9 +534,6 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
-#ifdef CONFIG_FSL_PFE
-	fdt_fixup_pfe_firmware(blob);
-#endif
 #ifndef CONFIG_ARCH_LS1012A
 	fsl_fdt_disable_usb(blob);
 #endif
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -10,12 +10,10 @@
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
-#include <asm/ptrace.h>
 #include <asm/system.h>
 #include <asm/arch/mp.h>
 #include <asm/arch/soc.h>
 #include <linux/delay.h>
-#include <linux/psci.h>
 #include "cpu.h"
 #include <asm/arch-fsl-layerscape/soc.h>
 #include <efi_loader.h>
@@ -303,41 +301,24 @@ int cpu_release(u32 nr, int argc, char *const argv[])
 	u64 *table = get_spin_tbl_addr();
 	int pos;

+	pos = core_to_pos(nr);
+	if (pos <= 0)
+		return -1;
+
+	table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
 	boot_addr = simple_strtoull(argv[0], NULL, 16);
-
-	if (check_psci()) {
-		/* SPIN Table is used */
-		pos = core_to_pos(nr);
-		if (pos <= 0)
-			return -1;
-
-		table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
-		table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
-		flush_dcache_range((unsigned long)table,
+	table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
+	flush_dcache_range((unsigned long)table,
 			   (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
-		asm volatile("dsb st");
+	asm volatile("dsb st");

-		/*
-		 * The secondary CPUs polling the spin-table above for a non-zero
-		 * value. To save power "wfe" is called. Thus call "sev" here to
-		 * wake the CPUs and let them check the spin-table again (see
-		 * slave_cpu loop in lowlevel.S)
-		 */
-		asm volatile("sev");
-	} else {
-		/* Use PSCI to kick the core */
-		struct pt_regs regs;
-
-		printf("begin to kick cpu core #%d to address %llx\n",
-		       nr, boot_addr);
-		regs.regs[0] = PSCI_0_2_FN64_CPU_ON;
-		regs.regs[1] = nr;
-		regs.regs[2] = boot_addr;
-		regs.regs[3] = 0;
-		smc_call(&regs);
-		if (regs.regs[0])
-			return -1;
-	}
+	/*
+	 * The secondary CPUs polling the spin-table above for a non-zero
+	 * value. To save power "wfe" is called. Thus call "sev" here to
+	 * wake the CPUs and let them check the spin-table again (see
+	 * slave_cpu loop in lowlevel.S)
+	 */
+	asm volatile("sev");

 	return 0;
 }
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
 * Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2020 NXP
 */

 #include <common.h>
@@ -218,7 +218,7 @@ static void erratum_a009007(void)
 }

 #if defined(CONFIG_FSL_LSCH3)
-static void erratum_a050204(void)
+static void erratum_a050106(void)
 {
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 	void __iomem *dcsr = (void __iomem *)DCSR_BASE;
@@ -277,7 +277,7 @@ static unsigned long get_internval_val_mhz(void)
 	ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);

 	if (interval)
-		interval_mhz = dectoul(interval, NULL);
+		interval_mhz = simple_strtoul(interval, NULL, 10);

 	return interval_mhz;
 }
@@ -329,7 +329,7 @@ static void erratum_rcw_src(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
 static void erratum_a009203(void)
 {
-#ifdef CONFIG_SYS_I2C_LEGACY
+#ifdef CONFIG_SYS_I2C
 	u8 __iomem *ptr;
 #ifdef I2C1_BASE_ADDR
 	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
@@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void)
 	erratum_a009798();
 	erratum_a008997();
 	erratum_a009007();
-	erratum_a050204();
+	erratum_a050106();
 #ifdef CONFIG_CHAIN_OF_TRUST
 	/* In case of Secure Boot, the IBR configures the SMMU
 	* to allow only Secure transactions.
@@ -953,15 +953,12 @@ int board_late_init(void)
 #endif
 #ifdef CONFIG_TFABOOT
 	/*
-	 * Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
-	 * not exists in env
+	 * Set bootcmd and mcinitcmd if they don't exist in the environment.
 	 */
-	if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
-		// Set bootcmd and mcinitcmd as per boot source
+	if (!env_get("bootcmd"))
 		fsl_setenv_bootcmd();
+	if (!env_get("mcinitcmd"))
 		fsl_setenv_mcinitcmd();
-		env_set("fsl_bootcmd_mcinitcmd_set", "y");
-	}
 #endif
 #ifdef CONFIG_QSPI_AHB_INIT
 	qspi_ahb_init();
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -6,9 +6,7 @@
 #include <common.h>
 #include <clock_legacy.h>
 #include <cpu_func.h>
-#include <debug_uart.h>
 #include <env.h>
-#include <hang.h>
 #include <image.h>
 #include <init.h>
 #include <log.h>
@@ -41,6 +39,9 @@ u32 spl_boot_device(void)

 #ifdef CONFIG_SPL_BUILD

+/* Define board data structure */
+static struct bd_info bdata __attribute__ ((section(".data")));
+
 void spl_board_init(void)
 {
 #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
@@ -66,19 +67,10 @@ void spl_board_init(void)

 void board_init_f(ulong dummy)
 {
-	int ret;
-
 	icache_enable();
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
-	if (IS_ENABLED(CONFIG_DEBUG_UART))
-		debug_uart_init();
 	board_early_init_f();
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
 	timer_init();
 #ifdef CONFIG_ARCH_LS2080A
 	env_init();
@@ -86,10 +78,10 @@ void board_init_f(ulong dummy)
 	get_clocks();

 	preloader_console_init();
-	spl_set_bd();
+	gd->bd = &bdata;

-#ifdef CONFIG_SYS_I2C_LEGACY
-#ifdef CONFIG_SPL_I2C
+#ifdef CONFIG_SYS_I2C
+#ifdef CONFIG_SPL_I2C_SUPPORT
 	i2c_init_all();
 #endif
 #endif
@@ -147,4 +139,13 @@ int spl_start_uboot(void)
 	return 1;
 }
 #endif	/* CONFIG_SPL_OS_BOOT */
+#ifdef CONFIG_SPL_LOAD_FIT
+__weak int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
 #endif /* CONFIG_SPL_BUILD */
--- a/arch/arm/cpu/armv8/s32v234/Makefile
+++ b/arch/arm/cpu/armv8/s32v234/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+
+obj-y += generic.o
+obj-y += cpu.o
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/mc_me_regs.h>
+#include <linux/bitops.h>
+#include "cpu.h"
+
+u32 cpu_mask(void)
+{
+	return readl(MC_ME_CS);
+}
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+
+#define S32V234_IRAM_BASE        0x3e800000UL
+#define S32V234_IRAM_SIZE        0x800000UL
+#define S32V234_DRAM_BASE1       0x80000000UL
+#define S32V234_DRAM_SIZE1       0x40000000UL
+#define S32V234_DRAM_BASE2       0xC0000000UL
+#define S32V234_DRAM_SIZE2       0x20000000UL
+#define S32V234_PERIPH_BASE      0x40000000UL
+#define S32V234_PERIPH_SIZE      0x40000000UL
+
+static struct mm_region s32v234_mem_map[] = {
+	{
+		.virt = S32V234_IRAM_BASE,
+		.phys = S32V234_IRAM_BASE,
+		.size = S32V234_IRAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		.virt = S32V234_DRAM_BASE1,
+		.phys = S32V234_DRAM_BASE1,
+		.size = S32V234_DRAM_SIZE1,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		.virt = S32V234_PERIPH_BASE,
+		.phys = S32V234_PERIPH_BASE,
+		.size = S32V234_PERIPH_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE
+			 /* TODO: Do we need these? */
+			 /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
+	}, {
+		.virt = S32V234_DRAM_BASE2,
+		.phys = S32V234_DRAM_BASE2,
+		.size = S32V234_DRAM_SIZE2,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = s32v234_mem_map;
+
+#endif
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+	int numcores;
+	u32 mask;
+
+	mask = cpu_mask();
+	numcores = hweight32(cpu_mask());
+
+	/* Verify if M4 is deactivated */
+	if (mask & 0x1)
+		numcores--;
+
+	return numcores;
+}
+
+#if defined(CONFIG_ARCH_EARLY_INIT_R)
+int arch_early_init_r(void)
+{
+	int rv;
+	asm volatile ("dsb sy");
+	rv = fsl_s32v234_wake_seconday_cores();
+
+	if (rv)
+		printf("Did not wake secondary cores\n");
+
+	asm volatile ("sev");
+	return 0;
+}
+#endif /* CONFIG_ARCH_EARLY_INIT_R */
--- a/arch/arm/cpu/armv8/s32v234/cpu.h
+++ b/arch/arm/cpu/armv8/s32v234/cpu.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
+ */
+
+u32 cpu_mask(void);
+int cpu_numcores(void);
--- a/arch/arm/cpu/armv8/s32v234/generic.c
+++ b/arch/arm/cpu/armv8/s32v234/generic.c
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <clock_legacy.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <net.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mc_cgm_regs.h>
+#include <asm/arch/mc_me_regs.h>
+#include <asm/arch/mc_rgm_regs.h>
+#include <netdev.h>
+#include <div64.h>
+#include <errno.h>
+
+u32 get_cpu_rev(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
+	u32 cpu = readl(&mscmir->cpxtype);
+
+	return cpu;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
+			     u32 pllfd, u32 selected_output)
+{
+	u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
+	u32 plldv_rfdphi_div = 0, fout = 0;
+	u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
+
+	if (selected_output > DFS_MAXNUMBER) {
+		return -1;
+	}
+
+	plldv_prediv =
+	    (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
+	plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
+
+	pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
+
+	plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
+
+	/* The formula for VCO is from TR manual, rev. D */
+	vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
+
+	if (selected_output != 0) {
+		/* Determine the RFDPHI for PHI1 */
+		plldv_rfdphi_div =
+		    (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
+		    PLLDIG_PLLDV_RFDPHI1_OFFSET;
+		plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
+		if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
+			dfs_portn =
+			    readl(DFS_DVPORTn(pll, selected_output - 1));
+			dfs_mfi =
+			    (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
+			    DFS_DVPORTn_MFI_OFFSET;
+			dfs_mfn =
+			    (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
+			    DFS_DVPORTn_MFI_OFFSET;
+			fout = vco / (dfs_mfi + (dfs_mfn / 256));
+		} else {
+			fout = vco / plldv_rfdphi_div;
+		}
+
+	} else {
+		/* Determine the RFDPHI for PHI0 */
+		plldv_rfdphi_div =
+		    (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
+		    PLLDIG_PLLDV_RFDPHI_OFFSET;
+		fout = vco / plldv_rfdphi_div;
+	}
+
+	return fout;
+
+}
+
+/* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
+static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
+			    u32 selected_output)
+{
+	u32 plldv, pllfd;
+
+	plldv = readl(PLLDIG_PLLDV(pll));
+	pllfd = readl(PLLDIG_PLLFD(pll));
+
+	return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
+}
+
+static u32 get_mcu_main_clk(void)
+{
+	u32 coreclk_div;
+	u32 sysclk_sel;
+	u32 freq = 0;
+
+	sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
+	sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
+
+	coreclk_div =
+	    readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
+	coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
+	coreclk_div += 1;
+
+	switch (sysclk_sel) {
+	case MC_CGM_SC_SEL_FIRC:
+		freq = FIRC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_XOSC:
+		freq = XOSC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_ARMPLL:
+		/* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
+		freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
+		break;
+	case MC_CGM_SC_SEL_CLKDISABLE:
+		printf("Sysclk is disabled\n");
+		break;
+	default:
+		printf("unsupported system clock select\n");
+	}
+
+	return freq / coreclk_div;
+}
+
+static u32 get_sys_clk(u32 number)
+{
+	u32 sysclk_div, sysclk_div_number;
+	u32 sysclk_sel;
+	u32 freq = 0;
+
+	switch (number) {
+	case 3:
+		sysclk_div_number = 0;
+		break;
+	case 6:
+		sysclk_div_number = 1;
+		break;
+	default:
+		printf("unsupported system clock \n");
+		return -1;
+	}
+	sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
+	sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
+
+	sysclk_div =
+	    readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
+	    MC_CGM_SC_DCn_PREDIV_MASK;
+	sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
+	sysclk_div += 1;
+
+	switch (sysclk_sel) {
+	case MC_CGM_SC_SEL_FIRC:
+		freq = FIRC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_XOSC:
+		freq = XOSC_CLK_FREQ;
+		break;
+	case MC_CGM_SC_SEL_ARMPLL:
+		/* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
+		freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
+		break;
+	case MC_CGM_SC_SEL_CLKDISABLE:
+		printf("Sysclk is disabled\n");
+		break;
+	default:
+		printf("unsupported system clock select\n");
+	}
+
+	return freq / sysclk_div;
+}
+
+static u32 get_peripherals_clk(void)
+{
+	u32 aux5clk_div;
+	u32 freq = 0;
+
+	aux5clk_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	aux5clk_div += 1;
+
+	freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
+
+	return freq / aux5clk_div;
+
+}
+
+static u32 get_uart_clk(void)
+{
+	u32 auxclk3_div, auxclk3_sel, freq = 0;
+
+	auxclk3_sel =
+	    readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
+	auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
+
+	auxclk3_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	auxclk3_div += 1;
+
+	switch (auxclk3_sel) {
+	case MC_CGM_ACn_SEL_FIRC:
+		freq = FIRC_CLK_FREQ;
+		break;
+	case MC_CGM_ACn_SEL_XOSC:
+		freq = XOSC_CLK_FREQ;
+		break;
+	case MC_CGM_ACn_SEL_PERPLLDIVX:
+		freq = get_peripherals_clk() / 3;
+		break;
+	case MC_CGM_ACn_SEL_SYSCLK:
+		freq = get_sys_clk(6);
+		break;
+	default:
+		printf("unsupported system clock select\n");
+	}
+
+	return freq / auxclk3_div;
+}
+
+static u32 get_fec_clk(void)
+{
+	u32 aux2clk_div;
+	u32 freq = 0;
+
+	aux2clk_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	aux2clk_div += 1;
+
+	freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
+
+	return freq / aux2clk_div;
+}
+
+static u32 get_usdhc_clk(void)
+{
+	u32 aux15clk_div;
+	u32 freq = 0;
+
+	aux15clk_div =
+	    readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
+	    MC_CGM_ACn_DCm_PREDIV_MASK;
+	aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
+	aux15clk_div += 1;
+
+	freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
+
+	return freq / aux15clk_div;
+}
+
+static u32 get_i2c_clk(void)
+{
+	return get_peripherals_clk();
+}
+
+/* return clocks in Hz */
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_mcu_main_clk();
+	case MXC_PERIPHERALS_CLK:
+		return get_peripherals_clk();
+	case MXC_UART_CLK:
+		return get_uart_clk();
+	case MXC_FEC_CLK:
+		return get_fec_clk();
+	case MXC_I2C_CLK:
+		return get_i2c_clk();
+	case MXC_USDHC_CLK:
+		return get_usdhc_clk();
+	default:
+		break;
+	}
+	printf("Error: Unsupported function to read the frequency! \
+			Please define it correctly!");
+	return -1;
+}
+
+/* Not yet implemented - int soc_clk_dump(); */
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static char *get_reset_cause(void)
+{
+	u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
+
+	switch (cause) {
+	case F_SWT4:
+		return "WDOG";
+	case F_JTAG:
+		return "JTAG";
+	case F_FCCU_SOFT:
+		return "FCCU soft reaction";
+	case F_FCCU_HARD:
+		return "FCCU hard reaction";
+	case F_SOFT_FUNC:
+		return "Software Functional reset";
+	case F_ST_DONE:
+		return "Self Test done reset";
+	case F_EXT_RST:
+		return "External reset";
+	default:
+		return "unknown reset";
+	}
+
+}
+
+#define SRC_SCR_SW_RST					(1<<12)
+
+void reset_cpu(ulong addr)
+{
+	printf("Feature not supported.\n");
+};
+
+int print_cpuinfo(void)
+{
+	printf("CPU:   Freescale Treerunner S32V234 at %d MHz\n",
+	       mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("Reset cause: %s\n", get_reset_cause());
+
+	return 0;
+}
+#endif
+
+int cpu_eth_init(struct bd_info * bis)
+{
+	int rc = -ENODEV;
+
+#if defined(CONFIG_FEC_MXC)
+	rc = fecmxc_initialize(bis);
+#endif
+
+	return rc;
+}
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC_IMX
+	gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
+#endif
+	return 0;
+}
--- a/arch/arm/cpu/armv8/spl_data.c
+++ b/arch/arm/cpu/armv8/spl_data.c
@@ -6,8 +6,8 @@
 #include <common.h>
 #include <spl.h>

-char __data_save_start[0] __section(".__data_save_start");
-char __data_save_end[0] __section(".__data_save_end");
+char __data_save_start[0] __section(.__data_save_start);
+char __data_save_end[0] __section(.__data_save_end);

 u32 cold_reboot_flag = 1;

--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -127,25 +127,20 @@ pie_fixup_done:
 	orr	x0, x0, #0xf			/* SCR_EL3.NS|IRQ|FIQ|EA */
 	msr	scr_el3, x0
 	msr	cptr_el3, xzr			/* Enable FP/SIMD */
-	b	0f
-2:	mrs	x1, hcr_el2
-	tbnz	x1, #34, 1f			/* HCR_EL2.E2H */
-	set_vbar vbar_el2, x0
-	mov	x0, #0x33ff
-	msr	cptr_el2, x0			/* Enable FP/SIMD */
-	b	0f
-1:	set_vbar vbar_el1, x0
-	mov	x0, #3 << 20
-	msr	cpacr_el1, x0			/* Enable FP/SIMD */
-0:
-
 #ifdef COUNTER_FREQUENCY
-	branch_if_not_highest_el x0, 4f
 	ldr	x0, =COUNTER_FREQUENCY
 	msr	cntfrq_el0, x0			/* Initialize CNTFRQ */
 #endif
-
-4:	isb
+	b	0f
+2:	set_vbar	vbar_el2, x0
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0			/* Enable FP/SIMD */
+	b	0f
+1:	set_vbar	vbar_el1, x0
+	mov	x0, #3 << 20
+	msr	cpacr_el1, x0			/* Enable FP/SIMD */
+0:
+	isb

 	/*
 	 * Enable SMPEN bit for coherency.
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -77,7 +77,6 @@ SECTIONS
 		KEEP(*(.__bss_end));
 	} >.sdram

-	/DISCARD/ : { *(.rela*) }
 	/DISCARD/ : { *(.dynsym) }
 	/DISCARD/ : { *(.dynstr*) }
 	/DISCARD/ : { *(.dynamic*) }
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -267,9 +267,9 @@ void i2c_clk_enable(void)
 	writel(readl(CKEN) | CKEN14_I2C, CKEN);
 }

-void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
+void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));

-void reset_cpu(void)
+void reset_cpu(ulong ignored)
 {
 	uint32_t tmp;

--- a/arch/arm/cpu/sa1100/cpu.c
+++ b/arch/arm/cpu/sa1100/cpu.c
@@ -55,7 +55,7 @@ static void cache_flush (void)
 #define RSRR	0x00
 #define RCSR	0x04

-__attribute__((noreturn)) void reset_cpu(void)
+__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
 {
 	/* repeat endlessly */
 	while (1) {
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -56,7 +56,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \
 	kirkwood-ns2lite.dtb \
 	kirkwood-ns2max.dtb \
 	kirkwood-ns2mini.dtb \
-	kirkwood-nsa310s.dtb \
 	kirkwood-openrd-base.dtb \
 	kirkwood-openrd-client.dtb \
 	kirkwood-openrd-ultimate.dtb \
@@ -115,7 +114,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
 	rk3328-rock-pi-e.dtb

 dtb-$(CONFIG_ROCKCHIP_RK3368) += \
-	rk3368-lion-haikou.dtb \
+	rk3368-lion.dtb \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \
 	rk3368-px5-evb.dtb \
@@ -132,9 +131,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-nanopc-t4.dtb \
 	rk3399-nanopi-m4.dtb \
 	rk3399-nanopi-m4-2gb.dtb \
-	rk3399-nanopi-m4b.dtb \
 	rk3399-nanopi-neo4.dtb \
-	rk3399-nanopi-r4s.dtb \
 	rk3399-orangepi.dtb \
 	rk3399-pinebook-pro.dtb \
 	rk3399-puma-haikou.dtb \
@@ -147,9 +144,6 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-rockpro64.dtb \
 	rk3399pro-rock-pi-n10.dtb

-dtb-$(CONFIG_ROCKCHIP_RK3568) += \
-	rk3568-evb.dtb
-
 dtb-$(CONFIG_ROCKCHIP_RV1108) += \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb
@@ -205,6 +199,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
 	tegra124-venice2.dtb \
 	tegra186-p2771-0000-000.dtb \
 	tegra186-p2771-0000-500.dtb \
+	tegra210-e2220-1170.dtb \
 	tegra210-p2371-0000.dtb \
 	tegra210-p2371-2180.dtb \
 	tegra210-p2571.dtb \
@@ -240,22 +235,12 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 	armada-xp-gp.dtb			\
 	armada-xp-maxbcm.dtb			\
 	armada-xp-synology-ds414.dtb		\
-	armada-xp-theadorable.dtb		\
-	cn9130-db-A.dtb				\
-	cn9130-db-B.dtb				\
-	cn9131-db-A.dtb				\
-	cn9131-db-B.dtb				\
-	cn9132-db-A.dtb				\
-	cn9132-db-B.dtb				\
-	cn9130-crb-A.dtb			\
-	cn9130-crb-B.dtb
+	armada-xp-theadorable.dtb

-dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
 	uniphier-ld11-global.dtb \
 	uniphier-ld11-ref.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \
-	uniphier-ld20-akebi96.dtb \
 	uniphier-ld20-global.dtb \
 	uniphier-ld20-ref.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \
@@ -317,10 +302,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-mini-emmc1.dtb			\
 	zynqmp-mini-nand.dtb			\
 	zynqmp-mini-qspi.dtb			\
-	zynqmp-sm-k26-revA.dtb			\
-	zynqmp-smk-k26-revA.dtb			\
-	zynqmp-sck-kv-g-revA.dtbo		\
-	zynqmp-sck-kv-g-revB.dtbo		\
 	zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb	\
 	zynqmp-zcu100-revC.dtb			\
 	zynqmp-zcu102-revA.dtb			\
@@ -366,7 +347,6 @@ dtb-$(CONFIG_AM33XX) += \
 	am335x-pocketbeagle.dtb \
 	am335x-pxm50.dtb \
 	am335x-rut.dtb \
-	am335x-sancloud-bbe.dtb \
 	am335x-shc.dtb \
 	am335x-pdu001.dtb \
 	am335x-chiliboard.dtb \
@@ -400,7 +380,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
 	socfpga_cyclone5_vining_fpga.dtb		\
-	socfpga_n5x_socdk.dtb				\
 	socfpga_stratix10_socdk.dtb

 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb	\
@@ -418,9 +397,6 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
 	ls1021a-qds-lpuart.dtb \
 	ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
 	ls1021a-iot-duart.dtb ls1021a-tsn.dtb
-dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb
-dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb
-
 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-qds-42-x.dtb \
 	fsl-ls2080a-rdb.dtb \
@@ -478,8 +454,7 @@ dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
 	stm32f769-disco.dtb \
 	stm32746g-eval.dtb
 dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
-	stm32h743i-eval.dtb \
-	stm32h750i-art-pi.dtb
+	stm32h743i-eval.dtb

 dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-a1000.dtb \
@@ -616,8 +591,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-plus.dtb \
 	sun8i-h3-orangepi-plus2e.dtb \
 	sun8i-h3-orangepi-zero-plus2.dtb \
-	sun8i-h3-rervision-dvk.dtb \
-	sun8i-h3-zeropi.dtb
+	sun8i-h3-rervision-dvk.dtb
 dtb-$(CONFIG_MACH_SUN8I_R40) += \
 	sun8i-r40-bananapi-m2-ultra.dtb \
 	sun8i-v40-bananapi-m2-berry.dtb
@@ -674,24 +648,12 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 	vf610-pcm052.dtb \
 	vf610-bk4r1.dtb

-dtb-$(CONFIG_MX23) += \
-	imx23-evk.dtb
-
-dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \
-	imx23-olinuxino.dtb
-
 dtb-$(CONFIG_MX28) += \
-	imx28-evk.dtb \
 	imx28-xea.dtb

-dtb-$(CONFIG_MX51) += \
-	imx51-babbage.dtb
-
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
-	imx53-qsb.dtb \
 	imx53-kp.dtb \
-	imx53-m53menlo.dtb \
-	imx53-usbarmory.dtb
+	imx53-m53menlo.dtb

 ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
 dtb-y += \
@@ -702,20 +664,6 @@ dtb-y += \
 	imx6dl-cubox-i-emmc-som-v15.dtb \
 	imx6dl-cubox-i-som-v15.dtb \
 	imx6dl-dhcom-pdk2.dtb \
-	imx6dl-gw51xx.dtb \
-	imx6dl-gw52xx.dtb \
-	imx6dl-gw53xx.dtb \
-	imx6dl-gw54xx.dtb \
-	imx6dl-gw551x.dtb \
-	imx6dl-gw552x.dtb \
-	imx6dl-gw553x.dtb \
-	imx6dl-gw560x.dtb \
-	imx6dl-gw5903.dtb \
-	imx6dl-gw5904.dtb \
-	imx6dl-gw5907.dtb \
-	imx6dl-gw5910.dtb \
-	imx6dl-gw5912.dtb \
-	imx6dl-gw5913.dtb \
 	imx6dl-hummingboard2.dtb \
 	imx6dl-hummingboard2-emmc-som-v15.dtb \
 	imx6dl-hummingboard2-som-v15.dtb \
@@ -730,8 +678,6 @@ dtb-y += \
 	imx6dl-mamoj.dtb \
 	imx6dl-nitrogen6x.dtb \
 	imx6dl-pico.dtb \
-	imx6dl-udoo.dtb \
-	imx6dl-riotboard.dtb \
 	imx6dl-sabreauto.dtb \
 	imx6dl-sabresd.dtb \
 	imx6dl-wandboard-revd1.dtb \
@@ -747,20 +693,6 @@ dtb-y += \
 	imx6q-cubox-i-som-v15.dtb \
 	imx6q-dhcom-pdk2.dtb \
 	imx6q-display5.dtb \
-	imx6q-gw51xx.dtb \
-	imx6q-gw52xx.dtb \
-	imx6q-gw53xx.dtb \
-	imx6q-gw54xx.dtb \
-	imx6q-gw551x.dtb \
-	imx6q-gw552x.dtb \
-	imx6q-gw553x.dtb \
-	imx6q-gw560x.dtb \
-	imx6q-gw5903.dtb \
-	imx6q-gw5904.dtb \
-	imx6q-gw5907.dtb \
-	imx6q-gw5910.dtb \
-	imx6q-gw5912.dtb \
-	imx6q-gw5913.dtb \
 	imx6q-hummingboard2.dtb \
 	imx6q-hummingboard2-emmc-som-v15.dtb \
 	imx6q-hummingboard2-som-v15.dtb \
@@ -772,7 +704,6 @@ dtb-y += \
 	imx6q-icore-rqs.dtb \
 	imx6q-kp.dtb \
 	imx6q-logicpd.dtb \
-	imx6q-marsboard.dtb \
 	imx6q-mba6a.dtb \
 	imx6q-mba6b.dtb \
 	imx6q-mccmon6.dtb\
@@ -780,7 +711,6 @@ dtb-y += \
 	imx6q-novena.dtb \
 	imx6q-pico.dtb \
 	imx6q-phytec-mira-rdk-nand.dtb \
-	imx6q-udoo.dtb \
 	imx6q-sabreauto.dtb \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
@@ -799,10 +729,7 @@ dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
 dtb-$(CONFIG_MX6SX) += \
 	imx6sx-sabreauto.dtb \
 	imx6sx-sdb.dtb \
-	imx6sx-softing-vining-2000.dtb \
-	imx6sx-udoo-neo-basic.dtb \
-	imx6sx-udoo-neo-extended.dtb \
-	imx6sx-udoo-neo-full.dtb
+	imx6sx-softing-vining-2000.dtb

 dtb-$(CONFIG_MX6UL) += \
 	imx6ul-geam.dtb \
@@ -821,7 +748,6 @@ dtb-$(CONFIG_MX6ULL) += \
 	imx6ull-14x14-evk.dtb \
 	imx6ull-colibri.dtb \
 	imx6ull-myir-mys-6ulx-eval.dtb \
-	imx6ull-seeed-npi-imx6ull-dev-board.dtb \
 	imx6ull-phytec-segin-ff-rdk-emmc.dtb \
 	imx6ull-dart-6ul.dtb \
 	imx6ull-somlabs-visionsom.dtb \
@@ -831,22 +757,15 @@ dtb-$(CONFIG_ARCH_MX6) += \
 	imx6-apalis.dtb \
 	imx6-colibri.dtb

-dtb-$(CONFIG_O4_IMX_NANO) += \
-	o4-imx-nano.dtb
-
-dtb-$(CONFIG_EV_IMX280_NANO_X_MB) += \
-	ev-imx280-nano-x-mb.dtb
-
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 	imx7d-sdb-qspi.dtb \
-	imx7-cm.dtb \
 	imx7-colibri-emmc.dtb \
 	imx7-colibri-rawnand.dtb \
 	imx7s-warp.dtb \
 	imx7d-meerkat96.dtb \
 	imx7d-pico-pi.dtb \
-	imx7d-pico-hobbit.dtb \
-	imx7d-smegw01.dtb
+	imx7d-pico-hobbit.dtb
+

 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
 	imx7ulp-evk.dtb
@@ -854,7 +773,6 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
 dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-apalis.dtb \
 	fsl-imx8qm-mek.dtb \
-	imx8qm-cgtqmx8.dtb \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
@@ -863,24 +781,11 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	imx8-deneb.dtb \
 	imx8-giedi.dtb

-dtb-$(CONFIG_ARCH_IMX8ULP) += \
-	imx8ulp-evk.dtb
-
 dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-evk.dtb \
-	imx8mm-icore-mx8mm-ctouch2.dtb \
-	imx8mm-icore-mx8mm-edimm2.2.dtb \
-	imx8mm-venice.dtb \
-	imx8mm-venice-gw71xx-0x.dtb \
-	imx8mm-venice-gw72xx-0x.dtb \
-	imx8mm-venice-gw73xx-0x.dtb \
-	imx8mm-venice-gw7901.dtb \
-	imx8mm-venice-gw7902.dtb \
 	imx8mm-verdin.dtb \
 	phycore-imx8mm.dtb \
 	imx8mn-ddr4-evk.dtb \
-	imx8mq-cm.dtb \
-	imx8mn-evk.dtb \
 	imx8mq-evk.dtb \
 	imx8mm-beacon-kit.dtb \
 	imx8mn-beacon-kit.dtb \
@@ -906,10 +811,6 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a774a1-beacon-rzg2m-kit.dtb \
 	r8a774b1-beacon-rzg2n-kit.dtb \
 	r8a774e1-beacon-rzg2h-kit.dtb \
-	r8a774a1-hihope-rzg2m-u-boot.dtb \
-	r8a774b1-hihope-rzg2n-u-boot.dtb \
-	r8a774c0-ek874-u-boot.dtb \
-	r8a774e1-hihope-rzg2h-u-boot.dtb \
 	r8a77950-ulcb-u-boot.dtb \
 	r8a77950-salvator-x-u-boot.dtb \
 	r8a77960-ulcb-u-boot.dtb \
@@ -919,8 +820,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a77970-eagle-u-boot.dtb \
 	r8a77980-condor-u-boot.dtb \
 	r8a77990-ebisu-u-boot.dtb \
-	r8a77995-draak-u-boot.dtb \
-	r8a779a0-falcon-u-boot.dtb
+	r8a77995-draak-u-boot.dtb

 ifdef CONFIG_RCAR_GEN3
 DTC_FLAGS += -R 4 -p 0x1000
@@ -1077,10 +977,6 @@ dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
 dtb-$(CONFIG_STM32MP15x) += \
 	stm32mp157a-dk1.dtb \
 	stm32mp157a-avenger96.dtb \
-	stm32mp157a-icore-stm32mp1-ctouch2.dtb \
-	stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
-	stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
-	stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
 	stm32mp157c-dk2.dtb \
 	stm32mp157c-ed1.dtb \
 	stm32mp157c-ev1.dtb \
@@ -1095,10 +991,6 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
 			      k3-j721e-r5-common-proc-board.dtb \
 			      k3-j7200-common-proc-board.dtb \
 			      k3-j7200-r5-common-proc-board.dtb
-dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
-			      k3-am642-r5-evm.dtb \
-			      k3-am642-sk.dtb \
-			      k3-am642-r5-sk.dtb

 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
@@ -1106,7 +998,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-bananapi-bpi-r64.dtb \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7629-rfb.dtb \
-	mt8183-pumpkin.dtb \
 	mt8512-bm1-emmc.dtb \
 	mt8516-pumpkin.dtb \
 	mt8518-ap1-emmc.dtb
@@ -1120,20 +1011,20 @@ dtb-$(CONFIG_TARGET_GE_BX50V3) += \
 dtb-$(CONFIG_TARGET_GE_B1X5V2) += imx6dl-b1x5v2.dtb
 dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb

+dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
+dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
+dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
+
 dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb

 dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb

 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb

-dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
-
-dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
-
 targets += $(dtb-y)

 # Add any required device tree compiler flags here
-DTC_FLAGS += -a 0x8
+DTC_FLAGS +=

 PHONY += dtbs
 dtbs: $(addprefix $(obj)/, $(dtb-y))
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -1,6 +1,9 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
 */

 / {
@@ -10,44 +13,44 @@
 		};
 	};

-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x10000000>; /* 256 MB */
-	};
-
 	chosen {
 		stdout-path = &uart0;
 		tick-timer = &timer2;
 	};

+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
 	leds {
 		pinctrl-names = "default";
 		pinctrl-0 = <&user_leds_s0>;

 		compatible = "gpio-leds";

-		led2 {
+		led@2 {
 			label = "beaglebone:green:heartbeat";
 			gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 			default-state = "off";
 		};

-		led3 {
+		led@3 {
 			label = "beaglebone:green:mmc0";
 			gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 			default-state = "off";
 		};

-		led4 {
+		led@4 {
 			label = "beaglebone:green:usr2";
 			gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "cpu0";
 			default-state = "off";
 		};

-		led5 {
+		led@5 {
 			label = "beaglebone:green:usr3";
 			gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc1";
@@ -55,7 +58,7 @@
 		};
 	};

-	vmmcsd_fixed: fixedregulator0 {
+	vmmcsd_fixed: fixedregulator@0 {
 		compatible = "regulator-fixed";
 		regulator-name = "vmmcsd_fixed";
 		regulator-min-microvolt = <3300000>;
@@ -69,118 +72,112 @@

 	user_leds_s0: user_leds_s0 {
 		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a5.gpio1_21 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gpmc_a6.gpio1_22 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a7.gpio1_23 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gpmc_a8.gpio1_24 */
+			0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
+			0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
+			0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a7.gpio1_23 */
+			0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_a8.gpio1_24 */
 		>;
 	};

 	i2c0_pins: pinmux_i2c0_pins {
 		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)	/* i2c0_sda.i2c0_sda */
-			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 		>;
 	};

 	i2c2_pins: pinmux_i2c2_pins {
 		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_ctsn.i2c2_sda */
-			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_rtsn.i2c2_scl */
+			0x178 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_ctsn.i2c2_sda */
+			0x17c (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_rtsn.i2c2_scl */
 		>;
 	};

 	uart0_pins: pinmux_uart0_pins {
 		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
 		>;
 	};

 	clkout2_pin: pinmux_clkout2_pin {
 		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
 		>;
 	};

 	cpsw_default: cpsw_default {
 		pinctrl-single,pins = <
 			/* Slave 1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
+			0x110 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxerr.mii1_rxerr */
+			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen.mii1_txen */
+			0x118 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxdv.mii1_rxdv */
+			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3.mii1_txd3 */
+			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2.mii1_txd2 */
+			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1.mii1_txd1 */
+			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0.mii1_txd0 */
+			0x12c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_txclk.mii1_txclk */
+			0x130 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxclk.mii1_rxclk */
+			0x134 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd3.mii1_rxd3 */
+			0x138 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd2.mii1_rxd2 */
+			0x13c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd1.mii1_rxd1 */
+			0x140 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd0.mii1_rxd0 */
 		>;
 	};

 	cpsw_sleep: cpsw_sleep {
 		pinctrl-single,pins = <
 			/* Slave 1 reset value */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 		>;
 	};

 	davinci_mdio_default: davinci_mdio_default {
 		pinctrl-single,pins = <
 			/* MDIO */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
+			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
 		>;
 	};

 	davinci_mdio_sleep: davinci_mdio_sleep {
 		pinctrl-single,pins = <
 			/* MDIO reset value */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
+			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 		>;
 	};

 	mmc1_pins: pinmux_mmc1_pins {
 		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)		/* spio0_cs1.gpio0_6 */
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+			0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
 		>;
 	};

 	emmc_pins: pinmux_emmc_pins {
 		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
-			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+			0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+			0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+			0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+			0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+			0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+			0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+			0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+			0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+			0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+			0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
 		>;
 	};
 };
@@ -192,16 +189,36 @@
 	status = "okay";
 };

+&usb {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb1_phy {
+	status = "okay";
+};
+
 &usb0 {
+	status = "okay";
 	dr_mode = "peripheral";
-	interrupts-extended = <&intc 18 &tps 0>;
-	interrupt-names = "mc", "vbus";
 };

 &usb1 {
+	status = "okay";
 	dr_mode = "host";
 };

+&cppi41dma  {
+	status = "okay";
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pins>;
@@ -214,7 +231,7 @@
 	};

 	baseboard_eeprom: baseboard_eeprom@50 {
-		compatible = "atmel,24c256";
+		compatible = "at,24c256";
 		reg = <0x50>;

 		#address-cells = <1>;
@@ -233,7 +250,7 @@
 	clock-frequency = <100000>;

 	cape_eeprom0: cape_eeprom0@54 {
-		compatible = "atmel,24c256";
+		compatible = "at,24c256";
 		reg = <0x54>;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -243,7 +260,7 @@
 	};

 	cape_eeprom1: cape_eeprom1@55 {
-		compatible = "atmel,24c256";
+		compatible = "at,24c256";
 		reg = <0x55>;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -253,7 +270,7 @@
 	};

 	cape_eeprom2: cape_eeprom2@56 {
-		compatible = "atmel,24c256";
+		compatible = "at,24c256";
 		reg = <0x56>;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -263,7 +280,7 @@
 	};

 	cape_eeprom3: cape_eeprom3@57 {
-		compatible = "atmel,24c256";
+		compatible = "at,24c256";
 		reg = <0x57>;
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -294,20 +311,8 @@
 	 * by the hardware problems. (Tip: double-check by performing a current
 	 * measurement after shutdown: it should be less than 1 mA.)
 	 */
-
-	interrupts = <7>; /* NMI */
-	interrupt-parent = <&intc>;
-
 	ti,pmic-shutdown-controller;

-	charger {
-		status = "okay";
-	};
-
-	pwrbutton {
-		status = "okay";
-	};
-
 	regulators {
 		dcdc1_reg: regulator@0 {
 			regulator-name = "vdds_dpr";
@@ -318,7 +323,7 @@
 			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 			regulator-name = "vdd_mpu";
 			regulator-min-microvolt = <925000>;
-			regulator-max-microvolt = <1351500>;
+			regulator-max-microvolt = <1325000>;
 			regulator-boot-on;
 			regulator-always-on;
 		};
@@ -393,8 +398,3 @@
 &sham {
 	status = "okay";
 };
-
-&rtc {
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-};
--- a/arch/arm/dts/am335x-bone.dts
+++ b/arch/arm/dts/am335x-bone.dts
@@ -1,6 +1,9 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
 */
 /dts-v1/;

--- a/arch/arm/dts/am335x-boneblack-common.dtsi
+++ b/arch/arm/dts/am335x-boneblack-common.dtsi
@@ -1,169 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include <dt-bindings/display/tda998x.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-&ldo3_reg {
-	regulator-min-microvolt = <1800000>;
-	regulator-max-microvolt = <1800000>;
-	regulator-always-on;
-};
-
-&mmc1 {
-	vmmc-supply = <&vmmcsd_fixed>;
-};
-
-&mmc2 {
-	vmmc-supply = <&vmmcsd_fixed>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_pins>;
-	bus-width = <8>;
-	status = "okay";
-	non-removable;
-};
-
-&am33xx_pinmux {
-	nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-		>;
-	};
-
-	nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
-		>;
-	};
-
-	mcasp0_pins: mcasp0_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
-		>;
-	};
-};
-
-&lcdc {
-	status = "okay";
-
-	/* If you want to get 24 bit RGB and 16 BGR mode instead of
-	 * current 16 bit RGB and 24 BGR modes, set the propety
-	 * below to "crossed" and uncomment the video-ports -property
-	 * in tda19988 node.
-	 */
-	blue-and-red-wiring = "straight";
-
-	port {
-		lcdc_0: endpoint@0 {
-			remote-endpoint = <&hdmi_0>;
-		};
-	};
-};
-
-&i2c0 {
-	tda19988: tda19988@70 {
-		compatible = "nxp,tda998x";
-		reg = <0x70>;
-		nxp,calib-gpios = <&gpio1 25 0>;
-		interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>;
-
-		pinctrl-names = "default", "off";
-		pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
-		pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
-
-		/* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
-		/* video-ports = <0x234501>; */
-
-		#sound-dai-cells = <0>;
-		audio-ports = <	TDA998x_I2S	0x03>;
-
-		ports {
-			port@0 {
-				hdmi_0: endpoint@0 {
-					remote-endpoint = <&lcdc_0>;
-				};
-			};
-		};
-	};
-};
-
-&rtc {
-	system-power-controller;
-};
-
-&mcasp0	{
-	#sound-dai-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcasp0_pins>;
-	status = "okay";
-	op-mode = <0>;	/* MCASP_IIS_MODE */
-	tdm-slots = <2>;
-	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
-			0 0 1 0
-		>;
-	tx-num-evt = <32>;
-	rx-num-evt = <32>;
-};
-
-/ {
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x20000000>; /* 512 MB */
-	};
-
-	clk_mcasp0_fixed: clk_mcasp0_fixed {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <24576000>;
-	};
-
-	clk_mcasp0: clk_mcasp0 {
-		#clock-cells = <0>;
-		compatible = "gpio-gate-clock";
-		clocks = <&clk_mcasp0_fixed>;
-		enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */
-	};
-
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "TI BeagleBone Black";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,bitclock-master = <&dailink0_master>;
-		simple-audio-card,frame-master = <&dailink0_master>;
-
-		dailink0_master: simple-audio-card,cpu {
-			sound-dai = <&mcasp0>;
-			clocks = <&clk_mcasp0>;
-		};
-
-		simple-audio-card,codec {
-			sound-dai = <&tda19988>;
-		};
-	};
-};
--- a/arch/arm/dts/am335x-boneblack.dts
+++ b/arch/arm/dts/am335x-boneblack.dts
@@ -1,169 +1,90 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
 */
 /dts-v1/;

 #include "am33xx.dtsi"
 #include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"

 / {
 	model = "TI AM335x BeagleBone Black";
 	compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-};
-
-&cpu0_opp_table {
-	/*
-	 * All PG 2.0 silicon may not support 1GHz but some of the early
-	 * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
-	 * to support 1GHz OPP so enable it for PG 2.0 on this board.
-	 */
-	oppnitro-1000000000 {
-		opp-supported-hw = <0x06 0x0100>;
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
 	};
 };

-&gpio0 {
-	gpio-line-names =
-		"[mdio_data]",
-		"[mdio_clk]",
-		"P9_22 [spi0_sclk]",
-		"P9_21 [spi0_d0]",
-		"P9_18 [spi0_d1]",
-		"P9_17 [spi0_cs0]",
-		"[mmc0_cd]",
-		"P8_42A [ecappwm0]",
-		"P8_35 [lcd d12]",
-		"P8_33 [lcd d13]",
-		"P8_31 [lcd d14]",
-		"P8_32 [lcd d15]",
-		"P9_20 [i2c2_sda]",
-		"P9_19 [i2c2_scl]",
-		"P9_26 [uart1_rxd]",
-		"P9_24 [uart1_txd]",
-		"[rmii1_txd3]",
-		"[rmii1_txd2]",
-		"[usb0_drvvbus]",
-		"[hdmi cec]",
-		"P9_41B",
-		"[rmii1_txd1]",
-		"P8_19 [ehrpwm2a]",
-		"P8_13 [ehrpwm2b]",
-		"NC",
-		"NC",
-		"P8_14",
-		"P8_17",
-		"[rmii1_txd0]",
-		"[rmii1_refclk]",
-		"P9_11 [uart4_rxd]",
-		"P9_13 [uart4_txd]";
+&ldo3_reg {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
 };

-&gpio1 {
-	gpio-line-names =
-		"P8_25 [mmc1_dat0]",
-		"[mmc1_dat1]",
-		"P8_5 [mmc1_dat2]",
-		"P8_6 [mmc1_dat3]",
-		"P8_23 [mmc1_dat4]",
-		"P8_22 [mmc1_dat5]",
-		"P8_3 [mmc1_dat6]",
-		"P8_4 [mmc1_dat7]",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"P8_12",
-		"P8_11",
-		"P8_16",
-		"P8_15",
-		"P9_15A",
-		"P9_23",
-		"P9_14 [ehrpwm1a]",
-		"P9_16 [ehrpwm1b]",
-		"[emmc rst]",
-		"[usr0 led]",
-		"[usr1 led]",
-		"[usr2 led]",
-		"[usr3 led]",
-		"[hdmi irq]",
-		"[usb vbus oc]",
-		"[hdmi audio]",
-		"P9_12",
-		"P8_26",
-		"P8_21 [emmc]",
-		"P8_20 [emmc]";
+&mmc1 {
+	vmmc-supply = <&vmmcsd_fixed>;
 };

-&gpio2 {
-	gpio-line-names =
-		"P9_15B",
-		"P8_18",
-		"P8_7",
-		"P8_8",
-		"P8_10",
-		"P8_9",
-		"P8_45 [hdmi]",
-		"P8_46 [hdmi]",
-		"P8_43 [hdmi]",
-		"P8_44 [hdmi]",
-		"P8_41 [hdmi]",
-		"P8_42 [hdmi]",
-		"P8_39 [hdmi]",
-		"P8_40 [hdmi]",
-		"P8_37 [hdmi]",
-		"P8_38 [hdmi]",
-		"P8_36 [hdmi]",
-		"P8_34 [hdmi]",
-		"[rmii1_rxd3]",
-		"[rmii1_rxd2]",
-		"[rmii1_rxd1]",
-		"[rmii1_rxd0]",
-		"P8_27 [hdmi]",
-		"P8_29 [hdmi]",
-		"P8_28 [hdmi]",
-		"P8_30 [hdmi]",
-		"[mmc0_dat3]",
-		"[mmc0_dat2]",
-		"[mmc0_dat1]",
-		"[mmc0_dat0]",
-		"[mmc0_clk]",
-		"[mmc0_cmd]";
+&mmc2 {
+	vmmc-supply = <&vmmcsd_fixed>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>;
+	bus-width = <8>;
+	status = "okay";
 };

-&gpio3 {
-	gpio-line-names =
-		"[mii col]",
-		"[mii crs]",
-		"[mii rx err]",
-		"[mii tx en]",
-		"[mii rx dv]",
-		"[i2c0 sda]",
-		"[i2c0 scl]",
-		"[jtag emu0]",
-		"[jtag emu1]",
-		"[mii tx clk]",
-		"[mii rx clk]",
-		"NC",
-		"NC",
-		"[usb vbus en]",
-		"P9_31 [spi1_sclk]",
-		"P9_29 [spi1_d0]",
-		"P9_30 [spi1_d1]",
-		"P9_28 [spi1_cs0]",
-		"P9_42B [ecappwm0]",
-		"P9_27",
-		"P9_41A",
-		"P9_25",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC",
-		"NC";
+&am33xx_pinmux {
+	nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
+		pinctrl-single,pins = <
+			0x1b0 0x03      /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+			0xa0 0x08       /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xa4 0x08       /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xa8 0x08       /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xac 0x08       /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xb0 0x08       /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xb4 0x08       /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xb8 0x08       /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xbc 0x08       /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xc0 0x08       /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xc4 0x08       /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xc8 0x08       /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xcc 0x08       /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xd0 0x08       /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xd4 0x08       /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xd8 0x08       /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xdc 0x08       /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
+			0xe0 0x00       /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+			0xe4 0x00       /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+			0xe8 0x00       /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+			0xec 0x00       /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
+		>;
+	};
+	nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
+		pinctrl-single,pins = <
+			0x1b0 0x03      /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+		>;
+	};
+};
+
+&lcdc {
+	status = "okay";
+};
+
+/ {
+	hdmi {
+		compatible = "ti,tilcdc,slave";
+		i2c = <&i2c0>;
+		pinctrl-names = "default", "off";
+		pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
+		pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
+		status = "okay";
+	};
+};
+
+&rtc {
+	system-power-controller;
 };
--- a/arch/arm/dts/am335x-bonegreen-common.dtsi
+++ b/arch/arm/dts/am335x-bonegreen-common.dtsi
@@ -1,41 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-&ldo3_reg {
-	regulator-min-microvolt = <1800000>;
-	regulator-max-microvolt = <1800000>;
-	regulator-always-on;
-};
-
-&mmc1 {
-	vmmc-supply = <&vmmcsd_fixed>;
-};
-
-&mmc2 {
-	vmmc-supply = <&vmmcsd_fixed>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_pins>;
-	bus-width = <8>;
-	status = "okay";
-};
-
-&am33xx_pinmux {
-	uart2_pins: uart2_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)	/* spi0_sclk.uart2_rxd */
-			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)	/* spi0_d0.uart2_txd */
-		>;
-	};
-};
-
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&rtc {
-	system-power-controller;
-};
--- a/arch/arm/dts/am335x-bonegreen.dts
+++ b/arch/arm/dts/am335x-bonegreen.dts
@@ -1,14 +1,57 @@
-// SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
 */
 /dts-v1/;

 #include "am33xx.dtsi"
 #include "am335x-bone-common.dtsi"
-#include "am335x-bonegreen-common.dtsi"

 / {
 	model = "TI AM335x BeagleBone Green";
 	compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+};
+
+&ldo3_reg {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
+};
+
+&mmc1 {
+	vmmc-supply = <&vmmcsd_fixed>;
+};
+
+&mmc2 {
+	vmmc-supply = <&vmmcsd_fixed>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&am33xx_pinmux {
+	uart2_pins: uart2_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)	/* spi0_sclk.uart2_rxd */
+			AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)	/* spi0_d0.uart2_txd */
+		>;
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+&rtc {
+	system-power-controller;
 };
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -762,8 +762,3 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dcan1_pins_default>;
 };
-
-&rtc {
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-};
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -724,8 +724,3 @@
 &lcdc {
      status = "okay";
 };
-
-&rtc {
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-};
--- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
+++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
@@ -42,17 +42,6 @@
 	u-boot,dm-pre-reloc;
 };

-&spi0 {
-	lcd0: display@0 {
-		compatible = "himax,hx8238d";
-		pinctrl-names = "default";
-		pinctrl-0 = <&lcd0_pins>;
-		reg = <0>;
-		label = "lcd";
-		spi-max-frequency = <100000>;
-	};
-};
-
 &uart0 {
 	u-boot,dm-pre-reloc;
 };
--- a/arch/arm/dts/am335x-guardian.dts
+++ b/arch/arm/dts/am335x-guardian.dts
@@ -87,7 +87,7 @@
 			ac-bias           = <255>;
 			ac-bias-intrpt    = <0>;
 			dma-burst-sz      = <16>;
-			bpp               = <16>;
+			bpp               = <24>;
 			bus-width         = <16>;
 			fdd               = <0x80>;
 			sync-edge         = <0>;
@@ -247,12 +247,6 @@
 &lcdc {
 	blue-and-red-wiring = "crossed";
 	status = "okay";
-
-	port {
-		lcdc_0: endpoint@0 {
-			remote-endpoint = <0>;
-		};
-	};
 };

 &mmc1 {
@@ -407,12 +401,12 @@

 	guardian_interface_pins: pinmux_guardian_interface_pins {
 		pinctrl-single,pins = <
-			AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP   | MUX_MODE7)
+			AM33XX_IOPAD(0x928, PIN_OUTPUT          | MUX_MODE7)
+			AM33XX_IOPAD(0x990, PIN_OUTPUT          | MUX_MODE7)
 			AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
-			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
 			AM33XX_IOPAD(0x980, PIN_INPUT           | MUX_MODE7)
 			AM33XX_IOPAD(0x984, PIN_INPUT           | MUX_MODE7)
-			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP   | MUX_MODE7)
+			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP   | MUX_MODE7)
 			AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
 			AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
 			AM33XX_IOPAD(0x91c, PIN_INPUT           | MUX_MODE7)
--- a/arch/arm/dts/am335x-osd335x-common.dtsi
+++ b/arch/arm/dts/am335x-osd335x-common.dtsi
@@ -122,9 +122,3 @@
 &sham {
 	status = "okay";
 };
-
-&rtc {
-	clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
-	clock-names = "ext-clk", "int-clk";
-	system-power-controller;
-};
--- a/arch/arm/dts/am335x-sancloud-bbe.dts
+++ b/arch/arm/dts/am335x-sancloud-bbe.dts
@@ -1,137 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "am33xx.dtsi"
-#include "am335x-bone-common.dtsi"
-#include "am335x-boneblack-common.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
-	model = "SanCloud BeagleBone Enhanced";
-	compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
-};
-
-&am33xx_pinmux {
-	pinctrl-names = "default";
-
-	cpsw_default: cpsw_default {
-		pinctrl-single,pins = <
-			/* Slave 1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
-		>;
-	};
-
-	cpsw_sleep: cpsw_sleep {
-		pinctrl-single,pins = <
-			/* Slave 1 reset value */
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	davinci_mdio_default: davinci_mdio_default {
-		pinctrl-single,pins = <
-			/* MDIO */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
-		>;
-	};
-
-	davinci_mdio_sleep: davinci_mdio_sleep {
-		pinctrl-single,pins = <
-			/* MDIO reset value */
-			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
-			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
-		>;
-	};
-
-	usb_hub_ctrl: usb_hub_ctrl {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)     /* rmii1_refclk.gpio0_29 */
-		>;
-	};
-
-	mpu6050_pins: pinmux_mpu6050_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7)    /* uart0_ctsn.gpio1_8 */
-		>;
-	};
-
-	lps3331ap_pins: pinmux_lps3331ap_pins {
-		pinctrl-single,pins = <
-			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)     /* gpmc_a10.gpio1_26 */
-		>;
-	};
-};
-
-&mac {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&cpsw_default>;
-	pinctrl-1 = <&cpsw_sleep>;
-	status = "okay";
-};
-
-&davinci_mdio {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&davinci_mdio_default>;
-	pinctrl-1 = <&davinci_mdio_sleep>;
-	status = "okay";
-
-	ethphy0: ethernet-phy@0 {
-		reg = <0>;
-	};
-};
-
-&cpsw_emac0 {
-	phy-handle = <&ethphy0>;
-	phy-mode = "rgmii-id";
-};
-
-&i2c0 {
-	lps331ap: barometer@5c {
-		compatible = "st,lps331ap-press";
-		st,drdy-int-pin = <1>;
-		reg = <0x5c>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <26 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	mpu6050: accelerometer@68 {
-		compatible = "invensense,mpu6050";
-		reg = <0x68>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <2 IRQ_TYPE_EDGE_RISING>;
-		orientation = <0xff 0 0 0 1 0 0 0 0xff>;
-	};
-
-	usb2512b: usb-hub@2c {
-		compatible = "microchip,usb2512b";
-		reg = <0x2c>;
-		reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
-		/* wifi on port 4 */
-	};
-};
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -380,24 +380,28 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ti,hwmods = "usb_otg_hs";
+			status = "disabled";

 			usb_ctrl_mod: control@44e10620 {
 				compatible = "ti,am335x-usb-ctrl-module";
 				reg = <0x44e10620 0x10
 					0x44e10648 0x4>;
 				reg-names = "phy_ctrl", "wakeup";
+				status = "disabled";
 			};

 			usb0_phy: usb-phy@47401300 {
 				compatible = "ti,am335x-usb-phy";
 				reg = <0x47401300 0x100>;
 				reg-names = "phy";
+				status = "disabled";
 				ti,ctrl_mod = <&usb_ctrl_mod>;
 				#phy-cells = <0>;
 			};

 			usb0: usb@47401000 {
 				compatible = "ti,musb-am33xx";
+				status = "disabled";
 				reg = <0x47401400 0x400
 					0x47401000 0x200>;
 				reg-names = "mc", "control";
@@ -439,12 +443,14 @@
 				compatible = "ti,am335x-usb-phy";
 				reg = <0x47401b00 0x100>;
 				reg-names = "phy";
+				status = "disabled";
 				ti,ctrl_mod = <&usb_ctrl_mod>;
 				#phy-cells = <0>;
 			};

 			usb1: usb@47401800 {
 				compatible = "ti,musb-am33xx";
+				status = "disabled";
 				reg = <0x47401c00 0x400
 					0x47401800 0x200>;
 				reg-names = "mc", "control";
--- a/arch/arm/dts/am3517-evm-ui.dtsi
+++ b/arch/arm/dts/am3517-evm-ui.dtsi
@@ -186,14 +186,14 @@
 };

 &mcbsp1 {
-	status = "okay";
+	status = "ok";
 	#sound-dai-cells = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcbsp1_pins>;
 };

 &mcbsp2 {
-	status = "okay";
+	status = "ok";
 	#sound-dai-cells = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcbsp2_pins>;
--- a/arch/arm/dts/am3517-evm.dts
+++ b/arch/arm/dts/am3517-evm.dts
@@ -193,7 +193,7 @@
 };

 &dss {
-	status = "okay";
+	status = "ok";

 	pinctrl-names = "default";
 	pinctrl-0 = <&dss_dpi_pins>;
--- a/arch/arm/dts/am437x-gp-evm.dts
+++ b/arch/arm/dts/am437x-gp-evm.dts
@@ -742,7 +742,7 @@
 };

 &dss {
-	status = "okay";
+	status = "ok";

 	pinctrl-names = "default";
 	pinctrl-0 = <&dss_pins>;
--- a/arch/arm/dts/am43x-epos-evm.dts
+++ b/arch/arm/dts/am43x-epos-evm.dts
@@ -752,7 +752,7 @@
 };

 &dss {
-	status = "okay";
+	status = "ok";

 	pinctrl-names = "default";
 	pinctrl-0 = <&dss_pins>;
--- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi
@@ -528,13 +528,13 @@
 };

 &dss {
-	status = "okay";
+	status = "ok";

 	vdda_video-supply = <&ldoln_reg>;
 };

 &hdmi {
-	status = "okay";
+	status = "ok";
 	vdda-supply = <&ldo4_reg>;

 	port {
@@ -545,7 +545,7 @@
 };

 &pcie1_rc {
-	status = "okay";
+	status = "ok";
 	gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
 };

--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -70,13 +70,13 @@

 &comphy {
 	phy0 {
-		phy-type = <COMPHY_TYPE_USB3_HOST0>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_2_5G>;
 	};

 	phy1 {
-		phy-type = <COMPHY_TYPE_PEX0>;
-		phy-speed = <COMPHY_SPEED_2_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};
 };

--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -83,18 +83,18 @@
 &comphy {
 	max-lanes = <3>;
 	phy0 {
-		phy-type = <COMPHY_TYPE_USB3_HOST0>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy1 {
-		phy-type = <COMPHY_TYPE_PEX0>;
-		phy-speed = <COMPHY_SPEED_2_5G>;
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_2_5G>;
 	};

 	phy2 {
-		phy-type = <COMPHY_TYPE_SATA0>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_SATA0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};
 };

@@ -164,24 +164,6 @@
 		reg = <0>; /* Chip select 0 */
 		spi-max-frequency = <50000000>;
 		m25p,fast-read;
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@firmware {
-				reg = <0 CONFIG_ENV_OFFSET>;
-				label = "firmware";
-			};
-
-			partition@u-boot-env {
-				reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
-				label = "u-boot-env";
-			};
-		};
-#endif
 	};
 };

--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -11,8 +11,6 @@
 /dts-v1/;

 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
 #include "armada-372x.dtsi"

 / {
@@ -36,28 +34,6 @@
 		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
 	};

-	leds {
-		compatible = "gpio-leds";
-
-		led {
-			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
-			color = <LED_COLOR_ID_RED>;
-			function = LED_FUNCTION_ACTIVITY;
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		reset {
-			compatible = "gpio-keys";
-			label = "reset";
-			linux,code = <KEY_RESTART>;
-			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
-			debounce-interval = <60>;
-		};
-	};
-
 	reg_usb3_vbus: usb3_vbus@0 {
 		compatible = "regulator-fixed";
 		regulator-name = "usb3-vbus";
@@ -97,18 +73,18 @@
 &comphy {
 	max-lanes = <3>;
 	phy0 {
-		phy-type = <COMPHY_TYPE_SGMII1>;
-		phy-speed = <COMPHY_SPEED_3_125G>;
+		phy-type = <PHY_TYPE_SGMII1>;
+		phy-speed = <PHY_SPEED_3_125G>;
 	};

 	phy1 {
-		phy-type = <COMPHY_TYPE_PEX0>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy2 {
-		phy-type = <COMPHY_TYPE_USB3_HOST0>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};
 };

@@ -164,37 +140,6 @@
 		reg = <0>;
 		spi-max-frequency = <20000000>;
 		m25p,fast-read;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "secure-firmware";
-				reg = <0x0 0x20000>;
-			};
-
-			partition@20000 {
-				label = "a53-firmware";
-				reg = <0x20000 0x160000>;
-			};
-
-			partition@180000 {
-				label = "u-boot-env";
-				reg = <0x180000 0x10000>;
-			};
-
-			partition@190000 {
-				label = "Rescue system";
-				reg = <0x190000 0x660000>;
-			};
-
-			partition@7f0000 {
-				label = "dtb";
-				reg = <0x7f0000 0x10000>;
-			};
-		};
 	};

 	moxtet@1 {
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -108,32 +108,31 @@

 &comphy {
 	phy0 {
-		phy-type = <COMPHY_TYPE_SGMII1>;
-		phy-speed = <COMPHY_SPEED_1_25G>;
+		phy-type = <PHY_TYPE_SGMII1>;
+		phy-speed = <PHY_SPEED_3_125G>;
 	};
+        phy1 {
+                phy-type = <PHY_TYPE_SGMII0>;
+                phy-speed = <PHY_SPEED_3_125G>;
+        };

-	phy1 {
-		phy-type = <COMPHY_TYPE_SGMII0>;
-		phy-speed = <COMPHY_SPEED_1_25G>;
-	};
-
-	phy2 {
-		phy-type = <COMPHY_TYPE_USB3_HOST1>;
-		phy-speed = <COMPHY_SPEED_5G>;
-	};
+        phy2 {
+                phy-type = <PHY_TYPE_USB3_HOST1>;
+                phy-speed = <PHY_SPEED_5G>;
+        };
 };

 &eth0 {
 	pinctrl-0 = <&pcie_pins>;
 	status = "okay";
-	phy-mode = "2500base-x";
+	phy-mode = "sgmii-2500";
 	managed = "in-band-status";
 	phy = <&ethphy0>;
 };

 &eth1 {
 	status = "okay";
-	phy-mode = "2500base-x";
+	phy-mode = "sgmii-2500";
 	managed = "in-band-status";
 	phy = <&ethphy1>;
 };
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -323,7 +323,7 @@
 		};

 		pcie0: pcie@d0070000 {
-			compatible = "marvell,armada-3700-pcie";
+			compatible = "marvell,armada-37xx-pcie";
 			reg = <0 0xd0070000 0 0x20000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
@@ -332,17 +332,10 @@
 			status = "disabled";

 			bus-range = <0 0xff>;
-			/*
-			 * The 128 MiB address range [0xe8000000-0xf0000000] is
-			 * dedicated for PCIe and can be assigned to 8 windows
-			 * with size a power of two. Use one 64 KiB window for
-			 * IO at the end and the remaining seven windows
-			 * (totaling 127 MiB) for MEM.
-			 */
 			ranges = <0x82000000 0 0xe8000000
-				 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
-				 0x81000000 0 0xefff0000
-				 0 0xefff0000 0 0x10000>; /* Port 0 IO*/
+				 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
+				 0x81000000 0 0xe9000000
+				 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
 		};
 	};
 };
--- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
+++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
@@ -41,19 +41,11 @@
 &spi0 {
 	u-boot,dm-pre-reloc;

-	spi-nor@0 {
+	spi-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
 		u-boot,dm-pre-reloc;
-
-		partitions {
-			partition@0 {
-				reg = <0x0 CONFIG_ENV_OFFSET>;
-			};
-
-			partition@f0000 {
-				reg = <CONFIG_ENV_OFFSET CONFIG_ENV_SIZE>;
-				label = "u-boot-env";
-			};
-		};
 	};
 };

--- a/arch/arm/dts/armada-7040-db-nand.dts
+++ b/arch/arm/dts/armada-7040-db-nand.dts
@@ -1,6 +1,43 @@
-// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2016- 2021 Marvell International Ltd.
+ * Copyright (C) 2017 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */

 /*
@@ -21,8 +58,8 @@
 	};

 	aliases {
-		i2c0 = &cp0_i2c0;
-		spi0 = &cp0_spi1;
+		i2c0 = &cpm_i2c0;
+		spi0 = &cpm_spi1;
 	};

 	memory@00000000 {
@@ -46,18 +83,18 @@
 };


-&cp0_pcie2 {
+&cpm_pcie2 {
 	status = "okay";
 };

-&cp0_i2c0 {
+&cpm_i2c0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c0_pins>;
+	pinctrl-0 = <&cpm_i2c0_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 };

-&cp0_pinctl {
+&cpm_pinctl {
 		/* MPP Bus:
 		 * AUDIO   [0-5]
                 * GBE     [6-11]
@@ -85,9 +122,9 @@
 		      0xe 0xe 0x0>;
 };

-&cp0_spi1 {
+&cpm_spi1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_spi0_pins>;
+	pinctrl-0 = <&cpm_spi0_pins>;
 	status = "disabled";

 	spi-flash@0 {
@@ -115,59 +152,59 @@
 	};
 };

-&cp0_sata0 {
+&cpm_sata0 {
 	status = "okay";
 };

-&cp0_usb3_0 {
+&cpm_usb3_0 {
 	status = "okay";
 };

-&cp0_usb3_1 {
+&cpm_usb3_1 {
 	status = "okay";
 };

-&cp0_comphy {
+&cpm_comphy {
 	phy0 {
-		phy-type = <COMPHY_TYPE_SGMII2>;
-		phy-speed = <COMPHY_SPEED_3_125G>;
+		phy-type = <PHY_TYPE_SGMII2>;
+		phy-speed = <PHY_SPEED_3_125G>;
 	};

 	phy1 {
-		phy-type = <COMPHY_TYPE_USB3_HOST0>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy2 {
-		phy-type = <COMPHY_TYPE_SGMII0>;
-		phy-speed = <COMPHY_SPEED_1_25G>;
+		phy-type = <PHY_TYPE_SGMII0>;
+		phy-speed = <PHY_SPEED_1_25G>;
 	};

 	phy3 {
-		phy-type = <COMPHY_TYPE_SATA1>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_SATA1>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy4 {
-		phy-type = <COMPHY_TYPE_USB3_HOST1>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST1>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy5 {
-		phy-type = <COMPHY_TYPE_PEX2>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_PEX2>;
+		phy-speed = <PHY_SPEED_5G>;
 	};
 };

-&cp0_nand {
+&cpm_nand {
 	status = "okay";
 };

-&cp0_utmi0 {
+&cpm_utmi0 {
 	status = "okay";
 };

-&cp0_utmi1 {
+&cpm_utmi1 {
 	status = "okay";
 };

@@ -178,7 +215,7 @@
 	non-removable;
 };

-&cp0_sdhci0 {
+&cpm_sdhci0 {
 	status = "okay";
 	bus-width = <4>;
 	no-1-8-v;
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -1,6 +1,43 @@
-// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2016- 2021 Marvell International Ltd.
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */

 /*
@@ -20,8 +57,8 @@
 	};

 	aliases {
-		i2c0 = &cp0_i2c0;
-		spi0 = &cp0_spi1;
+		i2c0 = &cpm_i2c0;
+		spi0 = &cpm_spi1;
 	};

 	memory@00000000 {
@@ -45,18 +82,18 @@
 };


-&cp0_pcie2 {
+&cpm_pcie2 {
 	status = "okay";
 };

-&cp0_i2c0 {
+&cpm_i2c0 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_i2c0_pins>;
+	pinctrl-0 = <&cpm_i2c0_pins>;
 	status = "okay";
 	clock-frequency = <100000>;
 };

-&cp0_pinctl {
+&cpm_pinctl {
 		/* MPP Bus:
 		 * TDM	 [0-11]
 		 * SPI   [13-16]
@@ -78,9 +115,9 @@
 		     0xE 0xE 0xE >;
 };

-&cp0_spi1 {
+&cpm_spi1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&cp0_spi0_pins>;
+	pinctrl-0 = <&cpm_spi0_pins>;
 	status = "okay";

 	spi-flash@0 {
@@ -108,55 +145,54 @@
 	};
 };

-&cp0_sata0 {
+&cpm_sata0 {
 	status = "okay";
 };

-&cp0_usb3_0 {
+&cpm_usb3_0 {
 	status = "okay";
 };

-&cp0_usb3_1 {
+&cpm_usb3_1 {
 	status = "okay";
 };

-&cp0_comphy {
+&cpm_comphy {
 	phy0 {
-		phy-type = <COMPHY_TYPE_SGMII1>;
-		phy-speed = <COMPHY_SPEED_1_25G>;
+		phy-type = <PHY_TYPE_SGMII1>;
+		phy-speed = <PHY_SPEED_1_25G>;
 	};

 	phy1 {
-		phy-type = <COMPHY_TYPE_USB3_HOST0>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy2 {
-		phy-type = <COMPHY_TYPE_SFI0>;
-		phy-speed = <COMPHY_SPEED_10_3125G>;
+		phy-type = <PHY_TYPE_SFI>;
 	};

 	phy3 {
-		phy-type = <COMPHY_TYPE_SATA1>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_SATA1>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy4 {
-		phy-type = <COMPHY_TYPE_USB3_HOST1>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_USB3_HOST1>;
+		phy-speed = <PHY_SPEED_5G>;
 	};

 	phy5 {
-		phy-type = <COMPHY_TYPE_PEX2>;
-		phy-speed = <COMPHY_SPEED_5G>;
+		phy-type = <PHY_TYPE_PEX2>;
+		phy-speed = <PHY_SPEED_5G>;
 	};
 };

-&cp0_utmi0 {
+&cpm_utmi0 {
 	status = "okay";
 };

-&cp0_utmi1 {
+&cpm_utmi1 {
 	status = "okay";
 };

@@ -167,15 +203,14 @@
 	non-removable;
 };

-&cp0_sdhci0 {
+&cpm_sdhci0 {
 	status = "okay";
 	bus-width = <4>;
 	no-1-8-v;
 	non-removable;
 };

-&cp0_mdio {
-	status = "okay";
+&cpm_mdio {
 	phy0: ethernet-phy@0 {
 		reg = <0>;
 	};
@@ -184,22 +219,22 @@
 	};
 };

-&cp0_ethernet {
+&cpm_ethernet {
 	status = "okay";
 };

-&cp0_eth0 {
+&cpm_eth0 {
 	status = "okay";
 	phy-mode = "sfi"; /* lane-2 */
 };

-&cp0_eth1 {
+&cpm_eth1 {
 	status = "okay";
 	phy = <&phy0>;
 	phy-mode = "sgmii";
 };

-&cp0_eth2 {
+&cpm_eth2 {
 	status = "okay";
 	phy = <&phy1>;
 	phy-mode = "rgmii-id";
--- a/arch/arm/dts/armada-7040.dtsi
+++ b/arch/arm/dts/armada-7040.dtsi
@@ -1,6 +1,43 @@
-// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2016- 2021 Marvell International Ltd.
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
 */

 /*
@@ -9,57 +46,11 @@
 */

 #include <dt-bindings/gpio/gpio.h>
-#include "armada-common.dtsi"
-#include "armada-8k.dtsi"
-#include "armada-ap806.dtsi"
-#include "armada-ap80x-quad.dtsi"
-
-/* CP110-0 Settings */
-#define CP110_NAME		cp0
-#define CP110_NUM		0
-
-#include "armada-cp110.dtsi"
-
-#undef CP110_NAME
-#undef CP110_NUM
+#include "armada-ap806-quad.dtsi"
+#include "armada-cp110-master.dtsi"

 / {
 	model = "Marvell Armada 7040";
 	compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
 		     "marvell,armada-ap806";
 };
-
-&cp0_pinctl {
-	compatible = "marvell,mvebu-pinctrl", "marvell,7k-pinctrl";
-	bank-name ="cp0-110";
-
-	cp0_i2c0_pins: cp0-i2c-pins-0 {
-		marvell,pins = < 37 38 >;
-		marvell,function = <2>;
-	};
-	cp0_i2c1_pins: cp0-i2c-pins-1 {
-		marvell,pins = < 35 36 >;
-	marvell,function = <2>;
-	};
-	cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
-		marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
-		marvell,function = <3>;
-	};
-	cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
-		marvell,pins = < 44 45 46 47 48 49 50 51
-				 52 53 54 55 >;
-		marvell,function = <1>;
-	};
-	cp0_pca0_pins: cp0-pca0_pins {
-		marvell,pins = <62>;
-		marvell,function = <0>;
-	};
-	cp0_sdhci_pins: cp0-sdhi-pins-0 {
-		marvell,pins = < 56 57 58 59 60 61 >;
-		marvell,function = <14>;
-	};
-	cp0_spi0_pins: cp0-spi-pins-0 {
-		marvell,pins = < 13 14 15 16 >;
-		marvell,function = <3>;
-	};
-};
--- a/arch/arm/dts/armada-8020.dtsi
+++ b/arch/arm/dts/armada-8020.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
+ * two CP110.
+ */
+
+#include "armada-ap806-dual.dtsi"
+#include "armada-cp110-master.dtsi"
+#include "armada-cp110-slave.dtsi"
+
+/ {
+	model = "Marvell Armada 8020";
+	compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
+		     "marvell,armada-ap806";
+};
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Tom Rini	b73d114213	pytest: Fix squashfs tests not checking for directory exists It is possible that we will have our "sqfs_src" directory already existing, and not be in an error condition. Don't try and make the directory again. Signed-off-by: Tom Rini <trini@konsulko.com>	2021-02-25 14:28:10 -05:00
Tom Rini	c0b354ed02	Azure/GitLab: Ensure we use requirements.txt for testsuites Given that test/py/requirements.txt has all required test modules, make use of that rather than a manual pip install list before running our assorted tool testsuites. Signed-off-by: Tom Rini <trini@konsulko.com>	2021-02-25 13:47:36 -05:00
Tom Rini	01585fbf6b	pytest: Lower pygit2 requirement The latest versions of pygit2 are not available in practically any distribution at this time. Furthermore, we don't need the latest in order to run all of our testsuites. Reduce this version requirement to something older that meets our needs while still supporting running our tests on older hosts (and so, test labs). Reported-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Rini <trini@konsulko.com>	2021-02-25 13:22:43 -05:00
Tom Rini	4e238b7c1a	GitLab: Remove "tags" stanzas Given the structure of our current GitLab tests, we don't make real use of the tags. Furthermore, these tags prevent the automatic usage of the default GitLab runners. Remove these tags. Reported-by: Roger Meier <r.meier@siemens.com> Signed-off-by: Tom Rini <trini@konsulko.com>	2021-02-25 13:20:07 -05:00