Merge tag 'u-boot-rockchip-20190819' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- Add ROC-RK3399-PC board support - Move CONFIG_SPI_FLASH_GIGADEVICE and CONFIG_CMD_USB_MASS_STORAGE to Kconfig - using SYSRESET_POWER_OFF for poweroff (Note that patch for rk8xx pmic is droped for it can not pass Travis build) - fix ofnode_get_name() assert
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
2019-08-19 09:22:57 -04:00 · 2019-08-19 09:21:46 -04:00 · 2019-08-19 12:43:26 +08:00 · 2019-08-19 12:43:26 +08:00 · 2019-08-19 12:43:26 +08:00 · 2019-08-19 12:43:26 +08:00
202 changed files with 2060 additions and 1152 deletions
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -93,6 +93,7 @@ config SANDBOX
 	select PCI_ENDPOINT
 	select SPI
 	select SUPPORT_OF_CONTROL
+	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
 	imply BITREVERSE
 	select BLOBLIST
 	imply CMD_DM
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -902,7 +902,7 @@ config ARCH_SOCFPGA
 	select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select SYSRESET
 	select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
-	select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
+	select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
 	imply CMD_DM
 	imply CMD_MTDPARTS
 	imply CRC32_VERIFY
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -119,6 +119,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
 	rk3399-puma-ddr1333.dtb \
 	rk3399-puma-ddr1600.dtb \
 	rk3399-puma-ddr1866.dtb \
+	rk3399-roc-pc.dtb \
 	rk3399-rock-pi-4.dtb \
 	rk3399-rock960.dtb \
 	rk3399-rockpro64.dtb
--- a/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Levin Du <djw@t-chip.com.cn>
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
+	};
+};
+
+&vdd_log {
+	regulator-min-microvolt = <430000>;
+	regulator-init-microvolt = <950000>;
+};
--- a/arch/arm/dts/rk3399-roc-pc.dts
+++ b/arch/arm/dts/rk3399-roc-pc.dts
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
+ */
+
+/dts-v1/;
+#include <dt-bindings/pwm/pwm.h>
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+	model = "Firefly ROC-RK3399-PC Board";
+	compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm0 0 25000 0>;
+	};
+
+	clkin_gmac: external-gmac-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "clkin_gmac";
+		#clock-cells = <0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+	};
+
+	vcc_vbus_typec0: vcc-vbus-typec0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_vbus_typec0";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	/*
+	 * should be placed inside mp8859, but not until mp8859 has
+	 * its own dt-binding.
+	 */
+	vcc12v_sys: mp8859-dcdc1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc12v_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		vin-supply = <&vcc_vbus_typec0>;
+	};
+
+	/* switched by pmic_sleep */
+	vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc1v8_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_1v8>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc12v_sys>;
+	};
+
+	/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
+	vcc5v0_host: vcc5v0-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
+		regulator-name = "vcc5v0_host";
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_vbus_typec1: vcc-vbus-typec1 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc_vbus_typec1_en>;
+		regulator-name = "vcc_vbus_typec1";
+		regulator-always-on;
+		vin-supply = <&vcc_sys>;
+	};
+
+	vcc_sys: vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc12v_sys>;
+	};
+
+	vdd_log: vdd-log {
+		compatible = "pwm-regulator";
+		pwms = <&pwm2 0 25000 1>;
+		regulator-name = "vdd_log";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+};
+
+&cpu_l0 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&vdd_cpu_l>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&vdd_cpu_b>;
+};
+
+&emmc_phy {
+	status = "okay";
+};
+
+&gmac {
+	assigned-clocks = <&cru SCLK_RMII_SRC>;
+	assigned-clock-parents = <&clkin_gmac>;
+	clock_in_out = "input";
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 50000>;
+	tx_delay = <0x28>;
+	rx_delay = <0x11>;
+	status = "okay";
+};
+
+&hdmi {
+	ddc-i2c-bus = <&i2c3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_cec>;
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	i2c-scl-rising-time-ns = <168>;
+	i2c-scl-falling-time-ns = <4>;
+	status = "okay";
+
+	rk808: pmic@1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <1>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int_l>;
+		rockchip,system-power-controller;
+		wakeup-source;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		vcc10-supply = <&vcc3v3_sys>;
+		vcc11-supply = <&vcc3v3_sys>;
+		vcc12-supply = <&vcc3v3_sys>;
+		vddio-supply = <&vcc1v8_pmu>;
+
+		regulators {
+			vdd_center: DCDC_REG1 {
+				regulator-name = "vdd_center";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_cpu_l: DCDC_REG2 {
+				regulator-name = "vdd_cpu_l";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-ramp-delay = <6001>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG4 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_codec: LDO_REG1 {
+				regulator-name = "vcca1v8_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_hdmi: LDO_REG2 {
+				regulator-name = "vcc1v8_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc1v8_pmu: LDO_REG3 {
+				regulator-name = "vcc1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcc_sdio: LDO_REG4 {
+				regulator-name = "vcc_sdio";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcca3v0_codec: LDO_REG5 {
+				regulator-name = "vcca3v0_codec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v5: LDO_REG6 {
+				regulator-name = "vcc_1v5";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1500000>;
+				};
+			};
+
+			vcca0v9_hdmi: LDO_REG7 {
+				regulator-name = "vcca0v9_hdmi";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v0: LDO_REG8 {
+				regulator-name = "vcc_3v0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3000000>;
+				};
+			};
+
+			vcc3v3_s3: vcc_lan: SWITCH_REG1 {
+				regulator-name = "vcc3v3_s3";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_s0: SWITCH_REG2 {
+				regulator-name = "vcc3v3_s0";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+
+	vdd_cpu_b: regulator@40 {
+		compatible = "silergy,syr827";
+		reg = <0x40>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel1_gpio>;
+		regulator-name = "vdd_cpu_b";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_gpu: regulator@41 {
+		compatible = "silergy,syr828";
+		reg = <0x41>;
+		fcs,suspend-voltage-selector = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vsel2_gpio>;
+		regulator-name = "vdd_gpu";
+		regulator-min-microvolt = <712500>;
+		regulator-max-microvolt = <1500000>;
+		regulator-ramp-delay = <1000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vcc3v3_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	i2c-scl-rising-time-ns = <300>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c3 {
+	i2c-scl-rising-time-ns = <450>;
+	i2c-scl-falling-time-ns = <15>;
+	status = "okay";
+};
+
+&i2c4 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+
+	fusb1: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb1_int>;
+		vbus-supply = <&vcc_vbus_typec1>;
+		status = "okay";
+	};
+};
+
+&i2c7 {
+	i2c-scl-rising-time-ns = <600>;
+	i2c-scl-falling-time-ns = <20>;
+	status = "okay";
+
+	fusb0: usb-typec@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&fusb0_int>;
+		vbus-supply = <&vcc_vbus_typec0>;
+		status = "okay";
+	};
+};
+
+&i2s0 {
+	rockchip,playback-channels = <8>;
+	rockchip,capture-channels = <8>;
+	status = "okay";
+};
+
+&i2s1 {
+	rockchip,playback-channels = <2>;
+	rockchip,capture-channels = <2>;
+	status = "okay";
+};
+
+&i2s2 {
+	status = "okay";
+};
+
+&io_domains {
+	audio-supply = <&vcca1v8_codec>;
+	bt656-supply = <&vcc_3v0>;
+	gpio1830-supply = <&vcc_3v0>;
+	sdmmc-supply = <&vcc_sdio>;
+	status = "okay";
+};
+
+&pmu_io_domains {
+	pmu1830-supply = <&vcc_3v0>;
+	status = "okay";
+};
+
+&pinctrl {
+	lcd-panel {
+		lcd_panel_reset: lcd-panel-reset {
+			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	pmic {
+		vsel1_gpio: vsel1-gpio {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+
+		vsel2_gpio: vsel2-gpio {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int_l: pmic-int-l {
+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb2 {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		hub_rst: hub-rst {
+			rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
+		};
+	};
+
+	usb-typec {
+		vcc_vbus_typec1_en: vcc-vbus-typec1-en {
+			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	fusb30x {
+		fusb0_int: fusb0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		fusb1_int: fusb1-int {
+			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca1v8_s3>;
+	status = "okay";
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	max-frequency = <150000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+	status = "okay";
+};
+
+&sdhci {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	non-removable;
+	status = "okay";
+};
+
+&tcphy0 {
+	status = "okay";
+};
+
+&tcphy1 {
+	status = "okay";
+};
+
+&tsadc {
+	/* tshut mode 0:CRU 1:GPIO */
+	rockchip,hw-tshut-mode = <1>;
+	/* tshut polarity 0:LOW 1:HIGH */
+	rockchip,hw-tshut-polarity = <1>;
+	status = "okay";
+};
+
+&u2phy0 {
+	status = "okay";
+
+	u2phy0_otg: otg-port {
+		phy-supply = <&vcc_vbus_typec0>;
+		status = "okay";
+	};
+
+	u2phy0_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&u2phy1 {
+	status = "okay";
+
+	u2phy1_otg: otg-port {
+		phy-supply = <&vcc_vbus_typec1>;
+		status = "okay";
+	};
+
+	u2phy1_host: host-port {
+		phy-supply = <&vcc5v0_host>;
+		status = "okay";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&usbdrd3_0 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_0 {
+	status = "okay";
+};
+
+&usbdrd3_1 {
+	status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&vopb {
+	status = "okay";
+};
+
+&vopb_mmu {
+	status = "okay";
+};
+
+&vopl {
+	status = "okay";
+};
+
+&vopl_mmu {
+	status = "okay";
+};
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -79,8 +79,6 @@ void board_init_f(ulong dummy)
 		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
 		       &sysmgr_regs->eccgrp_ocram);

-	memset(__bss_start, 0, __bss_end - __bss_start);
-
 	socfpga_sdram_remap_zero();
 	socfpga_pl310_clear();

--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -12,9 +12,6 @@ obj-y += spl.o
 else
 obj-y += bsec.o
 obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
-ifndef CONFIG_STM32MP1_TRUSTED
-obj-$(CONFIG_SYSRESET) += cmd_poweroff.o
-endif
 endif
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
 obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o
--- a/arch/arm/mach-stm32mp/cmd_poweroff.c
+++ b/arch/arm/mach-stm32mp/cmd_poweroff.c
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
-/*
- * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
- */
-
-#include <common.h>
-#include <command.h>
-#include <sysreset.h>
-
-int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int ret;
-
-	puts("poweroff ...\n");
-	mdelay(100);
-
-	ret = sysreset_walk(SYSRESET_POWER);
-
-	if (ret == -EINPROGRESS)
-		mdelay(1000);
-
-	/*NOTREACHED when power off*/
-	return CMD_RET_FAILURE;
-}
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -7,7 +7,6 @@
 #include <cpu.h>
 #include <dm.h>
 #include <log.h>
-#include <asm/csr.h>
 #include <asm/encoding.h>
 #include <dm/uclass-internal.h>

@@ -48,7 +47,7 @@ static inline bool supports_extension(char ext)
 	return false;
 #else  /* !CONFIG_CPU */
 #ifdef CONFIG_RISCV_MMODE
-	return csr_read(misa) & (1 << (ext - 'a'));
+	return csr_read(CSR_MISA) & (1 << (ext - 'a'));
 #else  /* !CONFIG_RISCV_MMODE */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
@@ -82,7 +81,7 @@ int arch_cpu_init_dm(void)
 	/* Enable FPU */
 	if (supports_extension('d') || supports_extension('f')) {
 		csr_set(MODE_PREFIX(status), MSTATUS_FS);
-		csr_write(fcsr, 0);
+		csr_write(CSR_FCSR, 0);
 	}

 	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
@@ -90,11 +89,11 @@ int arch_cpu_init_dm(void)
 		 * Enable perf counters for cycle, time,
 		 * and instret counters only
 		 */
-		csr_write(mcounteren, GENMASK(2, 0));
+		csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));

 		/* Disable paging */
 		if (supports_extension('s'))
-			csr_write(satp, 0);
+			csr_write(CSR_SATP, 0);
 	}

 	return 0;
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -13,7 +13,6 @@
 #include <config.h>
 #include <common.h>
 #include <elf.h>
-#include <asm/csr.h>
 #include <asm/encoding.h>
 #include <generated/asm-offsets.h>

@@ -41,7 +40,7 @@ secondary_harts_relocation_error:
 .globl _start
 _start:
 #ifdef CONFIG_RISCV_MMODE
-	csrr	a0, mhartid
+	csrr	a0, CSR_MHARTID
 #endif

 	/* save hart id and dtb pointer */
--- a/arch/riscv/include/asm/asm.h
+++ b/arch/riscv/include/asm/asm.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_ASM_H
+#define _ASM_RISCV_ASM_H
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x)	x
+#else
+#define __ASM_STR(x)	#x
+#endif
+
+#if __riscv_xlen == 64
+#define __REG_SEL(a, b)	__ASM_STR(a)
+#elif __riscv_xlen == 32
+#define __REG_SEL(a, b)	__ASM_STR(b)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#define REG_L		__REG_SEL(ld, lw)
+#define REG_S		__REG_SEL(sd, sw)
+#define SZREG		__REG_SEL(8, 4)
+#define LGREG		__REG_SEL(3, 2)
+
+#if __SIZEOF_POINTER__ == 8
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
+#define RISCV_LGPTR		3
+#else
+#define RISCV_PTR		".dword"
+#define RISCV_SZPTR		"8"
+#define RISCV_LGPTR		"3"
+#endif
+#elif __SIZEOF_POINTER__ == 4
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.word
+#define RISCV_SZPTR		4
+#define RISCV_LGPTR		2
+#else
+#define RISCV_PTR		".word"
+#define RISCV_SZPTR		"4"
+#define RISCV_LGPTR		"2"
+#endif
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#if (__SIZEOF_INT__ == 4)
+#define RISCV_INT		__ASM_STR(.word)
+#define RISCV_SZINT		__ASM_STR(4)
+#define RISCV_LGINT		__ASM_STR(2)
+#else
+#error "Unexpected __SIZEOF_INT__"
+#endif
+
+#if (__SIZEOF_SHORT__ == 2)
+#define RISCV_SHORT		__ASM_STR(.half)
+#define RISCV_SZSHORT		__ASM_STR(2)
+#define RISCV_LGSHORT		__ASM_STR(1)
+#else
+#error "Unexpected __SIZEOF_SHORT__"
+#endif
+
+#endif /* _ASM_RISCV_ASM_H */
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only */
 /*
 * Copyright (C) 2015 Regents of the University of California
 *
@@ -8,13 +8,14 @@
 #ifndef _ASM_RISCV_CSR_H
 #define _ASM_RISCV_CSR_H

+#include <asm/asm.h>
 #include <linux/const.h>

 /* Status register flags */
 #define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
 #define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
 #define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
-#define SR_SUM		_AC(0x00040000, UL) /* Supervisor access User Memory */
+#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */

 #define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
 #define SR_FS_OFF	_AC(0x00000000, UL)
@@ -35,7 +36,7 @@
 #endif

 /* SATP flags */
-#if __riscv_xlen == 32
+#ifndef CONFIG_64BIT
 #define SATP_PPN	_AC(0x003FFFFF, UL)
 #define SATP_MODE_32	_AC(0x80000000, UL)
 #define SATP_MODE	SATP_MODE_32
@@ -45,10 +46,18 @@
 #define SATP_MODE	SATP_MODE_39
 #endif

-/* Interrupt Enable and Interrupt Pending flags */
-#define MIE_MSIE	_AC(0x00000008, UL) /* Software Interrupt Enable */
-#define SIE_SSIE	_AC(0x00000002, UL) /* Software Interrupt Enable */
-#define SIE_STIE	_AC(0x00000020, UL) /* Timer Interrupt Enable */
+/* SCAUSE */
+#define SCAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
+
+#define IRQ_U_SOFT		0
+#define IRQ_S_SOFT		1
+#define IRQ_M_SOFT		3
+#define IRQ_U_TIMER		4
+#define IRQ_S_TIMER		5
+#define IRQ_M_TIMER		7
+#define IRQ_U_EXT		8
+#define IRQ_S_EXT		9
+#define IRQ_M_EXT		11

 #define EXC_INST_MISALIGNED	0
 #define EXC_INST_ACCESS		1
@@ -60,14 +69,47 @@
 #define EXC_LOAD_PAGE_FAULT	13
 #define EXC_STORE_PAGE_FAULT	15

-#ifndef __ASSEMBLY__
+/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
+#define MIE_MSIE		(_AC(0x1, UL) << IRQ_M_SOFT)
+#define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
+#define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
+#define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)

-#define xcsr(csr)	#csr
+#define CSR_FCSR		0x003
+#define CSR_CYCLE		0xc00
+#define CSR_TIME		0xc01
+#define CSR_INSTRET		0xc02
+#define CSR_SSTATUS		0x100
+#define CSR_SIE			0x104
+#define CSR_STVEC		0x105
+#define CSR_SCOUNTEREN		0x106
+#define CSR_SSCRATCH		0x140
+#define CSR_SEPC		0x141
+#define CSR_SCAUSE		0x142
+#define CSR_STVAL		0x143
+#define CSR_SIP			0x144
+#define CSR_SATP		0x180
+#define CSR_MSTATUS		0x300
+#define CSR_MISA		0x301
+#define CSR_MIE			0x304
+#define CSR_MTVEC		0x305
+#define CSR_MCOUNTEREN		0x306
+#define CSR_MSCRATCH		0x340
+#define CSR_MEPC		0x341
+#define CSR_MCAUSE		0x342
+#define CSR_MTVAL		0x343
+#define CSR_MIP			0x344
+#define CSR_CYCLEH		0xc80
+#define CSR_TIMEH		0xc81
+#define CSR_INSTRETH		0xc82
+#define CSR_MHARTID		0xf14
+
+#ifndef __ASSEMBLY__

 #define csr_swap(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1"	\
+	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -76,7 +118,7 @@
 #define csr_read(csr)						\
 ({								\
 	register unsigned long __v;				\
-	__asm__ __volatile__ ("csrr %0, " xcsr(csr)		\
+	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
 			      : "=r" (__v) :			\
 			      : "memory");			\
 	__v;							\
@@ -85,7 +127,7 @@
 #define csr_write(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrw " xcsr(csr) ", %0"		\
+	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })
@@ -93,7 +135,7 @@
 #define csr_read_set(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1"	\
+	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -102,7 +144,7 @@
 #define csr_set(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrs " xcsr(csr) ", %0"		\
+	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })
@@ -110,7 +152,7 @@
 #define csr_read_clear(csr, val)				\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1"	\
+	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -119,7 +161,7 @@
 #define csr_clear(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrc " xcsr(csr) ", %0"		\
+	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -7,6 +7,8 @@
 #ifndef RISCV_CSR_ENCODING_H
 #define RISCV_CSR_ENCODING_H

+#include <asm/csr.h>
+
 #ifdef CONFIG_RISCV_SMODE
 #define MODE_PREFIX(__suffix)	s##__suffix
 #else
@@ -49,13 +51,10 @@
 #define SSTATUS64_SD	0x8000000000000000

 #define MIP_SSIP	BIT(IRQ_S_SOFT)
-#define MIP_HSIP	BIT(IRQ_H_SOFT)
 #define MIP_MSIP	BIT(IRQ_M_SOFT)
 #define MIP_STIP	BIT(IRQ_S_TIMER)
-#define MIP_HTIP	BIT(IRQ_H_TIMER)
 #define MIP_MTIP	BIT(IRQ_M_TIMER)
 #define MIP_SEIP	BIT(IRQ_S_EXT)
-#define MIP_HEIP	BIT(IRQ_H_EXT)
 #define MIP_MEIP	BIT(IRQ_M_EXT)

 #define SIP_SSIP	MIP_SSIP
@@ -73,18 +72,6 @@
 #define VM_SV39		9
 #define VM_SV48		10

-#define IRQ_S_SOFT	1
-#define IRQ_H_SOFT	2
-#define IRQ_M_SOFT	3
-#define IRQ_S_TIMER	5
-#define IRQ_H_TIMER	6
-#define IRQ_M_TIMER	7
-#define IRQ_S_EXT	9
-#define IRQ_H_EXT	10
-#define IRQ_M_EXT	11
-#define IRQ_COP		12
-#define IRQ_HOST	13
-
 #define CAUSE_MISALIGNED_FETCH		0
 #define CAUSE_FETCH_ACCESS		1
 #define CAUSE_ILLEGAL_INSTRUCTION	2
@@ -167,227 +154,6 @@
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)

-/* CSR numbers */
-#define CSR_FFLAGS		0x1
-#define CSR_FRM			0x2
-#define CSR_FCSR		0x3
-
-#define CSR_SSTATUS		0x100
-#define CSR_SEDELEG		0x102
-#define CSR_SIDELEG		0x103
-#define CSR_SIE			0x104
-#define CSR_STVEC		0x105
-#define CSR_SCOUNTEREN		0x106
-#define CSR_SSCRATCH		0x140
-#define CSR_SEPC		0x141
-#define CSR_SCAUSE		0x142
-#define CSR_STVAL		0x143
-#define CSR_SIP			0x144
-#define CSR_SATP		0x180
-
-#define CSR_MSTATUS		0x300
-#define CSR_MISA		0x301
-#define CSR_MEDELEG		0x302
-#define CSR_MIDELEG		0x303
-#define CSR_MIE			0x304
-#define CSR_MTVEC		0x305
-#define CSR_MCOUNTEREN		0x306
-#define CSR_MHPMEVENT3		0x323
-#define CSR_MHPMEVENT4		0x324
-#define CSR_MHPMEVENT5		0x325
-#define CSR_MHPMEVENT6		0x326
-#define CSR_MHPMEVENT7		0x327
-#define CSR_MHPMEVENT8		0x328
-#define CSR_MHPMEVENT9		0x329
-#define CSR_MHPMEVENT10		0x32a
-#define CSR_MHPMEVENT11		0x32b
-#define CSR_MHPMEVENT12		0x32c
-#define CSR_MHPMEVENT13		0x32d
-#define CSR_MHPMEVENT14		0x32e
-#define CSR_MHPMEVENT15		0x32f
-#define CSR_MHPMEVENT16		0x330
-#define CSR_MHPMEVENT17		0x331
-#define CSR_MHPMEVENT18		0x332
-#define CSR_MHPMEVENT19		0x333
-#define CSR_MHPMEVENT20		0x334
-#define CSR_MHPMEVENT21		0x335
-#define CSR_MHPMEVENT22		0x336
-#define CSR_MHPMEVENT23		0x337
-#define CSR_MHPMEVENT24		0x338
-#define CSR_MHPMEVENT25		0x339
-#define CSR_MHPMEVENT26		0x33a
-#define CSR_MHPMEVENT27		0x33b
-#define CSR_MHPMEVENT28		0x33c
-#define CSR_MHPMEVENT29		0x33d
-#define CSR_MHPMEVENT30		0x33e
-#define CSR_MHPMEVENT31		0x33f
-#define CSR_MSCRATCH		0x340
-#define CSR_MEPC		0x341
-#define CSR_MCAUSE		0x342
-#define CSR_MTVAL		0x343
-#define CSR_MIP			0x344
-#define CSR_PMPCFG0		0x3a0
-#define CSR_PMPCFG1		0x3a1
-#define CSR_PMPCFG2		0x3a2
-#define CSR_PMPCFG3		0x3a3
-#define CSR_PMPADDR0		0x3b0
-#define CSR_PMPADDR1		0x3b1
-#define CSR_PMPADDR2		0x3b2
-#define CSR_PMPADDR3		0x3b3
-#define CSR_PMPADDR4		0x3b4
-#define CSR_PMPADDR5		0x3b5
-#define CSR_PMPADDR6		0x3b6
-#define CSR_PMPADDR7		0x3b7
-#define CSR_PMPADDR8		0x3b8
-#define CSR_PMPADDR9		0x3b9
-#define CSR_PMPADDR10		0x3ba
-#define CSR_PMPADDR11		0x3bb
-#define CSR_PMPADDR12		0x3bc
-#define CSR_PMPADDR13		0x3bd
-#define CSR_PMPADDR14		0x3be
-#define CSR_PMPADDR15		0x3bf
-
-#define CSR_TSELECT		0x7a0
-#define CSR_TDATA1		0x7a1
-#define CSR_TDATA2		0x7a2
-#define CSR_TDATA3		0x7a3
-#define CSR_DCSR		0x7b0
-#define CSR_DPC			0x7b1
-#define CSR_DSCRATCH		0x7b2
-
-#define CSR_MCYCLE		0xb00
-#define CSR_MINSTRET		0xb02
-#define CSR_MHPMCOUNTER3	0xb03
-#define CSR_MHPMCOUNTER4	0xb04
-#define CSR_MHPMCOUNTER5	0xb05
-#define CSR_MHPMCOUNTER6	0xb06
-#define CSR_MHPMCOUNTER7	0xb07
-#define CSR_MHPMCOUNTER8	0xb08
-#define CSR_MHPMCOUNTER9	0xb09
-#define CSR_MHPMCOUNTER10	0xb0a
-#define CSR_MHPMCOUNTER11	0xb0b
-#define CSR_MHPMCOUNTER12	0xb0c
-#define CSR_MHPMCOUNTER13	0xb0d
-#define CSR_MHPMCOUNTER14	0xb0e
-#define CSR_MHPMCOUNTER15	0xb0f
-#define CSR_MHPMCOUNTER16	0xb10
-#define CSR_MHPMCOUNTER17	0xb11
-#define CSR_MHPMCOUNTER18	0xb12
-#define CSR_MHPMCOUNTER19	0xb13
-#define CSR_MHPMCOUNTER20	0xb14
-#define CSR_MHPMCOUNTER21	0xb15
-#define CSR_MHPMCOUNTER22	0xb16
-#define CSR_MHPMCOUNTER23	0xb17
-#define CSR_MHPMCOUNTER24	0xb18
-#define CSR_MHPMCOUNTER25	0xb19
-#define CSR_MHPMCOUNTER26	0xb1a
-#define CSR_MHPMCOUNTER27	0xb1b
-#define CSR_MHPMCOUNTER28	0xb1c
-#define CSR_MHPMCOUNTER29	0xb1d
-#define CSR_MHPMCOUNTER30	0xb1e
-#define CSR_MHPMCOUNTER31	0xb1f
-#define CSR_MCYCLEH		0xb80
-#define CSR_MINSTRETH		0xb82
-#define CSR_MHPMCOUNTER3H	0xb83
-#define CSR_MHPMCOUNTER4H	0xb84
-#define CSR_MHPMCOUNTER5H	0xb85
-#define CSR_MHPMCOUNTER6H	0xb86
-#define CSR_MHPMCOUNTER7H	0xb87
-#define CSR_MHPMCOUNTER8H	0xb88
-#define CSR_MHPMCOUNTER9H	0xb89
-#define CSR_MHPMCOUNTER10H	0xb8a
-#define CSR_MHPMCOUNTER11H	0xb8b
-#define CSR_MHPMCOUNTER12H	0xb8c
-#define CSR_MHPMCOUNTER13H	0xb8d
-#define CSR_MHPMCOUNTER14H	0xb8e
-#define CSR_MHPMCOUNTER15H	0xb8f
-#define CSR_MHPMCOUNTER16H	0xb90
-#define CSR_MHPMCOUNTER17H	0xb91
-#define CSR_MHPMCOUNTER18H	0xb92
-#define CSR_MHPMCOUNTER19H	0xb93
-#define CSR_MHPMCOUNTER20H	0xb94
-#define CSR_MHPMCOUNTER21H	0xb95
-#define CSR_MHPMCOUNTER22H	0xb96
-#define CSR_MHPMCOUNTER23H	0xb97
-#define CSR_MHPMCOUNTER24H	0xb98
-#define CSR_MHPMCOUNTER25H	0xb99
-#define CSR_MHPMCOUNTER26H	0xb9a
-#define CSR_MHPMCOUNTER27H	0xb9b
-#define CSR_MHPMCOUNTER28H	0xb9c
-#define CSR_MHPMCOUNTER29H	0xb9d
-#define CSR_MHPMCOUNTER30H	0xb9e
-#define CSR_MHPMCOUNTER31H	0xb9f
-
-#define CSR_CYCLE		0xc00
-#define CSR_TIME		0xc01
-#define CSR_INSTRET		0xc02
-#define CSR_HPMCOUNTER3		0xc03
-#define CSR_HPMCOUNTER4		0xc04
-#define CSR_HPMCOUNTER5		0xc05
-#define CSR_HPMCOUNTER6		0xc06
-#define CSR_HPMCOUNTER7		0xc07
-#define CSR_HPMCOUNTER8		0xc08
-#define CSR_HPMCOUNTER9		0xc09
-#define CSR_HPMCOUNTER10	0xc0a
-#define CSR_HPMCOUNTER11	0xc0b
-#define CSR_HPMCOUNTER12	0xc0c
-#define CSR_HPMCOUNTER13	0xc0d
-#define CSR_HPMCOUNTER14	0xc0e
-#define CSR_HPMCOUNTER15	0xc0f
-#define CSR_HPMCOUNTER16	0xc10
-#define CSR_HPMCOUNTER17	0xc11
-#define CSR_HPMCOUNTER18	0xc12
-#define CSR_HPMCOUNTER19	0xc13
-#define CSR_HPMCOUNTER20	0xc14
-#define CSR_HPMCOUNTER21	0xc15
-#define CSR_HPMCOUNTER22	0xc16
-#define CSR_HPMCOUNTER23	0xc17
-#define CSR_HPMCOUNTER24	0xc18
-#define CSR_HPMCOUNTER25	0xc19
-#define CSR_HPMCOUNTER26	0xc1a
-#define CSR_HPMCOUNTER27	0xc1b
-#define CSR_HPMCOUNTER28	0xc1c
-#define CSR_HPMCOUNTER29	0xc1d
-#define CSR_HPMCOUNTER30	0xc1e
-#define CSR_HPMCOUNTER31	0xc1f
-#define CSR_CYCLEH		0xc80
-#define CSR_TIMEH		0xc81
-#define CSR_INSTRETH		0xc82
-#define CSR_HPMCOUNTER3H	0xc83
-#define CSR_HPMCOUNTER4H	0xc84
-#define CSR_HPMCOUNTER5H	0xc85
-#define CSR_HPMCOUNTER6H	0xc86
-#define CSR_HPMCOUNTER7H	0xc87
-#define CSR_HPMCOUNTER8H	0xc88
-#define CSR_HPMCOUNTER9H	0xc89
-#define CSR_HPMCOUNTER10H	0xc8a
-#define CSR_HPMCOUNTER11H	0xc8b
-#define CSR_HPMCOUNTER12H	0xc8c
-#define CSR_HPMCOUNTER13H	0xc8d
-#define CSR_HPMCOUNTER14H	0xc8e
-#define CSR_HPMCOUNTER15H	0xc8f
-#define CSR_HPMCOUNTER16H	0xc90
-#define CSR_HPMCOUNTER17H	0xc91
-#define CSR_HPMCOUNTER18H	0xc92
-#define CSR_HPMCOUNTER19H	0xc93
-#define CSR_HPMCOUNTER20H	0xc94
-#define CSR_HPMCOUNTER21H	0xc95
-#define CSR_HPMCOUNTER22H	0xc96
-#define CSR_HPMCOUNTER23H	0xc97
-#define CSR_HPMCOUNTER24H	0xc98
-#define CSR_HPMCOUNTER25H	0xc99
-#define CSR_HPMCOUNTER26H	0xc9a
-#define CSR_HPMCOUNTER27H	0xc9b
-#define CSR_HPMCOUNTER28H	0xc9c
-#define CSR_HPMCOUNTER29H	0xc9d
-#define CSR_HPMCOUNTER30H	0xc9e
-#define CSR_HPMCOUNTER31H	0xc9f
-
-#define CSR_MVENDORID		0xf11
-#define CSR_MARCHID		0xf12
-#define CSR_MIMPID		0xf13
-#define CSR_MHARTID		0xf14
-
 #endif /* __riscv */

 #endif /* RISCV_CSR_ENCODING_H */
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -355,7 +355,6 @@ void state_reset_for_test(struct sandbox_state *state)
 {
 	/* No reset yet, so mark it as such. Always allow power reset */
 	state->last_sysreset = SYSRESET_COUNT;
-	state->sysreset_allowed[SYSRESET_POWER] = true;
 	state->sysreset_allowed[SYSRESET_POWER_OFF] = true;

 	memset(&state->wdt, '\0', sizeof(state->wdt));
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -73,9 +73,6 @@ static void board_final_cleanup(void)

 int last_stage_init(void)
 {
-	if (gd->flags & GD_FLG_COLD_BOOT)
-		timestamp_add_to_bootstage();
-
 	/* start usb so that usb keyboard can be used as input device */
 	if (CONFIG_IS_ENABLED(USB_KEYBOARD))
 		usb_init();
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -40,9 +40,6 @@ _x86boot_start:
 	movl	%eax, %cr0
 	wbinvd

-	/* Tell 32-bit code it is being entered from an in-RAM copy */
-	movl	$GD_FLG_WARM_BOOT, %ebx
-
 	/*
 	 * Zero the BIST (Built-In Self Test) value since we don't have it.
 	 * It must be 0 or the previous loader would have reported an error.
@@ -55,11 +52,7 @@ _x86boot_start:
 	.align	4
 	.long	0x12345678
 _start:
-	/*
-	 * This is the 32-bit cold-reset entry point, coming from start16.
-	 * Set %ebx to GD_FLG_COLD_BOOT to indicate this.
-	 */
-	movl	$GD_FLG_COLD_BOOT, %ebx
+	/* This is the 32-bit cold-reset entry point, coming from start16 */

 	/* Save BIST */
 	movl	%eax, %ebp
--- a/arch/x86/cpu/start16.S
+++ b/arch/x86/cpu/start16.S
@@ -23,9 +23,6 @@ start16:
 	/* Save BIST */
 	movl	%eax, %ecx

-	/* Set the Cold Boot / Hard Reset flag */
-	movl	$GD_FLG_COLD_BOOT, %ebx
-
 	xorl	%eax, %eax
 	movl	%eax, %cr3	/* Invalidate TLB */

--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -137,10 +137,4 @@ static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)

 #endif

-/*
- * Our private Global Data Flags
- */
-#define GD_FLG_COLD_BOOT	0x10000	/* Cold Boot */
-#define GD_FLG_WARM_BOOT	0x20000	/* Warm Boot */
-
 #endif /* __ASM_GBL_DATA_H */
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -49,6 +49,12 @@ F:	configs/orangepi-rk3399_defconfig
 F:	arch/arm/dts/rk3399-u-boot.dtsi
 F:	arch/arm/dts/rk3399-orangepi-u-boot.dtsi

+ROC-RK3399-PC
+M:	Levin Du <djw@t-chip.com.cn>
+S:	Maintained
+F:	configs/roc-rk3399-pc_defconfig
+F:	arch/arm/dts/rk3399-roc-pc-u-boot.dtsi
+
 ROCK-PI-4
 M:	Akash Gajjar <akash@openedev.com>
 M:	Jagan Teki <jagan@amarulasolutions.com>
--- a/cmd/cbfs.c
+++ b/cmd/cbfs.c
@@ -29,7 +29,7 @@ static int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc,
 		}
 	}
 	file_cbfs_init(end_of_rom);
-	if (file_cbfs_result != CBFS_SUCCESS) {
+	if (cbfs_get_result() != CBFS_SUCCESS) {
 		printf("%s.\n", file_cbfs_error());
 		return 1;
 	}
@@ -67,7 +67,7 @@ static int do_cbfs_fsload(cmd_tbl_t *cmdtp, int flag, int argc,

 	file = file_cbfs_find(argv[2]);
 	if (!file) {
-		if (file_cbfs_result == CBFS_FILE_NOT_FOUND)
+		if (cbfs_get_result() == CBFS_FILE_NOT_FOUND)
 			printf("%s: %s\n", file_cbfs_error(), argv[2]);
 		else
 			printf("%s.\n", file_cbfs_error());
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -41,8 +41,8 @@ CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_DM_I2C=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
 # CONFIG_SPL_DM_MMC is not set
+CONFIG_MMC_OMAP_HS=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=24000000
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -58,9 +58,6 @@ CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
-CONFIG_WDT=y
-CONFIG_WDT_OMAP3=y
-# CONFIG_SPL_WDT is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
@@ -73,6 +70,8 @@ CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
 CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+# CONFIG_SPL_WDT is not set
 CONFIG_DYNAMIC_CRC_TABLE=y
 CONFIG_RSA=y
 CONFIG_LZO=y
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -50,6 +50,5 @@ CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_TPS65910=y
 CONFIG_CONS_INDEX=4
-# CONFIG_OMAP_WATCHDOG is not set
 # CONFIG_USE_TINY_PRINTF is not set
 # CONFIG_EFI_LOADER is not set
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x30000000
 CONFIG_AM43XX=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x110000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI,QSPI_BOOT"
 CONFIG_QSPI_BOOT=y
@@ -31,7 +32,6 @@ CONFIG_OF_LIST="am4372-generic am437x-sk-evm am437x-idk-evm"
 CONFIG_DTB_RESELECT=y
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 # CONFIG_BLK is not set
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
-CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 # CONFIG_ISO_PARTITION is not set
@@ -49,7 +48,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -66,7 +66,6 @@ CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 CONFIG_SPL_PINCTRL=y
--- a/configs/am65x_hs_evm_r5_defconfig
+++ b/configs/am65x_hs_evm_r5_defconfig
@@ -71,7 +71,6 @@ CONFIG_K3_SEC_PROXY=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_K3_ARASAN=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 CONFIG_SPL_PINCTRL=y
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_BOOTDELAY=3
 # CONFIG_DISPLAY_CPUINFO is not set
 # CONFIG_DISPLAY_BOARDINFO is not set
@@ -20,7 +21,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x10000
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x40000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
 CONFIG_BOOTDELAY=3
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -21,7 +22,6 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x10000
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
 CONFIG_BOOTDELAY=3
@@ -34,7 +35,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
 CONFIG_BOOTDELAY=3
@@ -34,7 +35,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
@@ -37,7 +38,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
@@ -37,7 +38,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
 CONFIG_BOOTDELAY=3
@@ -34,7 +35,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
 CONFIG_BOOTDELAY=3
@@ -34,7 +35,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEBUG_UART=y
 CONFIG_SPI_BOOT=y
 CONFIG_BOOTDELAY=3
@@ -34,7 +35,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
@@ -34,7 +35,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9rlek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 # CONFIG_NET is not set
 CONFIG_DM=y
 CONFIG_CLK=y
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_USE_DATAFLASH"
@@ -36,7 +37,6 @@ CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_SPI_BOOT=y
@@ -36,7 +37,6 @@ CONFIG_CMD_UBI=y
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
 CONFIG_DEBUG_UART_CLOCK=132000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DEBUG_UART=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
 CONFIG_BOOTDELAY=3
@@ -33,7 +34,6 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9260ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -71,6 +71,5 @@ CONFIG_DEBUG_UART_ATMEL=y
 CONFIG_ATMEL_USART=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_HEXDUMP=y
 # CONFIG_EFI_LOADER is not set
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -102,7 +102,6 @@ CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_TI=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-# CONFIG_OMAP_WATCHDOG is not set
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_SHA1=y
 CONFIG_SHA256=y
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -87,7 +87,6 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_LCD=y
-# CONFIG_OMAP_WATCHDOG is not set
 CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_OF_LIBFDT_OVERLAY is not set
 # CONFIG_EFI_LOADER is not set
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
 CONFIG_ROCKCHIP_RK3288=y
@@ -11,14 +12,17 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -39,16 +43,15 @@ CONFIG_SPL_PARTITION_UUIDS=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
@@ -58,12 +61,18 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINMUX is not set
+CONFIG_SPL_PINCONF=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK8XX=y
@@ -77,16 +86,14 @@ CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -76,6 +76,5 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
 CONFIG_ROCKCHIP_RK3288=y
 # CONFIG_SPL_MMC_SUPPORT is not set
-CONFIG_TARGET_CHROMEBOOK_JERRY=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEBUG_UART_BASE=0xff690000
@@ -11,7 +11,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
 CONFIG_LOG=y
@@ -20,8 +19,12 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -43,16 +46,15 @@ CONFIG_SPL_PARTITION_UUIDS=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-jerry"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
@@ -62,12 +64,18 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINMUX is not set
+CONFIG_SPL_PINCONF=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK8XX=y
@@ -83,19 +91,17 @@ CONFIG_I2S_ROCKCHIP=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
 CONFIG_CONSOLE_TRUETYPE=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_EDP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
 # CONFIG_USE_PRIVATE_LIBGCC is not set
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
 CONFIG_ROCKCHIP_RK3288=y
@@ -11,15 +12,18 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -41,16 +45,15 @@ CONFIG_SPL_PARTITION_UUIDS=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
@@ -60,12 +63,18 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINMUX is not set
+CONFIG_SPL_PINCONF=y
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK8XX=y
@@ -82,18 +91,16 @@ CONFIG_SOUND_MAX98090=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_EDP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
 CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00100000
 CONFIG_ROCKCHIP_RK3288=y
@@ -11,7 +12,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SILENT_CONSOLE=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
@@ -19,8 +19,12 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_TEXT_BASE=0xff704000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
+# CONFIG_SPL_CRC32_SUPPORT is not set
+CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -47,11 +51,9 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 # CONFIG_SPL_SIMPLE_BUS is not set
+# CONFIG_SPL_BLK is not set
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SYS_I2C_ROCKCHIP=y
@@ -61,12 +63,16 @@ CONFIG_CROS_EC_KEYB=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
+# CONFIG_SPL_DM_MMC is not set
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
 CONFIG_DM_PMIC=y
 # CONFIG_SPL_PMIC_CHILDREN is not set
 CONFIG_PMIC_RK8XX=y
@@ -80,20 +86,17 @@ CONFIG_ROCKCHIP_SERIAL=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_DWC2=y
 CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_DM_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
 CONFIG_CONSOLE_TRUETYPE=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_EDP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
 # CONFIG_USE_PRIVATE_LIBGCC is not set
+CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
-# CONFIG_SPL_OF_LIBFDT is not set
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -18,6 +18,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_TEXT_BASE=0xf4000a00
 # CONFIG_SPL_BANNER_PRINT is not set
 # CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_MMC_TINY=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_DM=y
 # CONFIG_CMD_FLASH is not set
@@ -39,10 +40,8 @@ CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 # CONFIG_MMC_VERBOSE is not set
-CONFIG_SPL_MMC_TINY=y
 CONFIG_JZ47XX_MMC=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_LZO=y
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0xc0000
 CONFIG_SPL=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -46,7 +47,6 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SECURE_BOOT=y
 CONFIG_TARGET_COLIBRI_IMX7=y
 CONFIG_TARGET_COLIBRI_IMX7_EMMC=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
 # CONFIG_CMD_DEKBLOB is not set
@@ -26,7 +27,6 @@ CONFIG_CRC32_VERIFY=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
-CONFIG_RANDOM_UUID=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
@@ -48,7 +48,6 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -88,9 +88,8 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_DM_VIDEO=y
-CONFIG_SYS_CONSOLE_FG_COL=0x00
+CONFIG_VIDEO_FSL_DCU_FB=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
 # CONFIG_EFI_UNICODE_CAPITALIZATION is not set
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -80,4 +80,3 @@ CONFIG_USB_MUSB_DA8XX=y
 CONFIG_USB_MUSB_PIO_ONLY=y
 CONFIG_USB_STORAGE=y
 # CONFIG_FAT_WRITE is not set
-CONFIG_USE_TINY_PRINTF=y
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ENV_SIZE=0x21000
 CONFIG_ENV_OFFSET=0x3DE000
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SECT_SIZE=0x21000
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTARGS=y
@@ -49,7 +50,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ethernut5"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
-CONFIG_ENV_SECT_SIZE=0x21000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -2,11 +2,11 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x00200000
 CONFIG_ROCKCHIP_RK3368=y
-CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
 CONFIG_TPL_LIBCOMMON_SUPPORT=y
 CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
 CONFIG_TARGET_EVB_PX5=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL_STACK_R_ADDR=0x600000
@@ -29,13 +29,11 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
-CONFIG_TPL_BOOTROM_SUPPORT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
 CONFIG_SPL_OF_CONTROL=y
@@ -67,7 +65,6 @@ CONFIG_DM_RESET=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYSRESET=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_TPL_TINY_MEMSET=y
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -5,7 +5,6 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x60000000
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_ROCKCHIP_RK3036=y
-CONFIG_TARGET_EVB_RK3036=y
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x0
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL_STACK_R_ADDR=0x80000
@@ -25,6 +24,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -46,18 +46,18 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 # CONFIG_SPL_DM_SERIAL is not set
-# CONFIG_SPL_SYSRESET is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
+# CONFIG_SPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x310a
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -47,5 +47,4 @@ CONFIG_USB_OHCI_GENERIC=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_ERRNO_STR=y
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -2,9 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x61000000
 CONFIG_ROCKCHIP_RK322X=y
-CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
 CONFIG_TARGET_EVB_RK3229=y
+CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds"
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL_STACK_R_ADDR=0x60600000
 CONFIG_DEBUG_UART_BASE=0x11030000
@@ -25,6 +25,7 @@ CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
 CONFIG_SPL_OPTEE=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -22,6 +22,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -74,7 +75,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -1,18 +1,18 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_TPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 CONFIG_SYS_TEXT_BASE=0x00200000
 CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_DEBUG_UART_BASE=0xFF130000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -22,16 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SPL_ATF_SUPPORT=y
-CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
-CONFIG_TPL_BOOTROM_SUPPORT=y
 CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_TPL_SERIAL_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_TPL_SERIAL_PRESENT=y
-CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000
-CONFIG_SPL_STACK_R_ADDR=0x600000
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
@@ -40,7 +31,9 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_TPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_TPL_DM=y
@@ -58,7 +51,6 @@ CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
-CONFIG_TPL_OF_PLATDATA=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
@@ -84,7 +76,6 @@ CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
@@ -99,7 +90,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_TPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -58,6 +58,5 @@ CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
 CONFIG_DISPLAY_ROCKCHIP_MIPI=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x60000000
 CONFIG_ROCKCHIP_RV1108=y
-CONFIG_TARGET_EVB_RV1108=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BASE=0x10210000
 CONFIG_DEBUG_UART_CLOCK=24000000
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -76,7 +77,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -47,5 +47,4 @@ CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_ERRNO_STR=y
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -25,6 +25,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -81,7 +82,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -53,6 +53,5 @@ CONFIG_USB_ETHER_ASIX88179=y
 CONFIG_USB_ETHER_MCS7830=y
 CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -69,7 +69,6 @@ CONFIG_LED_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_NAND_ATMEL=y
 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
-# CONFIG_CONFIG_UBI_SILENCE_MSG is not set
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
@@ -84,4 +83,3 @@ CONFIG_ATMEL_PIT_TIMER=y
 CONFIG_WDT=y
 CONFIG_WDT_AT91=y
 # CONFIG_UBIFS_SILENCE_MSG is not set
-CONFIG_USE_TINY_PRINTF=y
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -36,7 +36,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Ventana > "
 CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL_NAND_OFS=0x1100000
 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -36,7 +36,6 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Ventana > "
 CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPL_NAND_OFS=0x1100000
 CONFIG_CMD_SPL_WRITE_SIZE=0x20000
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
--- a/configs/hikey960_defconfig
+++ b/configs/hikey960_defconfig
@@ -4,21 +4,20 @@ CONFIG_SYS_TEXT_BASE=0x1ac98000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_IDENT_STRING="\nHikey960"
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=3
-CONFIG_SYS_PROMPT="U-Boot => "
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyAMA6,115200n8 root=/dev/mmcblk0p2 rw"
 CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_GPT=y
+CONFIG_SYS_PROMPT="U-Boot => "
 CONFIG_CMD_MD5SUM=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_DEFAULT_DEVICE_TREE="hi3660-hikey960"
 CONFIG_ENV_IS_IN_EXT4=y
 CONFIG_ENV_EXT4_INTERFACE="mmc"
 CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2"
@@ -28,3 +27,4 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_K3=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -59,6 +59,5 @@ CONFIG_SMC911X_32_BIT=y
 CONFIG_CONS_INDEX=3
 CONFIG_SPI=y
 CONFIG_OMAP3_SPI=y
-CONFIG_UBIFS_SILENCE_MSG=y
 CONFIG_BCH=y
 CONFIG_FDT_FIXUP_PARTITIONS=y
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MX6LOGICPD=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -14,7 +14,6 @@ CONFIG_DEBUG_UART_BASE=0x021f0000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_LIBDISK_SUPPORT=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_CMD_NANDBCB=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -8,7 +8,6 @@ CONFIG_TARGET_MX6Q_ENGICAM=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
 # CONFIG_CMD_BMODE is not set
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -30,8 +30,8 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -55,8 +55,8 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ATHEROS=y
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -12,9 +12,9 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
-# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_USE_BOOTCOMMAND=y
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -39,7 +39,6 @@ CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
-CONFIG_DOS_PARTITION=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
@@ -91,5 +90,4 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_FS_EXT4=y
-CONFIG_FS_FAT=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
@@ -47,12 +48,13 @@ CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_PINCTRL=y
 CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SPL_DM_SERIAL is not set
-# CONFIG_SPL_SYSRESET is not set
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
+# CONFIG_SPL_SYSRESET is not set
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_GADGET=y
@@ -60,7 +62,6 @@ CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
 CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x310a
 CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_FUNCTION_MASS_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_SMSC95XX=y
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -31,13 +31,11 @@ CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_SPL_TEXT_BASE=0x00000000
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
 CONFIG_SPL_ATF=y
 CONFIG_TPL=y
-CONFIG_TPL_BOOTROM_SUPPORT=y
 CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
@@ -88,7 +86,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
-CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_LZO=y
 CONFIG_ERRNO_STR=y
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012A2G5RDB=y
+CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1012afrdm_tfa_defconfig
+++ b/configs/ls1012afrdm_tfa_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AFRDM=y
+CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AFRWY=y
+CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SECURE_BOOT=y
-CONFIG_TFABOOT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AFRWY=y
-CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_TFABOOT=y
+CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AQDS=y
+CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SECURE_BOOT=y
 CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012AQDS=y
+CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012ARDB=y
+CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_SECURE_BOOT=y
 CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1012ARDB=y
+CONFIG_TFABOOT=y
 CONFIG_SYS_TEXT_BASE=0x82000000
 CONFIG_QSPI_AHB_INIT=y
-CONFIG_TFABOOT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
 CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -1,79 +1,56 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATSN=y
 CONFIG_SYS_TEXT_BASE=0x40100000
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
 CONFIG_QSPI_BOOT=y
 CONFIG_BOOTDELAY=3
-CONFIG_HUSH_PARSER=y
+CONFIG_SILENT_CONSOLE=y
+CONFIG_MISC_INIT_R=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
-CONFIG_CMD_FAT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
-CONFIG_SPI=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_NETDEVICES=y
-CONFIG_DM_ETH=y
-CONFIG_TSEC_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_DATAFLASH=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_PCI=y
-CONFIG_CMD_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_CMD_MMC=y
-CONFIG_DM_MMC=y
-CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_FSL=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_HAS_FSL_XHCI_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CMD_EXT2=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMDLINE_TAG=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_FIT=y
-CONFIG_CMD_DM=y
-CONFIG_AHCI=y
-CONFIG_CMD_I2C=y
-CONFIG_BLK=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_TSEC_ENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -1,91 +1,68 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATSN=y
-CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_TEXT_BASE=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_MISC_INIT_R=y
-CONFIG_SPL=y
-CONFIG_SPL_FRAMEWORK=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
 CONFIG_SD_BOOT=y
 CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_TEXT_BASE=0x10000000
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
-CONFIG_HUSH_PARSER=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_DM=y
 CONFIG_CMD_GPT=y
-CONFIG_CMD_FAT=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
-CONFIG_FSL_ESDHC=y
 CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FS_UUID=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
-CONFIG_SPI=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_NETDEVICES=y
-CONFIG_DM_ETH=y
-CONFIG_TSEC_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_DATAFLASH=y
-CONFIG_FSL_DSPI=y
-CONFIG_FSL_QSPI=y
-CONFIG_PCI=y
-CONFIG_CMD_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_FSL=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_HAS_FSL_XHCI_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_CMD_EXT2=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_GIGE=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_PHY_FIXED=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMDLINE_TAG=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_CMD_BOOTZ=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_FIT=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_CMD_DM=y
-CONFIG_AHCI=y
-CONFIG_CMD_I2C=y
-CONFIG_BLK=y
-CONFIG_DM_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_FS_UUID=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_TSEC_ENET=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -37,12 +37,12 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
-CONFIG_DM_ETH=y
 CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -37,12 +37,12 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
-CONFIG_DM_ETH=y
 CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -39,12 +39,12 @@ CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_SYS_FLASH_CFI=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
-CONFIG_DM_ETH=y
 CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -39,12 +39,12 @@ CONFIG_FSL_ESDHC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
 CONFIG_PHY_GIGE=y
 CONFIG_E1000=y
 CONFIG_MII=y
-CONFIG_DM_ETH=y
 CONFIG_TSEC_ENET=y
-CONFIG_PHY_ATHEROS=y
 CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Tom Rini	a2ca54ff52	Merge tag 'u-boot-rockchip-20190819' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add ROC-RK3399-PC board support - Move CONFIG_SPI_FLASH_GIGADEVICE and CONFIG_CMD_USB_MASS_STORAGE to Kconfig - using SYSRESET_POWER_OFF for poweroff (Note that patch for rk8xx pmic is droped for it can not pass Travis build) - fix ofnode_get_name() assert	2019-08-19 09:22:57 -04:00
Tom Rini	0ed2e2d825	Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 - QEMU build warning fix when CONFIG_DISTRO_DEFAULTS=n - Small fixes on x86 reST docs - Allow CBFS to be used in SPL - Remove x86 specific GD flags	2019-08-19 09:21:46 -04:00
Urja Rannikko	b8050511c6	sysreset: move stm32mp sysreset poweroff implementation to sysreset uclass This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF to signal when we need it. Enable it from the STPMIC1 config and in sandbox. The config flag is transitionary, that is it can be removed after all poweroff implementations use sysreset, and just have CMD_POWEROFF depend on sysreset. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>	2019-08-19 12:43:26 +08:00
Urja Rannikko	857f39d7b0	sysreset: switch to using SYSRESET_POWER_OFF for poweroff It seems that SYSRESET_POWER_OFF was added recently, and all previous code used SYSRESET_POWER for poweroff. SYSRESET_POWER is supposed to be a PMIC-level power cycle, not a poweroff. (Comment by Simon Glass) SYSRESET_POWER means to do a power reset (removing and reinstating all power) SYSRESET_POWER_OFF means to turn the device off and leave it off Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> (Update comment to help understand the patch) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>	2019-08-19 12:43:26 +08:00
Urja Rannikko	7ba79f2696	configs: update rk3288 veyron defconfigs Updates jerry, mickey, minnie and speedy defconfigs to: - fit the SPL in 32k - boot from SPI (only) - remove gadget support (these have no OTG port) Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Rebase on top of tree) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>	2019-08-19 12:43:26 +08:00
Urja Rannikko	a186e8aa67	configs: Move CONFIG_CMD_USB_MASS_STORAGE properly into Kconfig This affects RK3036, RK322X and RK3288 - the defconfig changes done by moveconfig.py for the veyrons were left out on purpose because they dont have an OTG port, and will get their config updated in the next commit. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>	2019-08-19 12:43:26 +08:00
Urja Rannikko	64df512e15	configs: Move CONFIG_SPI_FLASH_GIGADEVICE properly into Kconfig Affects rk3288 veyrons and rk3036, this was mostly done by moveconfig.py. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>	2019-08-19 12:43:26 +08:00
Kever Yang	8f0a70e816	core: ofnode: do not assert if node not valid in ofnode_get_name() In some case with LIVE DT, some node always not valid, or not have a valid name, eg. blk driver add by mmc. Return fail instead of Assert for this kind of ofnode, and this help with assert happen from time to time when of_live is enabled and DEBUG is enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>	2019-08-19 12:43:26 +08:00
Levin Du	8a681f4c5a	rockchip: rk3399: Add ROC-RK3399-PC support Add initial support for ROC-RK3399-PC board. Specification - Rockchip RK3399 - LPDDR4 4GiB - eMMC slot - SD card slot - RTL8211E 1Gbps - HDMI Out, DP, MIPI DSI/CSI, EDP - PCIe M.2 - USB 2.0, USB-3.0 - USB C Type Commit details of rk3399-roc-pc.dts sync from Linux v5.2: "arm64: dts: rockchip: add support for ROC-RK3399-PC board" (sha1: 8bb878cf20ae10809c36db96993bfce7026d062b) Signed-off-by: Levin Du <djw@t-chip.com.cn> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>	2019-08-19 12:43:26 +08:00
Stefan Roese	d117f917bf	global_data: Remove comment of reserved arch-specific GD flags With the removal of the x86 specific GD flags, there are no arch- specific GD flags any more. Let's remove the comment about reserving the upper 16 bits for arch-specific flags in the common header. This gives us more flexibility with the usage of the GD flags. As a matter of fact, we are already using more than 16 bits for common GD flags (with the addition of GD_FLG_WDT_READY). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>	2019-08-18 21:54:10 +08:00
Stefan Roese	8ad01ce36f	x86: Remove x86 specific GD flags as they are not referenced at all This patch removes the x86 architecture specific GD flags (GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S. But the coreboot target does not use start16.S at all and boots directly from the 32-bit start code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>	2019-08-18 21:54:10 +08:00
Simon Glass	ad79d603aa	cbfs: Rename camel-case variables Rename some camel-case variables to match U-Boot style. Camel case is not generally allowed in U-Boot. Rename this variable to fit in with the style. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Simon Glass	630b2f39dd	cbfs: Add functions to support multiple CBFSs Sometimes an image has multiple CBFS. The current CBFS API is limited to handling only one at time. Also it keeps track of the CBFS internally in BSS, which does not work before relocation, for example. Add a few new functions to overcome these limitations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Simon Glass	c7f1693474	cbfs: Move result variable into the struct Move the result variable into the struct also, so that it can be used when BSS is not available. Add a function to read it. Note that all functions sill use the BSS version of the data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Simon Glass	02e4af63a9	cbfs: Move static variables into a struct At present there are a number of static variables in BSS. This cannot work with SPL, at least until BSS is available in board_init_r(). Move the variables into a struct, so it is possible to malloc() it and use it before BSS is available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Simon Glass	fc7b9e16a0	cbfs: Move declarations above functions At present this file has a function at the top, above declarations. This is normally avoided, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Simon Glass	72b2465c6b	cbfs: Allow CBFS to be used in SPL Add a new Kconfig option to enable CBFS in SPL. This can be useful when the memory-init code is in CBFS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Heinrich Schuchardt	0c4a0e601b	doc: arch: correct links in x86.rst Correctly reference uefi/uefi.rst and uefi/u-boot_on_efi.rst. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Heinrich Schuchardt	79bf4450a1	doc: formatting slimbootloader.rst Avoid a warning when building the 'make htmldocs' target: doc/board/intel/slimbootloader.rst:90: WARNING: Title underline too short. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Bin Meng	039c031e08	x86: qemu: Fix build warnings with CONFIG_DISTRO_DEFAULTS=n Use DISTRO_BOOTENV to decouple BOOTENV from CONFIG_DISTRO_DEFAULTS. Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>	2019-08-18 21:54:10 +08:00
Tom Rini	81fed78c0a	Merge tag 'efi-2019-10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for v2019.10-rc3 This pull request provides corrections for the SetVirtualAddress runtime service and avoids possible calls to NULL by consumers of the EFI_PXE_BASE_CODE_PROTOCOL.	2019-08-17 10:31:25 -04:00
Tom Rini	8c650a9fed	Merge branch 'master' of git://git.denx.de/u-boot-socfpga - Misc gen5 fixes	2019-08-17 10:30:56 -04:00
Tom Rini	3d240d89c4	Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv - Fix sifive serial y-modem transfer. - Access CSRs using CSR numbers. - Update doc sifive-fu540 - Support big endian hosts and target.	2019-08-16 07:22:21 -04:00
Heinrich Schuchardt	9f8932d055	efi_loader: do not call efi_runtime_detach twice Commit `7f95104d91` ("efi_loader: detach runtime in ExitBootServices()") added a call to efi_runtime_detach() to ExitBootServices() but did not remove the call in SetVirtualAddressMap(). Remove the superfluous function call. Correct a comment referring to efi_runtime_detach(). Fixes: `7f95104d91` ("efi_loader: detach runtime in ExitBootServices()") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>	2019-08-15 20:33:10 +02:00
Heinrich Schuchardt	53e1d8fae8	efi_loader: parameter check in SetVirtualAddressMap Check the parameters DescriptorSize and DescriptiorVersion of SetVirtualAddressMap() as prescribed by the UEFI specification. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>	2019-08-15 20:33:10 +02:00
Heinrich Schuchardt	a6d37098bd	efi_loader: EFI_PXE_BASE_CODE_PROTOCOL stub U-Boot implements the EFI_PXE_BASE_CODE_PROTOCOL because GRUB uses the mode information for booting via PXE. All function pointers in the protocol were NULL up to now which will cause immediate crashes when the services of the protocol are called. Create function stubs for all services of the protocol returning EFI_UNSUPPORTED. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>	2019-08-15 20:33:10 +02:00
Simon Goldschmidt	a89441a74f	arm: socfpga: gen5: don't zero bss in board_init_f() The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the DDR driver does not use bss any more, bss is not used before board_init_r() and we can remove this hack. bss is normally zeroed by crt0.S, but after board_init_f(), before board_init_r(). socfpga just had this double-zeroing because it invalidly used bss in board_init_f() already (during DDR initialization). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>	2019-08-15 08:50:02 +02:00
Dalon Westergreen	998f7cb29a	ARM: socfpga: update CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot.img Bring cyclone5 / arria5 / arria10 in line with convention and use u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>	2019-08-15 08:50:00 +02:00
Ley Foon Tan	63b312d882	arm: socfpga: Fix SYSRESET_SOCFPGA_S10 config name The CONFIG name should be SYSRESET_SOCFPGA_S10 instead of SYSRESET_SOCFPGA_STRATIX10. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>	2019-08-15 08:50:00 +02:00
Marcus Comstedt	4539926a9c	riscv: tools: Add big endian target support to prelink-riscv Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> Cc: Rick Chen <rick@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>	2019-08-15 13:42:28 +08:00
Marcus Comstedt	e604410d3e	riscv: tools: Fix prelink-riscv to work on big endian hosts All ELF fields whose values are inspected by the code are converted to CPU byteorder first. Values which are copied verbatim (relocation fixups) are not swapped to CPU byteorder and back as it is not needed. Signed-off-by: Marcus Comstedt <marcus@mc.pp.se> Cc: Rick Chen <rick@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>	2019-08-15 13:42:28 +08:00
Anup Patel	88af42d3de	doc: sifive-fu540: Update README to explicitly load DTB for Linux We should explicitly load DTB from TFTP server or MMC/SD card for Linux booting. This will allow us: 1. To use different Linux DTB for SiFive Unleashed board with expansion board connected. 2. Avoid re-flashing OpenSBI firmware whenever board connections change. This patch updates reference bootlog in SiFive FU540 README as-per above. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>	2019-08-15 13:42:28 +08:00
Bin Meng	4d2583dba1	riscv: Access CSRs using CSR numbers We should prefer accessing CSRs using their CSR numbers because: 1. It compiles fine with older toolchains. 2. We can use latest CSR names in #define macro names of CSR numbers as-per RISC-V spec. 3. We can access newly added CSRs even if toolchain does not recognize newly added CSRs by name. This commit is inspired from Linux kernel commit a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers"). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>	2019-08-15 13:42:28 +08:00
Bin Meng	268753f8e6	riscv: Sync csr.h with Linux kernel v5.2 This syncs csr.h with Linux kernel 5.2, and imports asm.h that is required by csr.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>	2019-08-15 13:42:28 +08:00
Sagar Shrikant Kadam	8836384c75	riscv : serial: use rx watermark to indicate rx data is present In y-modem transfer mode, tstc/getc fail to check if there is any data available / received in RX FIFO, and so y-modem transfer never succeeds. Using receive watermark bit within ip register fixes the issue. This patch is based on commit c7392b7bc4e1 ("Use the RX watermark interrupt pending bit for TSTC") available at[1] [1] https://github.com/sifive/HiFive_U-Boot/tree/regression Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>	2019-08-15 13:42:28 +08:00
Tom Rini	df33f86468	configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>	2019-08-14 08:11:27 -04:00