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Author SHA1 Message Date
Tom Rini
a2ca54ff52 Merge tag 'u-boot-rockchip-20190819' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add ROC-RK3399-PC board support
- Move CONFIG_SPI_FLASH_GIGADEVICE and CONFIG_CMD_USB_MASS_STORAGE to
  Kconfig
- using SYSRESET_POWER_OFF for poweroff
  (Note that patch for rk8xx pmic is droped for it can not pass Travis
  build)
- fix ofnode_get_name() assert
2019-08-19 09:22:57 -04:00
Tom Rini
0ed2e2d825 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- QEMU build warning fix when CONFIG_DISTRO_DEFAULTS=n
- Small fixes on x86 reST docs
- Allow CBFS to be used in SPL
- Remove x86 specific GD flags
2019-08-19 09:21:46 -04:00
Urja Rannikko
b8050511c6 sysreset: move stm32mp sysreset poweroff implementation to sysreset uclass
This is a generic implementation. Add CONFIG_SYSRESET_CMD_POWEROFF
to signal when we need it. Enable it from the STPMIC1 config and in
sandbox.

The config flag is transitionary, that is it can be removed after all
poweroff implementations use sysreset, and just have CMD_POWEROFF depend
on sysreset.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-08-19 12:43:26 +08:00
Urja Rannikko
857f39d7b0 sysreset: switch to using SYSRESET_POWER_OFF for poweroff
It seems that SYSRESET_POWER_OFF was added recently, and all previous code
used SYSRESET_POWER for poweroff. SYSRESET_POWER is supposed to be a
PMIC-level power cycle, not a poweroff.

(Comment by Simon Glass)
SYSRESET_POWER means to do a power reset (removing and reinstating all power)
SYSRESET_POWER_OFF means to turn the device off and leave it off

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
(Update comment to help understand the patch)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19 12:43:26 +08:00
Urja Rannikko
7ba79f2696 configs: update rk3288 veyron defconfigs
Updates jerry, mickey, minnie and speedy defconfigs to:
- fit the SPL in 32k
- boot from SPI (only)
- remove gadget support (these have no OTG port)

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Rebase on top of tree)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19 12:43:26 +08:00
Urja Rannikko
a186e8aa67 configs: Move CONFIG_CMD_USB_MASS_STORAGE properly into Kconfig
This affects RK3036, RK322X and RK3288 - the defconfig changes done by
moveconfig.py for the veyrons were left out on purpose because they dont
have an OTG port, and will get their config updated in the next commit.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19 12:43:26 +08:00
Urja Rannikko
64df512e15 configs: Move CONFIG_SPI_FLASH_GIGADEVICE properly into Kconfig
Affects rk3288 veyrons and rk3036, this was mostly done by
moveconfig.py.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19 12:43:26 +08:00
Kever Yang
8f0a70e816 core: ofnode: do not assert if node not valid in ofnode_get_name()
In some case with LIVE DT, some node always not valid, or not have
a valid name, eg. blk driver add by mmc.
Return fail instead of Assert for this kind of ofnode, and this
help with assert happen from time to time when of_live is enabled
and DEBUG is enabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-08-19 12:43:26 +08:00
Levin Du
8a681f4c5a rockchip: rk3399: Add ROC-RK3399-PC support
Add initial support for ROC-RK3399-PC board.

Specification
- Rockchip RK3399
- LPDDR4 4GiB
- eMMC slot
- SD card slot
- RTL8211E 1Gbps
- HDMI Out, DP, MIPI DSI/CSI, EDP
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type

Commit details of rk3399-roc-pc.dts sync from Linux v5.2:
"arm64: dts: rockchip: add support for ROC-RK3399-PC board"
(sha1: 8bb878cf20ae10809c36db96993bfce7026d062b)

Signed-off-by: Levin Du <djw@t-chip.com.cn>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-19 12:43:26 +08:00
Stefan Roese
d117f917bf global_data: Remove comment of reserved arch-specific GD flags
With the removal of the x86 specific GD flags, there are no arch-
specific GD flags any more. Let's remove the comment about reserving the
upper 16 bits for arch-specific flags in the common header. This gives
us more flexibility with the usage of the GD flags.

As a matter of fact, we are already using more than 16 bits for common
GD flags (with the addition of GD_FLG_WDT_READY).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-08-18 21:54:10 +08:00
Stefan Roese
8ad01ce36f x86: Remove x86 specific GD flags as they are not referenced at all
This patch removes the x86 architecture specific GD flags
(GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only
GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S.
But the coreboot target does not use start16.S at all and boots directly
from the 32-bit start code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-18 21:54:10 +08:00
Simon Glass
ad79d603aa cbfs: Rename camel-case variables
Rename some camel-case variables to match U-Boot style.

Camel case is not generally allowed in U-Boot. Rename this variable to fit
in with the style.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Simon Glass
630b2f39dd cbfs: Add functions to support multiple CBFSs
Sometimes an image has multiple CBFS. The current CBFS API is limited to
handling only one at time. Also it keeps track of the CBFS internally in
BSS, which does not work before relocation, for example.

Add a few new functions to overcome these limitations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Simon Glass
c7f1693474 cbfs: Move result variable into the struct
Move the result variable into the struct also, so that it can be used when
BSS is not available. Add a function to read it.

Note that all functions sill use the BSS version of the data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Simon Glass
02e4af63a9 cbfs: Move static variables into a struct
At present there are a number of static variables in BSS. This cannot work
with SPL, at least until BSS is available in board_init_r().

Move the variables into a struct, so it is possible to malloc() it and use
it before BSS is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Simon Glass
fc7b9e16a0 cbfs: Move declarations above functions
At present this file has a function at the top, above declarations. This
is normally avoided, so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Simon Glass
72b2465c6b cbfs: Allow CBFS to be used in SPL
Add a new Kconfig option to enable CBFS in SPL. This can be useful when
the memory-init code is in CBFS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Heinrich Schuchardt
0c4a0e601b doc: arch: correct links in x86.rst
Correctly reference uefi/uefi.rst and uefi/u-boot_on_efi.rst.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Heinrich Schuchardt
79bf4450a1 doc: formatting slimbootloader.rst
Avoid a warning when building the 'make htmldocs' target:

doc/board/intel/slimbootloader.rst:90: WARNING: Title underline too short.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Bin Meng
039c031e08 x86: qemu: Fix build warnings with CONFIG_DISTRO_DEFAULTS=n
Use DISTRO_BOOTENV to decouple BOOTENV from CONFIG_DISTRO_DEFAULTS.

Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-18 21:54:10 +08:00
Tom Rini
81fed78c0a Merge tag 'efi-2019-10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for v2019.10-rc3

This pull request provides corrections for the SetVirtualAddress runtime
service and avoids possible calls to NULL by consumers of the
EFI_PXE_BASE_CODE_PROTOCOL.
2019-08-17 10:31:25 -04:00
Tom Rini
8c650a9fed Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Misc gen5 fixes
2019-08-17 10:30:56 -04:00
Tom Rini
3d240d89c4 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Fix sifive serial y-modem transfer.
- Access CSRs using CSR numbers.
- Update doc sifive-fu540
- Support big endian hosts and target.
2019-08-16 07:22:21 -04:00
Heinrich Schuchardt
9f8932d055 efi_loader: do not call efi_runtime_detach twice
Commit 7f95104d91 ("efi_loader: detach runtime in ExitBootServices()")
added a call to efi_runtime_detach() to ExitBootServices() but did not
remove the call in SetVirtualAddressMap().

Remove the superfluous function call.

Correct a comment referring to efi_runtime_detach().

Fixes: 7f95104d91 ("efi_loader: detach runtime in ExitBootServices()")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-08-15 20:33:10 +02:00
Heinrich Schuchardt
53e1d8fae8 efi_loader: parameter check in SetVirtualAddressMap
Check the parameters DescriptorSize and DescriptiorVersion of
SetVirtualAddressMap() as prescribed by the UEFI specification.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-08-15 20:33:10 +02:00
Heinrich Schuchardt
a6d37098bd efi_loader: EFI_PXE_BASE_CODE_PROTOCOL stub
U-Boot implements the EFI_PXE_BASE_CODE_PROTOCOL because GRUB uses the mode
information for booting via PXE. All function pointers in the protocol were
NULL up to now which will cause immediate crashes when the services of the
protocol are called.

Create function stubs for all services of the protocol returning
EFI_UNSUPPORTED.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-08-15 20:33:10 +02:00
Simon Goldschmidt
a89441a74f arm: socfpga: gen5: don't zero bss in board_init_f()
The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the
DDR driver does not use bss any more, bss is not used before board_init_r()
and we can remove this hack.

bss is normally zeroed by crt0.S, but after board_init_f(), before
board_init_r(). socfpga just had this double-zeroing because it invalidly
used bss in board_init_f() already (during DDR initialization).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-15 08:50:02 +02:00
Dalon Westergreen
998f7cb29a ARM: socfpga: update CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot.img
Bring cyclone5 / arria5 / arria10 in line with convention and use
u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
2019-08-15 08:50:00 +02:00
Ley Foon Tan
63b312d882 arm: socfpga: Fix SYSRESET_SOCFPGA_S10 config name
The CONFIG name should be SYSRESET_SOCFPGA_S10 instead of
SYSRESET_SOCFPGA_STRATIX10.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-15 08:50:00 +02:00
Marcus Comstedt
4539926a9c riscv: tools: Add big endian target support to prelink-riscv
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2019-08-15 13:42:28 +08:00
Marcus Comstedt
e604410d3e riscv: tools: Fix prelink-riscv to work on big endian hosts
All ELF fields whose values are inspected by the code are converted to
CPU byteorder first.  Values which are copied verbatim (relocation
fixups) are not swapped to CPU byteorder and back as it is not needed.

Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
Cc: Rick Chen <rick@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2019-08-15 13:42:28 +08:00
Anup Patel
88af42d3de doc: sifive-fu540: Update README to explicitly load DTB for Linux
We should explicitly load DTB from TFTP server or MMC/SD card
for Linux booting. This will allow us:
1. To use different Linux DTB for SiFive Unleashed board with
   expansion board connected.
2. Avoid re-flashing OpenSBI firmware whenever board connections
   change.

This patch updates reference bootlog in SiFive FU540 README
as-per above.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-15 13:42:28 +08:00
Bin Meng
4d2583dba1 riscv: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers
because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR
   numbers as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not
   recognize newly added CSRs by name.

This commit is inspired from Linux kernel commit a3182c91ef4e
("RISC-V: Access CSRs using CSR numbers").

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-08-15 13:42:28 +08:00
Bin Meng
268753f8e6 riscv: Sync csr.h with Linux kernel v5.2
This syncs csr.h with Linux kernel 5.2, and imports asm.h that
is required by csr.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-08-15 13:42:28 +08:00
Sagar Shrikant Kadam
8836384c75 riscv : serial: use rx watermark to indicate rx data is present
In y-modem transfer mode, tstc/getc fail to check if there is any
data available / received in RX FIFO, and so y-modem transfer never
succeeds. Using receive watermark bit within ip register fixes the
issue.

This patch is based on commit c7392b7bc4e1 ("Use the RX watermark
interrupt pending bit for TSTC") available at[1]

[1] https://github.com/sifive/HiFive_U-Boot/tree/regression

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2019-08-15 13:42:28 +08:00
Tom Rini
df33f86468 configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-14 08:11:27 -04:00
Tom Rini
f55e80f37e Prepare v2019.10-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-13 18:23:35 -04:00
Tom Rini
88c7a0a8c2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Various improvements to Keymile boards - mostly DT conversation
  (Pascal & Holger)
- Removal of now unsupported Keymile boards (Pascal & Holger)
- Small MVEBU PCI fix (Marek)
- Turris Omnia defconfig update (Marek)
- Misc Allied Telesis defconfig updates (Chris)
2019-08-12 23:03:44 -04:00
Tom Rini
60f38d82c4 Merge tag 'u-boot-amlogic-20190812' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- amlogic: add support for the SEI Robotic SEI510
2019-08-12 23:03:35 -04:00
Tom Rini
9c6115822e Merge branch '2019-08-11-ti-imports'
- More DaVinci updates and fixes
- PCIe support on am65x
- Watchdog converted to DM
- Assorted other bugfixes
2019-08-12 18:47:53 -04:00
Tom Rini
5939afc961 Merge branch '2019-08-11-master-imports'
- environment cleanup
- HiKey 960 support
- Some PCI fixes
2019-08-12 18:46:07 -04:00
Tom Rini
d7ae932152 gitlab-ci: Consolidate some testsuite jobs
We do not need to split binman, buildman, dtoc and patman test suite
runs into 3 jobs.  Instead, run them as a single job.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-12 15:19:18 -04:00
Tom Rini
edbe0d5664 gitlab-ci: Add USER environment variable to buildman/patman tests
The way that some of the tests here are designed, they expect USER to be
set in the environment.  This is not the case in the docker images, so
set a reasonable value.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-12 15:19:18 -04:00
Andreas Dannenberg
0805fe151d arm: K3: sysfw-loader: Do not require full printf() for version info
A previous commit...

commit 2a51e16bd5 ("configs: Make USE_TINY_PRINTF depend on SPL||TPL and be default")

...causes the System Firmware version string during SPL boot to no longer
getting printed to the console as expected. To fix this issue rework the
handling of that string to only use basic printf() syntax rather than
for example disabling CONFIG_USE_TINY_PRINTF on affected devices, this
way maintaining most of the memory size benefit the initial patch brings
when it comes to SPL.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-08-12 13:33:43 -04:00
Vignesh Raghavendra
c659a979ea firmware: ti_sci: Parse all resource ranges even if some is not available
Do not fail if any of the requested subtypes are not available, but set the
number of resources to 0 and continue parsing the resource ranges.

Based on Linux kernel patch by Peter Ujfalusi <peter.ujfalusi@ti.com>

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-08-12 13:33:43 -04:00
Adam Ford
51cd1e2373 ARM: da850-evm: Enable SPI Flash and NAND Flash when booting NOR
Historically there have been various boot options, SPI flash,
NAND or NOR. The NOR flash is mutually exclusive with MMC, but
it isn't mutually exclusive with NAND or SPI Flash, so this patch
enables both NAND flash and SPI Flash when booting from NOR.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-12 13:33:42 -04:00
Adam Ford
79bb64678c ARM: da850-evm: Enable filesystem commands when booting from NOR
The configuration with NOR is mutually exclusive with MMC, and as
such, the filesystem commands were disabled.  With the USB host
enabled, this patch enables the file system command which can
be executed on storage devices attached to the USB.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-12 13:33:42 -04:00
Adam Ford
d2c30190ee ARM: da850-evm: Increase environment NOR partition offset
The current size allocated to U-Boot is 384k, but U-Boot has grown
to 436K which means that saving the environmental variables wipes
out part of the U-Boot source and the board ceases to function.
Due to the sector and erase size for the NOR part and a desire to
not have to change partition sizes often, this patch moves the
U-Boot environmental variables to an offset of 1M so saveenv
does not brick the board.  This patch also sets up MTDIDS and
MTDPARTS to clearly show where U-Boot and U-Boot's environmental
variables are located.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-12 13:33:42 -04:00
Adam Ford
66e2637b19 ARM: da850-evm: Fix Lowlevel init
A previous patch for enabling the NAND config set a flag called
CONFIG_SKIP_LOWLEVEL_INIT when it should have been called
CONFIG_SKIP_LOWLEVEL_INIT_ONLY.  The affect this had was creating
a delay on startup for the NOR version which is XIP and doesn't have
SPL, so the lowlevel initialization functions need to operate.
This delay was not really noticeable at first, but the delays have been
getting longer, finally reached the point of nearly seven seconds
before the board would appear to start.

This patch sets the CONFIG_SKIP_LOWLEVEL_INIT_ONLY instead which means
"The normal CP15 init (such as enabling the instruction cache) is still
performed" per the README.  It doesn't appear to have any adverse
behavior on the SPI Flash or the NAND flash boards which use SPL.

Fixes: 93f3362762 ("ARM: configs: Add da850evm_nand to boot from NAND")

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-12 13:33:41 -04:00
Sekhar Nori
36de3b0668 configs: am65x_evm_a53: enable support for PCIe ethernet cards
Enable support for Intel E1000 based PCIe ethernet cards that
can be used to test PCIe RC functionality on AM65x EVM.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:41 -04:00
Sekhar Nori
476e991452 arm: dts: k3-am65: add support for PCIe and SERDES
Add needed device-tree nodes to support PCIe 0
and SERDES on AM65x SoC. The nodes are kept
disabled by default.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:40 -04:00
Sekhar Nori
e0598c4584 configs: am65x_evm_a53: enable PCIe support
Enable support for PCIe and related configurations
on AM654 EVM platform.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:40 -04:00
Sekhar Nori
888e1caeae phy: add support for AM654x SERDES
Add a new SERDES driver for TI's AM654x SoC which configures
the SERDES only for PCIe. Support fo USB3 can be added later.

SERDES in am654x has three input clocks (left input, external
reference clock and right input) and two output clocks (left
output and right output) in addition to a PLL mux clock which
the SERDES uses for Clock Multiplier Unit (CMU refclock).

The PLL mux clock can select from one of the three input
clocks. The right output can select between left input and
external reference clock while the left output can select
between the right input and external reference clock.

The driver has support to select PLL mux and left/right output
mux as specified in device tree.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:39 -04:00
Sekhar Nori
03c396bb5f pcie: ti: add driver for AM65x PCIe RC
Add driver supporting PCIe root-complex available
on TI's AM65x SoC.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:39 -04:00
Sekhar Nori
f5b904796f dm: core: add support for getting register address and size
Current dev_read_*() API lacks support to get address and size
of a "reg" property by name or index. Add support for the same.

Livetree support has been added but not tested on real hardware.

The existing unit tests testing reading address from device-tree
have been updated to test address as well as size.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:39 -04:00
Sekhar Nori
acbb7cd4d3 clk: add support for clk_is_match()
Add support for clk_is_match() which is required to
know if two clock pointers point to the same exact
physical clock.

Also add a unit test for the new API.

Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-12 13:33:38 -04:00
Nishanth Menon
71cd80af86 power: domain: ti-sci-power-domain: Add device ID info to get/set_device failure
Failure log for ti_sci_power_domain_on/off is as below:
"ti_sci_power_domain_on: get/set_device failed (-19)"

The above information is useless for debug without information
on what specific device access failed. So add that information as well.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-08-12 13:33:38 -04:00
Hannes Schmelzer
60df809f62 board/BuR/brsmarc1: initial commit
This commit adds support for the B&R brsmarc1 SoM.

The SoM is based on TI's AM335x SoC.
Mainly vxWorks 6.9.4.x is running on the board,
doing some PLC stuff on various carrier boards.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-08-12 13:33:37 -04:00
Suniel Mahesh
6912f2a8ae watchdog: omap_wdt: Disable DM watchdog support in SPL
This patch disables DM watchdog support for SPL builds and uses
the legacy omap watchdog driver on TI AM335x chipsets.

The following build error is reported if DM watchdog support was
enabled in SPL:

  CC      spl/drivers/usb/gadget/rndis.o
  LD      spl/drivers/usb/gadget/built-in.o
  LD      spl/drivers/usb/musb-new/built-in.o
  LD      spl/drivers/built-in.o
  LD      spl/u-boot-spl
arm-linux-ld.bfd: u-boot-spl section .u_boot_list will not fit in region .sram
arm-linux-ld.bfd: region .sram overflowed by 440 bytes
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2

Adjusted WATCHDOG_RESET macro accordingly. Earlier it was pointing
to hw_watchdog_reset. Since CONFIG_WATCHDOG replaces CONFIG_HW_WATCHDOG,
now WATCHDOG_RESET macro points to watchdog_reset. This watchdog_reset
is not defined anywhere for am33xx/omap2 and needs to be defined. Fixed
this by simply calling hw_watchdog_reset in watchdog_reset.

Built and tested on AM335x device (BeagleboneBlack), compile tested for
all other AM33xx/omap2 based boards.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
[trini: Fix watchdog.h logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-12 13:27:55 -04:00
Marek Behún
193a1e9f19 pci: pci_mvebu: set BAR0 after memory space is set
The non-DM version of this driver used to set BAR0 register after the
calls to pci_set_region.
I found out that for some strange reason the ath10k driver in kernel
fails to work if this is done the other way around.
I know that Linux's driver should not depend on how U-Boot does things,
but for some strange reason it does and this seems to be the simplest
solution. Fix it since it caused regressions on Omnia.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: VlaoMao <vlaomao@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 13:59:31 +02:00
Suniel Mahesh
7659ea32a6 watchdog: omap_wdt: Convert watchdog driver to use DT and DM
This patch adds device tree and driver model watchdog support,
converts the legacy omap watchdog driver to driver model for
TI AM335x chipsets. The following compile warning is removed:

===================== WARNING ======================
This board does not use CONFIG_WDT (DM watchdog support).
Please update the board to use CONFIG_WDT before the
v2019.10 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

CONFIG_HW_WATCHDOG is no more a default option for AM33XX devices
after DT/DM conversion, adjusted kconfig accordingly.

DM watchdog support is enabled by default in SPL. The SPL image
doesn't fit into SRAM because of size constraints and build breaks
with an overflow. For this reason DM watchdog support should be
disabled in SPL, driver code should be adjusted accordingly to serve
this purpose.
Built and tested on AM335x device (BeagleboneBlack), compile tested
for all other AM33xx based boards.

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-08-12 07:25:22 -04:00
Anselm Busse
2800bb155b ARM: omap3: overo: Fix MMC init for SPL
The SPL for the Overo board does not initialise the MMC. Hence, it
cannot load the main boot loader from the SD card susequently. This
patch moves the initialisation code for the MMC so it gets included in
the SPL.

[trini: Add missing header]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-12 07:24:29 -04:00
Neil Armstrong
eb1677250d configs: sei510: disable PSCI_RESET to support fastboot reboot_flag
Disable the PSCI_RESET reboot handler to permit handling the reboot
flag and calling the PSCI handler with the flag in parameter.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:05:10 +02:00
Neil Armstrong
9a34dedfae ARM: meson: Add support for fastboot_set_reboot_flag()
Add support for fastboot_set_reboot_flag() by storing the reboot
flag in the common code to be used by the custom PSCI reboot handler.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:05:10 +02:00
Jerome Brunet
0998367515 boards: meson: add g12a sei510
The SEI510 board is based on the Amlogic S905X2 SoC
from the Amlogic G12A SoC family.

The board has the following specifications :
- Amlogic S905X2 ARM Cortex-A53 quad-core SoC
- XGB DDR4 SDRAM
- 10/100 Ethernet (Internal PHY)
- 1 x USB 3.0 Host
- eMMC
- SDcard
- Infrared receiver
- SDIO WiFi Module

The board default behaviour is for booting Android and triggers
fastboot on recovery or reboot mode.

USB vendor ID (used by fastboot) is 0x18d1 (Google) for
default udev rules for existing android users work out of the box.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:04:03 +02:00
Neil Armstrong
b1dd7debea arm: meson: add sm command to retrieve the reboot reason
The Secure Monitor offers multiple services, like returning the
SoC unique serial number, and can provide the "reboot reason" as
set by the previous booted system.

This extends the Amlogic specific "sm" cmd with a "reboot_reason" subcommand
to print or set a specified environment variable with the reboot reason in
human readable format.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Neil Armstrong
559e6256f8 arm: meson: add sm cmd to retrieve SoC serial
The Secure Monitor offers multiple services, like returning the
SoC unique serial number, already used to generate an unique MAC
address.

This adds a new, Amlogic specific, "sm" cmd with a "serial" subcommand
to write the SoC unique serial to memory.

This "cm" command will be extended in further patches.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Neil Armstrong
191a374e65 configs: meson64: permit redefining ENV_SIZE
Permit redefining ENV_SIZE for board specific configs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Neil Armstrong
cddca4b4ca ARM: dts: Import Amlogic G12A SEI510 DT from Linux 5.3-rc1
Import Linux 5.2-rc1 sei510 DT from 5f9e832c1370 ("Linus 5.3-rc1") for the
meson-g12a-sei510 board.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-12 10:02:30 +02:00
Marek Behún
6de5a717c7 arm: mvebu: turris_omnia: update defconfig
Add Macronis SPI flash support - some Omnia routers are shipped with
this SPI flash chip.
Also add the memtest command to defconfig.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Chris Packham
9921179278 ARM: configs: Enable DM_ETH for SBx81LIFKW and SBx81LIFXCAT
The mvgbe driver supports DM_ETH so switch these boards to using it.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Holger Brunck
00f9baf8eb powerpc/km: remove unmaintained board KMLION1
This board is unmaintained and can be removed. This also allows us to
remove kmp204x-common.h and integrate it in kmp204x.h.

Signed-off-by: Valentin Longchamp <valentin.longchamp@ch.abb.com>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Holger Brunck
7b472733d8 powerpc/km: remove unmaintained target KMVECT1
Signed-off-by: Valentin Longchamp <valentin.longchamp@ch.abb.com>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
1bd17b9f7b km/arm: remove unmaintained target PORTL2
Remove the PORTL2 board and all its dependencies as it is no longer
supported by the company.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
abbaa8ed14 km/rgmii: port Ethernet interface of KM Kirkwood boards to driver model
Activate the driver model for the Ethernet interface (RGMII) in the KM
Kirkwood Kconfig file. Additionally, raise the auto negotiation timeout
to eight seconds as more time is required for those boards.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
b75e9e3fce km/uart: port UART interface of KM Kirkwood boards to driver model
Activate the driver model for the serial interface in the KM Kirkwood
Kconfig file. The associated preprocessor definitions could be removed
from the header file. However, the clock of 200 MHz needs to be declared
in the device tree.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
9db6bff8b5 km: fixed typo in KM Kirkwood header file
A typo in the km_kirkwood.h header prevented to undefine the initialization
of the Kirkwood PCIe interface.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
e5c9e830b8 km: clean up header files for KM Kirkwood boards
Remove unused preprocessor definitions and comments of already eliminated
code.

The Ethernet driver configuration is already declared in
arch/arm/mach-kirkwood/include/mach/config.h and, therefore, superfluous.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
432579c4d1 km: remove obsolete definitions in KM header files
After moving the KM specific configurations to Kconfig, the associated
preprocessor definitions can now be removed in the headers. Moreover, the
whitelist has been adapted correspondingly.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Pascal Linder
707f06f331 km: add Kconfig menus for KM boards
To execute the conversion away from board specific header files, Kconfig
menus have been implemented for all KM boards and additionally for those
having an ARM architecture.

For the moment, the preprocessor definitions stay in the headers. The
boolean types, however, needed a modification (#define CONFIG_* 1).

The default configuration files of some boards required an update in order
to not change the currently defined values of the configurations.

Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-08-12 09:12:38 +02:00
Simon Glass
ec1fa18561 common: Add a note about the effort to reduce common.h
This file has quite a lot of general definitions and include files. Add a
note about our intent to remove more of this.

The file should ultimately include the configuration and perhaps a very
other very common things used by most U-Boot files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 19:27:41 -04:00
Simon Glass
9e5616dea9 Drop PCMCIA
This is no-longer used in U-Boot and has not been converted to driver
model. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 19:27:41 -04:00
Simon Glass
f3998fdc4d env: Rename environment.h to env_internal.h
This file contains lots of internal details about the environment. Most
code can include env.h instead, calling the functions there as needed.

Rename this file and add a comment at the top to indicate its internal
nature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
[trini: Fixup apalis-tk1.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-11 19:27:31 -04:00
Simon Glass
e7dcf5645f env: Drop environment.h header file where not needed
This header file is now only used by files that access internal
environment features. Drop it from various places where it is not needed.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
f030b7b260 env: Move TOTAL_MALLOC_LEN to environment.h
This declaration is only used in three files. Although it relates to
malloc() it is actually only used during malloc() init. It uses CONFIG
options including CONFIG_ENV_ADDR which are defined only in environment.h
so this header must be included anyway, for TOTAL_MALLOC_LEN to be
correct.

Nove it to environment.h to simplify the common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11 16:43:41 -04:00
Simon Glass
cb2ba9db5f env: Drop the double underscores in search.h
There doesn't seem to be any good reason for using __ in the arguments in
this header file. A double underscore is usually reserved for compiler
features.

Drop these and remove the unnecessary 'extern' as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
3f0d680745 env: Drop the ACTION typedef
Avoid using a typedef here which is unnecessary. Add an 'env_' prefix to
both the enum and its members to make it clear that these are related to
the environment.

Add an ENV prefix to these two flags so that it is clear what they relate
to. Also move them to env.h since they are part of the public API. Use an
enum rather than a #define to tie them together.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
d3716dd64b env: Rename the redundancy flags
Add an ENV prefix to these two flags so that it is clear what they relate
to. Also move them to env.h since they are part of the public API. Use an
enum rather than a #define to tie them together.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
25e51e90fe env: Drop _ENTRY
This typedef does not need to be defined in the search.h header since it
is only used in one file (hashtable.c). Remove it from the header and
change it to a struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
dd2408cac1 env: Drop the ENTRY typedef
U-Boot is not supposed to use typedef for structs anymore. Also this name
is the same as the ENTRY() macro used in assembler files, and 'entry'
itself is widely used in U-Boot (>8k matches).

Drop the typedef and rename the struct to env_entry to reduce confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
02cf933428 env: Move callback definitions to env.h
These definitions are effectively part of the 'public' API of the
environment implementation since they do not require access to any
internal variables. Move them to the env.h header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
db19701039 env: Move env_valid to env.h
This enum is somewhat widely used to determine if the environment is valid
or not. Move it to the common environment header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
be54ec1624 env: Rename environment to embedded_environment
The name 'environment' is widely used in U-Boot so is not a very useful
name of a variable. Rename it to better indicate its purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11 16:43:41 -04:00
Simon Glass
c62f62b0fc env: Move env_reloc() to env.h
Move env_reloc() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
b5f449e8e9 env: Move env_get_char() to env.h
Move env_get_char() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
0ac7d722ed env: Move get/set_default_env() to env.h
Move these functions to the new header file and rename set_default_env()
to env_set_default() so that it has a consistent env_ prefix.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
1f3db0c135 env: Drop env_crc_update()
This function is not defined or used in U-Boot. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
4e9ce8a65f env: Move env import/export functions to env.h
Move these functions to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
4be490ae33 env: Move env_load/save functions to env.h
Move these function to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
0b9d8a0556 env: Move set_default_vars to env.h
Move this function to the new header file and rename it so it has an env_
prefix.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
03ed91887f env: Move env_fix_drivers() to env.h
Move this function over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
36c8b143c0 env: net: Move eth_parse_enetaddr() to net.c/h
This function fits better with the network subsystem, so move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
b79cf1af0d env: Move eth_env_get/set_enetaddr() to env.h
Move these two functions over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
7b51b576d6 env: Move env_get() to env.h
Move env_get() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
9fb625ce05 env: Move env_set() to env.h
Move env_set() over to the new header file.

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
cdbff9fc40 env: Move env_get_hex() to env.h
Move env_get_hex() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
6bf6dbee01 env: Move env_get_yesno() to env.h
Move env_get_yesno() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
9eef56dbe3 env: Move env_get_ulong() to env.h
Move env_get_ulong() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
168068fb3d env: Move env_set_ulong() to env.h
Move env_set_ulong() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
c7694dd483 env: Move env_set_hex() to env.h
Move env_set_hex() over to the new header file along with env_set_addr()
which uses it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
b9ca02c2d5 env: Move envmatch() to env.h
Move envmatch() over to the new header file. Also rename it to env_match()
to better line up with other functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
3f989e7b0e env: Move env_relocate() to env.h
Move env_relocate() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
4bfd1f5d62 env: Move env_init() to env.h
Move env_init() over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
3a7d55716d env: Move env_get_f() to env.h
Move this function over to the new header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
f1f0ae6a9c env: Move get_env_id() to env.h
Move this function over to the new header file. Also rename it to have an
env_ prefix like the other functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-08-11 16:43:41 -04:00
Simon Glass
af95f2061a env: Create a new file for environment functions
At present we have environment.h but this file includes all the
environment-related header files as well as internals such as
default_environment.

It seems desirable to have a new header to hold the commonly used
environment functions, so that most files can avoid including all of this
unnecessary stuff.

Create a new env.h header and move one function over to it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11 16:43:41 -04:00
Simon Glass
9fe657daa7 common: Remove video_setmem()
This function is no-longer defined in U-Boot. Drop the declaration from
common.h

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
3c1ecde402 common: Move lcd_setmem() to lcd.h
This function relates to lcd.h and is about to become obsolete with the
driver-model conversion. Move it out of common.h

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-11 16:43:41 -04:00
Simon Glass
4575a77b7a common: Drop the dpram_... functions
These declarations are not used anymore, so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11 16:43:41 -04:00
Simon Glass
0c670fc148 common: Move gzip functions into a new gzip header
As part of the effort to remove things from common.h, create a new header
for the gzip functions. Move the function declarations to it and add
missing documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11 16:43:41 -04:00
Igor Opaniuk
0d6c7c60ea MAINTAINERS: Add entries for Android A/B and AVB
1. Add myself as Android A/B and AVB maintainer
2. Add Sam Protsenko as Designated reviewer for A/B

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
379e574f7a MAINTAINERS: Add entry for HI3660 SoC
Add MAINTAINERS entry for HI3660 SoC by adding the arch includes.
While doing so, adding myself as the co-maintainer for HISILICON
SoCs since I'm planning to maintain HI3660 SoC separately and considering
doing improvements to the existing HiSilicon SoC architecture.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
122537e1f3 mmc: Add support for HI3660 SoC reusing hi6220_dw_mmc driver
This commit adds MMC driver support for HI3660 SoC reusing hi6220_dw_mmc
driver. Since HI3660 operates at different clock rate and uses fifo
mode now, let's introduce the platform data and utilize it for different
SoCs supported by this driver.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
c62c7ef779 board: hisilicon: Add support for Hikey960 board
This commit adds board support for Hikey960 board from Hisilicon. This
board is one of the Consumer Edition boards of the 96Boards family
powered by Kirin960 SoC.

More information about this board can be found in 96Boards website:
https://www.96boards.org/product/hikey960/

The initial supported/tested devices include:
 - Debug serial
 - SD

With these support, it's good enough for loading Linux Kernel from SD.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
881b6324f0 arm: dts: Add devicetree for Hikey960 board
This commit adds devicetree for Hikey960 board. Most of the contents are
copied from Linux kernel with some modifications for u-boot. To be
more precise, SD card's speed related properties are removed due to a
bug in u-boot clock implementation. Hence forcing the SD controller to
work in standard speed.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Manivannan Sadhasivam
af8a735ed0 arm: dts: Import HI3660 devicetree from Linux
This commit imports HI3660 SoC devicetree from Linux

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-11 16:43:41 -04:00
Simon Goldschmidt
d8c0332031 spl: implement stack usage check
This implements a stack usage check in SPL.

Many boards start up SPL to run code + data from one common, rather small
SRAM. To implement a sophisticated SPL binary size limit on such boards,
the stack size (as well as malloc size and global data size) must be
subtracted from this SRAM size.

However, to do that properly, the stack size first needs to be known.

This patch adds a new Kconfig option:
- SPL_SYS_REPORT_STACK_F_USAGE: memset(0xaa) the whole area of the stack
  very early and check stack usage based on this constant later before the
  stack is switched to DRAM

Initializing the stack and checking it is implemented in weak functions,
in case a board does not use the stack as saved in gd->start_addr_sp.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-11 16:43:41 -04:00
Ye Li
af325e9597 serial_lpuart: Fix config check issue when using clk driver in SPL
Should use CONFIG_IS_ENABLED not IS_ENABLED for CLK driver, so it will
check the CONFIG_SPL_CLK when building SPL

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-11 16:43:41 -04:00
Ley Foon Tan
d44f793207 pci: intel: Fix configuration type based on secondary number
This fix issue when access config from PCIe switch.

The PCIe controller need to send Type 0 config TLP if the targeting bus
matches with the secondary bus number, which is when the TLP is targeting
the immediate device on the link.

The PCIe controller send Type 1 config TLP if the targeting bus is
larger than the secondary bus, which is when the TLP is targeting the
device not immediate on the link.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11 16:43:41 -04:00
Ley Foon Tan
bf9b9813ad pci: intel: Fix error when enumerating multi-function PCIe device
Hardware return completion status non-zero when read from non exist
function in multi-function PCIe device. Return error will cause PCIe
enumeration fail.

Change it to return 0 and return value 0xffffffff when error.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11 16:43:41 -04:00
Ley Foon Tan
d0e52c6f29 pci: intel: Increase TLP polling counter
Some PCIe devices require longer time to response.
Increase polling counter to 20000 (~100ms).

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-08-11 16:43:41 -04:00
Anatolij Gustschin
490e6d6859 board: siemens: extend factoryset reading for giedi and deneb boards
giedi and deneb are i.MX8X based and have additional data with
WLAN MAC in factoryset container. Enable building for these
boards and adapt factoryset functions to set WLAN MAC and dtb
name in environment.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-08-11 16:42:03 -04:00
Anatolij Gustschin
4987bc2a1a board: siemens: adapt factoryset reading for DM_I2C enabled boards
For new boards we always enable DM_I2C. Extend factoryset functions
to support EEPROM reading on these boards.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2019-08-11 16:42:03 -04:00
Tom Rini
feb5a02f86 Merge branch 'master' of git://git.denx.de/u-boot-sh
- R8A77980 V3H support
2019-08-10 17:57:58 -04:00
Tom Rini
31d136926b Merge branch 'master' of git://git.denx.de/u-boot-usb
- DaVinci USB updates
- Various OHCI fixes
- Gadget fixes
2019-08-10 12:21:27 -04:00
Tom Rini
9fd8b2c8c7 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Enable SD slot on Intel Edison
- Populate CSRT ACPI table for shared DMA controller on Intel Tangier
- Convert Intel ICH-SPI driver to use new spi-mem ops
- Enable config_distro_bootcmd for QEMU x86
- Support U-Boot as a payload for Intel Slim Bootloader
- Avoid writing temporary asl files into the source tree which fixes the
  parallel build issue occasionally seen
2019-08-09 23:27:15 -04:00
Marek Vasut
3ebb91914f ARM: renesas: Add R8A77980 V3H Condor board code
Add board code for the R8A77980 V3H Condor board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
57ede1a3d4 ARM: renesas: Add R8A77980 V3H platform code
Add a few bits of platform code to support R8A77980 V3H SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
a811e19b91 ARM: dts: renesas: Add R8A77980 V3H DTs and headers
Import R8A77980 V3H DTs and headers from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
ca6da6dd93 clk: renesas: Add R8A77980 V3H clock tables
Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
f497ec368e pinctrl: renesas: Add R8A77980 V3H PFC tables
Import R8A77980 V3H PFC tables from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
7234a28664 net: sh_eth: Fix 64bit build warnings
Fix various type warnings when building this driver for 64bit machine.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
46c33166d1 net: sh_eth: Add R8A77980 V3H gether support
The R8A77980 V3H gether needs a few minor adjustments to the sh_eth
driver, add them to support ethernet on R8A77980.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Tom Rini
188f010905 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2019-08-09 13:21:53 -04:00
Igor Opaniuk
bd20266d19 apalis-tk1: configs: remove legacy usbboot command
Remove obsolete legacy usbboot wrapper, as distroboot can handle
booting from USB drivers.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Marcel Ziswiler
4c63a601b9 apalis-tk1: support v1.2 hardware revision
Support the V1.2 hardware revision with the following pin muxing
changes:

Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4
are now used as DDC pins.

Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are
now used as USB power enable signals.

Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power
enable signals are now used as GPIO3 and GPIO4.

Additionally a new device tree file tegra124-apalis-v1.2-eval.dtb is
loaded on V1.2 and later modules and resp. USB power enable signals
activated.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Dominik Sliwa
5a20adf446 apalis-tk1: remove non-essential power rails on boot
When mainline kernels reboot TK1 they use SW_RESET,
that reset mode does not reset PMIC. Some rails
need to be off for RAM Re-repair to work correctly.

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Marcel Ziswiler
d415eab4f0 apalis-tk1: remove default vesa vga mode from vidargs
Remove video=tegrafb0:640x480-16@60 aka VESA VGA mode from vidargs in
order for the panel specification in the device tree to be used. This
causes the default to be the 10.1" LVDS display which will be available
in the Toradex webshop shortly.

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Dominik Sliwa
fbcb925654 apalis-tk1/t30: colibri_t30: display reset reason
Display proper reset reason after the SoC info.

Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Igor Opaniuk
8c57395d49 apalis-tk1: switch to zImage
Switch to the generic compressed Kernel image type (zImage) instead of
the U-Boot specific uImage format.

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:35 -07:00
Igor Opaniuk
f7c668a4e8 apalis-tk1: add pcie_aspm=off to defargs
Disabling ASPM fixes incompatibilities with some PCIe cards

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Igor Opaniuk
11d96e122a apalis-tk1: enable user debug by default
Let the kernel print some debug messages when a user program
crashes due to an exception.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Igor Opaniuk
8fd734c49c apalis-tk1: provide proper USB vendor id
Use unified values for USB Product/Vendor numbers
when the config block is missing

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Igor Opaniuk
538ab6c0a1 apalis-tk1: set apalis gpio 8 aka fan_en
Make sure the Apalis GPIO 8 aka FAN_EN is on when using Apalis TK1
modules.

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Marcel Ziswiler
5b5de78b4a apalis-tk1: do not explicitly release reset_moci#
By keeping RESET_MOCI_CTRL low we avoid explicitly releasing
RESET_MOCI#.

Please note that module hardware versions up to V1.1A will already
release RESET_MOCI# in hardware coming out of reset.

Please further note that with this change the USB hub on the Apalis
Evaluation board is kept in reset in U-Boot and therefore none of its
ports are operational in U-Boot.

Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Igor Opaniuk
f028c9f437 colibri/apalis tegra: drop DFU support
We never really added a sensible DFU configuration for platforms
based on eMMC. Most of the things one might want to do can also be done
with UMS or fastboot, so drop the DFU configuration.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Trent Piepho
b78d97ea49 mmc: Move tegra loopback disable option to be under tegra
This is a configuration option specific to the tegra controller.

Doing it this way makes it show up directly under the tegra controller
option, indented one level, as "Disable external clock loopback".

The way it is now, it shows up at the end of the controller list, not
indented, as if it's some kind of generic MMC configuration option.

Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Simon Glass
b4bf71456d sound: Add codec enable to the sound bindings
For U-Boot we allow a GPIO to be specified to enable the codec. Add this
to the relevant binding files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Simon Glass
9944d753cb sound: tegra: Add the binding file for tegra-audio
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:34 -07:00
Simon Glass
e070311ce8 sound: snow: Add the binding file for snow
This file was missed when adding the sound driver to U-Boot. Bring it in
from Linux 5.0.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-08-09 10:01:33 -07:00
Park, Aiden
dbaec46767 x86: Skip setting up MTRRs in slimbootloader
The setting up MTRRs have already been done in previous
Slim Bootloader stages.

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
d8f6db4768 board: intel: Add new slimbootloader board
Add slimbootloader board to run U-boot as a Slim Bootloader payload
- Add new board/intel/slimbootloader directory with minimum codes
- Add slimbootloader configuration files
- Add doc/board/intel/slimbootloader.rst

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add slimbootloader board MAINTAINERS file]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
19cad267d9 x86: slimbootloader: Add a slimbootloader device tree
Add a new device tree which has very minimum nodes
- x86 reset
- x86 tsc_timer
- x86 pci
- Slim Bootloader serial

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
14360bf059 x86: slimbootloader: Set TSC information for tsc_timer
Slim Bootloader already calibrated TSC and provides it to U-Boot.
Therefore, U-Boot does not have to re-calibrate TSC.
Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass
TSC calibration and use the provided TSC frequency.
- Get TSC frequency from performance info hob
- Set tsc_base and clock_rate for tsc_timer driver

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
2869c3b3de x86: slimbootloader: Add serial driver
Slim Bootloader provides serial port info thru its HOB list pointer.
All these HOBs are eligible for Slim Bootloader based board only.
- Get serial port information from the serial port info HOB
- Leverage ns16550 driver with slimbootloader specific platform data

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
1fb17ea548 x86: slimbootloader: Add memory configuration
Slim Bootloader provides memory map info thru its HOB list pointer.
Configure memory size and relocation memory from the HOB data, and
provide e820 entries as well.
- Get memory size from the memory map info HOB
- Set available top memory lower than 4GB for U-Boot relocation
- Provide e820 entries from the memory map info HOB

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
7165fd584f x86: Add a common HOB library
FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER)
consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer.
Add a common HOB library in lib/hob.c and include/asm/hob.h.

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
5b931a5080 x86: lib: fsp: Use EFI_GUID and efi_guid_t
Use existing EFI_GUID and efi_guid_t instead of struct efi_guid.
This is pre-work before making a common HOB library.
- Change 'struct efi_guid' to efi_guit_t
- Remove 'struct efi_guid'
- Define GUIDs with EFI_GUID() macro
- Use guidcmp() instead of compare_guid()
- Remove compare_guid()

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Tested on MinnowMax
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Park, Aiden
544293f878 x86: Add new slimbootloader CPU type
This slimbootloader CPU type is to enable U-Boot as a payload which
runs on top of Slim Bootloader (https://github.com/slimbootloader).
The Slim Bootloader is designed with multi-stage architecture for
the execution from reset vector to OS booting, and supports QEMU,
Apollolake, Whiskeylake and Coffeelake platforms consuming Intel
FSP (https://github.com/IntelFsp) for silicon initialization
including CAR and memory initialization.
The Slim Bootloader generates new HOB (Hand Off Block) which are
serial port info, memory map info, performance data info and so on,
and passes it to a Payload. U-Boot as a payload will use these HOB
information for basic initialization such as serial console.

As an initial commit,
- Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type
- Add new arch/x86/cpu/slimbootloader directory with minimum codes
- Get hob_list pointer from Slim Bootloader

Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Bernhard Messerklinger
0709ddb68f x86: ich-spi: Convert driver to spi-mem ops
With the introduction of the new spi-mem model operations changed
slightly. The new spi-mem operations make things a bit easier to
handle for ich-spi flash interface. This patch converts the ich-spi
driver by using spi-mem operations.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Tested on Intel CrownBay and MinnowMax
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[bmeng: fix compiler warnings when building the driver for 64-bit]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Heinrich Schuchardt
fd95e10178 bios_emulator: remove stray break
Remove a stray break which suppresses some debug messages.

Indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Simon Glass
c1865bbd16 x86: Avoid writing temporary asl files into the source tree
At present the iasl tool (Intel ACPI (Advanced Configuration and Power
Interface) Source Language Compiler) is called in such a way that it uses
the source directory for its temporary files.

This means we end up with these files when building x86 boards:

   board/dfi/dfi-bt700/dsdt.aml
   board/dfi/dfi-bt700/dsdt.asl.tmp

Update the code to put temporary files in the target directory instead.

The iasl tool is quite confusing since it generates files with different
extensions and does not allow these to be individually specified. Add some
documentation to help with this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove dsdt.hex from 'make clean' rules and correct U-Boot spelling]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
5e99fde34a x86: tangier: Populate CSRT for shared DMA controller
Intel Tangier has a shared DMA controller that, according to Microsoft spec,
has to be presented in CSRT table.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
e3be52ceac x86: acpi: Enable ACPI companion for Intel iDMA 32-bit
ACPI has a capability to specify DMA parameters for DMA channel consumers.
To enable this for Intel Edison, describe GP DMA device in ACPI table
in order to get an ACPI handle to it in OS.

This works in conjunction with CSRT, which must be in align with DSDT.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
ddd2a4244c x86: acpi: Introduce a stub to generate CSRT
Here is a stub function that generates an empty CSRT. If the target platform
provides acpi_fill_csrt() function, it will be used to populate the table.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
eef3007945 x86: acpi: Add CSRT description
Add CSRT [1] description as it provided in Linux kernel.

[1]: http://www.uefi.org/sites/default/files/resources/CSRT%20v2.pdf

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Bin Meng
68d70a1cf6 x86: qemu: Fix non-working ramboot and nfsboot environment variables
With qemu-x86 starting to use config_distro_bootcmd, the pre-defined
ramboot and nfsboot commands do not work any more. This is caused by
undefined environment variable 'ramdiskaddr' that was previously set
in CONFIG_EXTRA_ENV_SETTINGS but later CONFIG_EXTRA_ENV_SETTINGS was
redefined for distro boot.

Update the x86 generic CONFIG_EXTRA_ENV_SETTINGS to consider distro
boot, and remove the one in qemu-x86.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Joshua Watt
00f237e226 qemu-x86: Use config_distro_bootcmd
Converts qemu x86 machines to boot using distro_config. The intent is to
allow u-boot in qemu to be maximally compatible with many boot methods
without having to change the config. Previously, u-boot would only boot
in a very limited set of circumstances where there was a /boot/vmlinuz
on scsi 0:3 with no ramdisk.

Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: convert doc updates to reST]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Andy Shevchenko
42ef707922 x86: edison: Enable SD slot
Enable SD slot on Intel Edison platform.

By default firmware doesn't put device on active state. Thus,
we have to do this explicitly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-08-09 22:24:02 +08:00
Tom Rini
163bc1e4da Merge tag 'mmc-8-9' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- mmc test fix
- sdhci driver fix
2019-08-09 07:29:54 -04:00
Tom Rini
21bc1935b1 Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add rk3399 boards Khadas Edge/-V/-Captain
- Add fully souce code support for rk3328 including TPL/DRAM init
- Enable boot from eMMC for rk3399 rock960/ficus boards
- turn on the IO supply for dw_mmc
2019-08-09 07:29:20 -04:00
Peng Fan
d569b4b0a4 mmc: tangier_sdhci: fix uninitialized pointer deref on probe
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-09 13:45:25 +08:00
Peng Fan
d703104507 mmc: sdhci-cadence: fix uninitialized pointer deref on probe
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-08-09 13:45:25 +08:00
Peng Fan
6f16cbe55b mmc: s5p: fix uninitialized pointer deref on probe
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-09 13:45:25 +08:00
Peng Fan
a5abe152b2 mmc: pci: fix uninitialized pointer deref on probe
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-09 13:45:25 +08:00
Peng Fan
6904e1b250 mmc: msm_sdhci: fix uninitialized pointer deref on probe
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-09 13:45:25 +08:00
Peng Fan
425d83346d mmc: bcm: fix uninitialized pointer deref on probe
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Matthias Brugger <mbrugger@suse.com>
Cc: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-09 13:45:25 +08:00
Peng Fan
7835e87322 mmc: atmel_sdhci: fix uninitialized pointer deref on probe
Commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-08-09 13:45:25 +08:00
Michal Simek
a09c1f7e1c test/py: Fix MMC/SD block write test dependency
Test is using random command which has own Kconfig symbol CMD_RANDOM which
already depends on CMD_MEMORY. That's why replace cmd_memory by cmd_random.

Fixes: 09da18deab ("test/py: add MMC/SD block write test")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-08-09 13:45:25 +08:00
Matwey V. Kornilov
3148a3c2d3 mmc: zynq_sdhci: fix uninitialized pointer deref on probe
Since commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field. Move the mmc field initialization before sdhci_setup_cfg()
call to avoid crash on mmc pointer dereference.

[this patch is based on commit 41a9fab8da ("mmc: mv_sdhci: fix
uninitialized pointer deref on probe") by Baruch Siach]

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu102/zc706)
2019-08-09 13:45:25 +08:00
Faiz Abbas
68b3e8b398 mmc: Select SPL_HS200_SUPPORT if SPL_HS400_SUPPORT is selected
Select SPL_HS200_SUPPORT if SPL_HS400_SUPPORT is selected as is being
done for the U-boot case.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-08-09 13:45:25 +08:00
Tom Rini
fef408679b Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Remove unused bcm2835 watchdog driver (still non-DM)
- Cosmetic fixup of mtk_wdt.c
2019-08-08 09:19:08 -04:00
Sam Protsenko
29a81142be fastboot: Remove "bootloader-version" variable
As per [1], there is no such fastboot variable as "bootloader-version".
Only "version-bootloader" is supported. Let's reflect this and not
confuse users further.

[1] https://android.googlesource.com/platform/system/core/+/refs/tags/android-q-preview-4/fastboot/README.md

Fixes: 3aab70afc5 ("usb/gadget: add the fastboot gadget")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-08-08 11:35:02 +02:00
Sam Protsenko
139db354b1 fastboot: getvar: Add "is-userspace" variable
As per documentation [1], Android-Q requires for bootloader to provide
"is-userspace" variable. "no" value should be always returned. This
patch implements this fastboot variable.

[1] https://android.googlesource.com/platform/system/core/+/refs/tags/android-q-preview-4/fastboot/README.md

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-08-08 11:35:02 +02:00
Ralph Siemsen
fe876984a4 usb: gadget: f_dfu.c: fix memory leak
dfu_prepare_function() allocates N+1 descriptor header structures,
the last one being the "DFU Functional Descriptor".

dfu_unbind() handles de-allocation, but fails to free the final
one (eg. "DFU Functional Descriptor"), leading to memory leak.

Fixed by incrementing counter, as in dfu_prepare_function().

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
2019-08-08 11:35:02 +02:00
Marek Szyprowski
ed3a37a248 thor: fix crash after usb initialization failure
Registration of USB download gadget might fail for various reasons, so
add a check for g_dnl_register() funtion return value. Without this fix,
thor_init() will try to access the registered gadget structures resulting
in NULL pointer dereference issue.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2019-08-08 11:35:02 +02:00
Sam Protsenko
160102d112 fastboot: Remove "slot-suffixes" variable
"slot-suffixes" variable was dropped in fastboot tool (in [1]). Let's
track AOSP/master and drop this variable in U-Boot as well.

[1] 42b18a518b

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
[lukma: Remove getvar_slot_suffixes() declaration]
Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-08-08 11:35:02 +02:00
Heiko Schocher
991e66017c usb, ohci, pci: add DM support for PCI-based OHCI USB controller
add new DM based PCI driver ohci-pci for PCI-based
OHCI USB support.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-08-08 11:35:02 +02:00
Heiko Schocher
f9c7fecbeb usb, ohci: add warning if none on pci found
Signed-off-by: Heiko Schocher <hs@denx.de>
2019-08-08 11:35:02 +02:00
Heiko Schocher
dc4e48d845 usb, ohci-hcd: set OHCI_USE_NPS if DM_PCI
set OHCI_USE_NPS if DM_PCI is enabled.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-08-08 11:35:02 +02:00
Heiko Schocher
a5a7486e62 usb, ohci: fix ohci swap register access
commit 57faca19a8 ("drivers: USB: OHCI: allow compilation for 64-bit targets")
broke ohci support for the mpc85xx based socrates board,
as it removed volatile keyword from ohci_readl/writel.

Fix this so usb works again on socrates board.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-08-08 11:35:02 +02:00
Heiko Schocher
b005d7d5f9 usb, ohci-hdc: fix warning 'ohci_pci_ids' defined but not used
var ohci_pci_ids is only used if DM_USB is not enabled.
So define this varaible only if
!CONFIG_IS_ENABLED(DM_USB)

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-08-08 11:35:02 +02:00
Adam Ford
2ed45fd6ac ARM: da850-evm: Enable the USB PHY and MUSB Driver
This patch will enable the MUSB driver to support mass storage
devices connected to the OTG port in host mode.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-08 11:35:02 +02:00
Adam Ford
5608331d81 usb: musb-new: Add support for da8xx-musb
With the recently added phy driver, this patch will enable the
musb driver on the da8xx to operate in host mode.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-08 11:35:02 +02:00
Adam Ford
fc58263d2e phy: Add support for phy-da8xx-usb
In preparation for supporting the musb driver, this patch
adds support for the usb phy associated with the musb driver.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-08 11:35:02 +02:00
Sam Protsenko
2e8fef747b test/py: avb: Move AVB test to android dir
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-08-07 23:15:13 -04:00
Tom Rini
db857dcbbf Merge branch '2019-08-07-master-imports'
- Misc Android / AVB bugfixes (including updating the header from
  Android).
- MediaTek updates
- Other assorted bugfixes.
2019-08-07 23:13:35 -04:00
Alex Deymo
0b6febfdb3 Update include/android_image.h from AOSP
This takes the latest changes from AOSP from the file
include/bootimg/bootimg.h from the repository:
https://android.googlesource.com/platform/system/tools/mkbootimg
and update the U-Boot version with the latest changes.

This file keeps the changes from AOSP to a minimum:
 * Comments were converted from C++ to C style.
 * Code inside __cplusplus #ifdef blocks were removed.
 * C++11 struct extensions replaced with a single struct.

Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-08-07 15:31:06 -04:00
Sam Protsenko
24434adbd1 common: image-android-dt: Fix logic in print fdt info routine
Do not attempt to print fdt info if root node wasn't found.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-08-07 15:31:05 -04:00
Julius Werner
bddd985734 fit: Do not automatically decompress ramdisk images
The Linux ramdisk should always be decompressed by the kernel itself,
not by U-Boot. Therefore, the 'compression' node in the FIT image should
always be set to "none" for ramdisk images, since the only point of
using that node is if you want U-Boot to do the decompression itself.

Yet some systems populate the node to the compression algorithm used by
the kernel instead. This used to be ignored, but now that we support
decompression of all image types it becomes a problem. Since ramdisks
should never be decompressed by U-Boot anyway, this patch adds a special
exception for them to avoid these issues. Still, setting the
'compression' node like that is wrong in the first place, so we still
want to print out a warning so that third-party distributions doing this
can notice and fix it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-08-07 15:31:05 -04:00
Patrick Delaunay
13551b9114 console: execute flush on uart when silent is removed
Avoid to flush buffer when silent console is activated as the
console can be reactivate later, after relocation, when the env will
be updated with the saved one.

Solve issue (missing beginning of U-Boot trace) when:
- CONFIG_SILENT_CONSOLE is activated
- silent=1 is defined in default environment (CONFIG_EXTRA_ENV_SETTINGS)
- silent is removed in saved environment with:
      > env delete silent; env save

Only functional when PRE_CONSOLE_BUFFER is activated.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-08-07 15:31:05 -04:00
Patrick Delaunay
bf46be7216 console: update silent tag after env load
Update the "silent" property with the variable "silent" get from
saved environment, it solves the issue when:
- CONFIG_SILENT_CONSOLE and CONFIG_SYS_CONSOLE_IS_IN_ENV are activated
- silent is not defined in default environment
- silent is requested in saved environment with:
  > env set silent 1; env save

On next reboot the console is not disabled as expected after relocation
and the environment load from flash (the callback is not called when
the INSERT is requested in the created hash table)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-08-07 15:31:04 -04:00
Sam Protsenko
97f3c09706 cmd: avb: Fix compiler warnings
When building U-Boot with AVB enabled, compiler shows next warnings:

    cmd/avb.c: In function 'do_avb_read_pvalue':
    cmd/avb.c:371:18: warning: format '%ld' expects argument of type
                      'long int', but argument 2 has type 'size_t'
                      {aka 'unsigned int'} [-Wformat=]
       printf("Read %ld bytes, value = %s\n", bytes_read,
                    ~~^                       ~~~~~~~~~~
                    %d

    cmd/avb.c: In function 'do_avb_write_pvalue':
    cmd/avb.c:404:19: warning: format '%ld' expects argument of type
                      'long int', but argument 2 has type '__kernel_size_t'
                      {aka 'unsigned int'} [-Wformat=]
       printf("Wrote %ld bytes\n", strlen(value) + 1);
                     ~~^           ~~~~~~~~~~~~~~~~~
                     %d

Fix those by using "%zu" specified.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2019-08-07 15:31:04 -04:00
Sam Protsenko
f254bd02a0 avb: Fix build when CONFIG_OPTEE_TA_AVB is disabled
When having only these AVB related configs enabled:

    CONFIG_AVB_VERIFY=y
    CONFIG_CMD_AVB=y
    CONFIG_LIBAVB=y

build fails with next errors:

    common/avb_verify.c: In function 'read_persistent_value':
    common/avb_verify.c:867:6: warning: implicit declaration of function
                                        'get_open_session'
    common/avb_verify.c:870:45: error: 'struct AvbOpsData' has no member
                                        named 'tee'
    common/avb_verify.c:894:7: warning: implicit declaration of function
                                        'invoke_func'
    common/avb_verify.c: In function 'write_persistent_value':
    common/avb_verify.c:931:45: error: 'struct AvbOpsData' has no member
                                       named 'tee'

Guard read_persistent_value() and write_persistent_value() functions
by checking if CONFIG_OPTEE_TA_AVB is enabled (as those are only used in
that case) to fix the build with mentioned configuration.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Igor Opaniuk <igor.opaniuk@gmail.com>
2019-08-07 15:31:04 -04:00
Ramon Fried
6948f1023f pci_ep: Fix Coverity warning
Fix the following Coverity warning:
CID 244086:  Incorrect expression  (BAD_COMPARE)
Comparing pointer "ep_bar" against NULL using anything besides == or
is likely to be incorrect.

Fixes: 914026d258 ("drivers: pci_ep: Introduce UCLASS_PCI_EP uclass")

Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
2019-08-07 15:31:04 -04:00
Ryder Lee
2d88b5a38e clk: MediaTek: add hifsys entry for MT7623 SoC.
This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.

The control block is shared with ethsys and accordingly rename the
related defines.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
2019-08-07 15:31:03 -04:00
Ryder Lee
4f3ee271eb ARM: dts: add hifsys reset for MediaTek SoCs
This adds missing hifsys reset parts in header files.

Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
2019-08-07 15:31:03 -04:00
Ryder Lee
8702e614d9 MAINTAINERS: MediaTek: add MediaTek team in the entry
Add MediaTek team as designated reviewer.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
2019-08-07 15:31:03 -04:00
Heiko Schocher
ecaae801d6 autoboot: fix bug using with CAAM and AUTOBOOT_ENCRYPTION
if  CONFIG_AUTOBOOT_KEYED, CONFIG_AUTOBOOT_ENCRYPTION and
CONFIG_AUTOBOOT_STOP_STR_SHA256 are enabled in conjunction
with CONFIG_SHA_HW_ACCEL and CONFIG_FSL_CAAM, we get the
Error when pressing a key while waiting for bootdelay:

Error: Address arguments are not aligned
CAAM was not setup properly or it is faulty

Reason is, that used variables are not cache aligned,
so malloc this variables cache aligned.

Probably this is also a bugfix for other hw accelerators
than CAAM.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-08-07 15:31:02 -04:00
Heinrich Schuchardt
b236f8c086 log: document the assign() macro
Provide a concise description of the assert() macro. Point out that the
tested expression is always executed, irrespective of the value of _DEBUG.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-08-07 15:31:02 -04:00
Weijie Gao
102b0b1119 arm: dts: change MT7629 to use spi-mem rather than qspi
The original mtk_qspi driver has been removed. We change MT7629 to use
newly added mtk-spimem driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-08-07 12:44:12 -04:00
Matwey V. Kornilov
6a452e5bd3 doc: rockchip: Adapt Pine64 Rock64 board instructions
Now we have our own TPL implementation. Remove obsolete notes.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:18:35 +08:00
Matwey V. Kornilov
ff3dd0a474 configs: rk3328: enable TPL for rock64-rk3328_defconfig
Until now, binary TPL by Rockchip has been required for booting
procedure. Starting from this commit we may use only u-boot to boot
the device.

Note, that using binary TPL instead of U-boot TPL is still working.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:18:31 +08:00
Kever Yang
8edc29bd88 rockchip: evb-rk3328: enable defconfig options for TPL/SPL
Enable driver options for TPL/SPL in evb-rk3328_defconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit df4f40acb4 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:18:27 +08:00
Kever Yang
3f47db0275 rockchip: Kconfig: enable TPL support for rk3328
Enable TPL support and some related option in Kconfig.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 430b01462b with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:16:52 +08:00
Kever Yang
ec552bf036 rockchip: dts: rk3328: update dmc node for driver
Update dmc node for full feature driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 1e14956365 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:53 +08:00
Kever Yang
85a38742e0 rockchip: ram: add full feature rk3328 DRAM driver
This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from commit 9fb0777ec3 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:45 +08:00
Matwey V. Kornilov
86e999f1a5 rockchip: dts: rk3328: Add rk3328-evb-u-boot.dtsi
Split u-boot specific dts configuration to separate
rk3328-evb-u-boot.dtsi

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:30 +08:00
Manivannan Sadhasivam
b06def3572 arm: dts: ficus: Enable booting from eMMC when using SPL
This commits enables booting from eMMC when using SPL on 96Boards
Ficus board by adding SDHCI to boot order. Since the SDHCI driver
already has the reloc flag, this works straightaway. While we are at it,
let's also include the common u-boot dtsi for rk3399.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:13 +08:00
Manivannan Sadhasivam
0b5130fa3e arm: dts: rock960: Enable booting from eMMC when using SPL
This commits enables booting from eMMC when using SPL on 96Boards
Rock960 board by adding SDHCI to boot order. Since the SDHCI driver
already has the reloc flag, this works straightaway. While we are at it,
let's also include the common u-boot dtsi for rk3399.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:14:04 +08:00
Nick Xie
a5f1249bd3 arm64: dts: rockchip: Add support for Khadas Edge-Captain
Add devicetree support for Khadas Edge-Captain.
Khadas Captain is the carrier board for Khadas Edge.

Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- SD card slot
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- Full 4 Lane M.2 Socket
- 16MB SPI Flash
- IR
- Programmable MCU

Commit details of rk3399-khadas-edge-*.dts sync from Linux 5.3-rc2:
"arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards"
(sha1: c2aacceedc86af87428d998e23a1aca24fd8aa2e)

Signed-off-by: Nick Xie <nick@khadas.com>
Tested-by: Chris Webb <chris@arachsys.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:12:23 +08:00
Nick Xie
6ce9ba02b1 arm64: dts: rockchip: Add support for Khadas Edge-V
Add devicetree support for Khadas Edge-V.
Khadas Edge-V is a Khadas VIM form factor Rockchip RK3399 board.

Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- SD card slot
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- Full 4 Lane M.2 Socket
- 16MB SPI Flash
- IR
- Programmable MCU

Commit details of rk3399-khadas-edge-*.dts sync from Linux 5.3-rc2:
"arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards"
(sha1: c2aacceedc86af87428d998e23a1aca24fd8aa2e)

Signed-off-by: Nick Xie <nick@khadas.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:56 +08:00
Nick Xie
a839828fa1 arm64: dts: rockchip: Add support for Khadas Edge
Add devicetree support for Khadas Edge.
Khadas Edge is an expandable Rockchip RK3399 board with goldfinger.

Specification
- Rockchip RK3399
- Dual-Channel 2GB/4GB LPDDR4
- Onboard 16GB/32GB/128GB eMMC
- RTL8211FD 1Gbps
- AP6356S/AP6398S WiFI/BT
- HDMI Out, DP
- USB 3.0, 2.0
- USB Type C power and data
- 16MB SPI Flash
- Programmable MCU

Commit details of rk3399-khadas-edge-*.dts sync from Linux 5.3-rc2:
"arm64: dts: rockchip: Add support for Khadas Edge/Edge-V/Captain boards"
(sha1: c2aacceedc86af87428d998e23a1aca24fd8aa2e)

Signed-off-by: Nick Xie <nick@khadas.com>
Tested-by: Chris Webb <chris@arachsys.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:29 +08:00
Matwey V. Kornilov
16593ccd07 rockchip: rk3328: enable DMA for MMCs at Rock64
DMA for MMCs can be enabled, since the previous patch fixes
the following issue in SPL:

    Trying to boot from MMC1
    spl: mmc init failed with error: -110
    SPL: failed to boot from all boot devices
    ### ERROR ### Please RESET the board ###

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:16 +08:00
Kever Yang
a9775a82a5 rockchip: rk3328: set DDR as non-secure in SPL
Set DDR as non-secure so that MMC DMA can access.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from bfe741ab9e and 73d952acc8 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-05 21:05:02 +08:00
Stefan Roese
c07f68dd66 watchdog: mtk_wdt: Cosmetic cleanup of latest changes
This patch cleans up some coding style related issues in the mtk_wtd
driver to make this driver comply again with the U-Boot coding style
standards.

The only minimal functional change is that the timeout parameter is now
passed in (u64) instead of (unsigned int) from mtk_wdt_start() to
mtk_wdt_set_timeout(), preserving the original value.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Shannon Barber <sbarber@dataspeedinc.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
2019-08-05 11:50:11 +02:00
Stefan Roese
c7adc0b5f9 watchdog: bcm2835_wdt: Remove unused BCM283x watchdog driver and its references
The BCM2835/2836 watchdog is not used in mainline U-Boot at all. This
patch removes the driver and its references (CONFIG_BCM2835_WDT)
completely.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Paolo Pisati <p.pisati@gmail.com>
2019-08-05 11:50:06 +02:00
Tom Rini
7127151d53 Merge tag 'efi-2019-10-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for v2019.10-rc2

With this pull request a workaround for GRUB on 32bit ARM is re-enabled
and made customizable. Without the patch booting on ARM 32bit with GRUB
prior to version 2.04 or with a cache which is not managed via CP15
fails.

Further work will be needed to achieve a UEFI compliant cache handling.
According to the UEFI spec all caches except those that cannot be
managed via CP15 should be enabled.

An implementation of the ConvertPointer() runtime service is provided.

efi_crt0 is always rebuild to avoid having to call 'make mrproper' when
switching architectures.
2019-08-04 19:39:54 -04:00
Tom Rini
898c40c0d6 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Port more CCF code to work with i.MX8 devices.
2019-08-02 13:29:46 -04:00
Tom Rini
7298d82d91 gitlab-ci: Add qemu-riscv64 testing
Mirror the qemu-riscv64 testing we do on Travis.  Update to a newer
Docker image that contains riscv64-softmmu for QEMU.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-02 11:32:37 -04:00
Tom Rini
1013233a08 gitlab-ci: Remove unused TOOLCHAIN environment variable
As part of copying the logic from Travis to GitLab I kept the TOOLCHAIN
variable.  However we don't use that now as the Docker container already
has all toolchains so we don't need to do any downloading.  Remove this
variable.

Signed-off-by: Tom Rini <trini@konsulko.com>
2019-08-02 11:31:42 -04:00
Heinrich Schuchardt
22c7b7d63b travis.yml: run Python tests on qemu-riscv64_defconfig
Run the Python tests on the RISC-V architecture too.

https://github.com/swarren/uboot-test-hooks has already been updated.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-08-02 11:29:38 -04:00
Tom Rini
db289a9d74 Merge branch '2019-08-02-autoboot-cleanup'
- Merge Simon Glass's series to cleanup the autoboot code
2019-08-02 11:19:23 -04:00
Simon Glass
5ec35ff3eb autoboot: Adjust the implementation in autoboot_command()
Avoid use of #ifdef and keep the common condion in a variable. This makes
the code easier to read.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
5fa3fd25ed autoboot: Move a few more options from #ifdef to if()
Adjust some of the code which can be trivially moved to use IS_ENABLED()
instead of #ifdef.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
14b9df1b48 autoboot: Add comments for menu_show()
Add comments for this function. Also remove the #ifdef around it so that
it can be called from 'if (IS_ENABLED(...))'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
cf9803a60b Convert CONFIG_AUTOBOOT_MENU_SHOW to Kconfig
This converts the following to Kconfig:
   CONFIG_AUTOBOOT_MENU_SHOW

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
e231306e48 autoboot: Rename CONFIG_MENU_SHOW to include AUTOBOOT
Rename this option to CONFIG_AUTOBOOT_MENU_SHOW this it relates to the
autoboot functionality.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
d915ad277a autoboot: Tidy up use of menukey
Move the variable to the top of the file and adjust the code which uses it
to use if() rather than #ifdef, to make it easier to read.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
daedaada38 snow: Define CONFIG_AUTOBOOT_MENUKEY
This option is not used by any boards. To avoid needing to remove it as
dead code, add it to 'snow'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
8fc31e23aa autoboot: Rename CONFIG_MENUKEY to CONFIG_AUTOBOOT_MENUKEY
Since this is part of the autoboot functionality, it makes sense to name
it with an AUTOBOOT prefix. No mainline boards use it so this should be
safe, and downstream boards will need to adjust.

Since this option is just an integer value, it really needs another option
to control whether the feature is enabled or not. Add a new
CONFIG_USE_AUTOBOOT_MENUKEY for that. This fits better with how things are
done with Kconfig, avoiding the need to use a specific value to disable
the feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
2452bb7636 autoboot: Drop unused CONFIG_MENUPROMPT
This is not defined by any board. We could use CONFIG_AUTOBOOT_PROMPT
instead perhaps, but this depends on CONFIG_AUTOBOOT_KEYED which is not
used for the single-key case.

So let's just remove CONFIG_MENUPROMPT.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
e79e4b250a autoboot: Drop #ifdef CONFIG_AUTOBOOT_KEYED
At present we have two functions named __autoboot() which do different
things. This is confusing. Fix it by using if() instead of #ifdef for
selecting the functions, and renaming them to meaningful names.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
42b4d14e34 autoboot: Use if() for CONFIG_SILENT_CONSOLE
Avoid an #ifdef in this function, to improve readability.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
88fa4beb63 autoboot: Improve docs for CONFIG_AUTOBOOT_ENCRYPTION
This option is not documented properly at present. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
e8c780560a autoboot: Drop #ifdef for CONFIG_AUTOBOOT_ENCRYPTION
Use if() instead for this option, renaming the two different
passwd_abort() functions to indicate their purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
0c4bd318f5 autoboot: Use CONFIG_AUTOBOOT_STOP_STR_SHA256 indirectly
This CONFIG option is only present if CONFIG_AUTOBOOT_ENCRYPTION is
enabled so it cannot be used in code without that #ifdef. But we want to
reduce the use of #ifdef in this file and in particular to avoid having
two different functions both named passwd_abort() but which do different
things.

In preparation for this, create an intermediate value which is set to an
empty string if there is no value for CONFIG_AUTOBOOT_STOP_STR_SHA256.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
37304aaf60 Convert CONFIG_USE_PREBOOT and CONFIG_PREBOOT to Kconfig
This converts the following to Kconfig:
   CONFIG_USE_PREBOOT
   CONFIG_PREBOOT

Both are together in one commit, since otherwise the former causes kconfig
to define the latter, which gives duplicate symbol errors.

Includes a manual fixup for CONFIG_PREBOOT in ids8313_defconfig since the
backslash lands in the wrong place. Similarly with socfpga_vining_fpga.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:19:14 -04:00
Simon Glass
b06da06dd4 Add CONFIG_USE_PREBOOT to boards that use CONFIG_PREBOOT
In order to use CONFIG_PREBOOT with Kconfig, CONFIG_USE_PREBOOT must be
defined for each board. To prepare for conversion to Kconfig, add this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:17:58 -04:00
Simon Glass
9f53146f39 Convert CONFIG_SHOW_BOOT_PROGRESS to Kconfig
This converts the following to Kconfig:
   CONFIG_SHOW_BOOT_PROGRESS

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:17:58 -04:00
Simon Glass
e9f6a37465 main: Use conditional run_preboot_environment_command()
The function name indicates that it does something, but its entire
operation is actually condition on a CONFIG. Move the condition outside
the function so this is clearer, and use if() instead of #ifdef, like the
reset of the file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-08-02 11:17:58 -04:00
Tom Rini
bbaf56eda0 Merge tag 'u-boot-amlogic-20190731' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- sync Amlogic G12A DT with linux 5.3-rc1
- add support for 4GiB DRAM memory
- add support for Amlogic G12B based Odroid-N2
- small duplicate logic fix for gxbb clock driver
2019-07-31 16:06:24 -04:00
Tom Rini
08c41ca1ef Merge branch '2019-07-31-ti-imports'
- Various DaVinci fixes
- Migrate am335x_boneblack_vboot to use more DM drivers
- Keystone updates
2019-07-31 14:20:55 -04:00
Adam Ford
b9ad74d901 Revert "ARM: davinci: da850: Manual pinmux only when PINCTRL not available"
This reverts commit 877ab2423b.

The above patch was designed to shrink code by only pin-muxing items
needed for SPL in SPL and relying on driver model or SPL to mux other
items.  Unfortunately, da850evm_direct_nor doesn't use SPL so items
that were only muxed during SPL are not muxed causing the board
to no longer boot.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-31 14:20:47 -04:00
Heinrich Schuchardt
51443f57d8 nand: davinci: avoid out of bounds array access
The array bounds have to be checked before accessing the array element.

Identified by cppcheck.

Fixes: 67ac6ffaee ("mtd: nand: davinci: add opportunity to write keystone U-boot image")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-31 13:08:07 -04:00
Adam Ford
3380d1c131 ARM: da850-evm: Remove references to CONFIG_DA850_AM18X_EVM
With the removal of da850_am18xxevm, there is at least one
whitelisted CONFIG option that can be deleted.  This patch
removes CONFIG_DA850_AM18X_EVM since it's not required any more

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-31 13:08:07 -04:00
Adam Ford
2fd156b307 ARM: dts: da850-evm: Fix MDIO pinmux
In attempts to speed up SPL and reduce size, the MDIO pin muxing
was inadvertently affected.  Since the ethernet driver will setup
the pin muxing when ethernet is loaded, this patch will also
pinmux the MDIO pins at the same time.  Once an DM compatible
MDIO driver is available, this  can be removed.

Fixes: 877ab2423b ("ARM: davinci: da850: Manual pinmux only
when PINCTRL not available")

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-31 13:08:07 -04:00
Suniel Mahesh
575ce432b8 configs: am335x_boneblack_vboot_defconfig: Add DM for SPI and Flash devices
This patch adds SPI and SPI_FLASH DM support for verified boot on
TI AM335 chipsets. The following compile warning is removed:

===================== WARNING ======================
This board does not use CONFIG_DM_SPI_FLASH. Please update
the board to use CONFIG_SPI_FLASH before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

Built and tested on AM335x device (BeagleboneBlack).

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-07-31 13:08:07 -04:00
Suniel Mahesh
a9c5d4ba0d configs: am335x_boneblack_vboot_defconfig: Fix regression by enabling BLK and DM support, disable in SPL
This patch adds BLK and DM support for verified boot on TI AM335x
chipsets. The following compile warnings are removed:

===================== WARNING ======================
This board does not use CONFIG_DM_MMC. Please update
the board to use CONFIG_DM_MMC before the v2019.04 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================
===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

BLK and DM_MMC are enabled by default in SPL as well, which is
making the build to break with an overflow(spl image doesn't
fit into SRAM because of size constraints).

  LD      spl/drivers/built-in.o
  LD      spl/u-boot-spl
arm-linux-ld.bfd: u-boot-spl section .u_boot_list will not fit in region .sram
arm-linux-ld.bfd: region .sram overflowed by 116 bytes
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2

For the above reason BLK and DM_MMC is disabled in SPL.
Built and tested on AM335x device (BeagleboneBlack).

Signed-off-by: Suniel Mahesh <sunil.m@techveda.org>
2019-07-31 13:08:07 -04:00
Suman Anna
5b56a4c162 configs: j721e_evm_a72: Disable K3_SYSTEM_CONTROLLER
The K3 System Controller driver is used for loading and starting
the System Firmware, and is used only on R5 SPL. It need not be
enabled and built for the A72 U-Boot and SPL, so disable it from
the j721e_evm_a72 defconfig.

While at this, also remove the unneeded CONFIG_SPL_REMOTEPROC and
CONFIG_CMD_REMOTEPROC as no remoteprocs are now loaded from A72 SPL.

Signed-off-by: Suman Anna <s-anna@ti.com>
2019-07-31 13:08:07 -04:00
Suman Anna
8162e8ac70 configs: am65x_evm_a53: Disable K3_SYSTEM_CONTROLLER
The K3 System Controller driver is used for loading and starting
the System Firmware, and is used only on R5 SPL. It need not be
enabled and built for the A53 U-Boot and SPL, so disable it from
both the GP and HS AM65x A53 defconfigs.

While at this, also remove the unneeded CONFIG_SPL_REMOTEPROC and
CONFIG_CMD_REMOTEPROC as no remoteprocs are now loaded from A53 SPL.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-31 13:08:07 -04:00
Suman Anna
dcddf0fd83 arm: dts: k3-am654-base-board: Fix cpsw_nuss power-domains property
The commit 355be915ed ("arm: dts: k3-am654: Update power-domains
property for each node") has updated the power-domain cells value
and updated power-domains property in various existing dts nodes but
missed updating the cpsw_nuss node. This results in the following
build warning, fix this.

arch/arm/dts/k3-am654-base-board.dtb: Warning (power_domains_property): /interconnect@100000/interconnect@28380000/cpsw_nuss@046000000:power-domains: property size (8) too small for cell size 2
arch/arm/dts/k3-am654-r5-base-board.dtb: Warning (power_domains_property): /interconnect@100000/interconnect@28380000/cpsw_nuss@046000000:power-domains: property size (8) too small for cell size 2

Fixes: 355be915ed ("arm: dts: k3-am654: Update power-domains property for each node")
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-31 13:08:07 -04:00
Adam Ford
3cdecb341e ARM: da850-evm: Replace CMD_SF with CMD_MTD
This patch enables MTD and CMD_MTD and it works with SPI NOR,
so the older CMD_SF can be removed.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-31 13:08:07 -04:00
Adam Ford
ef97842b43 ARM: da850evm: Split MTDPARTS into SPL and u-boot
The MTDPARTS currently lists just u-boot.ais as 512k in size.
This works when loading the ais file via serial port, but if one
wanted to update just the u-boot portion, it's not really possible.
This patch splits the MTDPARTS into a 32k SPL partiion and a 480k
u-boot partition which allows u-boot.img to be burned to the u-boot
partition.  The remaining partitions are left with the same sizes
and offsets to not break backwards compatibility.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-07-31 13:08:07 -04:00
Sam Protsenko
914694d6a9 configs: am57xx_evm_defconfig: Enable 'dtimg' command
We are going to implement DTBO partition for BeagleBoard X15 further. To
support this, 'dtimg' command must be enabled.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-07-31 13:08:07 -04:00
Sam Protsenko
29e783d672 configs: am57xx_evm_defconfig: Enable 'bcb' command
It is essential to have an access to BCB area of 'misc' partition on
Android devices [1]. For BeagleBoard X15 the 'bcb' command will be
further used for reboot reason implementation and booting to recovery.
It can be also used for debugging reasons, like checking RescueParty
messages in BCB area.

[1] doc/android/bcb.txt

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-07-31 13:08:07 -04:00
Sam Protsenko
4347b0b0b2 omap: Correct the fastboot product var
"fastboot flashall" expects "fastboot getvar product" value to be one of
values provided in android-info.txt file (in AOSP), from "require
board=" list. Before this patch, "am57xx" is returned for all AM57xx
based boards, as it's set in $board env var from SYS_BOARD in
board/ti/am57xx/Kconfig file, which is used for default implementation
of "fastboot getvar product".

In order to fix that inconsistency, let's do next:
  1. In U-Boot: override fastboot.product, reusing the value from
     $board_name
  2. In AOSP: provide values for all AM57xx boards we can use to
     device/ti/beagle_x15/board-info.txt file

This way requirements check in "fastboot flashall" will work as
expected, verifying that user tries to flash images to the board which
those images were built for.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Andrew F. Davis <afd@ti.com>
2019-07-31 13:08:07 -04:00
Sam Protsenko
3db0989e68 env: ti: boot: Handle reboot reason from BCB
In case of Android boot, reboot reason can be written into BCB (usually
it's an area in 'misc' partition). U-Boot then can obtain that reboot
reason from BCB and handle it accordingly to achieve correct Android
boot flow, like it was suggested in [1]:
  - if it's empty: perform normal Android boot from eMMC
  - if it contains "bootonce-bootloader": get into fastboot mode
  - if it contains "boot-recovery": perform recovery boot

The latter is not implemented yet, as it depends on some features that
are not implemented on TI platforms yet (in AOSP and in U-Boot).

[1] https://marc.info/?l=u-boot&m=152508418909737&w=2

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-07-31 13:08:07 -04:00
Tom Rini
3fe483b13e Merge tag 'mmc-7-31' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
A new mmc/sd block test case
Bug fixes for sdhci and mv_sdhci
2019-07-31 08:34:35 -04:00
Heinrich Schuchardt
0c0cdc8610 clk: meson: remove duplicate logic
First thing we check in meson_clk_set_rate_by_id() is current_rate == rate.
There is not need to check it again.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-31 12:11:04 +02:00
Neil Armstrong
b160fac9f7 board: amlogic: add support for Odroid-N2
ODROID-N2 is a single board computer manufactured by Hardkernel Co. Ltd
with the following specifications:

 - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
 - 4GB DDR4 SDRAM
 - Gigabit Ethernet
 - HDMI 2.1 4K/60Hz display
 - 40-pin GPIO header
 - 4 x USB 3.0 Host, 1 x USB OTG
 - eMMC, microSD
 - Infrared receiver

The board directory is W400, the name of the Amlogic Reference Design
of Amlogic G12B with Gigabit boards, which will be used for similar
boards.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-31 12:10:58 +02:00
Neil Armstrong
5e5db096a3 ARM: meson-g12a: Handle 4GiB DRAM size
When configured with 4GiB DRAM size, only 3.8GiB is available, the
I/O beeing mapped in the last 256MiB of the first 4GiB physical memory/

First fixup the mm_region to handle the first 3.8GiB as memory and the
last 256MiB as I/O.

Then limit the real memory reported by the firmware to the available
physical space, 3.8GiB aligned with the mm_region memory zone size.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-31 12:10:54 +02:00
Neil Armstrong
0d84acb00a ARM: dts: add support for Odroid-N2
Import HardKernel Odroid-N2 DT from Linux 5.3-rc1, commit 5f9e832c1370
("Linus 5.3-rc1") based on an Amlogic G12B S922X SoC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-31 12:10:50 +02:00
Neil Armstrong
d93757f2f6 ARM: dts: Sync Amlogic G12A with Linux 5.3-rc1
Sync the Amlogic Meson G12A DT and Bindings file with the Linux 5.3-rc1
from the commit 5f9e832c1370 ("Linus 5.3-rc1").

Also remove the meson-g12a-u-boot.dtsi and meson-g12a-u200-u-boot.dtsi,
now conflicting with the main DT content.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Mark Kettenis <kettenis@openbsd.org>
2019-07-31 12:10:42 +02:00
Baruch Siach
fea3939d31 mmc: relocate code comment
The comment about init op being NULL used to be next to the NULL check
code. Commit 8ca51e51c1 ("dm: mmc: Add a way to use driver model for
MMC operations") separated the comment from the code. Put them back
together.

Fixes: 8ca51e51c1 ("dm: mmc: Add a way to use driver model for MMC operations")
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 15:31:36 +08:00
Weijie Gao
caa332336d mmc: mtk-sd: add WATCHDOG_RESET() to prevent watchdog timeout
When reading large data in once (reading 512MiB is tested on MT7623), a
watchdog timeout is triggered due to watchdog not being fed.

This patch adds WATCHDOG_RESET() to msdc_start_data() so the watchdog will
be fed every 1024 blocks are read/written.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-31 15:31:36 +08:00
Baruch Siach
58d65d5082 mmc: sdhci: fix chip detect gpio property name
The standard property name for chip-detect gpio is "cd-gpios". All
in-tree DT files use only this name.

Fixes: 451931ea70 ("mmc: sdhci: Read cd-gpio from devicetree")
Cc: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 15:31:36 +08:00
Baruch Siach
41a9fab8da mmc: mv_sdhci: fix uninitialized pointer deref on probe
Since commit 3d296365e4 ("mmc: sdhci: Add support for
sdhci-caps-mask") sdhci_setup_cfg() expects a valid sdhci_host mmc
field. Move the mmc field initialization before sdhci_setup_cfg()
call to avoid crash on mmc pointer dereference.

Fixes: 3d296365e4 ("mmc: sdhci: Add support for sdhci-caps-mask")
Cc: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2019-07-31 15:31:36 +08:00
Jean-Jacques Hiblot
09da18deab test/py: add MMC/SD block write test
Add a standalone MMC block write test. This allows direct testing of MMC
access rather than relying on doing so as a side-effect of e.g. DFU or
UMS testing, which may not be enabled on all platforms.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2019-07-31 15:31:36 +08:00
Peng Fan
4f895988ad test: dm: clk_ccf: test composite clk
Test composite clk with dm ccf

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
8f611dc71c clk: sandbox: add composite clk
Add composite clk to sandbox driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
7bd6432210 configs: sandbox: Enable composite clk
Enable composite clk for sandbox test

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
2b12957d01 clk: gate: support sandbox
Introduce io_gate_val for sandbox clk gate test usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
0009763588 clk: add composite clk support
Import clk composite clk support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
d669d1ae03 clk-provider: include clk-uclass.h
Because clk-provider use clk_ops, so let's include clk-uclass.h

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
91944ef09d dm: clk: ignore default settings when node not valid
When the device not binded with a node, we need ignore
the parents and rate settings.

Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
4b91ec076d clk: imx: gate2 add set rate
Add set rate for imx clk-gate2

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
b6c56d90b8 clk: imx: import clk heplers
Import some clk helpers from Linux Kernel for i.MX8MM usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
4f305bf1b6 clk: fixed_rate: export clk_fixed_rate
Export the structure for others to use.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
fe69b030de clk: divider set rate supporrt
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
1c64330318 clk: add clk-gate support
Import clk-gate support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
1b0d09cddb clk: export mux/divider ops
Export mux/divider ops and divider_recalc_rate for composite usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
4b044082c1 clk: mux: add set parent support
Add set parent support for clk mux

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
5b27ff8986 clk: use clk_dev_binded
Preparing to support composite clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Peng Fan
2457612d6d clk: introduce clk_dev_binded
When support Clock Common Framework, U-Boot use dev for
clk tree information, there is no clk->parent. When
support composite clk, it contains mux/gate/divider,
but the mux/gate/divider is not binded with device.
So we could not use dev_get_uclass_priv to get the correct
clk_mux/gate/divider. So add clk_dev_binded to let
choose the correct method.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 09:20:51 +02:00
Urja Rannikko
2b157019bb dw_mmc: turn on the IO supply
Fixes the microSD slot on the ASUS C201.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com<mailto:peng.fan@nxp.com>>
2019-07-31 09:07:30 +08:00
Tom Rini
a239147fa2 Merge tag 'video-for-2019.10-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- fix EDID mode filtering
- extend mxc_ipuv3_fb to enable backlight/display
- include fb_base in global_data for DM_VIDEO
- show frame buffer address via board info
  as used to be with legacy VIDEO support
2019-07-30 19:19:54 -04:00
Tom Rini
476a3143d7 Merge tag 'xilinx-for-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx/FPGA changes for v2019.10

fpga:
- Xilinx virtex2 cleanup
- Altera cyclon2 cleanup

zynq:
- Minor Kconfig cleanup
- Add psu_init configuration for Z-turn board

zynqmp:
- Add support for pmufw config passing to PMU
- script for psu_init conversion
- zcu1275 renaming

xilinx:
- Add support for UltraZed-EV SoM
2019-07-30 19:19:34 -04:00
Tom Rini
dcf722ece6 Merge branch 'master' of git://git.denx.de/u-boot-sh 2019-07-30 19:19:04 -04:00
Heinrich Schuchardt
bb68957720 efi_selftest: sharpen ConvertPointer() test
Now that ConvertPointer() is implemented throw an error if the result is
incorrect.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Heinrich Schuchardt
7be56e864e efi_loader: implement ConvertPointer()
Implement the ConvertPointer() runtime service.

Suggested-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Heinrich Schuchardt
24e6722b8a efi_loader: definition of efi_virtual_address_map()
Use efi_uintn_t where the UEFI spec uses UINTN. Use efi_uintn_t also for
the result of the division of two efi_uintn_t.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Heinrich Schuchardt
c0a8a95263 efi_selftest: fix SetVirtualAddressMap unit test
We read the address map before assigning the memory for the pages that will
be mapped to virtual addresses. So these pages will overlap with the entry
for EFI_CONVENTIONAL_MEMORY. We have to ensure that every page is described
at most once in the map.

Remove EFI_CONVENTIONAL_MEMORY from the map that we pass to
SetVirtualAddressMap().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Heinrich Schuchardt
73d95c24a5 doc: integrate UEFI documentation into Sphinx toctree
Change the UEFI documentation to Sphinx style and integrate it into the
rest of the Sphinx generated documentation.

Remove the inaccurate TODO list in doc/uefi/uefi.rst.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Heinrich Schuchardt
a6ccba0c35 efi_loader: efidebug.c function documentation
make htmldocs produces a warning:
./cmd/efidebug.c:733: WARNING: Unexpected indentation.
Correct the indentation.

Remove 'See above for details of sub-commands.' which is not helpful in the
Sphinx generated documentation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Heinrich Schuchardt
4ed0d3c3ea efi_loader: always rebuild efi_crt0.o
When changing the architecture without calling 'make clean' a subsequent
make fails with
lib/efi_loader/efi_crt0.o: file not recognized: File format not recognized

Force efi_crt0.o to be always rebuild.

Reported-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Heinrich Schuchardt
6f3badb67d efi_loader: re-enable GRUB workaround on 32bit ARM
GRUB on ARM 32bit prior to version 2.04 lacks proper handling of caches.
In U-Boot v2019.04 a workaround for this was inadvertently removed.

The workaround is currently also needed for booting on systems with caches
that cannot be managed via CP15 (e.g. with an i.MX6 CPU).

Re-enable the workaround and make it customizable.

Fixes: f69d63fae2 ("efi_loader: use efi_start_image() for bootefi")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-07-30 21:36:22 +02:00
Michal Simek
cd228cc04a arm64: zynqmp: Do not include pm_cfg_obj.o when SPL is disabled
xilinx_zynqmp_mini configuration is throwing build error:
readlink: missing operand
Try 'readlink --help' for more information.

because CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE is not defined at all and
Makefile pass ifneq condition. Add SPL_BUILD dependency which is also
reflected in Kconfig.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 17:09:58 +02:00
Heiko Schocher
42a7ce27d9 mxc_ipuv3_fb.c: enable a backlight on a panel
check if we get a panel device, if so, enable
the backlight on it.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-30 12:58:33 +02:00
Heiko Schocher
f4ec1ae08e mxc_ipuv3_fb.c: call display_enable
call display_enable, so a display gets enabled.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-30 12:57:47 +02:00
Heiko Schocher
5a760f61c5 bdinfo: show fb base with DM_VIDEO
show Framebuffer base with CONFIG_DM_VIDEO
enabled.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-30 12:57:01 +02:00
Heiko Schocher
f03e56adad mxc_ipuv3_fb.c: set gd->fb_base
set gd->fb_base so it can be shown with bdinfo command.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-30 12:55:06 +02:00
Heiko Schocher
98a8279806 global_data: enable fb_base for DM_VIDEO
with CONFIG_VIDEO we store fb base address
in global data fb_base variable. Do this
also in DM_VIDEO case.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-30 12:54:37 +02:00
Alexander Dahl
5a4675a917 cmd: fpga: Change return value to avoid printing usage text
In cmd/fpga.c the commands should return enum command_ret_t, e.g.
CMD_RET_USAGE, CMD_RET_SUCCESS, or CMD_RET_FAILURE. What they actually
do is passing a return value from different 'fpga_' functions.

Passing on a return value of -1 from a called function leads to printing
out usage text. In case of actually correct usage with correctly
specified parameters but some fail at runtime printing out that usage
text is distracting.

The reason is most 'fpga_' functions return either FPGA_SUCCESS or
FPGA_FAIL, the latter was equal to -1 which is the same value as
CMD_RET_USAGE. So just passing on FPGA_FAIL lead to printing out usage.

We should only return CMD_RET_USAGE in cases, where the user sent wrong
input. Every other case should return CMD_RET_SUCCESS or
CMD_RET_FAILURE, and not simply pass an error code.

Simply changing FPGA_FAIL from -1 to 1 gets the job done.

Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30 10:21:16 +02:00
Alexander Dahl
b283d6ba67 fpga: altera: cyclon2: Check function pointer before calling
As already done for the 'pre' function, a check is added to not follow a
NULL pointer, if somebody has not assigned a 'post' function.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30 10:21:15 +02:00
Alexander Dahl
3911b19cac fpga: altera: cyclon2: Fix indentation
Some code parts stood too far left …

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30 10:21:14 +02:00
Alexander Dahl
bb2c0fa03e fpga: altera: cyclon2: Fix most checkpatch warnings
Nothing special, but done before further cleanup.

* spacing
* braces
* __FUNCTION__ → __func__

Suggested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30 10:21:13 +02:00
Alexander Dahl
3b2a595fc6 fpga: altera: Add some more device sizes
There seems to be only one place, where this is checked against:
`altera_validate()`. It should be non zero. Otherwise it is only used to
display it, so it probably does not really matter at the moment. But we
had the datasheet open anyway …

Sizes in datasheet are bit counts, display here is in bytes.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-07-30 10:21:11 +02:00
Luca Ceresoli
216dad7507 arm64: zynqmp: add MAINTAINERS entry for Avnet UltraZed-EV
The board was added without adding a MAINTAINERS entry.

Fixes:

  $ ./tools/genboardscfg.py -f
  WARNING: no status info for 'avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0'
  WARNING: no maintainers for 'avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0'
  $

Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Robert Hancock
175dccd710 fpga: virtex2: Add slave serial programming support
This adds support for slave serial programming, in addition to the
previously supported slave SelectMAP mode. There are two ways that this
can be used:

-Using the clk and wdata callbacks in order to write image data one bit
at a time using pure bit-banging. This works, but is rather painfully
slow with typical image sizes.

-By specifying the wbulkdata callback instead, the image loading process
can be offloaded to SPI hardware. In this mode the clk and wdata
callbacks do not need to be specified. This allows the image to be
loaded much faster, taking only a few seconds with even relatively large
images.

Slave serial programming has been tested on the Kintex-7 series of
FPGAs.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Robert Hancock
a0549f7390 fpga: virtex2: Add additional clock cycles after DONE assertion
Some Xilinx FPGA configuration options can result in the startup
sequence extending past the end of the FPGA bitstream. Continue applying
CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure
the startup sequence is complete, as recommended by Xilinx.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Robert Hancock
3372081cfd fpga: virtex2: Split out image writing from pre/post operations
This is in preparation for adding slave serial programming support,
which uses the same pre/post operations as slave SelectMAP, to avoid
duplicating code.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Robert Hancock
25d63a3677 fpga: virtex2: added Kconfig option
Add an option to allow this driver to be selected with Kconfig. As noted
in the description, this driver should also work with many newer Xilinx
FPGA families as the programming methods are essentially the same.

Also added a missing FPGA_XILINX dependency to the similar Spartan 3
driver.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Robert Hancock
fa57af0552 fpga: virtex2: cosmetic: Cleanup code style
Address Checkpatch warnings in virtex2 code prior to making other
changes. No functional change intended.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Luca Ceresoli
ac80ac09c8 arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit
Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
only publicly-available compatible carrier card. The SoM is based on the EV
version of the Xilinx ZynqMP SoC+FPGA.

The psu_init_gpl.c file has been generated from the board definition files
at [0] using Vivado 2018.3 and then minimized by
tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since
it is not mentioned in device tree and fixed a checkpatch error.

[0] 3686c9ff7d/ultrazed_7ev_cc/1.1

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Luca Ceresoli
7f492f3c11 tools: zynqmp_psu_init_minimize.sh: fix return lines coding style
Remove unneeded parenthess around return value. E.g.:
    return (0);   ->   return 0;

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Anton Gerasimov
5456935a1d ARM: zynq: Add configuration for Z-turn board
Basic (PS-only) configuration based on Vivado board files by
Sergiusz Bazanski <sergius@q3k.org>

Signed-off-by: Anton Gerasimov <tossel@gmail.com>
2019-07-30 10:20:06 +02:00
Robert P. J. Day
ce9e4e0d52 cmd: fpga: correct typo, capitalize "Xilinx"
A couple minor tweaks to printed strings in cmd/fpga.c.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Luca Ceresoli
84a2c83263 arm64: zynqmp: add tool to minimize psu_init_gpl.c files
This script transforms a pair of psu_init_gpl.c and .h files produced by
the Xilinx Vivado tool for ZynqMP into a smaller psu_init_gpl.c file that
is almost checkpatch compliant.

Based on a script by Michal Simek.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Luca Ceresoli
04d2b0c7c2 arm64: zynqmp: xil_io.h: declare functions as static
Fixes sparse warnings when building zynqmp defconfigs:
  ./board/xilinx/zynqmp/xil_io.h:12:6: warning: symbol 'Xil_Out32' was not declared. Should it be static?
  ./board/xilinx/zynqmp/xil_io.h:17:5: warning: symbol 'Xil_In32' was not declared. Should it be static?
  ./board/xilinx/zynqmp/xil_io.h:22:6: warning: symbol 'usleep' was not declared. Should it be static?

Also add __maybe_unused to usleep() since it is not used by minimized
psu_init_gpl.c files, so it would warn as "defined but not used".

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Luca Ceresoli
4f4b56205e arm64: zynqmp: add tool to convert PMU config object .c to binary
The recently-added ZYNQMP_SPL_PM_CFG_OBJ_FILE option allows SPL to load a
PMUFW configuration object from a binary blob. However the configuration
object is produced by Xilinx proprietary tools as a C source file and no
tool exists to easily convert it to a binary blob in an embedded Linux
build system for U-Boot to use.

Add a simple Python script to do the conversion.

It is definitely not a complete C language parser, but it is enough to
parse the known patterns generated by Xilinx tools, including:

 - defines
 - literal integers, optionally with a 'U' suffix
 - bitwise OR between them

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Luca Ceresoli
c28a9cfa40 arm64: zynqmp: spl: install a PMU firmware config object at runtime
Optionally allow U-Boot to load a configuration object into the Power
Management Unit (PMU) firmware on Xilinx ZynqMP.

The configuration object is required by the PMU FW to enable most SoC
peripherals. So far the only way to boot using U-Boot SPL was to hard-code
the configuration object in the PMU firmware. Allow a different boot
process, where the PMU FW is equal for any ZynqMP chip and its
configuration is passed at runtime by U-Boot SPL.

All the code for Inter-processor communication with the PMU is isolated in
a new file (pmu_ipc.c). The code is inspired by the same feature as
implemented in the Xilinx First Stage Bootloader (FSBL) and Arm Trusted
Firmware:

 * fb647e6b4c/lib/sw_apps/zynqmp_fsbl/src/xfsbl_misc_drivers.c (L295)
 * c48d02bade/plat/xilinx/zynqmp/pm_service/pm_api_sys.c (L357)

SPL logs on the console before loading the configuration object:

  U-Boot SPL 2019.07-rc1-00511-gaec224515c87 (May 15 2019 - 08:43:41 +0200)
  Loading PMUFW cfg obj (2008 bytes)
  EL Level:	EL3
  ...

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Michal Simek
420d446781 arm64: zynqmp: Rename zc1275 to zcu1275
Name of this platform has changed and released to customers that's why
name has also changed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Series-to: uboot
2019-07-30 10:20:06 +02:00
Robert P. J. Day
ce7b93d4fc ARM: zynq: delete long-dead CONFIG_USB_CABLE_CHECK
This Kbuild option disappeared way back in 2014:

 commit 75504e9592
 Author: Mateusz Zalega <m.zalega@samsung.com>
 Date:   Wed Apr 30 13:07:48 2014 +0200

    ... snip ...

    CONFIG_USB_CABLE_CHECK was removed.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-07-30 10:20:06 +02:00
Neil Armstrong
2f6dc79a4f edid: fix edid_get_timing_validate() mode_valid lookup
Add a condition to the break in the modes lookup, without this
when the first mode is not valid, then edid_get_timing_validate()
return an error instead of checking the next modes.

Fixes: 1c1ed441b0 ("edid: add edid_get_timing_validate() variant to filter out edid modes")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-07-29 19:14:58 +02:00
titron
b5f563e588 pinctrl: renesas: fix R-Car gpio0_00 operation fails with 'gpio -input' command
Fix GPIO bank 0 pin 0 request/release off by one error. Without this
patch, it is not possible to request/release GPIO bank 0 pin 0.

Signed-off-by: Tiezhuang Dong <tiezhuang.dong.yh@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-07-29 13:38:55 +02:00
Eugeniu Rosca
89c00f009c ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.2
Backport and squash below Linux 5.2 commits for R-Car Gen3:

Commit id       * Summary line
6fffb98645e67b5   arm64: dts: renesas: r8a77990: ebisu: Add GPIO expander
b068ed6efe6244d   arm64: dts: renesas: r8a77990: Fix SPDX license identifier style
96c25882252704d ! arm64: dts: renesas: r8a7796: remove unneeded sound #address/size-cells
71ac75dffdae2f8   arm64: dts: renesas: r8a77990: ebisu: Enable LVDS1 encoder
9a0ff5c727b60a3   arm64: dts: renesas: r8a77995: draak: Enable LVDS1 encoder
9130c15829846fa   arm64: dts: renesas: ebisu: Fix adv7482 hexadecimal register address
191f7dcd1f5ea1f   arm64: dts: renesas: r8a77965: add SSIU support for sound
a8f6110e64422d5   arm64: dts: renesas: ebisu: Enable VIN5
4162aa9db3d4469   arm64: dts: renesas: r8a77995: draak: Enable CAN0, CAN1
af965ba3248edde   arm64: dts: renesas: r8a77990: Remove invalid compatible value for CSI40
1f4c123a98098cc   arm64: dts: renesas: r8a77990-ebisu: Add BD9571 PMIC
474706117c2baa6   arm64: dts: renesas: ebisu: Add PMIC DDR0 Backup Power config
e2fa79de7ecbef4   arm64: dts: renesas: Update Ebisu and Draak bootargs
de8e8daaf7190ef   arm64: dts: renesas: salvator-common: Sort node label
05f1d882d28b871   arm64: dts: renesas: r8a77995: draak: Fix EthernetAVB phy mode to rgmii
7a516e49d975311   arm64: dts: renesas: use extended audio dmac register
e3414b8c45afa5c   arm64: dts: renesas: salvator-common: Add GPIO keys support
720066d17c973fd   arm64: dts: renesas: r8a7795: Add CMT device nodes
99cb95103e2d058   arm64: dts: renesas: r8a77965: Add CMT device nodes
28a5c61b5136d58   arm64: dts: renesas: r8a77990: Add CMT device nodes
32d622f3290b2a1   arm64: dts: renesas: r8a77965: Remove reg-names of display node

(*) Patch id mismatch between Linux and U-Boot commit.
[!] Dropped changes in arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts,
    since the file doesn't exist in the U-Boot tree.

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-23 13:38:23 +02:00
Eugeniu Rosca
70f3b164a6 dt-bindings: Synchronize R-Car Gen3 headers with Linux 5.2
Backport and squash below Linux v5.2 commits:

Commit id       *  Summary line
da3e1c57caf93e [1] soc: renesas: r8a77970-sysc: Remove non-existent CR7 power domain
b5eb730e031aca [1] soc: renesas: r8a77970-sysc: Correct names of A2DP/A2CN power domains
3961d355dfb512     dt-bindings: power: r8a77965: Remove non-existent A3IR power domain

(*) Patch id mismatch between Linux and U-Boot commit
[1] Dropped changes in drivers/soc/renesas/r8a77970-sysc.c,
    since the file doesn't exist in U-Boot.

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-23 13:38:23 +02:00
Eugeniu Rosca
7f2e60f1ba pinctrl: renesas: Synchronize Gen2/Gen3 tables with Linux 5.2
In spite of the summary line, U-Boot commits [1-2] seem to have
aligned the U-Boot PFC tables to Linux v5.1 rather than to v5.0, since
they also imported the Linux 5.1 commits listed in [3].

What current commit tries to accomplish is to align the Gen2 and Gen3
pinctrl tables to Linux v5.2. Importing these updates in two steps
as done before (i.e. separately for Gen2 and Gen3) is somewhat difficult
due to Linux commits like [5-6] which atomically update both Gen2/3
platforms and whose breakdown would not be easily possible.

The detailed list of Linux commits squashed into this U-Boot patch is
shown in [4]. The second column in [4] depicts the patch id mismatch
between the original Linux and the resulted U-Boot commit. The
exclamation mark means that manual conflict resolution was involved
during cherry picking Linux commit into U-Boot repository (this is
mainly caused by dropped changes in files like pfc-r8a7795-es1.c and
pfc-r8a77980.c which are missing in U-Boot).

This patch has been applied on top of v2019.07-rc4-155-g8754656680b6 and
boot-tested on:
 - H3-ES2.0-Salvator-X
 - M3-ES1.1-Salvator-XS
 - M3N-ES1.1-ULCB

[1] 8719ca8113 ("pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0")
[2] a6a743df24 ("pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0")

[3] Linux 5.1 commits already contained in [1-2]:
79dbbdbeccc6784 pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
729257d674bc2e6 pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
b9fd50488b4939c pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
a4b0350047f1b10 pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
fdbbd6b74c9278f pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions
16978e7d40f73be pinctrl: sh-pfc: r8a77990: Add TMU pins, groups and functions
86c045c2e4201e9 pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3
b8ba194ca5f4ca2 pinctrl: sh-pfc: r8a7791: Fix VIN1 versioned groups
81c585c96b7dd47 pinctrl: sh-pfc: r8a77970: Deduplicate VIN[01] pin definitions
08b7e2112a9b19c pinctrl: sh-pfc: r8a7796: Deduplicate VIN5 pin definitions
99fdb920f5534d1 pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions
85ccae133bde425 Revert "pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins"
f7d8b568e204d29 pinctrl: sh-pfc: r8a77990: GP6_9 does not have pull-down capability
5219aa33caec2f7 pinctrl: sh-pfc: r8a77995: Fix MOD_SEL bit numbering
3e3eebeacad79bd pinctrl: sh-pfc: r8a77990: Fix MOD_SEL bit numbering
7219a4b64520873 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit2 when using RX2, TX2 and SCK2
699c7d1346fbef6 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit3 when using TX0

[4] Linux 5.2 commits backported and squashed into this U-Boot patch
Linux commit id   Linux commit summary line
9925e8795726801   pinctrl: sh-pfc: Validate pins/marks in pin groups at build time
f83f97684a737f6   pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
5e8588c86d71e78   pinctrl: sh-pfc: Validate fixed-size field widths at build time
1c5c1101755c5ed   pinctrl: sh-pfc: r8a77970: Rename IOCTRLx registers
3df892fdbfe6919   pinctrl: sh-pfc: r8a77990: Rename IOCTRLx registers
dcd24e098d8df8b   pinctrl: sh-pfc: r8a7796: Move CANFD pin groups and functions
2cee6cb290ab30f   pinctrl: sh-pfc: r8a77990: Move CANFD pin groups and functions
d92ee9cf8ec8d7f ! pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume
efca8da0c5fcc7f ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
69f7be1c6314fb0 ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
19b593a1cf068ef ! pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
c481c8178420b8c   pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
fa4d36712f20e24 ! pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
360328c7dc15f48   pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
943ff71281c6ce4   pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
e167d723e1a472d   pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
e87882eb9be10b2   pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
5671f8e0270ad5e ! pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
662dc924a05e9df ! pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
624a7a12cc0cc77 ! pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
a040f3dec8eb7b1   pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
e551122cdb7fcb9   pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
baaa2effc684e49   pinctrl: sh-pfc: r8a77970: Fix spacing
f05603fa6aa3043   pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
0a042b355e60269   pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions

[5] efca8da0c5fcc7 ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro")
[6] 69f7be1c6314fb ("pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro")

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
2019-07-23 13:38:23 +02:00
Marek Vasut
b3db7be4e3 ARM: renesas: Update Gen3 PCIe dma-ranges before boot
Update "dma-ranges" DT property of all PCIe controllers in the system
with the up-to-date DRAM layout. This allows the PCIe controller take
full advantage of all the available DRAM.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-07-23 13:38:17 +02:00
Marek Vasut
3a8cd17d0e common: fdt_support: Add missing cpu_to_fdt32() to fdt_pci_dma_ranges()
The fdt_pci_dma_ranges() cannot work on e.g. ARM, since the DT entries
endianness is not adjusted at all. Fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2019-07-23 13:38:17 +02:00
1440 changed files with 31472 additions and 6913 deletions

View File

@@ -2,7 +2,7 @@
# Grab our configured image. The source for this is found at:
# https://gitlab.denx.de/u-boot/gitlab-ci-runner
image: trini/u-boot-gitlab-ci-runner:xenial-20190720-29Jul2019
image: trini/u-boot-gitlab-ci-runner:xenial-20190720-02Aug2019
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -145,34 +145,24 @@ Build tools-only:
script:
- make tools-only_config tools-only -j$(nproc)
# Run various tool tests
Run patman testsuite:
Run binman, buildman, dtoc and patman testsuites:
tags: [ 'all' ]
stage: testsuites
script:
- git config --global user.name "GitLab CI Runner"
- git config --global user.email trini@konsulko.com
- ./tools/patman/patman --test
Run buildman testsuite:
tags: [ 'all' ]
stage: testsuites
script:
- ./tools/buildman/buildman -t
Run binman and dtoc testsuite:
tags: [ 'all' ]
stage: testsuites
script:
- virtualenv /tmp/venv
- . /tmp/venv/bin/activate
- pip install pyelftools
- export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/sandbox_spl;
./tools/buildman/buildman -P sandbox_spl &&
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test &&
./tools/dtoc/dtoc -t
- git config --global user.name "GitLab CI Runner";
git config --global user.email trini@konsulko.com;
export USER=gitlab;
virtualenv /tmp/venv;
. /tmp/venv/bin/activate;
pip install pyelftools;
export UBOOT_TRAVIS_BUILD_DIR=`cd .. && pwd`/.bm-work/sandbox_spl;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
./tools/buildman/buildman -P sandbox_spl;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
./tools/patman/patman --test
# Test sandbox with test.py
sandbox test.py:
@@ -252,7 +242,6 @@ qemu_mips test.py:
TEST_PY_BD: "qemu_mips"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mips$"
TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu_mipsel test.py:
@@ -261,7 +250,6 @@ qemu_mipsel test.py:
TEST_PY_BD: "qemu_mipsel"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mipsel$"
TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu_mips64 test.py:
@@ -270,7 +258,6 @@ qemu_mips64 test.py:
TEST_PY_BD: "qemu_mips64"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mips64$"
TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu_mips64el test.py:
@@ -279,7 +266,6 @@ qemu_mips64el test.py:
TEST_PY_BD: "qemu_mips64el"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu_mips64el$"
TOOLCHAIN: "mips"
<<: *buildman_and_testpy_dfn
qemu-ppce500 test.py:
@@ -288,7 +274,14 @@ qemu-ppce500 test.py:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-ppce500$"
TOOLCHAIN: "powerpc"
<<: *buildman_and_testpy_dfn
qemu-riscv64 test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "qemu-riscv64"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-riscv64$"
<<: *buildman_and_testpy_dfn
qemu-x86 test.py:
@@ -297,7 +290,6 @@ qemu-x86 test.py:
TEST_PY_BD: "qemu-x86"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-x86$"
TOOLCHAIN: "i386"
<<: *buildman_and_testpy_dfn
qemu-x86_64 test.py:
@@ -306,7 +298,6 @@ qemu-x86_64 test.py:
TEST_PY_BD: "qemu-x86_64"
TEST_PY_TEST_SPEC: "not sleep"
BUILDMAN: "^qemu-x86_64$"
TOOLCHAIN: "i386"
<<: *buildman_and_testpy_dfn
zynq_zc702 test.py:
@@ -334,5 +325,4 @@ xtfpga test.py:
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
BUILDMAN: "^xtfpga$"
TOOLCHAIN: "xtensa-dc233c-elf"
<<: *buildman_and_testpy_dfn

View File

@@ -459,6 +459,13 @@ matrix:
QEMU_TARGET="ppc-softmmu"
BUILDMAN="^qemu-ppce500$"
TOOLCHAIN="powerpc"
- name: "test/py qemu-riscv64"
env:
- TEST_PY_BD="qemu-riscv64"
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="riscv64-softmmu"
BUILDMAN="^qemu-riscv64$"
TOOLCHAIN="riscv"
- name: "test/py qemu-x86"
env:
- TEST_PY_BD="qemu-x86"

View File

@@ -50,6 +50,26 @@ so much easier [Ed]
Maintainers List (try to look for most precise areas first)
-----------------------------------
ANDROID AB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: cmd/ab_select.c
F: common/android_ab.c
F: doc/android/ab.txt
F: include/android_ab.h
F: test/py/tests/test_android/test_ab.py
ANDROID AVB
M: Igor Opaniuk <igor.opaniuk@gmail.com>
S: Maintained
F: cmd/avb.c
F: common/avb_verify.c
F: doc/android/avb2.txt
F: include/avb_verify.h
F: lib/libavb/
F: test/py/tests/test_android/test_avb.py
ARC
M: Alexey Brodkin <alexey.brodkin@synopsys.com>
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
@@ -168,9 +188,11 @@ F: board/freescale/*mx*/
ARM HISILICON
M: Peter Griffin <peter.griffin@linaro.org>
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
S: Maintained
F: arch/arm/cpu/armv8/hisilicon
F: arch/arm/include/asm/arch-hi6220/
F: arch/arm/include/asm/arch-hi3660/
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <sr@denx.de>
@@ -196,6 +218,7 @@ F: arch/arm/include/asm/arch-pxa/
ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
@@ -485,9 +508,7 @@ M: Heinrich Schuchardt <xypron.glpk@gmx.de>
R: Alexander Graf <agraf@csgraf.de>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
F: doc/README.uefi
F: doc/README.iscsi
F: doc/efi.rst
F: doc/uefi/*
F: include/capitalization.h
F: include/charset.h
F: include/cp1250.h

View File

@@ -3,7 +3,7 @@
VERSION = 2019
PATCHLEVEL = 10
SUBLEVEL =
EXTRAVERSION = -rc1
EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*

169
README
View File

@@ -83,7 +83,7 @@ Where we come from:
* Provide extended interface to Linux boot loader
* S-Record download
* network boot
* PCMCIA / CompactFlash / ATA disk / SCSI ... boot
* ATA disk / SCSI ... boot
- create ARMBoot project (http://sourceforge.net/projects/armboot)
- add other CPU families (starting with ARM)
- create U-Boot project (http://sourceforge.net/projects/u-boot)
@@ -2134,171 +2134,6 @@ The following options need to be configured:
A better solution is to properly configure the firewall,
but sometimes that is not allowed.
- Show boot progress:
CONFIG_SHOW_BOOT_PROGRESS
Defining this option allows to add some board-
specific code (calling a user-provided function
"show_boot_progress(int)") that enables you to show
the system's boot progress on some display (for
example, some LED's) on your board. At the moment,
the following checkpoints are implemented:
Legacy uImage format:
Arg Where When
1 common/cmd_bootm.c before attempting to boot an image
-1 common/cmd_bootm.c Image header has bad magic number
2 common/cmd_bootm.c Image header has correct magic number
-2 common/cmd_bootm.c Image header has bad checksum
3 common/cmd_bootm.c Image header has correct checksum
-3 common/cmd_bootm.c Image data has bad checksum
4 common/cmd_bootm.c Image data has correct checksum
-4 common/cmd_bootm.c Image is for unsupported architecture
5 common/cmd_bootm.c Architecture check OK
-5 common/cmd_bootm.c Wrong Image Type (not kernel, multi)
6 common/cmd_bootm.c Image Type check OK
-6 common/cmd_bootm.c gunzip uncompression error
-7 common/cmd_bootm.c Unimplemented compression type
7 common/cmd_bootm.c Uncompression OK
8 common/cmd_bootm.c No uncompress/copy overwrite error
-9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX)
9 common/image.c Start initial ramdisk verification
-10 common/image.c Ramdisk header has bad magic number
-11 common/image.c Ramdisk header has bad checksum
10 common/image.c Ramdisk header is OK
-12 common/image.c Ramdisk data has bad checksum
11 common/image.c Ramdisk data has correct checksum
12 common/image.c Ramdisk verification complete, start loading
-13 common/image.c Wrong Image Type (not PPC Linux ramdisk)
13 common/image.c Start multifile image verification
14 common/image.c No initial ramdisk, no multifile, continue.
15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
-30 arch/powerpc/lib/board.c Fatal error, hang the system
-31 post/post.c POST test failed, detected by post_output_backlog()
-32 post/post.c POST test failed, detected by post_run_single()
34 common/cmd_doc.c before loading a Image from a DOC device
-35 common/cmd_doc.c Bad usage of "doc" command
35 common/cmd_doc.c correct usage of "doc" command
-36 common/cmd_doc.c No boot device
36 common/cmd_doc.c correct boot device
-37 common/cmd_doc.c Unknown Chip ID on boot device
37 common/cmd_doc.c correct chip ID found, device available
-38 common/cmd_doc.c Read Error on boot device
38 common/cmd_doc.c reading Image header from DOC device OK
-39 common/cmd_doc.c Image header has bad magic number
39 common/cmd_doc.c Image header has correct magic number
-40 common/cmd_doc.c Error reading Image from DOC device
40 common/cmd_doc.c Image header has correct magic number
41 common/cmd_ide.c before loading a Image from a IDE device
-42 common/cmd_ide.c Bad usage of "ide" command
42 common/cmd_ide.c correct usage of "ide" command
-43 common/cmd_ide.c No boot device
43 common/cmd_ide.c boot device found
-44 common/cmd_ide.c Device not available
44 common/cmd_ide.c Device available
-45 common/cmd_ide.c wrong partition selected
45 common/cmd_ide.c partition selected
-46 common/cmd_ide.c Unknown partition table
46 common/cmd_ide.c valid partition table found
-47 common/cmd_ide.c Invalid partition type
47 common/cmd_ide.c correct partition type
-48 common/cmd_ide.c Error reading Image Header on boot device
48 common/cmd_ide.c reading Image Header from IDE device OK
-49 common/cmd_ide.c Image header has bad magic number
49 common/cmd_ide.c Image header has correct magic number
-50 common/cmd_ide.c Image header has bad checksum
50 common/cmd_ide.c Image header has correct checksum
-51 common/cmd_ide.c Error reading Image from IDE device
51 common/cmd_ide.c reading Image from IDE device OK
52 common/cmd_nand.c before loading a Image from a NAND device
-53 common/cmd_nand.c Bad usage of "nand" command
53 common/cmd_nand.c correct usage of "nand" command
-54 common/cmd_nand.c No boot device
54 common/cmd_nand.c boot device found
-55 common/cmd_nand.c Unknown Chip ID on boot device
55 common/cmd_nand.c correct chip ID found, device available
-56 common/cmd_nand.c Error reading Image Header on boot device
56 common/cmd_nand.c reading Image Header from NAND device OK
-57 common/cmd_nand.c Image header has bad magic number
57 common/cmd_nand.c Image header has correct magic number
-58 common/cmd_nand.c Error reading Image from NAND device
58 common/cmd_nand.c reading Image from NAND device OK
-60 common/env_common.c Environment has a bad CRC, using default
64 net/eth.c starting with Ethernet configuration.
-64 net/eth.c no Ethernet found.
65 net/eth.c Ethernet found.
-80 common/cmd_net.c usage wrong
80 common/cmd_net.c before calling net_loop()
-81 common/cmd_net.c some error in net_loop() occurred
81 common/cmd_net.c net_loop() back without error
-82 common/cmd_net.c size == 0 (File with size 0 loaded)
82 common/cmd_net.c trying automatic boot
83 common/cmd_net.c running "source" command
-83 common/cmd_net.c some error in automatic boot or "source" command
84 common/cmd_net.c end without errors
FIT uImage format:
Arg Where When
100 common/cmd_bootm.c Kernel FIT Image has correct format
-100 common/cmd_bootm.c Kernel FIT Image has incorrect format
101 common/cmd_bootm.c No Kernel subimage unit name, using configuration
-101 common/cmd_bootm.c Can't get configuration for kernel subimage
102 common/cmd_bootm.c Kernel unit name specified
-103 common/cmd_bootm.c Can't get kernel subimage node offset
103 common/cmd_bootm.c Found configuration node
104 common/cmd_bootm.c Got kernel subimage node offset
-104 common/cmd_bootm.c Kernel subimage hash verification failed
105 common/cmd_bootm.c Kernel subimage hash verification OK
-105 common/cmd_bootm.c Kernel subimage is for unsupported architecture
106 common/cmd_bootm.c Architecture check OK
-106 common/cmd_bootm.c Kernel subimage has wrong type
107 common/cmd_bootm.c Kernel subimage type OK
-107 common/cmd_bootm.c Can't get kernel subimage data/size
108 common/cmd_bootm.c Got kernel subimage data/size
-108 common/cmd_bootm.c Wrong image type (not legacy, FIT)
-109 common/cmd_bootm.c Can't get kernel subimage type
-110 common/cmd_bootm.c Can't get kernel subimage comp
-111 common/cmd_bootm.c Can't get kernel subimage os
-112 common/cmd_bootm.c Can't get kernel subimage load address
-113 common/cmd_bootm.c Image uncompress/copy overwrite error
120 common/image.c Start initial ramdisk verification
-120 common/image.c Ramdisk FIT image has incorrect format
121 common/image.c Ramdisk FIT image has correct format
122 common/image.c No ramdisk subimage unit name, using configuration
-122 common/image.c Can't get configuration for ramdisk subimage
123 common/image.c Ramdisk unit name specified
-124 common/image.c Can't get ramdisk subimage node offset
125 common/image.c Got ramdisk subimage node offset
-125 common/image.c Ramdisk subimage hash verification failed
126 common/image.c Ramdisk subimage hash verification OK
-126 common/image.c Ramdisk subimage for unsupported architecture
127 common/image.c Architecture check OK
-127 common/image.c Can't get ramdisk subimage data/size
128 common/image.c Got ramdisk subimage data/size
129 common/image.c Can't get ramdisk load address
-129 common/image.c Got ramdisk load address
-130 common/cmd_doc.c Incorrect FIT image format
131 common/cmd_doc.c FIT image format OK
-140 common/cmd_ide.c Incorrect FIT image format
141 common/cmd_ide.c FIT image format OK
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
This option defines a board specific value for the
@@ -3586,6 +3421,8 @@ List of environment variables (most likely not complete):
allowed for use by the bootm command. See also "bootm_low"
environment variable.
bootstopkeysha256, bootdelaykey, bootstopkey - See README.autoboot
updatefile - Location of the software update file on a TFTP server, used
by the automatic software update feature. Please refer to
documentation in doc/README.update for more details.

View File

@@ -8,8 +8,9 @@
#include <config.h>
#include <command.h>
#include <common.h>
#include <env.h>
#include <malloc.h>
#include <environment.h>
#include <env_internal.h>
#include <linux/types.h>
#include <api_public.h>
@@ -496,7 +497,7 @@ static int API_env_enum(va_list ap)
{
int i, buflen;
char *last, **next, *s;
ENTRY *match, search;
struct env_entry *match, search;
static char *var;
last = (char *)va_arg(ap, unsigned long);
@@ -513,7 +514,7 @@ static int API_env_enum(va_list ap)
if (s != NULL)
*s = 0;
search.key = var;
i = hsearch_r(search, FIND, &match, &env_htab, 0);
i = hsearch_r(search, ENV_FIND, &match, &env_htab, 0);
if (i == 0) {
i = API_EINVAL;
goto done;

View File

@@ -93,6 +93,7 @@ config SANDBOX
select PCI_ENDPOINT
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
imply BITREVERSE
select BLOBLIST
imply CMD_DM

View File

@@ -902,7 +902,7 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_STRATIX10 if TARGET_SOCFPGA_STRATIX10
select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -1209,6 +1209,18 @@ config TARGET_HIKEY
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
config TARGET_HIKEY960
bool "Support HiKey960 96boards Consumer Edition Platform"
select ARM64
select DM
select DM_SERIAL
select OF_CONTROL
select PL01X_SERIAL
imply CMD_DM
help
Support for HiKey960 96boards platform. It features a HI3660
SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
config TARGET_POPLAR
bool "Support Poplar 96boards Enterprise Edition Platform"
select ARM64
@@ -1778,6 +1790,7 @@ source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/phytec/pcm051/Kconfig"

View File

@@ -6,7 +6,7 @@
#include <common.h>
#include <command.h>
#include <environment.h>
#include <env.h>
#include <i2c.h>
#include <net.h>
#include <linux/mtd/st_smi.h>

View File

@@ -9,6 +9,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/sys_proto.h>
#include <env.h>
#include <netdev.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>

View File

@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <env.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <linux/errno.h>
@@ -32,7 +33,7 @@
#include <fsl_qbman.h>
#ifdef CONFIG_TFABOOT
#include <environment.h>
#include <env_internal.h>
#ifdef CONFIG_CHAIN_OF_TRUST
#include <fsl_validate.h>
#endif

View File

@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <env.h>
#include <fsl_immap.h>
#include <fsl_ifc.h>
#include <asm/arch/fsl_serdes.h>
@@ -26,7 +27,7 @@
#endif
#include <fsl_immap.h>
#ifdef CONFIG_TFABOOT
#include <environment.h>
#include <env_internal.h>
DECLARE_GLOBAL_DATA_PTR;
#endif

View File

@@ -4,6 +4,7 @@
*/
#include <common.h>
#include <env.h>
#include <spl.h>
#include <asm/io.h>
#include <fsl_ifc.h>

View File

@@ -15,6 +15,7 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
exynos4412-odroid.dtb
dtb-$(CONFIG_TARGET_HIKEY) += hi6220-hikey.dtb
dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
@@ -108,6 +109,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-ficus.dtb \
rk3399-firefly.dtb \
rk3399-gru-bob.dtb \
rk3399-khadas-edge.dtb \
rk3399-khadas-edge-captain.dtb \
rk3399-khadas-edge-v.dtb \
rk3399-nanopc-t4.dtb \
rk3399-nanopi-m4.dtb \
rk3399-nanopi-neo4.dtb \
@@ -115,6 +119,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-puma-ddr1333.dtb \
rk3399-puma-ddr1600.dtb \
rk3399-puma-ddr1866.dtb \
rk3399-roc-pc.dtb \
rk3399-rock-pi-4.dtb \
rk3399-rock960.dtb \
rk3399-rockpro64.dtb
@@ -135,7 +140,9 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxm-khadas-vim2.dtb \
meson-axg-s400.dtb \
meson-g12a-u200.dtb
meson-g12a-u200.dtb \
meson-g12a-sei510.dtb \
meson-g12b-odroid-n2.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
@@ -240,6 +247,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
@@ -253,10 +261,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu104-revC.dtb \
zynqmp-zcu106-revA.dtb \
zynqmp-zcu111-revA.dtb \
zynqmp-zcu1275-revA.dtb \
zynqmp-zcu1275-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1275-revA.dtb \
zynqmp-zc1275-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm017-dc3.dtb \
@@ -276,6 +284,7 @@ dtb-$(CONFIG_AM33XX) += \
am335x-brppt1-nand.dtb \
am335x-brppt1-spi.dtb \
am335x-brxre1.dtb \
am335x-brsmarc1.dtb \
am335x-draco.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
@@ -640,6 +649,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77965-m3nulcb-u-boot.dtb \
r8a77965-salvator-x-u-boot.dtb \
r8a77970-eagle-u-boot.dtb \
r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb

View File

@@ -0,0 +1,416 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 B&R Industrial Automation GmbH
* http://www.br-automation.com
*
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "dt-bindings/thermal/thermal.h"
/ {
model = "BRSMARC1 SoM";
compatible = "ti,am33xx";
fset: factory-settings {
bl-version = " ";
order-no = " ";
cpu-order-no = " ";
hw-revision = " ";
serial-no = <0>;
device-id = <0x0>;
parent-id = <0x0>;
hw-variant = <0x0>;
hw-platform = <0x7>;
fram-offset = <0x100>;
fram-size = <0x1F00>;
cache-disable = <0x0>;
cpu-clock = <0x0>;
};
chosen {
bootargs = "console=ttyO0,115200 earlyprintk";
stdout-path = &uart0;
};
aliases {
fset = &fset;
mmc = &mmc2;
spi0 = &spi0;
spi1 = &spi1;
touch0 = &burtouch0;
screen0 = &lcdscreen0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
lcdscreen0: lcdscreen@0 {
/*backlight = <&tps_bl>; */
compatible = "ti,tilcdc,panel";
status = "okay";
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
rotation = <0>;
pupdelay = <0>;
pondelay = <0>;
pwrpin = <0x000000B1>;
brightdrv = <0>;
brightfdim = <100>;
brightdef = <50>;
};
display-timings {
default {
clock-frequency = <0>;
hactive = <0>;
vactive = <0>;
hfront-porch = <0>;
hback-porch = <0>;
hsync-len = <0>;
vfront-porch = <0>;
vback-porch = <0>;
vsync-len = <0>;
hsync-active = <0>;
vsync-active = <0>;
pupdelay = <10>;
pondelay = <10>;
};
};
};
board_thermal: board-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <2500>; /* milliseconds */
thermal-sensors = <&cputemp>;
trips {
crit_trip: crit-trip {
temperature = <95000>; /* millicelsius */
hysteresis = <5000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&crit_trip>;
cooling-device =
<&resetc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&uart0 { /* console uart */
u-boot,dm-spl;
status = "okay";
};
&uart2 { /* X2X - P2P */
status = "okay";
};
&uart3 { /* RS485 */
status = "okay";
};
&uart4 { /* RS232 */
status = "okay";
};
&i2c0 {
u-boot,dm-spl;
status = "okay";
clock-frequency = <100000>;
tps: tps@24 { /* PMIC controller */
u-boot,dm-spl;
reg = <0x24>;
compatible = "ti,tps65217";
};
cputemp: temperature-sensor@48 { /* cpu temperature */
#thermal-sensor-cells = <0>;
compatible = "nxp,pct2075";
reg = <0x48>;
};
basetemp: temperature-sensor@49 { /* baseboard temperature */
#thermal-sensor-cells = <0>;
compatible = "nxp,pct2075";
reg = <0x49>;
};
extrtc: rtc@51 { /* realtime clock */
compatible = "epson,rx8571";
reg = <0x51>;
};
resetc: reset-controller@60 {
compatible = "bur,rststm";
reg = <0x60>;
cooling-min-state = <0>;
cooling-max-state = <1>; /* reset gets fired */
#cooling-cells = <2>; /* min followed by max */
};
};
&i2c1 {
u-boot,dm-spl;
status = "okay";
};
&spi0 {
u-boot,dm-spl;
status = "okay";
cs-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>,
<&gpio0 6 GPIO_ACTIVE_HIGH>,
<0>,
<0>;
spi-max-frequency = <24000000>;
spi_flash: spiflash@0 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
compatible = "spidev", "spi-flash";
spi-max-frequency = <24000000>;
reg = <0>;
};
};
&spi1 {
u-boot,dm-spl;
status = "okay";
cs-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>,
<&gpio0 19 GPIO_ACTIVE_HIGH>,
<0>,
<0>;
spi-max-frequency = <24000000>;
};
&edma {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&davinci_mdio {
status = "okay";
};
&mac {
status = "okay";
};
&phy_sel {
rmii-clock-ext;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rmii";
ti,ledcr = <0x0480>;
};
&mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x8>;
ti,non-removable;
ti,needs-special-hs-handling;
ti,vcc-aux-disable-is-sleep;
status = "okay";
};
&lcdc {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&elm {
status = "okay";
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio1 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio2 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&gpio3 {
u-boot,dm-spl;
ti,no-reset-on-init;
};
&timer1 { /* today unused */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer2 { /* used for vxworks primary timer device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer3 { /* used sysdelay and hal tsc counter*/
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer4 { /* used for PWM beeper */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer5 { /* used for PWM backlight */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer6 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&timer7 { /* used for cpsw end device */
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&wdt2 {
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&epwmss0 {
status = "okay";
};
&tscadc {
status = "okay";
tsc {
burtouch0: burtouch@0 {
status = "okay";
compatible = "bur,DdVxSfTouchXXX";
bur,hwtree = "IF7";
bur,KX0 = <0x0>;
bur,KX1 = <0x0>;
bur,KX2 = <0x0>;
bur,KY0 = <0x0>;
bur,KY1 = <0x0>;
bur,KY2 = <0x0>;
};
};
};
&dcan0 {
status = "okay";
};
&dcan1 {
status = "okay";
};
&sham {
status = "disabled";
};
&aes {
status = "disabled";
};
&rng {
status = "disabled";
};

View File

@@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM)
* http://ultrazed.org/product/ultrazed-ev-carrier-card
*/
/dts-v1/;
#include "avnet-ultrazedev-som-v1.0.dtsi"
/ {
model = "Avnet UltraZed EV Carrier Card v1.0";
compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0",
"xlnx,zynqmp";
chosen {
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
aliases {
ethernet0 = &gem3;
serial0 = &uart0;
};
};
&uart0 {
device_type = "serial";
status = "okay";
};
&i2c_cc {
/* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
eeprom: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* IDT Versa Clock 5P49V5935B */
vc5: clock-generator@6a {
compatible = "idt,5p49v5935";
reg = <0x6a>;
#clock-cells = <1>;
};
};
/* Ethernet RJ-45 */
&gem3 {
status = "okay";
};
/* microSD card slot */
&sdhci1 {
status = "okay";
xlnx,mio_bank = <1>;
clock-frequency = <199998000>;
max-frequency = <50000000>;
no-1-8-v;
disable-wp;
};

View File

@@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* UltraZed-EV SoM v1
* http://ultrazed.org/product/ultrazed-ev
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "Avnet UltraZed EV SoM v1.0";
compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
<0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
};
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
i2cswitch@70 {
compatible = "nxp,pca9543";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
/* I2C connected to Carrier Card via JX3A1/JX3C1 */
i2c_cc: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
&gem3 {
phy-mode = "rgmii-id";
phy-handle = <&gem3phy>;
gem3phy: ethernet-phy@0 {
reg = <0>;
};
};
/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
&sdhci0 {
status = "okay";
xlnx,mio_bank = <0>;
clock-frequency = <199998000>;
};

View File

@@ -16,6 +16,10 @@
};
};
&eth0 {
pinctrl-0 = <&mii_pins>, <&mdio_pins>;
};
&flash {
compatible = "m25p64", "jedec,spi-nor";
};

View File

@@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* Copyright (c) 2019 Linaro Ltd.
*/
&dwmmc1 {
u-boot,dm-pre-reloc;
};

View File

@@ -0,0 +1,607 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Hisilicon HiKey960 Development Board
*
* Copyright (C) 2016, Hisilicon Ltd.
*
*/
/dts-v1/;
#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "HiKey960";
compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
aliases {
mshc1 = &dwmmc1;
mshc2 = &dwmmc2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
};
chosen {
stdout-path = "serial6:115200n8";
};
memory@0 {
device_type = "memory";
/* rewrite this at bootloader */
reg = <0x0 0x0 0x0 0x0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ramoops@32000000 {
compatible = "ramoops";
reg = <0x0 0x32000000 0x0 0x00100000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
};
};
reboot-mode-syscon@32100000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x32100000 0x0 0x00001000>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x0>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
};
};
keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
power {
wakeup-source;
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
};
leds {
compatible = "gpio-leds";
user_led1 {
label = "green:user1";
/* gpio_150_user_led1 */
gpios = <&gpio18 6 0>;
linux,default-trigger = "heartbeat";
};
user_led2 {
label = "green:user2";
/* gpio_151_user_led2 */
gpios = <&gpio18 7 0>;
linux,default-trigger = "none";
};
user_led3 {
label = "green:user3";
/* gpio_189_user_led3 */
gpios = <&gpio23 5 0>;
linux,default-trigger = "mmc0";
};
user_led4 {
label = "green:user4";
/* gpio_190_user_led4 */
gpios = <&gpio23 6 0>;
panic-indicator;
linux,default-trigger = "none";
};
wlan_active_led {
label = "yellow:wlan";
/* gpio_205_wifi_active */
gpios = <&gpio25 5 0>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
bt_active_led {
label = "blue:bt";
gpios = <&gpio25 7 0>;
/* gpio_207_user_led1 */
linux,default-trigger = "hci0-power";
default-state = "off";
};
};
pmic: pmic@fff34000 {
compatible = "hisilicon,hi6421v530-pmic";
reg = <0x0 0xfff34000 0x0 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
regulators {
ldo3: LDO3 { /* HDMI */
regulator-name = "VOUT3_1V85";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2200000>;
regulator-enable-ramp-delay = <120>;
};
ldo9: LDO9 { /* SDCARD I/O */
regulator-name = "VOUT9_1V8_2V95";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
ldo11: LDO11 { /* Low Speed Connector */
regulator-name = "VOUT11_1V8_2V95";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <240>;
};
ldo15: LDO15 { /* UFS VCC */
regulator-name = "VOUT15_3V0";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
regulator-enable-ramp-delay = <120>;
};
ldo16: LDO16 { /* SD VDD */
regulator-name = "VOUT16_2V95";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <360>;
};
};
};
wlan_en: wlan-en-1-8v {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* GPIO_051_WIFI_EN */
gpio = <&gpio6 3 0>;
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
/*
* Legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* "" = no idea, schematic doesn't say, could be
* unrouted (not connected to any external pin)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from "HiKey 960 Board ver A" schematics
* from Huawei. The 40 pin low speed expansion connector is named
* J2002 63453-140LF.
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Board naming of a line and the schematic name of
* the same line are in conflict, the 96Board specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART3. This is only for the informational lines i.e. "[FOO]",
* the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
* ones actually used for GPIO.
*/
&gpio0 {
/* GPIO_000-GPIO_007 */
gpio-line-names =
"",
"TP901", /* TEST_MODE connected to TP901 */
"[PMU0_SSI]",
"[PMU1_SSI]",
"[PMU2_SSI]",
"[PMU0_CLKOUT]",
"[JTAG_TCK]",
"[JTAG_TMS]";
};
&gpio1 {
/* GPIO_008-GPIO_015 */
gpio-line-names =
"[JTAG_TRST_N]",
"[JTAG_TDI]",
"[JTAG_TDO]",
"NC", "NC",
"[I2C3_SCL]",
"[I2C3_SDA]",
"NC";
};
&gpio2 {
/* GPIO_016-GPIO_023 */
gpio-line-names =
"NC", "NC", "NC",
"GPIO-J", /* LSEC pin 32: GPIO_019 */
"GPIO_020_HDMI_SEL",
"GPIO-L", /* LSEC pin 34: GPIO_021 */
"GPIO_022_UFSBUCK_INT_N",
"GPIO-G"; /* LSEC pin 29: LCD_TE0 */
};
&gpio3 {
/* GPIO_024-GPIO_031 */
/* The rail from pin BK36 is named LCD_TE0, we assume to be muxed as GPIO for GPIO-G */
gpio-line-names =
"[CSI0_MCLK]", /* HSEC pin 15: ISP_CCLK0_MCAM */
"[CSI1_MCLK]", /* HSEC pin 17: ISP_CCLK1_SCAM */
"NC",
"[I2C2_SCL]", /* HSEC pin 32: ISP_SCL0 */
"[I2C2_SDA]", /* HSEC pin 34: ISP_SDA0 */
"[I2C3_SCL]", /* HSEC pin 36: ISP_SCL1 */
"[I2C3_SDA]", /* HSEC pin 38: ISP_SDA1 */
"NC";
};
&gpio4 {
/* GPIO_032-GPIO_039 */
gpio-line-names =
"NC", "NC",
"PWR_BTN_N", /* LSEC pin 4: GPIO_034_PWRON_DET */
"GPIO_035_PMU2_EN",
"GPIO_036_USB_HUB_RESET",
"NC", "NC", "NC";
};
&gpio5 {
/* GPIO_040-GPIO_047 */
gpio-line-names =
"GPIO-H", /* LSEC pin 30: GPIO_040_LCD_RST_N */
"GPIO_041_HDMI_PD",
"TP904", /* Test point */
"TP905", /* Test point */
"NC", "NC",
"GPIO_046_HUB_VDD33_EN",
"GPIO_047_PMU1_EN";
};
&gpio6 {
/* GPIO_048-GPIO_055 */
gpio-line-names =
"NC", "NC", "NC",
"GPIO_051_WIFI_EN",
"GPIO-I", /* LSEC pin 31: GPIO_052_CAM0_RST_N */
/*
* These two pins should be used for SD(IO) data according to the
* 96boards specification but seems to be repurposed for a IRDA UART.
* They are however named according to the spec.
*/
"[SD_DAT1]", /* HSEC pin 3: UART0_IRDA_RXD */
"[SD_DAT2]", /* HSEC pin 5: UART0_IRDA_TXD */
"[UART1_RXD]"; /* LSEC pin 13: DEBUG_UART6_RXD */
};
&gpio7 {
/* GPIO_056-GPIO_063 */
gpio-line-names =
"[UART1_TXD]", /* LSEC pin 11: DEBUG_UART6_TXD */
"[UART0_CTS]", /* LSEC pin 3: UART3_CTS_N */
"[UART0_RTS]", /* LSEC pin 9: UART3_RTS_N */
"[UART0_RXD]", /* LSEC pin 7: UART3_RXD */
"[UART0_TXD]", /* LSEC pin 5: UART3_TXD */
"[SOC_BT_UART4_CTS_N]",
"[SOC_BT_UART4_RTS_N]",
"[SOC_BT_UART4_RXD]";
};
&gpio8 {
/* GPIO_064-GPIO_071 */
gpio-line-names =
"[SOC_BT_UART4_TXD]",
"NC",
"[PMU_HKADC_SSI]",
"NC",
"GPIO_068_SEL",
"NC", "NC", "NC";
};
&gpio9 {
/* GPIO_072-GPIO_079 */
gpio-line-names =
"NC", "NC", "NC",
"GPIO-K", /* LSEC pin 33: GPIO_075_CAM1_RST_N */
"NC", "NC", "NC", "NC";
};
&gpio10 {
/* GPIO_080-GPIO_087 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio11 {
/* GPIO_088-GPIO_095 */
gpio-line-names =
"NC",
"[PCIE_PERST_N]",
"NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio12 {
/* GPIO_096-GPIO_103 */
gpio-line-names = "NC", "NC", "NC", "", "", "", "", "NC";
};
&gpio13 {
/* GPIO_104-GPIO_111 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio14 {
/* GPIO_112-GPIO_119 */
gpio-line-names = "NC", "NC", "NC", "NC", "NC", "NC", "NC", "NC";
};
&gpio15 {
/* GPIO_120-GPIO_127 */
gpio-line-names =
"NC", "NC", "NC", "NC", "NC", "NC",
"GPIO_126_BT_EN",
"TP902"; /* GPIO_127_JTAG_SEL0 */
};
&gpio16 {
/* GPIO_128-GPIO_135 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio17 {
/* GPIO_136-GPIO_143 */
gpio-line-names = "", "", "", "", "", "", "", "";
};
&gpio18 {
/* GPIO_144-GPIO_151 */
gpio-line-names =
"[UFS_REF_CLK]",
"[UFS_RST_N]",
"[SPI1_SCLK]", /* HSEC pin 9: GPIO_146_SPI3_CLK */
"[SPI1_DIN]", /* HSEC pin 11: GPIO_147_SPI3_DI */
"[SPI1_DOUT]", /* HSEC pin 1: GPIO_148_SPI3_DO */
"[SPI1_CS]", /* HSEC pin 7: GPIO_149_SPI3_CS0_N */
"GPIO_150_USER_LED1",
"GPIO_151_USER_LED2";
};
&gpio19 {
/* GPIO_152-GPIO_159 */
gpio-line-names = "NC", "NC", "NC", "NC", "", "", "", "";
};
&gpio20 {
/* GPIO_160-GPIO_167 */
gpio-line-names =
"[SD_CLK]",
"[SD_CMD]",
"[SD_DATA0]",
"[SD_DATA1]",
"[SD_DATA2]",
"[SD_DATA3]",
"", "";
};
&gpio21 {
/* GPIO_168-GPIO_175 */
gpio-line-names =
"[WL_SDIO_CLK]",
"[WL_SDIO_CMD]",
"[WL_SDIO_DATA0]",
"[WL_SDIO_DATA1]",
"[WL_SDIO_DATA2]",
"[WL_SDIO_DATA3]",
"", "";
};
&gpio22 {
/* GPIO_176-GPIO_183 */
gpio-line-names =
"[GPIO_176_PMU_PWR_HOLD]",
"NA",
"[SYSCLK_EN]",
"GPIO_179_WL_WAKEUP_AP",
"GPIO_180_HDMI_INT",
"NA",
"GPIO-F", /* LSEC pin 28: LCD_BL_PWM */
"[I2C0_SCL]"; /* LSEC pin 15 */
};
&gpio23 {
/* GPIO_184-GPIO_191 */
gpio-line-names =
"[I2C0_SDA]", /* LSEC pin 17 */
"[I2C1_SCL]", /* Actual SoC I2C1 */
"[I2C1_SDA]", /* Actual SoC I2C1 */
"[I2C1_SCL]", /* LSEC pin 19: I2C7_SCL */
"[I2C1_SDA]", /* LSEC pin 21: I2C7_SDA */
"GPIO_189_USER_LED3",
"GPIO_190_USER_LED4",
"";
};
&gpio24 {
/* GPIO_192-GPIO_199 */
gpio-line-names =
"[PCM_DI]", /* LSEC pin 22: GPIO_192_I2S0_DI */
"[PCM_DO]", /* LSEC pin 20: GPIO_193_I2S0_DO */
"[PCM_CLK]", /* LSEC pin 18: GPIO_194_I2S0_XCLK */
"[PCM_FS]", /* LSEC pin 16: GPIO_195_I2S0_XFS */
"[GPIO_196_I2S2_DI]",
"[GPIO_197_I2S2_DO]",
"[GPIO_198_I2S2_XCLK]",
"[GPIO_199_I2S2_XFS]";
};
&gpio25 {
/* GPIO_200-GPIO_207 */
gpio-line-names =
"NC",
"NC",
"GPIO_202_VBUS_TYPEC",
"GPIO_203_SD_DET",
"GPIO_204_PMU12_IRQ_N",
"GPIO_205_WIFI_ACTIVE",
"GPIO_206_USBSW_SEL",
"GPIO_207_BT_ACTIVE";
};
&gpio26 {
/* GPIO_208-GPIO_215 */
gpio-line-names =
"GPIO-A", /* LSEC pin 23: GPIO_208 */
"GPIO-B", /* LSEC pin 24: GPIO_209 */
"GPIO-C", /* LSEC pin 25: GPIO_210 */
"GPIO-D", /* LSEC pin 26: GPIO_211 */
"GPIO-E", /* LSEC pin 27: GPIO_212 */
"[PCIE_CLKREQ_N]",
"[PCIE_WAKE_N]",
"[SPI0_CLK]"; /* LSEC pin 8: SPI2_CLK */
};
&gpio27 {
/* GPIO_216-GPIO_223 */
gpio-line-names =
"[SPI0_DIN]", /* LSEC pin 10: SPI2_DI */
"[SPI0_DOUT]", /* LSEC pin 14: SPI2_DO */
"[SPI0_CS]", /* LSEC pin 12: SPI2_CS0_N */
"GPIO_219_CC_INT",
"NC",
"NC",
"[PMU_INT]",
"";
};
&gpio28 {
/* GPIO_224-GPIO_231 */
gpio-line-names =
"", "", "", "", "", "", "", "";
};
&i2c0 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
&i2c1 {
status = "okay";
adv7533: adv7533@39 {
status = "ok";
compatible = "adi,adv7533";
reg = <0x39>;
};
};
&uart3 {
/* On Low speed expansion */
label = "LS-UART0";
status = "okay";
};
&uart4 {
status = "okay";
bluetooth {
compatible = "ti,wl1837-st";
enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
};
};
&i2c7 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
&uart6 {
/* On Low speed expansion */
label = "LS-UART1";
status = "okay";
};
&spi2 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
&spi3 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
&dwmmc1 {
cd-gpios = <&gpio25 3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sd_pmx_func
&sd_clk_cfg_func
&sd_cfg_func>;
vmmc-supply = <&ldo16>;
vqmmc-supply = <&ldo9>;
status = "okay";
};
&dwmmc2 { /* WIFI */
bus-width = <0x4>;
non-removable;
broken-cd;
cap-power-off-card;
pinctrl-names = "default";
pinctrl-0 = <&sdio_pmx_func
&sdio_clk_cfg_func
&sdio_cfg_func>;
/* WL_EN */
vmmc-supply = <&wlan_en>;
status = "ok";
wlcore: wlcore@2 {
compatible = "ti,wl1837";
reg = <2>; /* sdio func num */
/* WL_IRQ, GPIO_179_WL_WAKEUP_AP */
interrupt-parent = <&gpio22>;
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
};
};

1157
arch/arm/dts/hi3660.dtsi Normal file

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@@ -5,6 +5,9 @@
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/phy/phy-am654-serdes.h>
#include <dt-bindings/phy/phy.h>
&cbass_main {
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
@@ -143,4 +146,109 @@
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
scm_conf: scm_conf@100000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x00100000 0 0x1c000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
serdes_mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
<0x4090 0x3>; /* SERDES1 lane select */
};
pcie0_mode: pcie-mode@4060 {
compatible = "syscon";
reg = <0x00004060 0x4>;
};
pcie1_mode: pcie-mode@4070 {
compatible = "syscon";
reg = <0x00004070 0x4>;
};
serdes0_clk: serdes_clk@4080 {
compatible = "syscon";
reg = <0x00004080 0x4>;
};
serdes1_clk: serdes_clk@4090 {
compatible = "syscon";
reg = <0x00004090 0x4>;
};
pcie_devid: pcie-devid@210 {
compatible = "syscon";
reg = <0x00000210 0x4>;
};
};
serdes0: serdes@900000 {
compatible = "ti,phy-am654-serdes";
reg = <0x0 0x900000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
ti,serdes-clk = <&serdes0_clk>;
mux-controls = <&serdes_mux 0>;
#clock-cells = <1>;
};
serdes1: serdes@910000 {
compatible = "ti,phy-am654-serdes";
reg = <0x0 0x910000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
ti,serdes-clk = <&serdes1_clk>;
mux-controls = <&serdes_mux 1>;
#clock-cells = <1>;
};
pcie0_rc: pcie@5500000 {
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
ti,syscon-pcie-id = <&pcie_devid>;
ti,syscon-pcie-mode = <&pcie0_mode>;
bus-range = <0x0 0xff>;
status = "disabled";
device_type = "pci";
num-lanes = <1>;
num-ob-windows = <16>;
num-viewport = <16>;
max-link-speed = <3>;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
<0 0 0 2 &pcie0_intc 0>, /* INT B */
<0 0 0 3 &pcie0_intc 0>, /* INT C */
<0 0 0 4 &pcie0_intc 0>; /* INT D */
msi-map = <0x0 &gic_its 0x0 0x10000>;
pcie0_intc: legacy-interrupt-controller@1 {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
};
};
};

View File

@@ -69,6 +69,7 @@
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
/* MCUSS Range */
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,

View File

@@ -98,7 +98,7 @@
dma-coherent;
clocks = <&k3_clks 5 10>;
clock-names = "fck";
power-domains = <&k3_pds 5>;
power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
ti,psil-base = <0x7000>;
dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,

View File

@@ -22,6 +22,7 @@
serial@12000 {
status = "okay";
clock-frequency = <200000000>;
};
};

View File

@@ -0,0 +1,502 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre SAS. All rights reserved.
*/
/dts-v1/;
#include "meson-g12a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "seirobotics,sei510", "amlogic,g12a";
model = "SEI Robotics SEI510";
adc_keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
button-onoff {
label = "On/Off";
linux,code = <KEY_POWER>;
press-threshold-microvolt = <1700000>;
};
};
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
};
mono_dac: audio-codec-0 {
compatible = "maxim,max98357a";
#sound-dai-cells = <0>;
sound-name-prefix = "U16";
sdmode-gpios = <&gpio GPIOX_8 GPIO_ACTIVE_HIGH>;
};
dmics: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "dmic-codec";
num-channels = <2>;
wakeup-delay-ms = <50>;
status = "okay";
sound-name-prefix = "MIC";
};
chosen {
stdout-path = "serial0:115200n8";
};
cvbs-connector {
compatible = "composite-video-connector";
port {
cvbs_connector_in: endpoint {
remote-endpoint = <&cvbs_vdac_out>;
};
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
ao_5v: regulator-ao_5v {
compatible = "regulator-fixed";
regulator-name = "AO_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_in>;
regulator-always-on;
};
dc_in: regulator-dc_in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
emmc_1v8: regulator-emmc_1v8 {
compatible = "regulator-fixed";
regulator-name = "EMMC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_in>;
regulator-always-on;
};
vddao_3v3_t: regultor-vddao_3v3_t {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3_T";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
};
vddio_ao1v8: regulator-vddio_ao1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
reserved-memory {
/* TEE Reserved Memory */
bl32_reserved: bl32@5000000 {
reg = <0x0 0x05300000 0x0 0x2000000>;
no-map;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sound {
compatible = "amlogic,axg-sound-card";
model = "G12A-SEI510";
audio-aux-devs = <&tdmout_a>, <&tdmout_b>,
<&tdmin_a>, <&tdmin_b>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
"TDM_A Playback", "TDMOUT_A OUT",
"TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT",
"TODDR_A IN 4", "PDM Capture",
"TODDR_B IN 4", "PDM Capture",
"TODDR_C IN 4", "PDM Capture",
"TDMIN_A IN 0", "TDM_A Capture",
"TDMIN_A IN 3", "TDM_A Loopback",
"TDMIN_B IN 0", "TDM_A Capture",
"TDMIN_B IN 3", "TDM_A Loopback",
"TDMIN_A IN 1", "TDM_B Capture",
"TDMIN_A IN 4", "TDM_B Loopback",
"TDMIN_B IN 1", "TDM_B Capture",
"TDMIN_B IN 4", "TDM_B Loopback",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT",
"TODDR_A IN 1", "TDMIN_B OUT",
"TODDR_B IN 1", "TDMIN_B OUT",
"TODDR_C IN 1", "TDMIN_B OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
dai-link-3 {
sound-dai = <&toddr_a>;
};
dai-link-4 {
sound-dai = <&toddr_b>;
};
dai-link-5 {
sound-dai = <&toddr_c>;
};
/* internal speaker interface */
dai-link-6 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
mclk-fs = <256>;
codec-0 {
sound-dai = <&mono_dac>;
};
codec-1 {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>;
};
};
/* 8ch hdmi interface */
dai-link-7 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec@0 {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
/* internal digital mics */
dai-link-8 {
sound-dai = <&pdm>;
codec {
sound-dai = <&dmics>;
};
};
/* hdmi glue */
dai-link-9 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
};
};
&arb {
status = "okay";
};
&cec_AO {
pinctrl-0 = <&cec_ao_a_h_pins>;
pinctrl-names = "default";
status = "disabled";
hdmi-phandle = <&hdmi_tx>;
};
&cecb_AO {
pinctrl-0 = <&cec_ao_b_h_pins>;
pinctrl-names = "default";
status = "okay";
hdmi-phandle = <&hdmi_tx>;
};
&clkc_audio {
status = "okay";
};
&cvbs_vdac_port {
cvbs_vdac_out: endpoint {
remote-endpoint = <&cvbs_connector_in>;
};
};
&ethmac {
status = "okay";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
pinctrl-names = "default";
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
clocks = <&xtal>;
clock-names = "clkin0";
};
&pdm {
pinctrl-0 = <&pdm_din0_z_pins>, <&pdm_din1_z_pins>,
<&pdm_din2_z_pins>, <&pdm_din3_z_pins>,
<&pdm_dclk_z_pins>;
pinctrl-names = "default";
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao1v8>;
};
/* SDIO */
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr50;
max-frequency = <100000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_ao1v8>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddao_3v3>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&emmc_1v8>;
};
&tdmif_a {
pinctrl-0 = <&tdm_a_dout0_pins>, <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>;
pinctrl-names = "default";
status = "okay";
assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD0>,
<&clkc_audio AUD_CLKID_TDM_LRCLK_PAD0>;
assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_A_SCLK>,
<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
assigned-clock-rates = <0>, <0>;
};
&tdmif_b {
status = "okay";
};
&tdmin_a {
status = "okay";
};
&tdmin_b {
status = "okay";
};
&tdmout_a {
status = "okay";
};
&tdmout_b {
status = "okay";
};
&toddr_a {
status = "okay";
};
&toddr_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
&tohdmitx {
status = "okay";
};
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;
clock-names = "lpo";
vbat-supply = <&vddao_3v3>;
vddio-supply = <&vddio_ao1v8>;
};
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
dr_mode = "host";
};

View File

@@ -1,216 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/ {
soc {
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac", "snps,dwmac-3.710",
"snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000
0x0 0xff634540 0x0 0x8>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
status = "disabled";
mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
};
sd_emmc_a: sd@ffe03000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe03000 0x0 0x800>;
interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
};
sd_emmc_b: sd@ffe05000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
sd_emmc_c: mmc@ffe07000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe07000 0x0 0x800>;
interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
};
};
&periphs_pinctrl {
emmc_pins: emmc {
mux {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_clk",
"emmc_cmd";
function = "emmc";
bias-pull-up;
};
};
emmc_ds_pins: emmc-ds {
mux {
groups = "emmc_nand_ds";
function = "emmc";
bias-pull-down;
};
};
emmc_clk_gate_pins: emmc_clk_gate {
mux {
groups = "BOOT_8";
function = "gpio_periphs";
bias-pull-down;
};
};
eth_leds_pins: eth-leds {
mux {
groups = "eth_link_led",
"eth_act_led";
function = "eth";
bias-disable;
};
};
eth_rmii_pins: eth-rmii {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_rgmii_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_txen",
"eth_txd0",
"eth_txd1";
function = "eth";
bias-disable;
};
};
eth_rgmii_pins: eth-rgmii {
mux {
groups = "eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
bias-disable;
};
};
sdcard_c_pins: sdcard_c {
mux {
groups = "sdcard_d0_c",
"sdcard_d1_c",
"sdcard_d2_c",
"sdcard_d3_c",
"sdcard_cmd_c",
"sdcard_clk_c";
function = "sdcard";
bias-pull-up;
};
};
sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
mux {
groups = "GPIOC_4";
function = "gpio_periphs";
bias-pull-down;
};
};
sdcard_z_pins: sdcard_z {
mux {
groups = "sdcard_d0_z",
"sdcard_d1_z",
"sdcard_d2_z",
"sdcard_d3_z",
"sdcard_cmd_z",
"sdcard_clk_z";
function = "sdcard";
bias-pull-up;
};
};
sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
mux {
groups = "GPIOZ_6";
function = "gpio_periphs";
bias-pull-down;
};
};
};
&periphs {
eth_phy: mdio-multiplexer@4c000 {
compatible = "amlogic,g12a-mdio-mux";
reg = <0x0 0x4c000 0x0 0xa4>;
clocks = <&clkc CLKID_ETH_PHY>,
<&xtal>,
<&clkc CLKID_MPLL_5OM>;
clock-names = "pclk", "clkin0", "clkin1";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
ext_mdio: mdio@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
int_mdio: mdio@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
internal_ephy: ethernet_phy@8 {
compatible = "ethernet-phy-id0180.3300",
"ethernet-phy-ieee802.3-c22";
reg = <8>;
max-speed = <100>;
/* FIXME: Add irq support */
};
};
};
};

View File

@@ -1,63 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-g12a-u-boot.dtsi"
/ {
aliases {
ethernet0 = &ethmac;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
};
&ethmac {
status = "okay";
pinctrl-0 = <&eth_leds_pins>;
pinctrl-names = "default";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddao_3v3>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&flash_1v8>;
};

View File

@@ -15,14 +15,12 @@
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
cvbs-connector {
compatible = "composite-video-connector";
@@ -34,13 +32,9 @@
};
};
flash_1v8: regulator-flash_1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
@@ -54,6 +48,20 @@
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
flash_1v8: regulator-flash_1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
@@ -62,6 +70,17 @@
regulator-always-on;
};
usb_pwr_en: regulator-usb_pwr_en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
@@ -92,17 +111,6 @@
enable-active-high;
};
usb_pwr_en: regulator-usb_pwr_en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
@@ -143,6 +151,12 @@
};
};
&ethmac {
status = "okay";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
@@ -156,6 +170,70 @@
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
/* i2c Touch */
&i2c0 {
status = "okay";
pinctrl-0 = <&i2c0_sda_z0_pins>, <&i2c0_sck_z1_pins>;
pinctrl-names = "default";
};
/* i2c CM */
&i2c2 {
status = "okay";
pinctrl-0 = <&i2c2_sda_z_pins>, <&i2c2_sck_z_pins>;
pinctrl-names = "default";
};
/* i2c Audio */
&i2c3 {
status = "okay";
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
pinctrl-names = "default";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddao_3v3>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&flash_1v8>;
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,386 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
/dts-v1/;
#include "meson-g12b.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/meson-g12a-gpio.h>
#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
/ {
compatible = "hardkernel,odroid-n2", "amlogic,g12b";
model = "Hardkernel ODROID-N2";
aliases {
serial0 = &uart_AO;
ethernet0 = &ethmac;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
};
leds {
compatible = "gpio-leds";
blue {
label = "n2:blue";
gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
tflash_vdd: regulator-tflash_vdd {
compatible = "regulator-fixed";
regulator-name = "TFLASH_VDD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
tf_io: gpio-regulator-tf_io {
compatible = "regulator-gpio";
regulator-name = "TF_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <3300000 0
1800000 1>;
};
flash_1v8: regulator-flash_1v8 {
compatible = "regulator-fixed";
regulator-name = "FLASH_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&main_12v>;
};
vcc_1v8: regulator-vcc_1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
/* FIXME: actually controlled by VDDCPU_B_EN */
};
hub_5v: regulator-hub_5v {
compatible = "regulator-fixed";
regulator-name = "HUB_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
/* Connected to the Hub CHIPENABLE, LOW sets low power state */
gpio = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_pwr_en: regulator-usb_pwr_en {
compatible = "regulator-fixed";
regulator-name = "USB_PWR_EN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc_5v>;
/* Connected to the microUSB port power enable */
gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddao_1v8: regulator-vddao_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_12v>;
regulator-always-on;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
sound {
compatible = "amlogic,axg-sound-card";
model = "G12A-ODROIDN2";
audio-aux-devs = <&tdmout_b>;
audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
"TDMOUT_B IN 1", "FRDDR_B OUT 1",
"TDMOUT_B IN 2", "FRDDR_C OUT 1",
"TDM_B Playback", "TDMOUT_B OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
status = "okay";
dai-link-0 {
sound-dai = <&frddr_a>;
};
dai-link-1 {
sound-dai = <&frddr_b>;
};
dai-link-2 {
sound-dai = <&frddr_c>;
};
/* 8ch hdmi interface */
dai-link-3 {
sound-dai = <&tdmif_b>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
dai-tdm-slot-tx-mask-1 = <1 1>;
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-tx-mask-3 = <1 1>;
mclk-fs = <256>;
codec {
sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
};
};
/* hdmi glue */
dai-link-4 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
sound-dai = <&hdmi_tx>;
};
};
};
};
&arb {
status = "okay";
};
&cec_AO {
pinctrl-0 = <&cec_ao_a_h_pins>;
pinctrl-names = "default";
status = "disabled";
hdmi-phandle = <&hdmi_tx>;
};
&cecb_AO {
pinctrl-0 = <&cec_ao_b_h_pins>;
pinctrl-names = "default";
status = "okay";
hdmi-phandle = <&hdmi_tx>;
};
&clkc_audio {
status = "okay";
};
&ext_mdio {
external_phy: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
max-speed = <1000>;
reset-assert-us = <10000>;
reset-deassert-us = <30000>;
reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
interrupt-parent = <&gpio_intc>;
/* MAC_INTR on GPIOZ_14 */
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
};
};
&ethmac {
pinctrl-0 = <&eth_pins>, <&eth_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
phy-mode = "rgmii";
phy-handle = <&external_phy>;
amlogic,tx-delay-ns = <2>;
};
&frddr_a {
status = "okay";
};
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
};
&gpio {
/*
* WARNING: The USB Hub on the Odroid-N2 needs a reset signal
* to be turned high in order to be detected by the USB Controller
* This signal should be handled by a USB specific power sequence
* in order to reset the Hub when USB bus is powered down.
*/
usb-hub {
gpio-hog;
gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb-hub-reset";
};
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
pinctrl-names = "default";
hdmi-supply = <&vcc_5v>;
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&ir {
status = "okay";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
/* SD card */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_c_pins>;
pinctrl-1 = <&sdcard_clk_gate_c_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&tf_io>;
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&flash_1v8>;
};
&tdmif_b {
status = "okay";
};
&tdmout_b {
status = "okay";
};
&tohdmitx {
status = "okay";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
vbus-supply = <&usb_pwr_en>;
};
&usb2_phy0 {
phy-supply = <&vcc_5v>;
};
&usb2_phy1 {
/* Enable the hub which is connected to this port */
phy-supply = <&hub_5v>;
};

View File

@@ -0,0 +1,82 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#include "meson-g12a.dtsi"
/ {
compatible = "amlogic,g12b";
cpus {
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
cluster1 {
core0 {
cpu = <&cpu100>;
};
core1 {
cpu = <&cpu101>;
};
core2 {
cpu = <&cpu102>;
};
core3 {
cpu = <&cpu103>;
};
};
};
/delete-node/ cpu@2;
/delete-node/ cpu@3;
cpu100: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu101: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu102: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu103: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a73";
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&l2>;
};
};
};
&clkc {
compatible = "amlogic,g12b-clkc";
};

View File

@@ -248,6 +248,13 @@
status = "disabled";
};
hifsys: syscon@1a000000 {
compatible = "mediatek,mt7623-hifsys", "syscon";
reg = <0x1a000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7623-ethsys", "syscon";
reg = <0x1b000000 0x1000>;

View File

@@ -13,7 +13,7 @@
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
spi0 = &qspi;
spi0 = &snfi;
};
chosen {
@@ -33,7 +33,14 @@
};
&pinctrl {
qspi_pins: qspi-pins {
snfi_pins: snfi-pins {
mux {
function = "flash";
groups = "snfi";
};
};
snor_pins: snor-pins {
mux {
function = "flash";
groups = "spi_nor";
@@ -55,9 +62,10 @@
};
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&qspi_pins>;
&snfi {
pinctrl-names = "default", "snfi";
pinctrl-0 = <&snor_pins>;
pinctrl-1 = <&snfi_pins>;
status = "okay";
spi-flash@0{

View File

@@ -215,10 +215,16 @@
status = "disabled";
};
qspi: qspi@11014000 {
compatible = "mediatek,mt7629-qspi";
reg = <0x11014000 0xe0>, <0x30000000 0x10000000>;
reg-names = "reg_base", "mem_base";
snfi: snfi@1100d000 {
compatible = "mediatek,mtk-snfi-spi";
reg = <0x1100d000 0x2000>;
clocks = <&pericfg CLK_PERI_NFI_PD>,
<&pericfg CLK_PERI_SNFI_PD>;
clock-names = "nfi_clk", "pad_clk";
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
<&topckgen CLK_TOP_NFI_INFRA_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
<&topckgen CLK_TOP_UNIVPLL2_D8>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

View File

@@ -462,6 +462,76 @@
reg = <0 0xe6060000 0 0x50c>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a7795-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a7795-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a7795-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a7795-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -1836,7 +1906,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,

View File

@@ -68,6 +68,7 @@
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;

View File

@@ -1775,7 +1775,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@@ -2162,17 +2162,6 @@
dma-names = "rx", "tx";
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
};
audma0: dma-controller@ec700000 {

View File

@@ -317,6 +317,76 @@
reg = <0 0xe6060000 0 0x50c>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a77965-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a77965-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a77965-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a77965-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77965-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -1461,7 +1531,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
@@ -1585,56 +1655,267 @@
};
};
rcar_sound,ssiu {
ssiu00: ssiu-0 {
dmas = <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx";
};
ssiu01: ssiu-1 {
dmas = <&audma0 0x35>, <&audma1 0x36>;
dma-names = "rx", "tx";
};
ssiu02: ssiu-2 {
dmas = <&audma0 0x37>, <&audma1 0x38>;
dma-names = "rx", "tx";
};
ssiu03: ssiu-3 {
dmas = <&audma0 0x47>, <&audma1 0x48>;
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
dmas = <&audma0 0x3F>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dmas = <&audma0 0x43>, <&audma1 0x44>;
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
dmas = <&audma0 0x4F>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dmas = <&audma0 0x53>, <&audma1 0x54>;
dma-names = "rx", "tx";
};
ssiu10: ssiu-8 {
dmas = <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
dmas = <&audma0 0x4B>, <&audma1 0x4C>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dmas = <&audma0 0x57>, <&audma1 0x58>;
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
dmas = <&audma0 0x59>, <&audma1 0x5A>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
dmas = <&audma0 0x5F>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
dmas = <&audma0 0xC3>, <&audma1 0xC4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
dmas = <&audma0 0xC7>, <&audma1 0xC8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
dmas = <&audma0 0xCB>, <&audma1 0xCC>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dmas = <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx";
};
ssiu21: ssiu-17 {
dmas = <&audma0 0x67>, <&audma1 0x68>;
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
dmas = <&audma0 0x6B>, <&audma1 0x6C>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
dmas = <&audma0 0x6D>, <&audma1 0x6E>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
dmas = <&audma0 0xCF>, <&audma1 0xCE>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
dmas = <&audma0 0xEB>, <&audma1 0xEC>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
dmas = <&audma0 0xED>, <&audma1 0xEE>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
dmas = <&audma0 0xEF>, <&audma1 0xF0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dmas = <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx";
};
ssiu31: ssiu-25 {
dmas = <&audma0 0x21>, <&audma1 0x22>;
dma-names = "rx", "tx";
};
ssiu32: ssiu-26 {
dmas = <&audma0 0x23>, <&audma1 0x24>;
dma-names = "rx", "tx";
};
ssiu33: ssiu-27 {
dmas = <&audma0 0x25>, <&audma1 0x26>;
dma-names = "rx", "tx";
};
ssiu34: ssiu-28 {
dmas = <&audma0 0x27>, <&audma1 0x28>;
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
dmas = <&audma0 0x29>, <&audma1 0x2A>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
dmas = <&audma0 0x2B>, <&audma1 0x2C>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
dmas = <&audma0 0x2D>, <&audma1 0x2E>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
dmas = <&audma0 0x17>, <&audma1 0x18>;
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
dmas = <&audma0 0x19>, <&audma1 0x1A>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
dmas = <&audma0 0x1B>, <&audma1 0x1C>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
dmas = <&audma0 0x1D>, <&audma1 0x1E>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
dmas = <&audma0 0x1F>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dmas = <&audma0 0x31>, <&audma1 0x32>;
dma-names = "rx", "tx";
};
ssiu47: ssiu-39 {
dmas = <&audma0 0x33>, <&audma1 0x34>;
dma-names = "rx", "tx";
};
ssiu50: ssiu-40 {
dmas = <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx";
};
ssiu60: ssiu-41 {
dmas = <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx";
};
ssiu70: ssiu-42 {
dmas = <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx";
};
ssiu80: ssiu-43 {
dmas = <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx";
};
ssiu90: ssiu-44 {
dmas = <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
dmas = <&audma0 0x7F>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dmas = <&audma0 0x81>, <&audma1 0x82>;
dma-names = "rx", "tx";
};
ssiu93: ssiu-47 {
dmas = <&audma0 0x83>, <&audma1 0x84>;
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
dmas = <&audma0 0xA3>, <&audma1 0xA4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
dmas = <&audma0 0xA5>, <&audma1 0xA6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
dmas = <&audma0 0xA7>, <&audma1 0xA8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
dmas = <&audma0 0xA9>, <&audma1 0xAA>;
dma-names = "rx", "tx";
};
};
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x01>, <&audma1 0x02>;
dma-names = "rx", "tx";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x03>, <&audma1 0x04>;
dma-names = "rx", "tx";
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x05>, <&audma1 0x06>;
dma-names = "rx", "tx";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x07>, <&audma1 0x08>;
dma-names = "rx", "tx";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x09>, <&audma1 0x0a>;
dma-names = "rx", "tx";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x0b>, <&audma1 0x0c>;
dma-names = "rx", "tx";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x0d>, <&audma1 0x0e>;
dma-names = "rx", "tx";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x0f>, <&audma1 0x10>;
dma-names = "rx", "tx";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x11>, <&audma1 0x12>;
dma-names = "rx", "tx";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x13>, <&audma1 0x14>;
dma-names = "rx", "tx";
};
};
};
@@ -2166,7 +2447,6 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77965";
reg = <0 0xfeb00000 0 0x80000>;
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;

View File

@@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Condor board
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r8a77980-condor.dts"
#include "r8a77980-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&rpc {
num-cs = <1>;
status = "okay";
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "s25fs512s", "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
reg = <0>;
status = "okay";
};
};

View File

@@ -0,0 +1,292 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor board
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77980.dtsi"
/ {
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
aliases {
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
d1_8v: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander0: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
io_expander1: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1_8v>;
dvdd-supply = <&d1_8v>;
pvdd-supply = <&d1_8v>;
bgvdd-supply = <&d1_8v>;
dvdd-3v-supply = <&d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
};
&pciec {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pcie_phy {
status = "okay";
};
&pfc {
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <3300>;
};
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};

View File

@@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on RCar R8A77980 SoC
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
u-boot,dm-pre-reloc;
};
/ {
soc {
rpc: rpc@0xee200000 {
compatible = "renesas,rpc-r8a77980", "renesas,rpc";
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
clocks = <&cpg CPG_MOD 917>;
bank-width = <2>;
status = "disabled";
};
};
};

1605
arch/arm/dts/r8a77980.dtsi Normal file

File diff suppressed because it is too large Load Diff

View File

@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the ebisu board
*
@@ -19,7 +19,7 @@
};
chosen {
bootargs = "ignore_loglevel";
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -337,6 +337,15 @@
&i2c0 {
status = "okay";
io_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
@@ -398,7 +407,7 @@
};
port@a {
reg = <0xa>;
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
@@ -440,6 +449,28 @@
};
};
&i2c_dvfs {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0x1>;
rohm,rstbmode-level;
};
};
&lvds0 {
status = "okay";
@@ -458,6 +489,13 @@
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
@@ -495,6 +533,11 @@
function = "du";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
@@ -650,6 +693,10 @@
status = "okay";
};
&vin5 {
status = "okay";
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";

View File

@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 */
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car E3 (R8A77990) SoC
*
@@ -284,6 +284,76 @@
status = "disabled";
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a77990-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a77990-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a77990-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a77990-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
@@ -1656,7 +1726,7 @@
};
csi40: csi2@feaa0000 {
compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
compatible = "renesas,r8a77990-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;

View File

@@ -20,7 +20,7 @@
};
chosen {
bootargs = "ignore_loglevel";
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -168,7 +168,6 @@
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
@@ -179,6 +178,18 @@
};
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
@@ -356,6 +367,13 @@
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x12_clk>,
<&extal_clk>;
@@ -375,6 +393,16 @@
};
};
can0_pins: can0 {
groups = "can0_data_a";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data_a";
function = "can1";
};
du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du";

View File

@@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
*/
#include "rk3328-sdram-ddr3-666.dtsi"
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};

View File

@@ -4,6 +4,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include "rk3328-sdram-lpddr3-1600.dtsi"
/ {
aliases {
mmc0 = &emmc;
@@ -25,10 +27,8 @@
&emmc {
u-boot,dm-pre-reloc;
fifo-mode;
};
&sdmmc {
u-boot,dm-pre-reloc;
fifo-mode;
};

View File

@@ -0,0 +1,215 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
&dmc {
rockchip,sdram-params = <
0x1
0xC
0x3
0x1
0x0
0x0
0x10
0x10
0
0x9028b189
0x00000000
0x00000021
0x00000482
0x00000015
0x00000222
0x000000ff
333
3
0
0x00000000
0x43041001
0x00000064
0x0028003b
0x000000d0
0x00020053
0x000000d4
0x00020000
0x000000d8
0x00000100
0x000000dc
0x03200000
0x000000e0
0x00000000
0x000000e4
0x00090000
0x000000f4
0x000f011f
0x00000100
0x07090b06
0x00000104
0x00050209
0x00000108
0x03030407
0x0000010c
0x00202006
0x00000110
0x03020204
0x00000114
0x03030202
0x00000120
0x00000903
0x00000180
0x00800020
0x00000184
0x00000000
0x00000190
0x07010001
0x00000198
0x05001100
0x000001a0
0xc0400003
0x00000240
0x06000604
0x00000244
0x00000201
0x00000250
0x00000f00
0x00000490
0x00000001
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000a
0x00000028
0x00000006
0x0000002c
0x00000000
0x00000030
0x00000005
0xffffffff
0xffffffff
0x77
0x88
0x79
0x79
0x87
0x97
0x87
0x78
0x77
0x78
0x87
0x88
0x87
0x87
0x77
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
>;
};

View File

@@ -0,0 +1,215 @@
/*
* (C) 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
&dmc {
rockchip,sdram-params = <
0x1
0xC
0x3
0x1
0x0
0x0
0x10
0x10
0
0x98899459
0x00000000
0x0000002e
0x00000544
0x00000015
0x00000432
0x000000ff
800
6
1
0x00000000
0x43041008
0x00000064
0x00300054
0x000000d0
0x00500002
0x000000d4
0x00010000
0x000000d8
0x00000e03
0x000000dc
0x0043001a
0x000000e0
0x00010000
0x000000e4
0x000e0005
0x000000f4
0x000f011f
0x00000100
0x0b141b11
0x00000104
0x0003031a
0x00000108
0x03060809
0x0000010c
0x00606000
0x00000110
0x08020409
0x00000114
0x01010606
0x00000118
0x02020004
0x00000120
0x00000404
0x00000138
0x00000058
0x00000180
0x00900024
0x00000184
0x01400000
0x00000190
0x07050002
0x00000198
0x05001100
0x000001a0
0xc0400003
0x00000240
0x0a020b28
0x00000244
0x00000101
0x00000250
0x00000f00
0x00000490
0x00000001
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000b
0x00000028
0x0000000c
0x0000002c
0x00000000
0x00000030
0x00000006
0xffffffff
0xffffffff
0x77
0x88
0x79
0x79
0x87
0x97
0x87
0x78
0x77
0x78
0x87
0x88
0x87
0x87
0x77
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
>;
};

View File

@@ -0,0 +1,215 @@
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
&dmc {
rockchip,sdram-params = <
0x1
0xC
0x3
0x1
0x0
0x0
0x10
0x10
0
0x0c48a18a
0x00000000
0x00000021
0x00000482
0x00000015
0x0000021a
0x000000ff
333
6
0
0x00000000
0xc3040008
0x00000064
0x00140023
0x000000d0
0x00220002
0x000000d4
0x00010000
0x000000d8
0x00000703
0x000000dc
0x00830004
0x000000e0
0x00010000
0x000000e4
0x00070003
0x00000100
0x06090b07
0x00000104
0x0002020b
0x00000108
0x02030506
0x0000010c
0x00505000
0x00000110
0x03020204
0x00000114
0x01010303
0x00000118
0x02020003
0x00000120
0x00000303
0x00000138
0x00000025
0x00000180
0x003c000f
0x00000184
0x00900000
0x00000190
0x07020000
0x00000198
0x05001100
0x000001a0
0xc0400003
0x00000240
0x0900090c
0x00000244
0x00000101
0x00000250
0x00000f00
0x00000490
0x00000001
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0xffffffff
0x00000004
0x0000000b
0x00000028
0x00000006
0x0000002c
0x00000000
0x00000030
0x00000003
0xffffffff
0xffffffff
0x77
0x88
0x79
0x79
0x87
0x97
0x87
0x78
0x77
0x78
0x87
0x88
0x87
0x87
0x77
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x78
0x77
0x79
0x9
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x78
0x69
0x9
0x77
0x78
0x77
0x77
0x77
0x77
0x77
0x77
0x77
0x79
0x9
>;
};

View File

@@ -351,10 +351,15 @@
status = "disabled";
};
dmc: dmc@ff400000 {
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-dmc", "syscon";
reg = <0x0 0xff400000 0x0 0x1000>;
compatible = "rockchip,rk3328-dmc";
reg = <0x0 0xff400000 0x0 0x1000
0x0 0xff780000 0x0 0x3000
0x0 0xff100000 0x0 0x1000
0x0 0xff440000 0x0 0x1000
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
cru: clock-controller@ff440000 {

View File

@@ -3,4 +3,11 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-ddr3-1600.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
};

View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Nick Xie <nick@khadas.com>
*/
#include "rk3399-khadas-edge-u-boot.dtsi"

View File

@@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
* (https://www.khadas.com)
*/
/dts-v1/;
#include "rk3399-khadas-edge.dtsi"
/ {
model = "Khadas Edge-Captain";
compatible = "khadas,edge-captain", "rockchip,rk3399";
};
&gmac {
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
status = "okay";
};

View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Nick Xie <nick@khadas.com>
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};

View File

@@ -0,0 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Nick Xie <nick@khadas.com>
*/
#include "rk3399-khadas-edge-u-boot.dtsi"

View File

@@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
* (https://www.khadas.com)
*/
/dts-v1/;
#include "rk3399-khadas-edge.dtsi"
/ {
model = "Khadas Edge-V";
compatible = "khadas,edge-v", "rockchip,rk3399";
};
&gmac {
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
status = "okay";
};

View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
* (https://www.khadas.com)
*/
/dts-v1/;
#include "rk3399-khadas-edge.dtsi"
/ {
model = "Khadas Edge";
compatible = "khadas,edge", "rockchip,rk3399";
};

View File

@@ -0,0 +1,804 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd.
* (https://www.khadas.com)
*/
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
chosen {
stdout-path = "serial2:1500000n8";
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_pcie: vcc3v3-pcie-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vsys_5v0>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
vin-supply = <&vsys_3v3>;
};
vsys: vsys {
compatible = "regulator-fixed";
regulator-name = "vsys";
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: vsys-3v3 {
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys>;
};
vsys_5v0: vsys-5v0 {
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vsys>;
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
recovery {
label = "Recovery";
linux,code = <KEY_VENDOR>;
press-threshold-microvolt = <18000>;
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Key Power";
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&sys_led_gpio>, <&user_led_gpio>;
sys-led {
label = "sys_led";
linux,default-trigger = "heartbeat";
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
};
user-led {
label = "user_led";
default-state = "off";
gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <0 150 200 255>;
#cooling-cells = <2>;
fan-supply = <&vsys_5v0>;
pwms = <&pwm0 0 40000 0>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_thermal {
trips {
cpu_warm: cpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map2 {
trip = <&cpu_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map3 {
trip = <&cpu_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
};
&gpu_thermal {
trips {
gpu_warm: gpu_warm {
temperature = <55000>;
hysteresis = <2000>;
type = "active";
};
gpu_hot: gpu_hot {
temperature = <65000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&gpu_warm>;
cooling-device = <&fan THERMAL_NO_LIMIT 1>;
};
map2 {
trip = <&gpu_hot>;
cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
};
};
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&hdmi_sound {
status = "okay";
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vsys_3v3>;
vcc2-supply = <&vsys_3v3>;
vcc3-supply = <&vsys_3v3>;
vcc4-supply = <&vsys_3v3>;
vcc6-supply = <&vsys_3v3>;
vcc7-supply = <&vsys_3v3>;
vcc8-supply = <&vsys_3v3>;
vcc9-supply = <&vsys_3v3>;
vcc10-supply = <&vsys_3v3>;
vcc11-supply = <&vsys_3v3>;
vcc12-supply = <&vsys_3v3>;
vddio-supply = <&vcc_1v8>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc1v8_apio2: LDO_REG1 {
regulator-name = "vcc1v8_apio2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_vldo2: LDO_REG2 {
regulator-name = "vcc_vldo2";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmupll: LDO_REG3 {
regulator-name = "vcc1v8_pmupll";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG4 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc_vldo5: LDO_REG5 {
regulator-name = "vcc_vldo5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcc1v8_codec: LDO_REG7 {
regulator-name = "vcc1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&cpu_b_sleep>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vsys_3v3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&gpu_sleep>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vsys_3v3>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c8 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <160>;
i2c-scl-falling-time-ns = <30>;
status = "okay";
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
bt656-supply = <&vcc1v8_apio2>;
audio-supply = <&vcc1v8_codec>;
sdmmc-supply = <&vccio_sd>;
gpio1830-supply = <&vcc_3v0>;
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_1v8>;
status = "okay";
};
&pinctrl {
bt {
bt_host_wake_l: bt-host-wake-l {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_reg_on_h: bt-reg-on-h {
rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_l: bt-wake-l {
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
pwrbtn: pwrbtn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
sys_led_gpio: sys_led-gpio {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
user_led_gpio: user_led-gpio {
rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
};
cpu_b_sleep: cpu-b-sleep {
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
gpu_sleep: gpu-sleep {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_host_wake_l: wifi-host-wake-l {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdio0 {
/* WiFi & BT combo module Ampak AP6356S */
bus-width = <4>;
cap-sdio-irq;
cap-sd-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
sd-uhs-sdr104;
vqmmc-supply = <&vcc1v8_s3>;
vmmc-supply = <&vccio_sd>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rk808 1>;
clock-names = "lpo";
device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
max-speed = <4000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>;
vbat-supply = <&vsys_3v3>;
vddio-supply = <&vcc_1v8>;
};
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
dr_mode = "otg";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

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@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Levin Du <djw@t-chip.com.cn>
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc;
};
};
&vdd_log {
regulator-min-microvolt = <430000>;
regulator-init-microvolt = <950000>;
};

View File

@@ -0,0 +1,680 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Firefly ROC-RK3399-PC Board";
compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399";
chosen {
stdout-path = "serial2:1500000n8";
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm0 0 25000 0>;
};
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
vcc_vbus_typec0: vcc-vbus-typec0 {
compatible = "regulator-fixed";
regulator-name = "vcc_vbus_typec0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
/*
* should be placed inside mp8859, but not until mp8859 has
* its own dt-binding.
*/
vcc12v_sys: mp8859-dcdc1 {
compatible = "regulator-fixed";
regulator-name = "vcc12v_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
vin-supply = <&vcc_vbus_typec0>;
};
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc12v_sys>;
};
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en &hub_rst>;
regulator-name = "vcc5v0_host";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_vbus_typec1: vcc-vbus-typec1 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc_vbus_typec1_en>;
regulator-name = "vcc_vbus_typec1";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_sys>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
regulator-name = "vdd_log";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
vin-supply = <&vcc3v3_sys>;
};
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l1 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l2 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
&cpu_b1 {
cpu-supply = <&vdd_cpu_b>;
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&hdmi {
ddc-i2c-bus = <&i2c3>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>;
i2c-scl-falling-time-ns = <4>;
status = "okay";
rk808: pmic@1b {
compatible = "rockchip,rk808";
reg = <0x1b>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc3v3_sys>;
vcc2-supply = <&vcc3v3_sys>;
vcc3-supply = <&vcc3v3_sys>;
vcc4-supply = <&vcc3v3_sys>;
vcc6-supply = <&vcc3v3_sys>;
vcc7-supply = <&vcc3v3_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc3v3_sys>;
vcc10-supply = <&vcc3v3_sys>;
vcc11-supply = <&vcc3v3_sys>;
vcc12-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc1v8_pmu>;
regulators {
vdd_center: DCDC_REG1 {
regulator-name = "vdd_center";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_l: DCDC_REG2 {
regulator-name = "vdd_cpu_l";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_1v8: DCDC_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca1v8_codec: LDO_REG1 {
regulator-name = "vcca1v8_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_hdmi: LDO_REG2 {
regulator-name = "vcc1v8_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG3 {
regulator-name = "vcc1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcca3v0_codec: LDO_REG5 {
regulator-name = "vcca3v0_codec";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v5: LDO_REG6 {
regulator-name = "vcc_1v5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1500000>;
};
};
vcca0v9_hdmi: LDO_REG7 {
regulator-name = "vcca0v9_hdmi";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_3v0: LDO_REG8 {
regulator-name = "vcc_3v0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3000000>;
};
};
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
regulator-name = "vcc3v3_s3";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_s0: SWITCH_REG2 {
regulator-name = "vcc3v3_s0";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
vdd_cpu_b: regulator@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel1_gpio>;
regulator-name = "vdd_cpu_b";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: regulator@41 {
compatible = "silergy,syr828";
reg = <0x41>;
fcs,suspend-voltage-selector = <1>;
pinctrl-names = "default";
pinctrl-0 = <&vsel2_gpio>;
regulator-name = "vdd_gpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
fusb1: usb-typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb1_int>;
vbus-supply = <&vcc_vbus_typec1>;
status = "okay";
};
};
&i2c7 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
fusb0: usb-typec@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
vbus-supply = <&vcc_vbus_typec0>;
status = "okay";
};
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
status = "okay";
};
&i2s1 {
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
status = "okay";
};
&i2s2 {
status = "okay";
};
&io_domains {
audio-supply = <&vcca1v8_codec>;
bt656-supply = <&vcc_3v0>;
gpio1830-supply = <&vcc_3v0>;
sdmmc-supply = <&vcc_sdio>;
status = "okay";
};
&pmu_io_domains {
pmu1830-supply = <&vcc_3v0>;
status = "okay";
};
&pinctrl {
lcd-panel {
lcd_panel_reset: lcd-panel-reset {
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pmic {
vsel1_gpio: vsel1-gpio {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
vsel2_gpio: vsel2-gpio {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
hub_rst: hub-rst {
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>;
};
};
usb-typec {
vcc_vbus_typec1_en: vcc-vbus-typec1-en {
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
fusb1_int: fusb1-int {
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm0 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&saradc {
vref-supply = <&vcca1v8_s3>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
status = "okay";
};
&sdhci {
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
&tcphy0 {
status = "okay";
};
&tcphy1 {
status = "okay";
};
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;
/* tshut polarity 0:LOW 1:HIGH */
rockchip,hw-tshut-polarity = <1>;
status = "okay";
};
&u2phy0 {
status = "okay";
u2phy0_otg: otg-port {
phy-supply = <&vcc_vbus_typec0>;
status = "okay";
};
u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&u2phy1 {
status = "okay";
u2phy1_otg: otg-port {
phy-supply = <&vcc_vbus_typec1>;
status = "okay";
};
u2phy1_host: host-port {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
status = "okay";
};
&usbdrd3_1 {
status = "okay";
};
&usbdrd_dwc3_1 {
status = "okay";
dr_mode = "host";
};
&vopb {
status = "okay";
};
&vopb_mmu {
status = "okay";
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};

View File

@@ -3,4 +3,11 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr3-2GB-1600.dtsi"
/ {
chosen {
u-boot,spl-boot-order = &sdhci, &sdmmc;
};
};

View File

@@ -29,6 +29,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
@@ -86,6 +87,63 @@
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&keys_pins>;
pinctrl-names = "default";
key-1 {
gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW4-1";
wakeup-source;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW4-2";
wakeup-source;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW4-3";
wakeup-source;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW4-4";
wakeup-source;
debounce-interval = <20>;
};
key-a {
gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
linux,code = <KEY_A>;
label = "TSW0";
wakeup-source;
debounce-interval = <20>;
};
key-b {
gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_B>;
label = "TSW1";
wakeup-source;
debounce-interval = <20>;
};
key-c {
gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_C>;
label = "TSW2";
wakeup-source;
debounce-interval = <20>;
};
};
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -572,6 +630,11 @@
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_5_17", "GP_5_20", "GP_5_22";
bias-pull-up;
};
pwm1_pins: pwm1 {
groups = "pwm1_a";
function = "pwm1";
@@ -719,6 +782,11 @@
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
@@ -857,11 +925,6 @@
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";

View File

@@ -1,5 +1,5 @@
/*
* Copyright 2016 Toradex AG
* Copyright 2016-2019 Toradex AG
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -230,19 +230,21 @@
};
/* Apalis GPIO */
ddc_scl_pv4 {
nvidia,pins = "ddc_scl_pv4";
usb_vbus_en0_pn4 {
nvidia,pins = "usb_vbus_en0_pn4";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ddc_sda_pv5 {
nvidia,pins = "ddc_sda_pv5";
usb_vbus_en1_pn5 {
nvidia,pins = "usb_vbus_en1_pn5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
pex_l0_rst_n_pdd1 {
nvidia,pins = "pex_l0_rst_n_pdd1";
@@ -333,24 +335,6 @@
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
/* Apalis I2C2 (DDC) */
gen2_i2c_scl_pt5 {
nvidia,pins = "gen2_i2c_scl_pt5";
nvidia,function = "i2c2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
gen2_i2c_sda_pt6 {
nvidia,pins = "gen2_i2c_sda_pt6";
nvidia,function = "i2c2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
/* Apalis I2C3 (CAM) */
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1";
@@ -369,6 +353,24 @@
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
};
/* Apalis I2C4 (DDC) */
ddc_scl_pv4 {
nvidia,pins = "ddc_scl_pv4";
nvidia,function = "i2c4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
};
ddc_sda_pv5 {
nvidia,pins = "ddc_sda_pv5";
nvidia,function = "i2c4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
};
/* Apalis MMC1 */
sdmmc1_cd_n_pv3 { /* CD# GPIO */
nvidia,pins = "sdmmc1_wp_n_pv3";
@@ -470,12 +472,12 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
/* PWM3 active on pu6 being Apalis BKL1_PWM */
/* PWM3 active on pu6 being Apalis BKL1_PWM as well */
ph3 {
nvidia,pins = "ph3";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,function = "pwm3";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
@@ -736,8 +738,8 @@
};
/* Apalis USBH_EN */
usb_vbus_en1_pn5 {
nvidia,pins = "usb_vbus_en1_pn5";
gen2_i2c_sda_pt6 {
nvidia,pins = "gen2_i2c_sda_pt6";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -755,8 +757,8 @@
};
/* Apalis USBO1_EN */
usb_vbus_en0_pn4 {
nvidia,pins = "usb_vbus_en0_pn4";
gen2_i2c_scl_pt5 {
nvidia,pins = "gen2_i2c_scl_pt5";
nvidia,function = "rsvd2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
@@ -1501,10 +1503,14 @@
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pv0 { /* NC */
/*
* PCB Version Indication: V1.2 and later have GPIO_PV0
* wired to GND, was NC before
*/
pv0 {
nvidia,pins = "pv0";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
@@ -1630,13 +1636,7 @@
};
};
/*
* GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
*/
hdmi_ddc: i2c@7000c400 {
status = "okay";
clock-frequency = <10000>;
};
/* GEN2_I2C: unused */
/*
* CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
@@ -1647,7 +1647,14 @@
clock-frequency = <400000>;
};
/* I2C4 (DDC): unused */
/*
* I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207
* (e.g. display EDID)
*/
hdmi_ddc: i2c@7000c700 {
status = "okay";
clock-frequency = <10000>;
};
/* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
i2c@7000d000 {
@@ -2112,7 +2119,7 @@
regulator-name = "VCC_USBO1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_5v0>;
};
@@ -2123,7 +2130,7 @@
regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_5v0>;
};

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZC1275
* dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
*
@@ -14,8 +14,9 @@
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevA";
compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
model = "ZynqMP ZCU1275 RevA";
compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
"xlnx,zynqmp";
aliases {
serial0 = &uart0;

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP ZC1275 RevB
* dts file for Xilinx ZynqMP ZCU1275 RevB
*
* (C) Copyright 2018, Xilinx, Inc.
*
@@ -14,8 +14,9 @@
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevB";
compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
model = "ZynqMP ZCU1275 RevB";
compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
"xlnx,zynqmp";
aliases {
serial0 = &uart0;

View File

@@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2019 Linaro
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
#ifndef __HI3660_H__
#define __HI3660_H__
#define HI3660_UART6_BASE 0xfff32000
#define PMU_REG_BASE 0xfff34000
#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2))
#define SCTRL_REG_BASE 0xfff0a000
#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120)
#define SCTRL_SCFPLLCTRL0_FPLL0_EN BIT(0)
#define CRG_REG_BASE 0xfff35000
#define CRG_PEREN2 (CRG_REG_BASE + 0x020)
#define CRG_PERDIS2 (CRG_REG_BASE + 0x024)
#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028)
#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C)
#define CRG_PEREN4 (CRG_REG_BASE + 0x040)
#define CRG_PERDIS4 (CRG_REG_BASE + 0x044)
#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048)
#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C)
#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078)
#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C)
#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080)
#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084)
#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088)
#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C)
#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090)
#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094)
#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098)
#define CRG_ISOEN (CRG_REG_BASE + 0x144)
#define CRG_ISODIS (CRG_REG_BASE + 0x148)
#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C)
#define PINMUX4_BASE 0xfff11000
#define PINMUX4_SDDET (PINMUX4_BASE + 0x60)
#define PINCONF3_BASE 0xff37e800
#define PINCONF3_SDCLK (PINCONF3_BASE + 0x00)
#define PINCONF3_SDCMD (PINCONF3_BASE + 0x04)
#define PINCONF3_SDDATA0 (PINCONF3_BASE + 0x08)
#define PINCONF3_SDDATA1 (PINCONF3_BASE + 0x0c)
#define PINCONF3_SDDATA2 (PINCONF3_BASE + 0x10)
#define PINCONF3_SDDATA3 (PINCONF3_BASE + 0x14)
#endif /*__HI3660_H__*/

View File

@@ -12,4 +12,22 @@ ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
int meson_sm_get_serial(void *buffer, size_t size);
enum {
REBOOT_REASON_COLD = 0,
REBOOT_REASON_NORMAL = 1,
REBOOT_REASON_RECOVERY = 2,
REBOOT_REASON_UPDATE = 3,
REBOOT_REASON_FASTBOOT = 4,
REBOOT_REASON_SUSPEND_OFF = 5,
REBOOT_REASON_HIBERNATE = 6,
REBOOT_REASON_BOOTLOADER = 7,
REBOOT_REASON_SHUTDOWN_REBOOT = 8,
REBOOT_REASON_RPMBP = 9,
REBOOT_REASON_CRASH_DUMP = 11,
REBOOT_REASON_KERNEL_PANIC = 12,
REBOOT_REASON_WATCHDOG_REBOOT = 13,
};
int meson_sm_get_reboot_reason(void);
#endif /* __MESON_SM_H__ */

View File

@@ -0,0 +1,441 @@
/*
* Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SDRAM_RK3328_H
#define _ASM_ARCH_SDRAM_RK3328_H
#define SR_IDLE 93
#define PD_IDLE 13
#define SDRAM_ADDR 0x00000000
#define PATTERN (0x5aa5f00f)
/* ddr pctl registers define */
#define DDR_PCTL2_MSTR 0x0
#define DDR_PCTL2_STAT 0x4
#define DDR_PCTL2_MSTR1 0x8
#define DDR_PCTL2_MRCTRL0 0x10
#define DDR_PCTL2_MRCTRL1 0x14
#define DDR_PCTL2_MRSTAT 0x18
#define DDR_PCTL2_MRCTRL2 0x1c
#define DDR_PCTL2_DERATEEN 0x20
#define DDR_PCTL2_DERATEINT 0x24
#define DDR_PCTL2_PWRCTL 0x30
#define DDR_PCTL2_PWRTMG 0x34
#define DDR_PCTL2_HWLPCTL 0x38
#define DDR_PCTL2_RFSHCTL0 0x50
#define DDR_PCTL2_RFSHCTL1 0x54
#define DDR_PCTL2_RFSHCTL2 0x58
#define DDR_PCTL2_RFSHCTL4 0x5c
#define DDR_PCTL2_RFSHCTL3 0x60
#define DDR_PCTL2_RFSHTMG 0x64
#define DDR_PCTL2_RFSHTMG1 0x68
#define DDR_PCTL2_RFSHCTL5 0x6c
#define DDR_PCTL2_INIT0 0xd0
#define DDR_PCTL2_INIT1 0xd4
#define DDR_PCTL2_INIT2 0xd8
#define DDR_PCTL2_INIT3 0xdc
#define DDR_PCTL2_INIT4 0xe0
#define DDR_PCTL2_INIT5 0xe4
#define DDR_PCTL2_INIT6 0xe8
#define DDR_PCTL2_INIT7 0xec
#define DDR_PCTL2_DIMMCTL 0xf0
#define DDR_PCTL2_RANKCTL 0xf4
#define DDR_PCTL2_CHCTL 0xfc
#define DDR_PCTL2_DRAMTMG0 0x100
#define DDR_PCTL2_DRAMTMG1 0x104
#define DDR_PCTL2_DRAMTMG2 0x108
#define DDR_PCTL2_DRAMTMG3 0x10c
#define DDR_PCTL2_DRAMTMG4 0x110
#define DDR_PCTL2_DRAMTMG5 0x114
#define DDR_PCTL2_DRAMTMG6 0x118
#define DDR_PCTL2_DRAMTMG7 0x11c
#define DDR_PCTL2_DRAMTMG8 0x120
#define DDR_PCTL2_DRAMTMG9 0x124
#define DDR_PCTL2_DRAMTMG10 0x128
#define DDR_PCTL2_DRAMTMG11 0x12c
#define DDR_PCTL2_DRAMTMG12 0x130
#define DDR_PCTL2_DRAMTMG13 0x134
#define DDR_PCTL2_DRAMTMG14 0x138
#define DDR_PCTL2_DRAMTMG15 0x13c
#define DDR_PCTL2_DRAMTMG16 0x140
#define DDR_PCTL2_ZQCTL0 0x180
#define DDR_PCTL2_ZQCTL1 0x184
#define DDR_PCTL2_ZQCTL2 0x188
#define DDR_PCTL2_ZQSTAT 0x18c
#define DDR_PCTL2_DFITMG0 0x190
#define DDR_PCTL2_DFITMG1 0x194
#define DDR_PCTL2_DFILPCFG0 0x198
#define DDR_PCTL2_DFILPCFG1 0x19c
#define DDR_PCTL2_DFIUPD0 0x1a0
#define DDR_PCTL2_DFIUPD1 0x1a4
#define DDR_PCTL2_DFIUPD2 0x1a8
#define DDR_PCTL2_DFIMISC 0x1b0
#define DDR_PCTL2_DFITMG2 0x1b4
#define DDR_PCTL2_DFITMG3 0x1b8
#define DDR_PCTL2_DFISTAT 0x1bc
#define DDR_PCTL2_DBICTL 0x1c0
#define DDR_PCTL2_ADDRMAP0 0x200
#define DDR_PCTL2_ADDRMAP1 0x204
#define DDR_PCTL2_ADDRMAP2 0x208
#define DDR_PCTL2_ADDRMAP3 0x20c
#define DDR_PCTL2_ADDRMAP4 0x210
#define DDR_PCTL2_ADDRMAP5 0x214
#define DDR_PCTL2_ADDRMAP6 0x218
#define DDR_PCTL2_ADDRMAP7 0x21c
#define DDR_PCTL2_ADDRMAP8 0x220
#define DDR_PCTL2_ADDRMAP9 0x224
#define DDR_PCTL2_ADDRMAP10 0x228
#define DDR_PCTL2_ADDRMAP11 0x22c
#define DDR_PCTL2_ODTCFG 0x240
#define DDR_PCTL2_ODTMAP 0x244
#define DDR_PCTL2_SCHED 0x250
#define DDR_PCTL2_SCHED1 0x254
#define DDR_PCTL2_PERFHPR1 0x25c
#define DDR_PCTL2_PERFLPR1 0x264
#define DDR_PCTL2_PERFWR1 0x26c
#define DDR_PCTL2_DQMAP0 0x280
#define DDR_PCTL2_DQMAP1 0x284
#define DDR_PCTL2_DQMAP2 0x288
#define DDR_PCTL2_DQMAP3 0x28c
#define DDR_PCTL2_DQMAP4 0x290
#define DDR_PCTL2_DQMAP5 0x294
#define DDR_PCTL2_DBG0 0x300
#define DDR_PCTL2_DBG1 0x304
#define DDR_PCTL2_DBGCAM 0x308
#define DDR_PCTL2_DBGCMD 0x30c
#define DDR_PCTL2_DBGSTAT 0x310
#define DDR_PCTL2_SWCTL 0x320
#define DDR_PCTL2_SWSTAT 0x324
#define DDR_PCTL2_POISONCFG 0x36c
#define DDR_PCTL2_POISONSTAT 0x370
#define DDR_PCTL2_ADVECCINDEX 0x374
#define DDR_PCTL2_ADVECCSTAT 0x378
#define DDR_PCTL2_PSTAT 0x3fc
#define DDR_PCTL2_PCCFG 0x400
#define DDR_PCTL2_PCFGR_n 0x404
#define DDR_PCTL2_PCFGW_n 0x408
#define DDR_PCTL2_PCTRL_n 0x490
/* PCTL2_MRSTAT */
#define MR_WR_BUSY BIT(0)
/* PHY_REG0 */
#define DIGITAL_DERESET BIT(3)
#define ANALOG_DERESET BIT(2)
#define DIGITAL_RESET (0 << 3)
#define ANALOG_RESET (0 << 2)
/* PHY_REG1 */
#define PHY_DDR2 (0)
#define PHY_LPDDR2 (1)
#define PHY_DDR3 (2)
#define PHY_LPDDR3 (3)
#define PHY_DDR4 (4)
#define PHY_BL_4 (0 << 2)
#define PHY_BL_8 BIT(2)
/* PHY_REG2 */
#define PHY_DTT_EN BIT(0)
#define PHY_DTT_DISB (0 << 0)
#define PHY_WRITE_LEVELING_EN BIT(2)
#define PHY_WRITE_LEVELING_DISB (0 << 2)
#define PHY_SELECT_CS0 (2)
#define PHY_SELECT_CS1 (1)
#define PHY_SELECT_CS0_1 (0)
#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6)
#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4)
#define PHY_DDR3_RON_RTT_DISABLE (0)
#define PHY_DDR3_RON_RTT_451ohm (1)
#define PHY_DDR3_RON_RTT_225ohm (2)
#define PHY_DDR3_RON_RTT_150ohm (3)
#define PHY_DDR3_RON_RTT_112ohm (4)
#define PHY_DDR3_RON_RTT_90ohm (5)
#define PHY_DDR3_RON_RTT_75ohm (6)
#define PHY_DDR3_RON_RTT_64ohm (7)
#define PHY_DDR3_RON_RTT_56ohm (16)
#define PHY_DDR3_RON_RTT_50ohm (17)
#define PHY_DDR3_RON_RTT_45ohm (18)
#define PHY_DDR3_RON_RTT_41ohm (19)
#define PHY_DDR3_RON_RTT_37ohm (20)
#define PHY_DDR3_RON_RTT_34ohm (21)
#define PHY_DDR3_RON_RTT_33ohm (22)
#define PHY_DDR3_RON_RTT_30ohm (23)
#define PHY_DDR3_RON_RTT_28ohm (24)
#define PHY_DDR3_RON_RTT_26ohm (25)
#define PHY_DDR3_RON_RTT_25ohm (26)
#define PHY_DDR3_RON_RTT_23ohm (27)
#define PHY_DDR3_RON_RTT_22ohm (28)
#define PHY_DDR3_RON_RTT_21ohm (29)
#define PHY_DDR3_RON_RTT_20ohm (30)
#define PHY_DDR3_RON_RTT_19ohm (31)
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
/* noc registers define */
#define DDRCONF 0x8
#define DDRTIMING 0xc
#define DDRMODE 0x10
#define READLATENCY 0x14
#define AGING0 0x18
#define AGING1 0x1c
#define AGING2 0x20
#define AGING3 0x24
#define AGING4 0x28
#define AGING5 0x2c
#define ACTIVATE 0x38
#define DEVTODEV 0x3c
#define DDR4TIMING 0x40
/* DDR GRF */
#define DDR_GRF_CON(n) (0 + (n) * 4)
#define DDR_GRF_STATUS_BASE (0X100)
#define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
/* CRU_SOFTRESET_CON5 */
#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15))
#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14))
#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13))
#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12))
#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11))
#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9))
#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8))
#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7))
/* CRU_SOFTRESET_CON9 */
#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9))
/* CRU register */
#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
#define CRU_MODE (0x80)
#define CRU_GLB_CNT_TH (0x90)
#define CRU_CLKSEL_CON_BASE 0x100
#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON_BASE + ((i) * 4))
#define CRU_CLKGATE_CON_BASE 0x200
#define CRU_CLKGATE_CON(i) (CRU_CLKGATE_CON_BASE + ((i) * 4))
#define CRU_CLKSFTRST_CON_BASE 0x300
#define CRU_CLKSFTRST_CON(i) (CRU_CLKSFTRST_CON_BASE + ((i) * 4))
/* CRU_PLL_CON0 */
#define PB(n) ((0x1 << (15 + 16)) | ((n) << 15))
#define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12))
#define FBDIV(n) ((0xFFF << 16) | (n))
/* CRU_PLL_CON1 */
#define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15))
#define RST(n) ((0x1 << (14 + 16)) | ((n) << 14))
#define PD(n) ((0x1 << (13 + 16)) | ((n) << 13))
#define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12))
#define LOCK(n) (((n) >> 10) & 0x1)
#define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
#define REFDIV(n) ((0x3F << 16) | (n))
union noc_ddrtiming {
u32 d32;
struct {
unsigned acttoact:6;
unsigned rdtomiss:6;
unsigned wrtomiss:6;
unsigned burstlen:3;
unsigned rdtowr:5;
unsigned wrtord:5;
unsigned bwratio:1;
} b;
} NOC_TIMING_T;
union noc_activate {
u32 d32;
struct {
unsigned rrd:4;
unsigned faw:6;
unsigned fawbank:1;
unsigned reserved1:21;
} b;
};
union noc_devtodev {
u32 d32;
struct {
unsigned busrdtord:2;
unsigned busrdtowr:2;
unsigned buswrtord:2;
unsigned reserved2:26;
} b;
};
union noc_ddr4timing {
u32 d32;
struct {
unsigned ccdl:3;
unsigned wrtordl:5;
unsigned rrdl:4;
unsigned reserved2:20;
} b;
};
union noc_ddrmode {
u32 d32;
struct {
unsigned autoprecharge:1;
unsigned bwratioextended:1;
unsigned reserved3:30;
} b;
};
u32 addrmap[21][9] = {
/* map0 map1 map2 map3 map4 map5 map6 map7 map8 */
{22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
0x06060606, 0x00000f0f, 0x3f3f},
{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
0x07070707, 0x00000f0f, 0x3f3f},
{23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
0x0f080808, 0x00000f0f, 0x3f3f},
{24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
0x08080808, 0x00000f0f, 0x3f3f},
{24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
0x0f090909, 0x00000f0f, 0x3f3f},
{6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707,
0x07070707, 0x00000f0f, 0x3f3f},
{7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808,
0x08080808, 0x00000f0f, 0x3f3f},
{8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909,
0x0f090909, 0x00000f0f, 0x3f3f},
{22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
0x06060606, 0x00000f0f, 0x3f3f},
{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
0x0f070707, 0x00000f0f, 0x3f3f},
{24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
0x08080808, 0x00000f0f, 0x0801},
{23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
0x0f080808, 0x00000f0f, 0x0801},
{24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
0x07070707, 0x00000f07, 0x0700},
{23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
0x07070707, 0x00000f0f, 0x0700},
{24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
0x07070707, 0x00000f07, 0x3f01},
{23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
0x07070707, 0x00000f0f, 0x3f01},
{24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
0x06060606, 0x00000f06, 0x3f00},
{8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909,
0x0f090909, 0x00000f0f, 0x0801},
{7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808,
0x08080808, 0x00000f0f, 0x0700},
{7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
0x08080808, 0x00000f0f, 0x3f01},
{6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
0x07070707, 0x00000f07, 0x3f00}
};
struct rk3328_msch_timings {
union noc_ddrtiming ddrtiming;
union noc_ddrmode ddrmode;
u32 readlatency;
union noc_activate activate;
union noc_devtodev devtodev;
union noc_ddr4timing ddr4timing;
u32 agingx0;
};
struct rk3328_msch_regs {
u32 coreid;
u32 revisionid;
u32 ddrconf;
u32 ddrtiming;
u32 ddrmode;
u32 readlatency;
u32 aging0;
u32 aging1;
u32 aging2;
u32 aging3;
u32 aging4;
u32 aging5;
u32 reserved[2];
u32 activate;
u32 devtodev;
u32 ddr4_timing;
};
struct rk3328_ddr_grf_regs {
u32 ddr_grf_con[4];
u32 reserved[(0x100 - 0x10) / 4];
u32 ddr_grf_status[11];
};
struct rk3328_ddr_pctl_regs {
u32 pctl[30][2];
};
struct rk3328_ddr_phy_regs {
u32 phy[5][2];
};
struct rk3328_ddr_skew {
u32 a0_a1_skew[15];
u32 cs0_dm0_skew[11];
u32 cs0_dm1_skew[11];
u32 cs0_dm2_skew[11];
u32 cs0_dm3_skew[11];
u32 cs1_dm0_skew[11];
u32 cs1_dm1_skew[11];
u32 cs1_dm2_skew[11];
u32 cs1_dm3_skew[11];
};
struct rk3328_sdram_channel {
unsigned int rank;
unsigned int col;
/* 3:8bank, 2:4bank */
unsigned int bk;
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int bw;
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned int dbw;
unsigned int row_3_4;
unsigned int cs0_row;
unsigned int cs1_row;
unsigned int ddrconfig;
struct rk3328_msch_timings noc_timings;
};
struct rk3328_sdram_params {
struct rk3328_sdram_channel ch;
unsigned int ddr_freq;
unsigned int dramtype;
unsigned int odt;
struct rk3328_ddr_pctl_regs pctl_regs;
struct rk3328_ddr_phy_regs phy_regs;
struct rk3328_ddr_skew skew;
};
#define PHY_REG(base, n) (base + 4 * (n))
#endif

View File

@@ -56,4 +56,9 @@ struct wd_timer {
unsigned int wdt_unfr; /* offset 0x100 */
};
struct omap3_wdt_priv {
struct wd_timer *regs;
unsigned int wdt_trgr_pattern;
};
#endif /* __OMAP_WDT_H__ */

View File

@@ -15,6 +15,7 @@
#include <command.h>
#include <dm.h>
#include <dm/root.h>
#include <env.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>

View File

@@ -23,11 +23,7 @@
/* max ticks timeout */
#define BCM2835_WDOG_MAX_TIMEOUT 0x000fffff
#ifdef CONFIG_BCM2835_WDT
extern void hw_watchdog_disable(void);
#else
void hw_watchdog_disable(void) {}
#endif
__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;

View File

@@ -9,7 +9,7 @@
*/
#include <common.h>
#include <environment.h>
#include <env.h>
#include <i2c.h>
#include <net.h>
#include <asm/arch/hardware.h>

View File

@@ -7,7 +7,6 @@
#include <common.h>
#include <command.h>
#include <environment.h>
#include <malloc.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>

View File

@@ -13,7 +13,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <environment.h>
#include <env.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -127,7 +127,7 @@ int board_late_init(void)
/* In bootstrap don't use the env vars */
if (((reg & 0x3000000) >> 24) == 0x1) {
set_default_env(NULL, 0);
env_set_default(NULL, 0);
env_set("preboot", "");
}

View File

@@ -14,6 +14,7 @@
#include <asm/arch/imx-rdc.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
#include <fsl_sec.h>
#include <asm/setup.h>

View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <env.h>
#include <linux/errno.h>
#include <asm/mach-imx/video.h>

View File

@@ -251,10 +251,21 @@ void k3_sysfw_loader(void (*config_pm_done_callback)(void))
if (config_pm_done_callback)
config_pm_done_callback();
/* Output System Firmware version info */
printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%.*s')\n",
/*
* Output System Firmware version info. Note that since the
* 'firmware_description' field is not guaranteed to be zero-
* terminated we manually add a \0 terminator if needed. Further
* note that we intentionally no longer rely on the extended
* printf() formatter '%.*s' to not having to require a more
* full-featured printf() implementation.
*/
char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
strncpy(fw_desc, ti_sci->version.firmware_description,
sizeof(ti_sci->version.firmware_description));
fw_desc[sizeof(fw_desc) - 1] = '\0';
printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
ti_sci->version.abi_major, ti_sci->version.abi_minor,
ti_sci->version.firmware_revision,
sizeof(ti_sci->version.firmware_description),
ti_sci->version.firmware_description);
ti_sci->version.firmware_revision, fw_desc);
}

View File

@@ -6,6 +6,7 @@
*/
#include <common.h>
#include <env.h>
#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>

View File

@@ -5,15 +5,20 @@
#include <common.h>
#include <asm/arch/boot.h>
#include <env.h>
#include <linux/libfdt.h>
#include <linux/err.h>
#include <environment.h>
#include <asm/arch/mem.h>
#include <asm/arch/sm.h>
#include <asm/armv8/mmu.h>
#include <asm/unaligned.h>
#include <efi_loader.h>
#if CONFIG_IS_ENABLED(FASTBOOT)
#include <asm/psci.h>
#include <fastboot.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
__weak int board_init(void)
@@ -142,7 +147,35 @@ int board_late_init(void)
return meson_board_late_init();
}
#if CONFIG_IS_ENABLED(FASTBOOT)
static unsigned int reboot_reason = REBOOT_REASON_NORMAL;
int fastboot_set_reboot_flag()
{
reboot_reason = REBOOT_REASON_BOOTLOADER;
printf("Using reboot reason: 0x%x\n", reboot_reason);
return 0;
}
void reset_cpu(ulong addr)
{
struct pt_regs regs;
regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
regs.regs[1] = reboot_reason;
printf("Rebooting with reason: 0x%lx\n", regs.regs[1]);
smc_call(&regs);
while (1)
;
}
#else
void reset_cpu(ulong addr)
{
psci_system_reset();
}
#endif

View File

@@ -62,21 +62,21 @@ void meson_init_reserved_memory(void *fdt)
phys_size_t get_effective_memsize(void)
{
/* Size is reported in MiB, convert it in bytes */
return ((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M;
return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
>> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
}
static struct mm_region g12a_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.size = 0xf5000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xf0000000UL,
.phys = 0xf0000000UL,
.size = 0x10000000UL,
.virt = 0xf5000000UL,
.phys = 0xf5000000UL,
.size = 0x0b000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -129,6 +129,7 @@ void meson_eth_init(phy_interface_t mode, unsigned int flags)
G12A_ETH_REG_0_TX_RATIO(4) |
G12A_ETH_REG_0_PHY_CLK_EN |
G12A_ETH_REG_0_CLK_EN);
g12a_enable_external_mdio();
break;
case PHY_INTERFACE_MODE_RMII:

View File

@@ -8,6 +8,10 @@
#include <common.h>
#include <asm/arch/sm.h>
#include <linux/kernel.h>
#include <dm.h>
#include <linux/bitfield.h>
#include <regmap.h>
#include <syscon.h>
#define FN_GET_SHARE_MEM_INPUT_BASE 0x82000020
#define FN_GET_SHARE_MEM_OUTPUT_BASE 0x82000021
@@ -77,3 +81,132 @@ int meson_sm_get_serial(void *buffer, size_t size)
return 0;
}
#define AO_SEC_SD_CFG15 0xfc
#define REBOOT_REASON_MASK GENMASK(15, 12)
int meson_sm_get_reboot_reason(void)
{
struct regmap *regmap;
int nodeoffset;
ofnode node;
unsigned int reason;
/* find the offset of compatible node */
nodeoffset = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"amlogic,meson-gx-ao-secure");
if (nodeoffset < 0) {
printf("%s: failed to get amlogic,meson-gx-ao-secure\n",
__func__);
return -ENODEV;
}
/* get regmap from the syscon node */
node = offset_to_ofnode(nodeoffset);
regmap = syscon_node_to_regmap(node);
if (IS_ERR(regmap)) {
printf("%s: failed to get regmap\n", __func__);
return -EINVAL;
}
regmap_read(regmap, AO_SEC_SD_CFG15, &reason);
/* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */
return FIELD_GET(REBOOT_REASON_MASK, reason);
}
static int do_sm_serial(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
ulong address;
int ret;
if (argc < 2)
return CMD_RET_USAGE;
address = simple_strtoul(argv[1], NULL, 0);
ret = meson_sm_get_serial((void *)address, SM_CHIP_ID_SIZE);
if (ret)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
#define MAX_REBOOT_REASONS 14
static const char *reboot_reasons[MAX_REBOOT_REASONS] = {
[REBOOT_REASON_COLD] = "cold_boot",
[REBOOT_REASON_NORMAL] = "normal",
[REBOOT_REASON_RECOVERY] = "recovery",
[REBOOT_REASON_UPDATE] = "update",
[REBOOT_REASON_FASTBOOT] = "fastboot",
[REBOOT_REASON_SUSPEND_OFF] = "suspend_off",
[REBOOT_REASON_HIBERNATE] = "hibernate",
[REBOOT_REASON_BOOTLOADER] = "bootloader",
[REBOOT_REASON_SHUTDOWN_REBOOT] = "shutdown_reboot",
[REBOOT_REASON_RPMBP] = "rpmbp",
[REBOOT_REASON_CRASH_DUMP] = "crash_dump",
[REBOOT_REASON_KERNEL_PANIC] = "kernel_panic",
[REBOOT_REASON_WATCHDOG_REBOOT] = "watchdog_reboot",
};
static int do_sm_reboot_reason(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
const char *reason_str;
char *destarg = NULL;
int reason;
if (argc > 1)
destarg = argv[1];
reason = meson_sm_get_reboot_reason();
if (reason < 0)
return CMD_RET_FAILURE;
if (reason >= MAX_REBOOT_REASONS ||
!reboot_reasons[reason])
reason_str = "unknown";
else
reason_str = reboot_reasons[reason];
if (destarg)
env_set(destarg, reason_str);
else
printf("reboot reason: %s (%x)\n", reason_str, reason);
return CMD_RET_SUCCESS;
}
static cmd_tbl_t cmd_sm_sub[] = {
U_BOOT_CMD_MKENT(serial, 2, 1, do_sm_serial, "", ""),
U_BOOT_CMD_MKENT(reboot_reason, 1, 1, do_sm_reboot_reason, "", ""),
};
static int do_sm(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
cmd_tbl_t *c;
if (argc < 2)
return CMD_RET_USAGE;
/* Strip off leading 'sm' command argument */
argc--;
argv++;
c = find_cmd_tbl(argv[0], &cmd_sm_sub[0], ARRAY_SIZE(cmd_sm_sub));
if (c)
return c->cmd(cmdtp, flag, argc, argv);
else
return CMD_RET_USAGE;
}
U_BOOT_CMD(
sm, 5, 0, do_sm,
"Secure Monitor Control",
"serial <address> - read chip unique id to memory address\n"
"sm reboot_reason [name] - get reboot reason and store to to environment"
);

View File

@@ -176,6 +176,7 @@ source "arch/arm/mach-omap2/omap5/Kconfig"
source "arch/arm/mach-omap2/am33xx/Kconfig"
source "board/BuR/brxre1/Kconfig"
source "board/BuR/brsmarc1/Kconfig"
source "board/BuR/brppt1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"

View File

@@ -121,6 +121,10 @@ config TARGET_BRXRE1
bool "Support BRXRE1"
select BOARD_LATE_INIT
config TARGET_BRSMARC1
bool "Support BRSMARC1"
select BOARD_LATE_INIT
config TARGET_BRPPT1
bool "Support BRPPT1"
select BOARD_LATE_INIT

View File

@@ -9,7 +9,6 @@
#include <common.h>
#include <ahci.h>
#include <environment.h>
#include <spl.h>
#include <asm/omap_common.h>
#include <asm/arch/omap.h>
@@ -208,7 +207,7 @@ void spl_board_init(void)
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
#if defined(CONFIG_HW_WATCHDOG)
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
hw_watchdog_init();
#endif
#ifdef CONFIG_AM33XX

View File

@@ -17,7 +17,6 @@
#include <asm/arch/clocks_omap3.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <environment.h>
#include <command.h>
/******************************************************************************

View File

@@ -4,7 +4,7 @@
* Aneesh V <aneesh@ti.com>
*/
#include <common.h>
#include <environment.h>
#include <env.h>
#include <asm/setup.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
@@ -129,12 +129,25 @@ static inline void omap_set_fastboot_userdata_size(void)
{
}
#endif /* CONFIG_FASTBOOT_FLASH_MMC */
static void omap_set_fastboot_product(void)
{
const char *board_name;
board_name = env_get("board_name");
if (board_name == NULL)
printf("Warning: fastboot.product: unknown board\n");
env_set("fastboot.product", board_name);
}
void omap_set_fastboot_vars(void)
{
omap_set_fastboot_cpu();
omap_set_fastboot_secure();
omap_set_fastboot_board_rev();
omap_set_fastboot_userdata_size();
omap_set_fastboot_product();
}
#endif /* CONFIG_FASTBOOT_FLASH */

View File

@@ -21,6 +21,7 @@ config RCAR_GEN3
imply CMD_GPT
imply CMD_UUID
imply CMD_MMC_SWRITE if MMC
imply OF_BOARD_SETUP if PCI
imply SUPPORT_EMMC_RPMB if MMC
imply SPL
imply SPL_BOARD_INIT

View File

@@ -22,6 +22,11 @@ config R8A77970
imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970
config R8A77980
bool "Renesas SoC R8A77980"
imply CLK_R8A77980
imply PINCTRL_PFC_R8A77980
config R8A77990
bool "Renesas SoC R8A77990"
imply CLK_R8A77990
@@ -38,6 +43,12 @@ choice
prompt "Renesas ARM64 SoCs board select"
optional
config TARGET_CONDOR
bool "Condor board"
imply R8A77980
help
Support for Renesas R-Car Gen3 Condor platform
config TARGET_DRAAK
bool "Draak board"
imply R8A77995
@@ -83,6 +94,7 @@ endchoice
config SYS_SOC
default "rmobile"
source "board/renesas/condor/Kconfig"
source "board/renesas/draak/Kconfig"
source "board/renesas/eagle/Kconfig"
source "board/renesas/ebisu/Kconfig"

View File

@@ -5,6 +5,7 @@
*/
#include <common.h>
#include <asm/io.h>
#include <env.h>
#include <linux/ctype.h>
#ifdef CONFIG_ARCH_CPU_INIT
@@ -64,6 +65,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },

View File

@@ -36,6 +36,7 @@
#define RMOBILE_CPU_TYPE_R8A7796 0x52
#define RMOBILE_CPU_TYPE_R8A77965 0x55
#define RMOBILE_CPU_TYPE_R8A77970 0x54
#define RMOBILE_CPU_TYPE_R8A77980 0x56
#define RMOBILE_CPU_TYPE_R8A77990 0x57
#define RMOBILE_CPU_TYPE_R8A77995 0x58

View File

@@ -110,9 +110,14 @@ config ROCKCHIP_RK3328
select ARM64
select SUPPORT_SPL
select SPL
select SUPPORT_TPL
select TPL
select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
select TPL_NEEDS_SEPARATE_STACK if TPL
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
imply SPL_SEPARATE_BSS
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT

View File

@@ -4,6 +4,7 @@
*/
#include <common.h>
#include <dm.h>
#include <env.h>
#include <clk.h>
#include <asm/armv7.h>
#include <asm/io.h>

View File

@@ -27,6 +27,18 @@ config SPL_LIBCOMMON_SUPPORT
config SPL_LIBGENERIC_SUPPORT
default y
config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_TEXT_BASE
default 0xff091000
config TPL_MAX_SIZE
default 28672
config TPL_STACK
default 0xff098000
source "board/rockchip/evb_rk3328/Kconfig"
endif

View File

@@ -16,6 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CRU_BASE 0xFF440000
#define GRF_BASE 0xFF100000
#define UART2_BASE 0xFF130000
#define FW_DDR_CON_REG 0xFF7C0040
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000",
@@ -46,8 +47,12 @@ struct mm_region *mem_map = rk3328_mem_map;
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
/* We do some SoC one time setting here. */
/* Disable the ddr secure region setting to make it non-secure */
rk_setreg(FW_DDR_CON_REG, 0x200);
#endif
return 0;
}

View File

@@ -5,6 +5,7 @@
#include <common.h>
#include <asm/io.h>
#include <env.h>
#include <errno.h>
#include <fdtdec.h>
#include <linux/libfdt.h>

View File

@@ -6,6 +6,7 @@
#include <altera.h>
#include <common.h>
#include <env.h>
#include <errno.h>
#include <fdtdec.h>
#include <miiphy.h>

View File

@@ -79,8 +79,6 @@ void board_init_f(ulong dummy)
writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
&sysmgr_regs->eccgrp_ocram);
memset(__bss_start, 0, __bss_end - __bss_start);
socfpga_sdram_remap_zero();
socfpga_pl310_clear();

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