Prepare 2010.06

Update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
powerpc: fix wrong comment at GOT definitions
2010-06-29 23:28:28 +02:00 · 2010-06-29 23:03:40 +02:00 · 2010-06-29 23:03:40 +02:00 · 2010-06-29 23:03:40 +02:00 · 2010-06-29 23:03:40 +02:00 · 2010-06-29 23:03:39 +02:00
3621 changed files with 227614 additions and 230149 deletions
--- a/11464
+++ b/11464
--- a/7
+++ b/7
@@ -437,7 +437,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor

 N: Andre Schwarz
 E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P)
+D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)

 N: Robert Schwebel
 E: r.schwebel@pengutronix.de
@@ -511,6 +511,11 @@ N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board

+N: David Wu
+E: support@arcturusnetworks.com
+D: Mercury Security EP2500
+W: http://www.arcturusnetworks.com
+
 N: Ming-Len Wu
 E: minglen_wu@techware.com.tw
 D: Motorola MX1ADS board support
--- a/145
+++ b/145
@@ -36,6 +36,7 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 	mecp5200	MPC5200
 	pf5200		MPC5200

+	caddy2		MPC8349
 	vme8349		MPC8349

 	CPCI750		PPC750FX/GX
@@ -61,6 +62,10 @@ Oliver Brown <obrown@adventnetworks.com>

 	gw8260		MPC8260

+Cyril Chemparathy <cyril@ti.com>
+
+	tnetv107x_evm	tnetv107x
+
 Conn Clark <clark@esteem.com>

 	ESTEEM192E	MPC8xx
@@ -79,7 +84,6 @@ Torsten Demke <torsten.demke@fci.com>

 Wolfgang Denk <wd@denx.de>

-	IceCube_5100	MGT5100
 	IceCube_5200	MPC5200

 	ARIA		MPC5121e
@@ -117,7 +121,6 @@ Wolfgang Denk <wd@denx.de>

 	CU824		MPC8240
 	Sandpoint8240	MPC8240
-	SL8245		MPC8245

 	ATC		MPC8250
 	PM825		MPC8250
@@ -133,8 +136,6 @@ Wolfgang Denk <wd@denx.de>
 	PCIPPC2		MPC750
 	PCIPPC6		MPC750

-	EXBITGEN	PPC405GP
-
 Jon Diekema <jon.diekema@smiths-aerospace.com>

 	sbc8260		MPC8260
@@ -151,6 +152,10 @@ Dave Ellis <DGE@sixnetio.com>

 	SXNI855T	MPC8xx

+Fred Fan <fanyefeng@gmail.com>
+
+	mx51evk		i.MX51
+
 Thomas Frieden <ThomasF@hyperion-entertainment.com>

 	AmigaOneG3SE	MPC7xx
@@ -193,6 +198,10 @@ Niklaus Giger <niklaus.giger@netstal.com>
 	MCU25		PPC405GPr
 	HCU5		PPC440EPx

+Siddarth Gore <gores@marvell.com>
+
+	guruplug	ARM926EJS (Kirkwood SoC)
+
 Frank Gottschling <fgottschling@eltec.de>

 	MHPC		MPC8xx
@@ -201,6 +210,8 @@ Frank Gottschling <fgottschling@eltec.de>

 Wolfgang Grandegger <wg@denx.de>

+	ipek01		MPC5200
+
 	CCM		MPC855

 	PN62		MPC8240
@@ -221,6 +232,7 @@ Ilko Iliev <iliev@ronetix.at>

 	PM9261		AT91SAM9261
 	PM9263		AT91SAM9263
+	PM9G45		ARM926EJS (AT91SAM9G45 SoC)

 Gary Jennejohn <garyj@denx.de>

@@ -342,6 +354,10 @@ Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240		MPC8240
 	sbc405		PPC405GP

+Sudhakar Rajashekhara <sudhakar.raj@ti.com>
+
+	da850evm	ARM926EJS (DA850/OMAP-L138)
+
 Ricardo Ribalda <ricardo.ribalda@uam.es>

 	ml507 		PPC440x5
@@ -365,6 +381,7 @@ Stefan Roese <sr@denx.de>
 	ebony		PPC440GP
 	glacier		PPC460GT
 	haleakala	PPC405EXr
+	icon		PPC440SPe
 	katmai		PPC440SPe
 	kilauea		PPC405EX
 	lwmon5		PPC440EPx
@@ -408,9 +425,9 @@ Heiko Schocher <hs@denx.de>
 	muas3001	MPC8270
 	municse		MPC5200
 	sc3		PPC405GP
+	suen3		ARM926EJS (Kirkwood SoC)
 	uc101		MPC5200

-
 Peter De Schrijver <p2@mind.be>

 	ML2		PPC4xx
@@ -419,6 +436,7 @@ Andre Schwarz <andre.schwarz@matrix-vision.de>

 	mvbc_p		MPC5200
 	mvblm7		MPC8343
+	mvsmr		MPC5200

 Jon Smirl <jonsmirl@gmail.com>

@@ -463,6 +481,10 @@ Josef Wagner <Wagner@Microsys.de>
 	CPC45		MPC8245
 	PM520		MPC5200

+Michael Weiss <michael.weiss@ifm.com>
+
+	PDM360NG	MPC5121e
+
 Stephen Williams <steve@icarus.com>

 	JSE		PPC405GPr
@@ -512,6 +534,10 @@ Unknown / orphaned boards:
 #	Board		CPU						#
 #########################################################################

+Albert ARIBAUD <albert.aribaud@free.fr>
+
+	edminiv2	ARM926EJS (Orion5x SoC)
+
 Rowel Atienza <rowel@diwalabs.com>

 	armadillo	ARM720T
@@ -543,6 +569,10 @@ Rick Bronson <rick@efn.org>

 	AT91RM9200DK	at91rm9200

+Po-Yu Chuang <ratbert@faraday-tech.com>
+
+	a320evb		FA526 (ARM920T-like) (a320 SoC)
+
 George G. Davis <gdavis@mvista.com>

 	assabet		SA1100
@@ -567,6 +597,7 @@ Peter Figuli <peposh@etc.sk>
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>

 	meesc		ARM926EJS (AT91SAM9263 SoC)
+	otc570		ARM926EJS (AT91SAM9263 SoC)

 Sedji Gaouaou<sedji.gaouaou@atmel.com>
 	at91sam9g10ek		ARM926EJS (AT91SAM9G10 SoC)
@@ -582,6 +613,10 @@ Kshitij Gupta <kshitij@ti.com>
 	omap1510inn	ARM925T
 	omap1610inn	ARM926EJS

+Vaibhav Hiremath <hvaibhav@ti.com>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+
 Grazvydas Ignotas <notasas@gmail.com>

 	omap3_pandora	ARM CORTEX-A8 (OMAP3xx SoC)
@@ -591,6 +626,16 @@ Gary Jennejohn <garyj@denx.de>
 	smdk2400	ARM920T
 	trab		ARM920T

+Matthias Kaehlcke <matthias@kaehlcke.net>
+	edb9301			ARM920T (EP9301)
+	edb9302			ARM920T (EP9302)
+	edb9302a		ARM920T (EP9302)
+	edb9307			ARM920T (EP9307)
+	edb9307a		ARM920T (EP9307)
+	edb9312			ARM920T (EP9312)
+	edb9315			ARM920T (EP9315)
+	edb9315a		ARM920T (EP9315)
+
 Konstantin Kletschke <kletschke@synertronixx.de>
 	scb9328		ARM920T

@@ -602,6 +647,11 @@ Nishant Kamat <nskamat@ti.com>

 	omap1610h2	ARM926EJS

+Minkyu Kang <mk7.kang@samsung.com>
+
+	s5p_goni	ARM CORTEX-A8 (S5PC110 SoC)
+	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
+
 Frederik Kriewitz <frederik@kriewitz.eu>

 	devkit8000	ARM CORTEX-A8 (OMAP3530 SoC)
@@ -612,27 +662,21 @@ Sergey Kubushyn <ksi@koi8.net>
 	SONATA		ARM926EJS
 	SCHMOOGIE	ARM926EJS

-Sandeep Paulraj <s-paulraj@ti.com>
-
-	davinci_dm355evm	ARM926EJS
-	davinci_dm355leopard	ARM926EJS
-	davinci_dm365evm	ARM926EJS
-	davinci_dm6467evm	ARM926EJS
-
 Prakash Kumar <prakash@embedx.com>

 	cerf250		xscale

+Vipin Kumar <vipin.kumar@st.com>
+
+	spear300	ARM926EJS (spear300 Soc)
+	spear310	ARM926EJS (spear310 Soc)
+	spear320	ARM926EJS (spear320 Soc)
+	spear600	ARM926EJS (spear600 Soc)
+
 Sergey Lapin <slapin@ossfans.org>

 	afeb9260	ARM926EJS (AT91SAM9260 SoC)

-Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-
-	imx31_phycore_eet	i.MX31
-	mx31ads			i.MX31
-	SMDK6400		S3C6400
-
 Nishanth Menon <nm@ti.com>

 	omap3_sdp3430	ARM CORTEX-A8 (OMAP3xx SoC)
@@ -655,6 +699,13 @@ Kyungmin Park <kyungmin.park@samsung.com>

 	apollon		ARM1136EJS

+Sandeep Paulraj <s-paulraj@ti.com>
+
+	davinci_dm355evm	ARM926EJS
+	davinci_dm355leopard	ARM926EJS
+	davinci_dm365evm	ARM926EJS
+	davinci_dm6467evm	ARM926EJS
+
 Peter Pearse <peter.pearse@arm.com>
 	integratorcp	All current ARM supplied & supported core modules
 			-see http://www.arm.com/products/DevTools/Hardware_Platforms.html
@@ -681,6 +732,10 @@ Tom Rix <Tom.Rix@windriver.com>

 	omap3_zoom2	ARM CORTEX-A8 (OMAP3xx SoC)

+John Rigby <jcrigby@gmail.com>
+
+	tx25		i.MX25
+
 Stefan Roese <sr@denx.de>

 	ixdpg425	xscale
@@ -690,12 +745,20 @@ Stefan Roese <sr@denx.de>
 Alessandro Rubini <rubini@unipv.it>
 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>

-	nmdk8815	ARM926EJS (Nomadik 8815 Soc)
+	nhk8815		ARM926EJS (Nomadik 8815 Soc)

 Steve Sakoman <sakoman@gmail.com>

 	omap3_overo	ARM CORTEX-A8 (OMAP3xx SoC)

+Jens Scharsig <esw@bus-elektronik.de>
+
+	eb_cpux9k2	ARM920T (AT91RM9200 SoC)
+
+Heiko Schocher <hs@denx.de>
+
+	magnesium	i.MX27
+
 Robert Schwebel <r.schwebel@pengutronix.de>

 	csb226		xscale
@@ -712,6 +775,10 @@ Andrea Scian <andrea.scian@dave-tech.it>

 	B2		ARM7TDMI (S3C44B0X)

+Nick Thompson <nick.thompson@gefanuc.com>
+
+	da830evm	ARM926EJS (DA830/OMAP-L137)
+
 Albin Tonnerre <albin.tonnerre@free-electrons.com>

 	sbc35_a9g20	ARM926EJS (AT91SAM9G20 SoC)
@@ -743,10 +810,6 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110

-Minkyu Kang <mk7.kang@samsung.com>
-
-	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
-
 -------------------------------------------------------------------------

 Unknown / orphaned boards:
@@ -756,6 +819,10 @@ Unknown / orphaned boards:
 	ixdp425		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address
 	lubbock		xscale	Kyle Harris <kharris@nexus-tech.net> / dead address

+	imx31_phycore_eet i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
+	mx31ads		  i.MX31  Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
+	SMDK6400	  S3C6400 Guennadi Liakhovetski <g.liakhovetski@gmx.de> / resigned
+
 #########################################################################
 # x86 Systems:								#
 #									#
@@ -790,22 +857,6 @@ Stefan Roese <sr@denx.de>

 	vct_xxx		MIPS32 4Kc

-#########################################################################
-# Nios-32 Systems:							#
-#									#
-# Maintainer Name, Email Address					#
-#	Board		CPU						#
-#########################################################################
-
-Stephan Linz <linz@li-pro.net>
-
-	DK1S10		Nios-32
-	ADNPESC1	Nios-32
-
-Scott McNutt <smcnutt@psyent.com>
-
-	DK1C20		Nios-32
-
 #########################################################################
 # Nios-II Systems:							#
 #									#
@@ -820,6 +871,7 @@ Scott McNutt <smcnutt@psyent.com>
 	EP1C20		Nios-II
 	EP1S10		Nios-II
 	EP1S40		Nios-II
+	nios2-generic	Nios-II

 #########################################################################
 # MicroBlaze Systems:							#
@@ -859,6 +911,10 @@ TsiChung Liew <Tsi-Chung.Liew@freescale.com>
 	M5475EVB	mcf547x_8x
 	M5485EVB	mcf547x_8x

+Wolfgang Wegner <w.wegner@astro-kom.de>
+
+	astro_mcf5373l	MCF5373L
+
 #########################################################################
 # AVR32 Systems:							#
 #									#
@@ -932,6 +988,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF518F-EZBRD	BF518
 	BF526-EZBRD	BF526
 	BF527-EZKIT	BF527
+	BF527-EZKIT-V2	BF527
 	BF533-EZKIT	BF533
 	BF533-STAMP	BF533
 	BF537-PNAV	BF537
@@ -949,6 +1006,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	CM-BF537U	BF537
 	CM-BF548	BF548
 	CM-BF561	BF561
+	TCM-BF518	BF518
 	TCM-BF537	BF537

 Martin Strubel <strubel@section5.ch>
@@ -967,6 +1025,15 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>

 	IBF-DSP561	BF561

+Valentin Yakovenkov <yakovenkov@niistt.ru>
+Anton Shurpin <shurpin.aa@niistt.ru>
+
+	BF561-ACVILON	BF561
+
+Brent Kandetzki <brentk@teleco.com>
+
+	IP04		BF532
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
--- a/80
+++ b/80
@@ -61,21 +61,21 @@ LIST_5xxx="		\
 	EVAL5200	\
 	fo300		\
 	galaxy5200	\
-	icecube_5100	\
 	icecube_5200	\
 	inka4x0		\
+	ipek01		\
 	lite5200b	\
 	mcc200		\
 	mecp5200	\
 	motionpro	\
 	munices		\
 	MVBC_P		\
+	MVSMR		\
 	o2dnt		\
 	pcm030		\
 	pf5200		\
 	PM520		\
 	TB5200		\
-	Total5100	\
 	Total5200	\
 	Total5200_Rev2	\
 	TQM5200		\
@@ -92,6 +92,7 @@ LIST_512x="		\
 	aria		\
 	mecp5123	\
 	mpc5121ads	\
+	pdm360ng	\
 "

 #########################################################################
@@ -185,6 +186,7 @@ LIST_4xx="		\
 	ADCIOP		\
 	alpr		\
 	AP1000		\
+	APC405		\
 	AR405		\
 	arches		\
 	ASH405		\
@@ -212,7 +214,6 @@ LIST_4xx="		\
 	DU440		\
 	ebony		\
 	ERIC		\
-	EXBITGEN	\
 	fx12mm		\
 	G2000		\
 	gdppc440etx	\
@@ -223,6 +224,7 @@ LIST_4xx="		\
 	hcu5		\
 	HH405		\
 	HUB405		\
+	icon		\
 	intip		\
 	JSE		\
 	KAREF		\
@@ -238,7 +240,6 @@ LIST_4xx="		\
 	MIP405		\
 	MIP405T		\
 	ML2		\
-	ml300		\
 	ml507		\
 	ml507_flash	\
 	neo		\
@@ -312,7 +313,6 @@ LIST_824x="		\
 	Sandpoint8240	\
 	Sandpoint8245	\
 	sbc8240		\
-	SL8245		\
 	utx8245		\
 "

@@ -357,10 +357,12 @@ LIST_8260="		\
 #########################################################################

 LIST_83xx="		\
+	caddy2		\
 	kmeter1		\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
+	MPC8315ERDB_NAND	\
 	MPC8323ERDB	\
 	MPC832XEMDS	\
 	MPC832XEMDS_ATM	\
@@ -391,6 +393,7 @@ LIST_85xx="		\
 	MPC8536DS_NAND	\
 	MPC8536DS_SDCARD	\
 	MPC8536DS_SPIFLASH	\
+	MPC8536DS_36BIT	\
 	MPC8540ADS	\
 	MPC8540EVAL	\
 	MPC8541CDS	\
@@ -400,6 +403,8 @@ LIST_85xx="		\
 	MPC8560ADS	\
 	MPC8568MDS	\
 	MPC8569MDS	\
+	MPC8569MDS_ATM	\
+	MPC8569MDS_NAND \
 	MPC8572DS	\
 	MPC8572DS_36BIT	\
 	P2020DS		\
@@ -449,6 +454,7 @@ LIST_85xx="		\

 LIST_86xx="		\
 	MPC8610HPCD	\
+	MPC8641HPCN_36BIT \
 	MPC8641HPCN	\
 	sbc8641d	\
 	XPEDITE5170	\
@@ -488,7 +494,7 @@ LIST_TSEC="		\
 	${LIST_86xx}	\
 "

-LIST_ppc="		\
+LIST_powerpc="		\
 	${LIST_5xx}	\
 	${LIST_512x}	\
 	${LIST_5xxx}	\
@@ -504,6 +510,12 @@ LIST_ppc="		\
 	${LIST_7xx}	\
 "

+# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
+# still using "ppc" instead of "powerpc"
+LIST_ppc="		\
+	${LIST_powerpc}	\
+"
+
 #########################################################################
 ## StrongARM Systems
 #########################################################################
@@ -539,6 +551,7 @@ LIST_ARM7="		\
 #########################################################################

 LIST_ARM9="			\
+	a320evb			\
 	ap920t			\
 	ap922_XA10		\
 	ap926ejs		\
@@ -549,8 +562,21 @@ LIST_ARM9="			\
 	cp926ejs		\
 	cp946es			\
 	cp966			\
+	da830evm		\
+	da850evm		\
+	edb9301			\
+	edb9302			\
+	edb9302a		\
+	edb9307			\
+	edb9307a		\
+	edb9312			\
+	edb9315			\
+	edb9315a		\
+	edminiv2		\
+	guruplug		\
 	imx27lite		\
 	lpd7a400		\
+	magnesium		\
 	mv88f6281gtw_ge		\
 	mx1ads			\
 	mx1fs2			\
@@ -569,6 +595,11 @@ LIST_ARM9="			\
 	sheevaplug		\
 	smdk2400		\
 	smdk2410		\
+	spear300		\
+	spear310		\
+	spear320		\
+	spear600		\
+	suen3			\
 	trab			\
 	VCMA9			\
 	versatile		\
@@ -581,6 +612,7 @@ LIST_ARM9="			\
 	davinci_sonata		\
 	davinci_dm355evm	\
 	davinci_dm355leopard	\
+	davinci_dm365evm	\
 	davinci_dm6467evm	\
 "

@@ -607,13 +639,16 @@ LIST_ARM11="			\
 	mx31pdk_nand		\
 	qong			\
 	smdk6400		\
+	tnetv107x_evm		\
 "

 #########################################################################
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="		\
+	am3517_evm		\
 	devkit8000		\
+	mx51evk			\
 	omap3_beagle		\
 	omap3_overo		\
 	omap3_evm		\
@@ -621,6 +656,7 @@ LIST_ARM_CORTEX_A8="		\
 	omap3_sdp3430		\
 	omap3_zoom1		\
 	omap3_zoom2		\
+	s5p_goni		\
 	smdkc100		\
 "

@@ -645,12 +681,15 @@ LIST_at91="			\
 	CPU9260			\
 	CPU9G20			\
 	csb637			\
+	eb_cpux9k2		\
 	kb9202			\
 	meesc			\
 	mp2usb			\
 	m501sk			\
+	otc570			\
 	pm9261			\
 	pm9263			\
+	pm9g45			\
 	SBC35_A9G20		\
 	TNY_A9260		\
 	TNY_A9G20		\
@@ -779,21 +818,6 @@ LIST_x86="		\
 	${LIST_I486}	\
 "

-#########################################################################
-## NIOS Systems
-#########################################################################
-
-LIST_nios="			\
-	ADNPESC1		\
-	ADNPESC1_base_32	\
-	ADNPESC1_DNPEVA2_base_32\
-	DK1C20			\
-	DK1C20_standard_32	\
-	DK1S10			\
-	DK1S10_standard_32	\
-	DK1S10_mtx_ldk_20	\
-"
-
 #########################################################################
 ## Nios-II Systems
 #########################################################################
@@ -804,6 +828,7 @@ LIST_nios2="		\
 	EP1S40		\
 	PCI5441		\
 	PK1C20		\
+	nios2-generic	\
 "

 #########################################################################
@@ -819,6 +844,7 @@ LIST_microblaze="			\
 #########################################################################

 LIST_coldfire="			\
+	astro_mcf5373l		\
 	cobra5272		\
 	EB+MCF-EV123		\
 	EB+MCF-EV123_internal	\
@@ -866,6 +892,7 @@ LIST_blackfin="		\
 	bf518f-ezbrd	\
 	bf526-ezbrd	\
 	bf527-ezkit	\
+	bf527-ezkit-v2	\
 	bf533-ezkit	\
 	bf533-stamp	\
 	bf537-minotaur	\
@@ -874,6 +901,7 @@ LIST_blackfin="		\
 	bf537-stamp	\
 	bf538f-ezkit	\
 	bf548-ezkit	\
+	bf561-acvilon	\
 	bf561-ezkit	\
 	blackstamp	\
 	cm-bf527	\
@@ -883,6 +911,8 @@ LIST_blackfin="		\
 	cm-bf548	\
 	cm-bf561	\
 	ibf-dsp561	\
+	ip04		\
+	tcm-bf518	\
 	tcm-bf537	\
 "

@@ -924,8 +954,8 @@ LIST_sparc="gr_xc3s_1500	gr_cpci_ax2000	gr_ep2s60	grsim	grsim_leon2"

 #-----------------------------------------------------------------------

-#----- for now, just run PPC by default -----
-[ $# = 0 ] && set $LIST_ppc
+#----- for now, just run PowerPC by default -----
+[ $# = 0 ] && set $LIST_powerpc

 #-----------------------------------------------------------------------

@@ -980,8 +1010,8 @@ do
 	|coldfire \
 	|microblaze \
 	|mips|mips_el \
-	|nios|nios2 \
-	|ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
+	|nios2 \
+	|ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
 	|sh|sh2|sh3|sh4 \
 	|sparc \
 	|x86|I486 \
--- a/923
+++ b/923
--- a/256
+++ b/256
@@ -138,68 +138,88 @@ U-Boot will always have a patchlevel of "0".
 Directory Hierarchy:
 ====================

- api		Machine/arch independent API for external apps
- board		Board dependent files
- common	Misc architecture independent functions
- cpu		CPU specific files
-  - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
-  - arm720t	Files specific to ARM 720 CPUs
-  - arm920t	Files specific to ARM 920 CPUs
-    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
-    - imx	Files specific to Freescale MC9328 i.MX CPUs
-    - s3c24x0	Files specific to Samsung S3C24X0 CPUs
-  - arm925t	Files specific to ARM 925 CPUs
-  - arm926ejs	Files specific to ARM 926 CPUs
-  - arm1136	Files specific to ARM 1136 CPUs
-  - at32ap	Files specific to Atmel AVR32 AP CPUs
-  - blackfin	Files specific to Analog Devices Blackfin CPUs
-  - i386	Files specific to i386 CPUs
-  - ixp		Files specific to Intel XScale IXP CPUs
-  - leon2	Files specific to Gaisler LEON2 SPARC CPU
-  - leon3	Files specific to Gaisler LEON3 SPARC CPU
-  - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
-  - mcf5227x	Files specific to Freescale ColdFire MCF5227x CPUs
-  - mcf532x	Files specific to Freescale ColdFire MCF5329 CPUs
-  - mcf5445x	Files specific to Freescale ColdFire MCF5445x CPUs
-  - mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
-  - mips	Files specific to MIPS CPUs
-  - mpc5xx	Files specific to Freescale MPC5xx  CPUs
-  - mpc5xxx	Files specific to Freescale MPC5xxx CPUs
-  - mpc8xx	Files specific to Freescale MPC8xx  CPUs
-  - mpc8220	Files specific to Freescale MPC8220 CPUs
-  - mpc824x	Files specific to Freescale MPC824x CPUs
-  - mpc8260	Files specific to Freescale MPC8260 CPUs
-  - mpc85xx	Files specific to Freescale MPC85xx CPUs
-  - nios	Files specific to Altera NIOS CPUs
-  - nios2	Files specific to Altera Nios-II CPUs
-  - ppc4xx	Files specific to AMCC PowerPC 4xx CPUs
-  - pxa		Files specific to Intel XScale PXA CPUs
-  - s3c44b0	Files specific to Samsung S3C44B0 CPUs
-  - sa1100	Files specific to Intel StrongARM SA1100 CPUs
- disk		Code for disk drive partition handling
- doc		Documentation (don't expect too much)
- drivers	Commonly used device drivers
- examples	Example code for standalone applications, etc.
- fs		Filesystem code (cramfs, ext2, jffs2, etc.)
- include	Header Files
- lib_arm	Files generic to ARM	 architecture
- lib_avr32	Files generic to AVR32	 architecture
- lib_blackfin	Files generic to Blackfin architecture
- lib_generic	Files generic to all	 architectures
- lib_i386	Files generic to i386	 architecture
- lib_m68k	Files generic to m68k	 architecture
- lib_microblaze Files generic to microblaze architecture
- lib_mips	Files generic to MIPS	 architecture
- lib_nios	Files generic to NIOS	 architecture
- lib_nios2	Files generic to NIOS2	 architecture
- lib_ppc	Files generic to PowerPC architecture
- lib_sh	Files generic to SH	 architecture
- lib_sparc	Files generic to SPARC	 architecture
- libfdt	Library files to support flattened device trees
- net		Networking code
- post		Power On Self Test
- rtc		Real Time Clock drivers
- tools		Tools to build S-Record or U-Boot images, etc.
+/arch			Architecture specific files
+  /arm			Files generic to ARM architecture
+    /cpu		CPU specific files
+      /arm720t		Files specific to ARM 720 CPUs
+      /arm920t		Files specific to ARM 920 CPUs
+	/at91rm9200	Files specific to Atmel AT91RM9200 CPU
+	/imx		Files specific to Freescale MC9328 i.MX CPUs
+	/s3c24x0	Files specific to Samsung S3C24X0 CPUs
+      /arm925t		Files specific to ARM 925 CPUs
+      /arm926ejs	Files specific to ARM 926 CPUs
+      /arm1136		Files specific to ARM 1136 CPUs
+      /ixp		Files specific to Intel XScale IXP CPUs
+      /pxa		Files specific to Intel XScale PXA CPUs
+      /s3c44b0		Files specific to Samsung S3C44B0 CPUs
+      /sa1100		Files specific to Intel StrongARM SA1100 CPUs
+    /lib		Architecture specific library files
+  /avr32		Files generic to AVR32 architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /blackfin		Files generic to Analog Devices Blackfin architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /i386			Files generic to i386 architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /m68k			Files generic to m68k architecture
+    /cpu		CPU specific files
+      /mcf52x2		Files specific to Freescale ColdFire MCF52x2 CPUs
+      /mcf5227x		Files specific to Freescale ColdFire MCF5227x CPUs
+      /mcf532x		Files specific to Freescale ColdFire MCF5329 CPUs
+      /mcf5445x		Files specific to Freescale ColdFire MCF5445x CPUs
+      /mcf547x_8x	Files specific to Freescale ColdFire MCF547x_8x CPUs
+    /lib		Architecture specific library files
+  /microblaze		Files generic to microblaze architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /mips			Files generic to MIPS architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /nios2		Files generic to Altera NIOS2 architecture
+    /cpu		CPU specific files
+    /lib		Architecture specific library files
+  /powerpc		Files generic to PowerPC architecture
+    /cpu		CPU specific files
+      /74xx_7xx		Files specific to Freescale MPC74xx and 7xx CPUs
+      /mpc5xx		Files specific to Freescale MPC5xx CPUs
+      /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
+      /mpc8xx		Files specific to Freescale MPC8xx CPUs
+      /mpc8220		Files specific to Freescale MPC8220 CPUs
+      /mpc824x		Files specific to Freescale MPC824x CPUs
+      /mpc8260		Files specific to Freescale MPC8260 CPUs
+      /mpc85xx		Files specific to Freescale MPC85xx CPUs
+      /ppc4xx		Files specific to AMCC PowerPC 4xx CPUs
+    /lib		Architecture specific library files
+  /sh			Files generic to SH architecture
+    /cpu		CPU specific files
+      /sh2		Files specific to sh2 CPUs
+      /sh3		Files specific to sh3 CPUs
+      /sh4		Files specific to sh4 CPUs
+    /lib		Architecture specific library files
+  /sparc		Files generic to SPARC architecture
+    /cpu		CPU specific files
+      /leon2		Files specific to Gaisler LEON2 SPARC CPU
+      /leon3		Files specific to Gaisler LEON3 SPARC CPU
+    /lib		Architecture specific library files
+/api			Machine/arch independent API for external apps
+/board			Board dependent files
+/common			Misc architecture independent functions
+/disk			Code for disk drive partition handling
+/doc			Documentation (don't expect too much)
+/drivers		Commonly used device drivers
+/examples		Example code for standalone applications, etc.
+/fs			Filesystem code (cramfs, ext2, jffs2, etc.)
+/include		Header Files
+/lib			Files generic to all architectures
+  /libfdt		Library files to support flattened device trees
+  /lzma			Library files to support LZMA decompression
+  /lzo			Library files to support LZO decompression
+/net			Networking code
+/post			Power On Self Test
+/rtc			Real Time Clock drivers
+/tools			Tools to build S-Record or U-Boot images, etc.

 Software Configuration:
 =======================
@@ -777,7 +797,7 @@ The following options need to be configured:
 		CONFIG_LBA48

 		Set this to enable support for disks larger than 137GB
-		Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
+		Also look at CONFIG_SYS_64BIT_LBA.
 		Whithout these , LBA48 support uses 32bit variables and will 'only'
 		support disks up to 2.1TB.

@@ -822,6 +842,16 @@ The following options need to be configured:

 - NETWORK Support (other):

+		CONFIG_DRIVER_AT91EMAC
+		Support for AT91RM9200 EMAC.
+
+			CONFIG_RMII
+			Define this to use reduced MII inteface
+
+			CONFIG_DRIVER_AT91EMAC_QUIET
+			If this defined, the driver is quiet.
+			The driver doen't show link status messages.
+
 		CONFIG_DRIVER_LAN91C96
 		Support for SMSC's LAN91C96 chips.

@@ -1123,6 +1153,12 @@ The following options need to be configured:
 		images, gzipped BMP images can be displayed via the
 		splashscreen support or the bmp command.

+- Run length encoded BMP image (RLE8) support: CONFIG_VIDEO_BMP_RLE8
+
+		If this option is set, 8-bit RLE compressed BMP images
+		can be displayed via the splashscreen support or the
+		bmp command.
+
 - Compression support:
 		CONFIG_BZIP2

@@ -1377,10 +1413,11 @@ The following options need to be configured:
 		to run and CONFIG_SYS_I2C_SLAVE to be the address of this node (ie
 		the CPU's i2c node address).

-		Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c)
-		sets the CPU up as a master node and so its address should
-		therefore be cleared to 0 (See, eg, MPC823e User's Manual
-		p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0.
+		Now, the u-boot i2c code for the mpc8xx
+		(arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
+		and so its address should therefore be cleared to 0 (See,
+		eg, MPC823e User's Manual p.16-473). So, set
+		CONFIG_SYS_I2C_SLAVE to 0.

 		CONFIG_SYS_I2C_INIT_MPC5XXX

@@ -1469,6 +1506,17 @@ The following options need to be configured:
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.

+		CONFIG_SYS_I2C_BOARD_LATE_INIT
+
+		An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
+		defined a custom i2c_board_late_init() routine in
+		boards/xxx/board.c is run AFTER the operations in i2c_init()
+		is completed. This callpoint can be used to unreset i2c bus
+		using CPU i2c controller register accesses for CPUs whose i2c
+		controller provide such a method. It is called at the end of
+		i2c_init() to allow i2c_init operations to setup the i2c bus
+		controller on the CPU (e.g. setting bus speed & slave address).
+
 		CONFIG_I2CFAST (PPC405GP|PPC405EP only)

 		This option enables configuration of bi_iic_fast[] flags
@@ -1924,9 +1972,9 @@ Legacy uImage format:
   13	common/image.c		Start multifile image verification
   14	common/image.c		No initial ramdisk, no multifile, continue.

-   15	lib_<arch>/bootm.c	All preparation done, transferring control to OS
+   15	arch/<arch>/lib/bootm.c	All preparation done, transferring control to OS

-  -30	lib_ppc/board.c		Fatal error, hang the system
+  -30	arch/powerpc/lib/board.c	Fatal error, hang the system
  -31	post/post.c		POST test failed, detected by post_output_backlog()
  -32	post/post.c		POST test failed, detected by post_run_single()

@@ -2447,6 +2495,19 @@ to save the current settings.
 	- CONFIG_SYS_EEPROM_SIZE:
 	  The size in bytes of the EEPROM device.

+	- CONFIG_ENV_EEPROM_IS_ON_I2C
+	  define this, if you have I2C and SPI activated, and your
+	  EEPROM, which holds the environment, is on the I2C bus.
+
+	- CONFIG_I2C_ENV_EEPROM_BUS
+	  if you have an Environment on an EEPROM reached over
+	  I2C muxes, you can define here, how to reach this
+	  EEPROM. For example:
+
+	  #define CONFIG_I2C_ENV_EEPROM_BUS	  "pca9547:70:d\0"
+
+	  EEPROM which holds the environment, is reached over
+	  a pca9547 i2c mux with address 0x70, channel 3.

 - CONFIG_ENV_IS_IN_DATAFLASH:

@@ -2524,13 +2585,6 @@ use the "saveenv" command to store a valid environment.
 - CONFIG_SYS_FAULT_MII_ADDR:
 		MII address of the PHY to check for the Ethernet link state.

- CONFIG_SYS_64BIT_VSPRINTF:
-		Makes vsprintf (and all *printf functions) support printing
-		of 64bit values by using the L quantifier
-
- CONFIG_SYS_64BIT_STRTOUL:
-		Adds simple_strtoull that returns a 64bit value
-
 - CONFIG_NS16550_MIN_FUNCTIONS:
 		Define this if you desire to only have use of the NS16550_init
 		and NS16550_putc functions for the serial driver located at
@@ -2681,7 +2735,7 @@ Low Level (hardware related) configuration options:
  CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
  CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
  CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
-		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
+		Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.

 - CONFIG_PCI_DISABLE_PCIE:
 		Disable PCI-Express on systems where it is supported but not
@@ -2989,7 +3043,9 @@ environment. As long as you don't save the environment you are
 working with an in-memory copy. In case the Flash area containing the
 environment is erased by accident, a default environment is provided.

-Some configuration options can be set using Environment Variables:
+Some configuration options can be set using Environment Variables.
+
+List of environment variables (most likely not complete):

  baudrate	- see CONFIG_BAUDRATE

@@ -3101,7 +3157,7 @@ Some configuration options can be set using Environment Variables:
 		  available network interfaces.
 		  It just stays at the currently selected interface.

-   netretry	- When set to "no" each network operation will
+  netretry	- When set to "no" each network operation will
 		  either succeed or fail without retrying.
 		  When set to "once" the network operation will
 		  fail when all the available network interfaces
@@ -3117,7 +3173,18 @@ Some configuration options can be set using Environment Variables:
  tftpdstport	- If this is set, the value is used for TFTP's UDP
 		  destination port instead of the Well Know Port 69.

-   vlan		- When set to a value < 4095 the traffic over
+  tftpblocksize - Block size to use for TFTP transfers; if not set,
+		  we use the TFTP server's default block size
+
+  tftptimeout	- Retransmission timeout for TFTP packets (in milli-
+		  seconds, minimum value is 1000 = 1 second). Defines
+		  when a packet is considered to be lost so it has to
+		  be retransmitted. The default is 5000 = 5 seconds.
+		  Lowering this value may make downloads succeed
+		  faster in networks with high packet loss rates or
+		  with unreliable TFTP servers.
+
+  vlan		- When set to a value < 4095 the traffic over
 		  Ethernet is encapsulated/received over 802.1q
 		  VLAN tagged frames.

@@ -3233,6 +3300,11 @@ o If both the SROM and the environment contain a MAC address, and the
 o If neither SROM nor the environment contain a MAC address, an error
  is raised.

+If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses
+will be programmed into hardware as part of the initialization process.  This
+may be skipped by setting the appropriate 'ethmacskip' environment variable.
+The naming convention is as follows:
+"ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc.

 Image Formats:
 ==============
@@ -3262,8 +3334,8 @@ details; basically, the header defines the following image properties:
  Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
  INTEGRITY).
 * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
-  IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC).
+  IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+  Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point
@@ -3314,7 +3386,7 @@ configure the Linux device drivers for use with your target hardware
 (no, we don't intend to provide a full virtual machine interface to
 Linux :-).

-But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).
+But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).

 Just make sure your machine specific header file (for instance
 include/asm-ppc/tqm8xx.h) includes the same definition of the Board
@@ -3412,7 +3484,7 @@ So a typical call to build a U-Boot image would read:

 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
 	> examples/uImage.TQM850L
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
@@ -3436,10 +3508,10 @@ speed for memory and install an UNCOMPRESSED image instead: this
 needs more space in Flash, but boots much faster since it does not
 need to be uncompressed:

-	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz
+	-> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
 	-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
 	> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \
+	> -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
 	> examples/uImage.TQM850L-uncompressed
 	Image Name:   2.4.4 kernel for TQM850L
 	Created:      Wed Jul 19 02:34:59 2000
@@ -3916,7 +3988,9 @@ For PowerPC, the following registers have specific use:
 	R30:	GOT pointer
 	R31:	frame pointer

-	(U-Boot also uses R14 as internal GOT pointer.)
+	(U-Boot also uses R12 as internal GOT pointer. r12
+	is a volatile register so r12 needs to be reset when
+	going back and forth between asm and C)

    ==> U-Boot will use R2 to hold a pointer to the global data

@@ -3946,6 +4020,14 @@ On ARM, the following registers are used:

    ==> U-Boot will use R8 to hold a pointer to the global data

+On Nios II, the ABI is documented here:
+	http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
+
+    ==> U-Boot will use gp to hold a pointer to the global data
+
+    Note: on Nios II, we give "-G0" option to gcc and don't use gp
+    to access small data sections, so gp is free.
+
 NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
 or current versions of GCC may "optimize" the code too much.

--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
--- a/arch/.gitignore
+++ b/arch/.gitignore
@@ -0,0 +1,2 @@
+/*/include/asm/arch
+/*/include/asm/proc
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -0,0 +1,66 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CROSS_COMPILE ?= arm-linux-
+
+ifeq ($(BOARD),omap2420h4)
+STANDALONE_LOAD_ADDR = 0x80300000
+else
+ifeq ($(SOC),omap3)
+STANDALONE_LOAD_ADDR = 0x80300000
+else
+STANDALONE_LOAD_ADDR = 0xc100000
+endif
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
+
+# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
+PLATFORM_CPPFLAGS += $(call cc-option,-marm,)
+
+# Try if EABI is supported, else fall back to old API,
+# i. e. for example:
+# - with ELDK 4.2 (EABI supported), use:
+#	-mabi=aapcs-linux -mno-thumb-interwork
+# - with ELDK 4.1 (gcc 4.x, no EABI), use:
+#	-mabi=apcs-gnu -mno-thumb-interwork
+# - with ELDK 3.1 (gcc 3.x), use:
+#	-mapcs-32 -mno-thumb-interwork
+PLATFORM_CPPFLAGS += $(call cc-option,\
+				-mabi=aapcs-linux -mno-thumb-interwork,\
+				$(call cc-option,\
+					-mapcs-32,\
+					$(call cc-option,\
+						-mabi=apcs-gnu,\
+					)\
+				) $(call cc-option,-mno-thumb-interwork,)\
+			)
+
+# For EABI, make sure to provide raise()
+ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
+# This file is parsed several times; make sure to add only once.
+ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS)))
+PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
+endif
+endif
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
--- a/arch/arm/cpu/arm1136/config.mk
+++ b/arch/arm/cpu/arm1136/config.mk
--- a/arch/arm/cpu/arm1136/cpu.c
+++ b/arch/arm/cpu/arm1136/cpu.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+#ifdef CONFIG_LCD
+	{
+		extern void lcd_disable(void);
+		extern void lcd_panel_disable(void);
+
+		lcd_disable(); /* proper disable of lcd & panel */
+		lcd_panel_disable();
+	}
+#endif
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+static void cache_flush(void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+}
--- a/arch/arm/cpu/arm1136/mx31/Makefile
+++ b/arch/arm/cpu/arm1136/mx31/Makefile
--- a/arch/arm/cpu/arm1136/mx31/devices.c
+++ b/arch/arm/cpu/arm1136/mx31/devices.c
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
--- a/arch/arm/cpu/arm1136/mx31/timer.c
+++ b/arch/arm/cpu/arm1136/mx31/timer.c
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+#include <div64.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
+#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
+#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
+#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+static ulong timestamp;
+static ulong lastinc;
+
+/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
+#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CONFIG_MX31_CLK32);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	time *= CONFIG_MX31_CLK32;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * CONFIG_MX31_CLK32 + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	do_div(tick, TICK_PER_TIME);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us += US_PER_TICK - 1;
+	do_div(us, US_PER_TICK);
+	return us;
+}
+#endif
+
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init (void)
+{
+	int i;
+
+	/* setup GP Timer 1 */
+	GPTCR = GPTCR_SWR;
+	for (i = 0; i < 100; i++)
+		GPTCR = 0; /* We have no udelay by now */
+	GPTPR = 0; /* 32Khz */
+	/* Freerun Mode, PERCLK1 input */
+	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+	return 0;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = GPTCNT; /* capture current incrementer value time */
+	timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+	ulong now = GPTCNT; /* current tick value */
+
+	if (now >= lastinc)	/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		timestamp += (now - lastinc);
+	else			/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+void reset_cpu (ulong addr)
+{
+	__REG16(WDOG_BASE) = 4;
+}
--- a/arch/arm/cpu/arm1136/omap24xx/Makefile
+++ b/arch/arm/cpu/arm1136/omap24xx/Makefile
--- a/arch/arm/cpu/arm1136/omap24xx/reset.S
+++ b/arch/arm/cpu/arm1136/omap24xx/reset.S
--- a/arch/arm/cpu/arm1136/omap24xx/timer.c
+++ b/arch/arm/cpu/arm1136/omap24xx/timer.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/omap2420.h>
+
+#define TIMER_LOAD_VAL 0
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init (void)
+{
+	int32_t val;
+
+	/* Start the counter ticking up */
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;	/* reload value on overflow*/
+	val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0;		/* mask to enable timer*/
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
+
+	reset_timer_masked(); /* init the timestamp and lastinc value */
+
+	return(0);
+}
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	if (usec >= 1000) {		/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;	/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;	/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;		/* finish normalize. */
+	} else {			/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	tmp = get_timer (0);		/* get current timestamp */
+	if ( (tmo + tmp + 1) < tmp )	/* if setting this forward will roll time stamp */
+		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastinc value */
+	else
+		tmo	+= tmp;		/* else, set advancing stamp wake up time */
+	while (get_timer_masked () < tmo)/* loop till event */
+		/*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = READ_TIMER;		/* capture current incrementer value time */
+	timestamp = 0;			/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current tick value */
+
+	if (now >= lastinc)		/* normal mode (non roll) */
+		timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
+	else				/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;			/* finish normalize. */
+	} else {					/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -0,0 +1,444 @@
+/*
+ *  armboot - Startup Code for OMP2420/ARM1136 CPU-core
+ *
+ *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *
+ *  Copyright (c) 2001	Marius Gr<EFBFBD>ger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Z<EFBFBD>pke <azu@sysgo.de>
+ *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+.globl _start
+_start: b	reset
+#ifdef CONFIG_PRELOADER
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678	/* now 16*4=64 */
+#else
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+_pad:			.word 0x12345678 /* now 16*4=64 */
+#endif	/* CONFIG_PRELOADER */
+.global _end_vect
+_end_vect:
+
+	.balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0xd3
+	msr	cpsr,r0
+
+#ifdef CONFIG_OMAP2420H4
+       /* Copy vectors to mask ROM indirect addr */
+	adr	r0, _start		/* r0 <- current position of code   */
+		add     r0, r0, #4				/* skip reset vector			*/
+	mov	r2, #64			/* r2 <- size to copy  */
+	add	r2, r0, r2		/* r2 <- source end address	    */
+	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
+	mov	r3, #SRAM_OFFSET1
+	add	r1, r1, r3
+	mov	r3, #SRAM_OFFSET2
+	add	r1, r1, r3
+next:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next			/* loop until equal */
+	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
+#endif
+	/* the mask ROM code should have PLL and others stable */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl  cpu_init_crit
+#endif
+
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+relocate:				/* relocate U-Boot to RAM	    */
+	adr	r0, _start		/* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
+	cmp	r0, r1			/* don't reloc during debug	    */
+#ifndef CONFIG_PRELOADER
+	beq	stack_setup
+#endif	/* CONFIG_PRELOADER */
+
+	ldr	r2, _armboot_start
+	ldr	r3, _bss_start
+	sub	r2, r3, r2		/* r2 <- size of armboot	    */
+	add	r2, r0, r2		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */
+	ble	copy_loop
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
+
+	/* Set up the stack						    */
+stack_setup:
+	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+#ifdef CONFIG_PRELOADER
+	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
+#else
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area			    */
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo			    */
+#ifdef CONFIG_USE_IRQ
+	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+#endif	/* CONFIG_PRELOADER */
+	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
+
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment	    */
+	ldr	r1, _bss_end		/* stop here			    */
+	mov	r2, #0x00000000		/* clear			    */
+
+#ifndef CONFIG_PRELOADER
+clbss_l:str	r2, [r0]		/* clear loop...		    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	bne	clbss_l
+#endif
+
+	ldr	pc, _start_armboot
+
+#ifdef CONFIG_NAND_SPL
+_start_armboot: .word nand_boot
+#else
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
+_start_armboot: .word start_armboot
+#endif /* CONFIG_ONENAND_IPL */
+#endif /* CONFIG_NAND_SPL */
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I+D+BTB caches */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate Unified TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Jump to board specific initialization... The Mask ROM will have already initialized
+	 * basic memory.  Go here to bump up clock rate and handle wake up conditions.
+	 */
+	mov	ip, lr		/* persevere link reg across call */
+	bl	lowlevel_init	/* go setup pll,mux,memory */
+	mov	lr, ip		/* restore link */
+	mov	pc, lr		/* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_PRELOADER
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current user stack
+	stmia	sp, {r0 - r12}			@ Save user registers (now in svc mode) r0-r12
+
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
+	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort stack
+	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc and cpsr (into parm regs)
+	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
+	mov	r0, sp				@ save current stack into r0 (param register)
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC			@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, _armboot_start		@ setup our mode stack (enter in banked mode)
+	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
+	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
+
+	str	lr, [r13]			@ save caller lr in position 0 of saved stack
+	mrs	lr, spsr			@ get the spsr
+	str	lr, [r13, #4]			@ save spsr in position 1 of saved stack
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	@ msr	spsr_c, r13
+	msr	spsr, r13			@ switch modes, make sure moves will execute
+	mov	lr, pc				@ capture return pc
+	movs	pc, lr				@ jump to next instruction & switch modes.
+	.endm
+
+	.macro get_bad_stack_swi
+	sub	r13, r13, #4			@ space on current stack for scratch reg.
+	str	r0, [r13]			@ save R0's value.
+	ldr	r0, _armboot_start		@ get data regions start
+	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)	@ move past malloc pool
+	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ move past gbl and a couple spots for abort stack
+	str	lr, [r0]			@ save caller lr in position 0 of saved stack
+	mrs	r0, spsr			@ get the spsr
+	str	lr, [r0, #4]			@ save spsr in position 1 of saved stack
+	ldr	r0, [r13]			@ restore r0
+	add	r13, r13, #4			@ pop stack entry
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+#endif	/* CONFIG_PRELOADER */
+
+/*
+ * exception handlers
+ */
+#ifdef CONFIG_PRELOADER
+	.align	5
+do_hang:
+	ldr	sp, _TEXT_BASE			/* use 32 words about stack */
+	bl	hang				/* hang and never return */
+#else	/* !CONFIG_PRELOADER */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+	.align 5
+.global arm1136_cache_flush
+arm1136_cache_flush:
+		mcr	p15, 0, r1, c7, c5, 0	@ invalidate I cache
+		mov	pc, lr			@ back to caller
+#endif	/* CONFIG_PRELOADER */
--- a/arch/arm/cpu/arm1136/u-boot.lds
+++ b/arch/arm/cpu/arm1136/u-boot.lds
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2009
+ * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * Copyright (C) 2005-2007 Samsung Electronics
+ * Kyungin Park <kyugnmin.park@samsung.com>
+ *
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/arm/cpu/arm1136/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
--- a/arch/arm/cpu/arm1176/config.mk
+++ b/arch/arm/cpu/arm1176/config.mk
--- a/arch/arm/cpu/arm1176/cpu.c
+++ b/arch/arm/cpu/arm1176/cpu.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+static void cache_flush (void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	/* invalidate both caches and flush btb */
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
+	/* mem barrier to sync things */
+	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
+}
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
--- a/arch/arm/cpu/arm1176/s3c64xx/config.mk
+++ b/arch/arm/cpu/arm1176/s3c64xx/config.mk
--- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
+++ b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
@@ -0,0 +1,135 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/s3c6400.h>
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	/* DMC1 base address 0x7e001000 */
+	ldr	r0, =ELFIN_DMC1_BASE
+
+	ldr	r1, =0x4
+	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+	ldr	r1, =DMC_DDR_REFRESH_PRD
+	str	r1, [r0, #INDEX_DMC_REFRESH_PRD]
+
+	ldr	r1, =DMC_DDR_CAS_LATENCY
+	str	r1, [r0, #INDEX_DMC_CAS_LATENCY]
+
+	ldr	r1, =DMC_DDR_t_DQSS
+	str	r1, [r0, #INDEX_DMC_T_DQSS]
+
+	ldr	r1, =DMC_DDR_t_MRD
+	str	r1, [r0, #INDEX_DMC_T_MRD]
+
+	ldr	r1, =DMC_DDR_t_RAS
+	str	r1, [r0, #INDEX_DMC_T_RAS]
+
+	ldr	r1, =DMC_DDR_t_RC
+	str	r1, [r0, #INDEX_DMC_T_RC]
+
+	ldr	r1, =DMC_DDR_t_RCD
+	ldr	r2, =DMC_DDR_schedule_RCD
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RCD]
+
+	ldr	r1, =DMC_DDR_t_RFC
+	ldr	r2, =DMC_DDR_schedule_RFC
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RFC]
+
+	ldr	r1, =DMC_DDR_t_RP
+	ldr	r2, =DMC_DDR_schedule_RP
+	orr	r1, r1, r2
+	str	r1, [r0, #INDEX_DMC_T_RP]
+
+	ldr	r1, =DMC_DDR_t_RRD
+	str	r1, [r0, #INDEX_DMC_T_RRD]
+
+	ldr	r1, =DMC_DDR_t_WR
+	str	r1, [r0, #INDEX_DMC_T_WR]
+
+	ldr	r1, =DMC_DDR_t_WTR
+	str	r1, [r0, #INDEX_DMC_T_WTR]
+
+	ldr	r1, =DMC_DDR_t_XP
+	str	r1, [r0, #INDEX_DMC_T_XP]
+
+	ldr	r1, =DMC_DDR_t_XSR
+	str	r1, [r0, #INDEX_DMC_T_XSR]
+
+	ldr	r1, =DMC_DDR_t_ESR
+	str	r1, [r0, #INDEX_DMC_T_ESR]
+
+	ldr	r1, =DMC1_MEM_CFG
+	str	r1, [r0, #INDEX_DMC_MEMORY_CFG]
+
+	ldr	r1, =DMC1_MEM_CFG2
+	str	r1, [r0, #INDEX_DMC_MEMORY_CFG2]
+
+	ldr	r1, =DMC1_CHIP0_CFG
+	str	r1, [r0, #INDEX_DMC_CHIP_0_CFG]
+
+	ldr	r1, =DMC_DDR_32_CFG
+	str	r1, [r0, #INDEX_DMC_USER_CONFIG]
+
+	/* DMC0 DDR Chip 0 configuration direct command reg */
+	ldr	r1, =DMC_NOP0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Precharge All */
+	ldr	r1, =DMC_PA0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Auto Refresh 2 time */
+	ldr	r1, =DMC_AR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* MRS */
+	ldr	r1, =DMC_mDDR_EMR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Mode Reg */
+	ldr	r1, =DMC_mDDR_MR0
+	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+	/* Enable DMC1 */
+	mov	r1, #0x0
+	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+check_dmc1_ready:
+	ldr	r1, [r0, #INDEX_DMC_MEMC_STATUS]
+	mov	r2, #0x3
+	and	r1, r1, r2
+	cmp	r1, #0x1
+	bne	check_dmc1_ready
+	nop
+
+	mov	pc, lr
+
+	.ltorg
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ b/arch/arm/cpu/arm1176/s3c64xx/reset.S
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/s3c6400.h>
+
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, =ELFIN_CLOCK_POWER_BASE
+	ldr	r2, [r1, #SYS_ID_OFFSET]
+	ldr	r3, =0xffff
+	and	r2, r3, r2, lsr #12
+	str	r2, [r1, #SW_RST_OFFSET]
+_loop_forever:
+	b	_loop_forever
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+#include <asm/arch/s3c6400.h>
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+
+/* ------------------------------------------------------------------------- */
+/*
+ * NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+	ulong r, m, p, s;
+
+	switch (pllreg) {
+	case APLL:
+		r = APLL_CON_REG;
+		break;
+	case MPLL:
+		r = MPLL_CON_REG;
+		break;
+	case EPLL:
+		r = EPLL_CON0_REG;
+		break;
+	default:
+		hang();
+	}
+
+	m = (r >> 16) & 0x3ff;
+	p = (r >> 8) & 0x3f;
+	s = r & 0x7;
+
+	return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
+}
+
+/* return ARMCORE frequency */
+ulong get_ARMCLK(void)
+{
+	ulong div;
+
+	div = CLK_DIV0_REG;
+
+	return get_PLLCLK(APLL) / ((div & 0x7) + 1);
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	return get_PLLCLK(APLL);
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	ulong fclk;
+
+	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
+	uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
+
+	/*
+	 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
+	 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
+	 */
+	if (OTHERS_REG & 0x80)
+		fclk = get_FCLK();		/* SYNC Mode	*/
+	else
+		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
+
+	return fclk / (hclk_div * hclkx2_div);
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	ulong fclk;
+	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
+	uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
+
+	if (OTHERS_REG & 0x80)
+		fclk = get_FCLK();		/* SYNC Mode	*/
+	else
+		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
+
+	return fclk / (hclkx2_div * pre_div);
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	return get_PLLCLK(EPLL);
+}
+
+int print_cpuinfo(void)
+{
+	printf("\nCPU:     S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
+	printf("         Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
+	       get_FCLK() / 1000000, get_HCLK() / 1000000,
+	       get_PCLK() / 1000000);
+
+	if (OTHERS_REG & 0x80)
+		printf("(SYNC Mode) \n");
+	else
+		printf("(ASYNC Mode) \n");
+	return 0;
+}
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+#include <asm/arch/s3c6400.h>
+#include <div64.h>
+
+static ulong timer_load_val;
+
+#define PRESCALER	167
+
+static s3c64xx_timers *s3c64xx_get_base_timers(void)
+{
+	return (s3c64xx_timers *)ELFIN_TIMER_BASE;
+}
+
+/* macro to read the 16 bit timer */
+static inline ulong read_timer(void)
+{
+	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+
+	return timers->TCNTO4;
+}
+
+/* Internal tick units */
+/* Last decremneter snapshot */
+static unsigned long lastdec;
+/* Monotonic incrementing timer */
+static unsigned long long timestamp;
+
+int timer_init(void)
+{
+	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+
+	/* use PWM Timer 4 because it has no output */
+	/*
+	 * We use the following scheme for the timer:
+	 * Prescaler is hard fixed at 167, divider at 1/4.
+	 * This gives at PCLK frequency 66MHz approx. 10us ticks
+	 * The timer is set to wrap after 100s, at 66MHz this obviously
+	 * happens after 10,000,000 ticks. A long variable can thus
+	 * keep values up to 40,000s, i.e., 11 hours. This should be
+	 * enough for most uses:-) Possible optimizations: select a
+	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
+	 * the prescaler automatically for other PCLK frequencies.
+	 */
+	timers->TCFG0 = PRESCALER << 8;
+	if (timer_load_val == 0) {
+		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
+		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
+	}
+
+	/* load value for 10 ms timeout */
+	lastdec = timers->TCNTB4 = timer_load_val;
+	/* auto load, manual update of Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
+		TCON_4_UPDATE;
+
+	/* auto load, start Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	ulong now = read_timer();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + timer_load_val - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	/* We overrun in 100s */
+	return (ulong)(timer_load_val / 100);
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = read_timer();
+	timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	unsigned long long res = get_ticks();
+	do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
+	return res;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = (usec + 9) / 10;
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)/* loop till event */
+		 /*NOP*/;
+}
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -0,0 +1,498 @@
+/*
+ *  armboot - Startup Code for ARM1176 CPU-core
+ *
+ * Copyright (c) 2007	Samsung Electronics
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
+ * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
+ * jsgood (jsgood.yang@samsung.com)
+ * Base codes by scsuh (sc.suh)
+ */
+
+#include <config.h>
+#include <version.h>
+#ifdef CONFIG_ENABLE_MMU
+#include <asm/proc/domain.h>
+#endif
+
+#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
+#define CONFIG_SYS_PHY_UBOOT_BASE	CONFIG_SYS_UBOOT_BASE
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+.globl _start
+_start: b	reset
+#ifndef CONFIG_NAND_SPL
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+	ldr	pc, _not_used
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+_pad:
+	.word 0x12345678 /* now 16*4=64 */
+#else
+	. = _start + 64
+#endif
+
+.global _end_vect
+_end_vect:
+	.balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+/*
+ * Below variable is very important because we use MMU in U-Boot.
+ * Without it, we cannot run code correctly before MMU is ON.
+ * by scsuh.
+ */
+_TEXT_PHY_BASE:
+	.word	CONFIG_SYS_PHY_UBOOT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x3f
+	orr	r0, r0, #0xd3
+	msr	cpsr, r0
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+cpu_init_crit:
+	/*
+	 * When booting from NAND - it has definitely been a reset, so, no need
+	 * to flush caches and disable the MMU
+	 */
+#ifndef CONFIG_NAND_SPL
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
+
+	/* Prepare to disable the MMU */
+	adr	r2, mmu_disable_phys
+	sub	r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE)
+	b	mmu_disable
+
+	.align 5
+	/* Run in a single cache-line */
+mmu_disable:
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	mov	pc, r2
+mmu_disable_phys:
+
+#ifdef CONFIG_DISABLE_TCM
+	/*
+	 * Disable the TCMs
+	 */
+	mrc	p15, 0, r0, c0, c0, 2	/* Return TCM details */
+	cmp	r0, #0
+	beq	skip_tcmdisable
+	mov	r1, #0
+	mov	r2, #1
+	tst	r0, r2
+	mcrne	p15, 0, r1, c9, c1, 1	/* Disable Instruction TCM if present*/
+	tst	r0, r2, LSL #16
+	mcrne	p15, 0, r1, c9, c1, 0	/* Disable Data TCM if present*/
+skip_tcmdisable:
+#endif
+#endif
+
+#ifdef CONFIG_PERIPORT_REMAP
+	/* Peri port setup */
+	ldr	r0, =CONFIG_PERIPORT_BASE
+	orr	r0, r0, #CONFIG_PERIPORT_SIZE
+	mcr	p15,0,r0,c15,c2,4
+#endif
+
+	/*
+	 * Go setup Memory and board specific bits prior to relocation.
+	 */
+	bl	lowlevel_init		/* go setup pll,mux,memory */
+
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+relocate:				/* relocate U-Boot to RAM	    */
+	adr	r0, _start		/* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
+	cmp     r0, r1                  /* don't reloc during debug         */
+	beq     stack_setup
+
+	ldr	r2, _armboot_start
+	ldr	r3, _bss_start
+	sub	r2, r3, r2		/* r2 <- size of armboot            */
+	add	r2, r0, r2		/* r2 <- source end address         */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */
+	ble	copy_loop
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
+
+#ifdef CONFIG_ENABLE_MMU
+enable_mmu:
+	/* enable domain access */
+	ldr	r5, =0x0000ffff
+	mcr	p15, 0, r5, c3, c0, 0	/* load domain access register */
+
+	/* Set the TTB register */
+	ldr	r0, _mmu_table_base
+	ldr	r1, =CONFIG_SYS_PHY_UBOOT_BASE
+	ldr	r2, =0xfff00000
+	bic	r0, r0, r2
+	orr	r1, r0, r1
+	mcr	p15, 0, r1, c2, c0, 0
+
+	/* Enable the MMU */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #1		/* Set CR_M to enable MMU */
+
+	/* Prepare to enable the MMU */
+	adr	r1, skip_hw_init
+	and	r1, r1, #0x3fc
+	ldr	r2, _TEXT_BASE
+	ldr	r3, =0xfff00000
+	and	r2, r2, r3
+	orr	r2, r2, r1
+	b	mmu_enable
+
+	.align 5
+	/* Run in a single cache-line */
+mmu_enable:
+
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	mov	pc, r2
+skip_hw_init:
+#endif
+
+	/* Set up the stack						    */
+stack_setup:
+	ldr	r0, =CONFIG_SYS_UBOOT_BASE	/* base of copy in DRAM	    */
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
+
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment        */
+	ldr	r1, _bss_end		/* stop here                        */
+	mov 	r2, #0			/* clear                            */
+
+clbss_l:
+	str	r2, [r0]		/* clear loop...                    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	ble	clbss_l
+
+#ifndef CONFIG_NAND_SPL
+	ldr	pc, _start_armboot
+
+_start_armboot:
+	.word start_armboot
+#else
+	b	nand_boot
+/*	.word nand_boot*/
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+_mmu_table_base:
+	.word mmu_table
+#endif
+
+#ifndef CONFIG_NAND_SPL
+/*
+ * we assume that cache operation is done before. (eg. cleanup_before_linux())
+ * actually, we don't need to do anything about cache if not use d-cache in
+ * U-Boot. So, in this function we clean only MMU. by scsuh
+ *
+ * void	theLastJump(void *kernel, int arch_num, uint boot_params);
+ */
+#ifdef CONFIG_ENABLE_MMU
+	.globl theLastJump
+theLastJump:
+	mov	r9, r0
+	ldr	r3, =0xfff00000
+	ldr	r4, _TEXT_PHY_BASE
+	adr	r5, phy_last_jump
+	bic	r5, r5, r3
+	orr	r5, r5, r4
+	mov	pc, r5
+phy_last_jump:
+	/*
+	 * disable MMU stuff
+	 */
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+	mcr	p15, 0, r0, c1, c0, 0
+
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	mov	r0, #0
+	mov	pc, r9
+#endif
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ */
+
+	.macro	bad_save_user_regs
+	/* carve out a frame on current user stack */
+	sub	sp, sp, #S_FRAME_SIZE
+	/* Save user registers (now in svc mode) r0-r12 */
+	stmia	sp, {r0 - r12}
+
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
+	/* set base 2 words into abort stack */
+	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
+	/* get values for "aborted" pc and cpsr (into parm regs) */
+	ldmia	r2, {r2 - r3}
+	/* grab pointer to old stack */
+	add	r0, sp, #S_FRAME_SIZE
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	/* save sp_SVC, lr_SVC, pc, cpsr */
+	stmia	r5, {r0 - r3}
+	/* save current stack into r0 (param register) */
+	mov	r0, sp
+	.endm
+
+	.macro get_bad_stack
+	/* setup our mode stack (enter in banked mode) */
+	ldr	r13, _armboot_start
+	/* move past malloc pool */
+	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)
+	/* move to reserved a couple spots for abort stack */
+	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
+
+	/* save caller lr in position 0 of saved stack */
+	str	lr, [r13]
+	/* get the spsr */
+	mrs	lr, spsr
+	/* save spsr in position 1 of saved stack */
+	str	lr, [r13, #4]
+
+	/* prepare SVC-Mode */
+	mov	r13, #MODE_SVC
+	@ msr	spsr_c, r13
+	/* switch modes, make sure moves will execute */
+	msr	spsr, r13
+	/* capture return pc */
+	mov	lr, pc
+	/* jump to next instruction & switch modes. */
+	movs	pc, lr
+	.endm
+
+	.macro get_bad_stack_swi
+	/* space on current stack for scratch reg. */
+	sub	r13, r13, #4
+	/* save R0's value. */
+	str	r0, [r13]
+	/* get data regions start */
+	ldr	r0, _armboot_start
+	/* move past malloc pool */
+	sub	r0, r0, #(CONFIG_SYS_MALLOC_LEN)
+	/* move past gbl and a couple spots for abort stack */
+	sub	r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
+	/* save caller lr in position 0 of saved stack */
+	str	lr, [r0]
+	/* get the spsr */
+	mrs	r0, spsr
+	/* save spsr in position 1 of saved stack */
+	str	lr, [r0, #4]
+	/* restore r0 */
+	ldr	r0, [r13]
+	/* pop stack entry */
+	add	r13, r13, #4
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack_swi
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+#endif /* CONFIG_NAND_SPL */
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile
@@ -0,0 +1,44 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	+= aemif.o clock.o init.o mux.o timer.o wdt.o
+SOBJS	+= lowlevel_init.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
@@ -0,0 +1,93 @@
+/*
+ * TNETV107X: Asynchronous EMIF Configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define ASYNC_EMIF_BASE			TNETV107X_ASYNC_EMIF_CNTRL_BASE
+#define ASYNC_EMIF_CONFIG(cs)		(ASYNC_EMIF_BASE+0x10+(cs)*4)
+#define ASYNC_EMIF_ONENAND_CONTROL	(ASYNC_EMIF_BASE+0x5c)
+#define ASYNC_EMIF_NAND_CONTROL		(ASYNC_EMIF_BASE+0x60)
+#define ASYNC_EMIF_WAITCYCLE_CONFIG	(ASYNC_EMIF_BASE+0x4)
+
+#define CONFIG_SELECT_STROBE(v)		((v) ? 1 << 31 : 0)
+#define CONFIG_EXTEND_WAIT(v)		((v) ? 1 << 30 : 0)
+#define CONFIG_WR_SETUP(v)		(((v) & 0x0f) << 26)
+#define CONFIG_WR_STROBE(v)		(((v) & 0x3f) << 20)
+#define CONFIG_WR_HOLD(v)		(((v) & 0x07) << 17)
+#define CONFIG_RD_SETUP(v)		(((v) & 0x0f) << 13)
+#define CONFIG_RD_STROBE(v)		(((v) & 0x3f) << 7)
+#define CONFIG_RD_HOLD(v)		(((v) & 0x07) << 4)
+#define CONFIG_TURN_AROUND(v)		(((v) & 0x03) << 2)
+#define CONFIG_WIDTH(v)			(((v) & 0x03) << 0)
+
+#define NUM_CS				4
+
+#define set_config_field(reg, field, val)			\
+	do {							\
+		if (val != -1) {				\
+			reg &= ~CONFIG_##field(0xffffffff);	\
+			reg |=	CONFIG_##field(val);		\
+		}						\
+	} while (0)
+
+void configure_async_emif(int cs, struct async_emif_config *cfg)
+{
+	unsigned long tmp;
+
+	if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
+		tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
+
+	} else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
+		tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
+		tmp |= (1 << cs);
+		__raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
+	}
+
+	tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
+
+	set_config_field(tmp, SELECT_STROBE,	cfg->select_strobe);
+	set_config_field(tmp, EXTEND_WAIT,	cfg->extend_wait);
+	set_config_field(tmp, WR_SETUP,		cfg->wr_setup);
+	set_config_field(tmp, WR_STROBE,	cfg->wr_strobe);
+	set_config_field(tmp, WR_HOLD,		cfg->wr_hold);
+	set_config_field(tmp, RD_SETUP,		cfg->rd_setup);
+	set_config_field(tmp, RD_STROBE,	cfg->rd_strobe);
+	set_config_field(tmp, RD_HOLD,		cfg->rd_hold);
+	set_config_field(tmp, TURN_AROUND,	cfg->turn_around);
+	set_config_field(tmp, WIDTH,		cfg->width);
+
+	__raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
+}
+
+void init_async_emif(int num_cs, struct async_emif_config *config)
+{
+	int cs;
+
+	clk_enable(TNETV107X_LPSC_AEMIF);
+
+	for (cs = 0; cs < num_cs; cs++)
+		configure_async_emif(cs, config + cs);
+}
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -0,0 +1,451 @@
+/*
+ * TNETV107X: Clock management APIs
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm-generic/errno.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+
+#define CLOCK_BASE		TNETV107X_CLOCK_CONTROL_BASE
+#define PSC_BASE		TNETV107X_PSC_BASE
+
+#define BIT(x)			(1 << (x))
+
+#define MAX_PREDIV		64
+#define MAX_POSTDIV		8
+#define MAX_MULT		512
+#define MAX_DIV			(MAX_PREDIV * MAX_POSTDIV)
+
+/* LPSC registers */
+#define PSC_PTCMD		0x120
+#define PSC_PTSTAT		0x128
+#define PSC_MDSTAT(n)		(0x800 + (n) * 4)
+#define PSC_MDCTL(n)		(0xA00 + (n) * 4)
+
+#define PSC_MDCTL_LRSTZ		BIT(8)
+
+#define psc_reg_read(reg)	__raw_readl((u32 *)(PSC_BASE + (reg)))
+#define psc_reg_write(reg, val)	__raw_writel(val, (u32 *)(PSC_BASE + (reg)))
+
+/* SSPLL registers */
+struct sspll_regs {
+	u32	modes;
+	u32	postdiv;
+	u32	prediv;
+	u32	mult_factor;
+	u32	divider_range;
+	u32	bw_divider;
+	u32	spr_amount;
+	u32	spr_rate_div;
+	u32	diag;
+};
+
+/* SSPLL base addresses */
+static struct sspll_regs *sspll_regs[] = {
+	(struct sspll_regs *)(CLOCK_BASE + 0x040),
+	(struct sspll_regs *)(CLOCK_BASE + 0x080),
+	(struct sspll_regs *)(CLOCK_BASE + 0x0c0),
+};
+
+#define sspll_reg(pll, reg)		(&(sspll_regs[pll]->reg))
+#define sspll_reg_read(pll, reg)	__raw_readl(sspll_reg(pll, reg))
+#define sspll_reg_write(pll, reg, val)	__raw_writel(val, sspll_reg(pll, reg))
+
+
+/* PLL Control Registers */
+struct pllctl_regs {
+	u32	ctl;		/* 00 */
+	u32	ocsel;		/* 04 */
+	u32	secctl;		/* 08 */
+	u32	__pad0;
+	u32	mult;		/* 10 */
+	u32	prediv;		/* 14 */
+	u32	div1;		/* 18 */
+	u32	div2;		/* 1c */
+	u32	div3;		/* 20 */
+	u32	oscdiv1;	/* 24 */
+	u32	postdiv;	/* 28 */
+	u32	bpdiv;		/* 2c */
+	u32	wakeup;		/* 30 */
+	u32	__pad1;
+	u32	cmd;		/* 38 */
+	u32	stat;		/* 3c */
+	u32	alnctl;		/* 40 */
+	u32	dchange;	/* 44 */
+	u32	cken;		/* 48 */
+	u32	ckstat;		/* 4c */
+	u32	systat;		/* 50 */
+	u32	ckctl;		/* 54 */
+	u32	__pad2[2];
+	u32	div4;		/* 60 */
+	u32	div5;		/* 64 */
+	u32	div6;		/* 68 */
+	u32	div7;		/* 6c */
+	u32	div8;		/* 70 */
+};
+
+struct lpsc_map {
+	int	pll, div;
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+	(struct pllctl_regs *)(CLOCK_BASE + 0x700),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x300),
+	(struct pllctl_regs *)(CLOCK_BASE + 0x500),
+};
+
+#define pllctl_reg(pll, reg)		(&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg)	__raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val)	__raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val)			\
+	pllctl_reg_write(pll, reg,				\
+		(pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask)			\
+	pllctl_reg_rmw(pll, reg, mask, 0)
+
+/* PLLCTL Bits */
+#define PLLCTL_CLKMODE		BIT(8)
+#define PLLCTL_PLLSELB		BIT(7)
+#define PLLCTL_PLLENSRC		BIT(5)
+#define PLLCTL_PLLDIS		BIT(4)
+#define PLLCTL_PLLRST		BIT(3)
+#define PLLCTL_PLLPWRDN		BIT(1)
+#define PLLCTL_PLLEN		BIT(0)
+
+#define PLLDIV_ENABLE		BIT(15)
+
+static int pll_div_offset[] = {
+#define div_offset(reg)	offsetof(struct pllctl_regs, reg)
+	div_offset(div1), div_offset(div2), div_offset(div3),
+	div_offset(div4), div_offset(div5), div_offset(div6),
+	div_offset(div7), div_offset(div8),
+};
+
+static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
+static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
+
+/* Mappings from PLL+DIV to subsystem clocks */
+#define sys_arm1176_clk		{SYS_PLL, 0}
+#define sys_dsp_clk		{SYS_PLL, 1}
+#define sys_ddr_clk		{SYS_PLL, 2}
+#define sys_full_clk		{SYS_PLL, 3}
+#define sys_lcd_clk		{SYS_PLL, 4}
+#define sys_vlynq_ref_clk	{SYS_PLL, 5}
+#define sys_tsc_clk		{SYS_PLL, 6}
+#define sys_half_clk		{SYS_PLL, 7}
+
+#define eth_clk_5		{ETH_PLL, 0}
+#define eth_clk_50		{ETH_PLL, 1}
+#define eth_clk_125		{ETH_PLL, 2}
+#define eth_clk_250		{ETH_PLL, 3}
+#define eth_clk_25		{ETH_PLL, 4}
+
+#define tdm_clk			{TDM_PLL, 0}
+#define tdm_extra_clk		{TDM_PLL, 1}
+#define tdm1_clk		{TDM_PLL, 2}
+
+/* Optimization barrier */
+#define barrier()	\
+	__asm__ __volatile__("mov r0, r0\n" : : : "memory");
+
+static const struct lpsc_map lpsc_clk_map[] = {
+	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
+	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
+	[TNETV107X_LPSC_DDR2_PHY]		= sys_ddr_clk,
+	[TNETV107X_LPSC_TPCC]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC0]			= sys_full_clk,
+	[TNETV107X_LPSC_TPTC1]			= sys_full_clk,
+	[TNETV107X_LPSC_RAM]			= sys_full_clk,
+	[TNETV107X_LPSC_MBX_LITE]		= sys_arm1176_clk,
+	[TNETV107X_LPSC_LCD]			= sys_lcd_clk,
+	[TNETV107X_LPSC_ETHSS]			= eth_clk_125,
+	[TNETV107X_LPSC_AEMIF]			= sys_full_clk,
+	[TNETV107X_LPSC_CHIP_CFG]		= sys_half_clk,
+	[TNETV107X_LPSC_TSC]			= sys_tsc_clk,
+	[TNETV107X_LPSC_ROM]			= sys_half_clk,
+	[TNETV107X_LPSC_UART2]			= sys_half_clk,
+	[TNETV107X_LPSC_PKTSEC]			= sys_half_clk,
+	[TNETV107X_LPSC_SECCTL]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYMGR]			= sys_half_clk,
+	[TNETV107X_LPSC_KEYPAD]			= sys_half_clk,
+	[TNETV107X_LPSC_GPIO]			= sys_half_clk,
+	[TNETV107X_LPSC_MDIO]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART0]			= sys_half_clk,
+	[TNETV107X_LPSC_UART1]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER0]			= sys_half_clk,
+	[TNETV107X_LPSC_TIMER1]			= sys_half_clk,
+	[TNETV107X_LPSC_WDT_ARM]		= sys_half_clk,
+	[TNETV107X_LPSC_WDT_DSP]		= sys_half_clk,
+	[TNETV107X_LPSC_SSP]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM0]			= tdm_clk,
+	[TNETV107X_LPSC_VLYNQ]			= sys_vlynq_ref_clk,
+	[TNETV107X_LPSC_MCDMA]			= sys_half_clk,
+	[TNETV107X_LPSC_USB0]			= sys_half_clk,
+	[TNETV107X_LPSC_TDM1]			= tdm1_clk,
+	[TNETV107X_LPSC_DEBUGSS]		= sys_half_clk,
+	[TNETV107X_LPSC_ETHSS_RGMII]		= eth_clk_250,
+	[TNETV107X_LPSC_SYSTEM]			= sys_half_clk,
+	[TNETV107X_LPSC_IMCOP]			= sys_dsp_clk,
+	[TNETV107X_LPSC_SPARE]			= sys_half_clk,
+	[TNETV107X_LPSC_SDIO1]			= sys_half_clk,
+	[TNETV107X_LPSC_USB1]			= sys_half_clk,
+	[TNETV107X_LPSC_USBSS]			= sys_half_clk,
+	[TNETV107X_LPSC_DDR2_EMIF1_VRST]	= sys_ddr_clk,
+	[TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST]	= sys_ddr_clk,
+};
+
+static const unsigned long pll_ext_freq[] = {
+	[SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
+	[ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
+	[TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
+};
+
+static unsigned long pll_freq_get(int pll)
+{
+	unsigned long mult = 1, prediv = 1, postdiv = 1;
+	unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
+	unsigned long ret;
+	u32 bypass;
+
+	bypass = __raw_readl((u32 *)(CLOCK_BASE));
+	if (!(bypass & pll_bypass_mask[pll])) {
+		mult	= sspll_reg_read(pll, mult_factor);
+		prediv	= sspll_reg_read(pll, prediv) + 1;
+		postdiv	= sspll_reg_read(pll, postdiv) + 1;
+	}
+
+	if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
+		ref = pll_ext_freq[pll];
+
+	if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
+		return ref;
+
+	ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
+	ret /= (prediv * postdiv);
+
+	return ret;
+}
+
+static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
+					int div)
+{
+	int divider = 1;
+	unsigned long divreg;
+
+	divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
+
+	if (divreg & PLLDIV_ENABLE)
+		divider = (divreg & pll_div_mask[pll]) + 1;
+
+	return fpll / divider;
+}
+
+static unsigned long pll_div_freq_get(int pll, int div)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
+			       unsigned long hz)
+{
+	int divider = (fpll / hz - 1);
+
+	divider &= pll_div_mask[pll];
+	divider |= PLLDIV_ENABLE;
+
+	__raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
+	pllctl_reg_setbits(pll, alnctl, (1 << div));
+	pllctl_reg_setbits(pll, dchange, (1 << div));
+}
+
+static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
+{
+	unsigned int fpll = pll_freq_get(pll);
+
+	__pll_div_freq_set(pll, fpll, div, hz);
+
+	pllctl_reg_write(pll, cmd, 1);
+
+	/* Wait until new divider takes effect */
+	while (pllctl_reg_read(pll, stat) & 0x01);
+
+	return __pll_div_freq_get(pll, fpll, div);
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+	return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
+}
+
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
+{
+	unsigned long fpll, divider, pll;
+
+	pll = lpsc_clk_map[clk].pll;
+	fpll = pll_freq_get(pll);
+	divider = (fpll / hz - 1);
+	divider &= pll_div_mask[pll];
+
+	return fpll / (divider + 1);
+}
+
+int clk_set_rate(unsigned int clk, unsigned long _hz)
+{
+	unsigned long hz;
+
+	hz = clk_round_rate(clk, _hz);
+	if (hz != _hz)
+		return -EINVAL;	/* Cannot set to target freq */
+
+	pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
+	return 0;
+}
+
+void lpsc_control(int mod, unsigned long state, int lrstz)
+{
+	u32 mdctl;
+
+	mdctl = psc_reg_read(PSC_MDCTL(mod));
+	mdctl &= ~0x1f;
+	mdctl |= state;
+
+	if (lrstz == 0)
+		mdctl &= ~PSC_MDCTL_LRSTZ;
+	else if (lrstz == 1)
+		mdctl |= PSC_MDCTL_LRSTZ;
+
+	psc_reg_write(PSC_MDCTL(mod), mdctl);
+
+	psc_reg_write(PSC_PTCMD, 1);
+
+	/* wait for power domain transition to end */
+	while (psc_reg_read(PSC_PTSTAT) & 1);
+
+	/* Wait for module state change */
+	while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
+}
+
+int lpsc_status(unsigned int id)
+{
+	return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
+}
+
+static void init_pll(const struct pll_init_data *data)
+{
+	unsigned long fpll;
+	unsigned long best_pre = 0, best_post = 0, best_mult = 0;
+	unsigned long div, prediv, postdiv, mult;
+	unsigned long delta, actual;
+	long best_delta = -1;
+	int i;
+	u32 tmp;
+
+	if (data->pll == SYS_PLL)
+		return; /* cannot reconfigure system pll on the fly */
+
+	tmp = pllctl_reg_read(data->pll, ctl);
+	if (data->internal_osc) {
+		tmp &= ~PLLCTL_CLKMODE;
+		fpll = CONFIG_SYS_INT_OSC_FREQ;
+	} else {
+		tmp |= PLLCTL_CLKMODE;
+		fpll = pll_ext_freq[data->pll];
+	}
+	pllctl_reg_write(data->pll, ctl, tmp);
+
+	mult = data->pll_freq / fpll;
+	for (mult = MAX(mult, 1); mult <= MAX_MULT; mult++) {
+		div = (fpll * mult) / data->pll_freq;
+		if (div < 1 || div > MAX_DIV)
+			continue;
+
+		for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
+			prediv = div / postdiv;
+			if (prediv < 1 || prediv > MAX_PREDIV)
+				continue;
+
+			actual = (fpll / prediv) * (mult / postdiv);
+			delta = (actual - data->pll_freq);
+			if (delta < 0)
+				delta = -delta;
+			if ((delta < best_delta) || (best_delta == -1)) {
+				best_delta = delta;
+				best_mult = mult;
+				best_pre = prediv;
+				best_post = postdiv;
+				if (delta == 0)
+					goto done;
+			}
+		}
+	}
+done:
+
+	if (best_delta == -1) {
+		printf("pll cannot derive %lu from %lu\n",
+				data->pll_freq, fpll);
+		return;
+	}
+
+	fpll = fpll * best_mult;
+	fpll /= best_pre * best_post;
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
+
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
+
+	sspll_reg_write(data->pll, mult_factor,	(best_mult - 1) << 8);
+	sspll_reg_write(data->pll, prediv,	best_pre - 1);
+	sspll_reg_write(data->pll, postdiv,	best_post - 1);
+
+	for (i = 0; i < 10; i++)
+		if (data->div_freq[i])
+			__pll_div_freq_set(data->pll, fpll, i,
+					   data->div_freq[i]);
+
+	pllctl_reg_write(data->pll, cmd, 1);
+
+	/* Wait until pll "go" operation completes */
+	while (pllctl_reg_read(data->pll, stat) & 0x01);
+
+	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
+	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
+}
+
+void init_plls(int num_pll, struct pll_init_data *config)
+{
+	int i;
+
+	for (i = 0; i < num_pll; i++)
+		init_pll(&config[i]);
+}
--- a/arch/arm/cpu/arm1176/tnetv107x/init.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/init.c
@@ -0,0 +1,37 @@
+/*
+ * TNETV107X: Architecture initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void chip_configuration_unlock(void)
+{
+       __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
+       __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
+}
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+       chip_configuration_unlock();
+
+       return 0;
+}
--- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
+++ b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
@@ -0,0 +1,25 @@
+/*
+ * TNETV107X: Low-level pre-relocation initialization
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+	/* nothing for now, maybe needed for more exotic boot modes */
+	mov	pc, lr
--- a/arch/arm/cpu/arm1176/tnetv107x/mux.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/mux.c
@@ -0,0 +1,334 @@
+/*
+ * TNETV107X: Pinmux configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+
+#define MUX_MODE_1		0x00
+#define MUX_MODE_2		0x04
+#define MUX_MODE_3		0x0c
+#define MUX_MODE_4		0x1c
+
+#define MUX_DEBUG		0
+
+static const struct pin_config pin_table[] = {
+	/*		  reg	shift	mode	*/
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(0,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(1,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(2,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(3,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(4,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(4,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(5,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(6,	25,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(7,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(8,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(8,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	0,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	5,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	10,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(9,	20,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(10,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(11,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(11,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(12,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(13,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(14,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(15,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(15,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(16,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(16,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(17,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(18,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(19,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(19,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(20,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(20,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(21,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(22,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	20,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(22,	25,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(23,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(24,	25,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	0,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	5,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	10,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_3),
+	TNETV107X_MUX_CFG(25,	15,	MUX_MODE_4),
+	TNETV107X_MUX_CFG(26,	0,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	5,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	10,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	15,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	20,	MUX_MODE_2),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_1),
+	TNETV107X_MUX_CFG(26,	25,	MUX_MODE_2),
+};
+
+const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
+
+int mux_select_pin(short index)
+{
+	const struct pin_config *cfg;
+	unsigned long mask, mode, reg;
+
+	if (index >= pin_table_size)
+		return 0;
+
+	cfg = &pin_table[index];
+
+	mask = 0x1f << cfg->mask_offset;
+	mode = cfg->mode << cfg->mask_offset;
+
+	reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
+	reg = (reg & ~mask) | mode;
+	__raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
+
+	return 1;
+}
+
+int mux_select_pins(const short *pins)
+{
+	int i, ret = 1;
+
+	for (i = 0; pins[i] >= 0; i++)
+		ret &= mux_select_pin(pins[i]);
+
+	return ret;
+}
--- a/arch/arm/cpu/arm1176/tnetv107x/timer.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/timer.c
@@ -0,0 +1,122 @@
+/*
+ * TNETV107X: Timer implementation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+struct timer_regs {
+	u_int32_t pid12;
+	u_int32_t pad[3];
+	u_int32_t tim12;
+	u_int32_t tim34;
+	u_int32_t prd12;
+	u_int32_t prd34;
+	u_int32_t tcr;
+	u_int32_t tgcr;
+	u_int32_t wdtcr;
+};
+
+#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
+
+#define TIMER_LOAD_VAL	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define TIM_CLK_DIV	16
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init(void)
+{
+	clk_enable(TNETV107X_LPSC_TIMER0);
+
+	lastinc = timestamp = 0;
+
+	/* We are using timer34 in unchained 32-bit mode, full speed */
+	__raw_writel(0x0, &regs->tcr);
+	__raw_writel(0x0, &regs->tgcr);
+	__raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
+	__raw_writel(0x0, &regs->tim34);
+	__raw_writel(TIMER_LOAD_VAL, &regs->prd34);
+	__raw_writel(2 << 22, &regs->tcr);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	lastinc = timestamp = 0;
+
+	__raw_writel(0,		&regs->tcr);
+	__raw_writel(0,		&regs->tim34);
+	__raw_writel(2 << 22,	&regs->tcr);
+}
+
+static ulong get_timer_raw(void)
+{
+	ulong now = __raw_readl(&regs->tim34);
+
+	if (now >= lastinc)
+		timestamp += now - lastinc;
+	else
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
+
+	lastinc = now;
+
+	return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= (1000 * TIM_CLK_DIV);
+
+	endtime = get_timer_raw() + tmo;
+
+	do {
+		ulong now = get_timer_raw();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
--- a/arch/arm/cpu/arm1176/tnetv107x/wdt.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/wdt.c
@@ -0,0 +1,180 @@
+/*
+ * TNETV107X: Watchdog timer implementation (for reset)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#define MAX_DIV		0xFFFE0001
+
+struct wdt_regs {
+	u32 kick_lock;
+#define KICK_LOCK_1	0x5555
+#define KICK_LOCK_2	0xaaaa
+	u32 kick;
+
+	u32 change_lock;
+#define CHANGE_LOCK_1	0x6666
+#define CHANGE_LOCK_2	0xbbbb
+	u32 change;
+
+	u32 disable_lock;
+#define DISABLE_LOCK_1	0x7777
+#define DISABLE_LOCK_2	0xcccc
+#define DISABLE_LOCK_3	0xdddd
+	u32 disable;
+
+	u32 prescale_lock;
+#define PRESCALE_LOCK_1	0x5a5a
+#define PRESCALE_LOCK_2	0xa5a5
+	u32 prescale;
+};
+
+static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
+
+#define wdt_reg_read(reg)	__raw_readl(&regs->reg)
+#define wdt_reg_write(reg, val)	__raw_writel((val), &regs->reg)
+
+static int write_prescale_reg(unsigned long prescale_value)
+{
+	wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
+	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
+	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(prescale, prescale_value);
+
+	return 0;
+}
+
+static int write_change_reg(unsigned long initial_timer_value)
+{
+	wdt_reg_write(change_lock, CHANGE_LOCK_1);
+	if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(change_lock, CHANGE_LOCK_2);
+	if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(change, initial_timer_value);
+
+	return 0;
+}
+
+static int wdt_control(unsigned long disable_value)
+{
+	wdt_reg_write(disable_lock, DISABLE_LOCK_1);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(disable_lock, DISABLE_LOCK_2);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
+		return -1;
+
+	wdt_reg_write(disable_lock, DISABLE_LOCK_3);
+	if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(disable, disable_value);
+	return 0;
+}
+
+static int wdt_set_period(unsigned long msec)
+{
+	unsigned long change_value, count_value;
+	unsigned long prescale_value = 1;
+	unsigned long refclk_khz, maxdiv;
+	int ret;
+
+	refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
+	maxdiv = (MAX_DIV / refclk_khz);
+
+	if ((!msec) || (msec > maxdiv))
+		return -1;
+
+	count_value = refclk_khz * msec;
+	if (count_value > 0xffff) {
+		change_value = count_value / 0xffff + 1;
+		prescale_value = count_value / change_value;
+	} else {
+		change_value = count_value;
+	}
+
+	ret = write_prescale_reg(prescale_value - 1);
+	if (ret)
+		return ret;
+
+	ret = write_change_reg(change_value);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+unsigned long last_wdt = -1;
+
+int wdt_start(unsigned long msecs)
+{
+	int ret;
+	ret = wdt_control(0);
+	if (ret)
+		return ret;
+	ret = wdt_set_period(msecs);
+	if (ret)
+		return ret;
+	ret = wdt_control(1);
+	if (ret)
+		return ret;
+	ret = wdt_kick();
+	last_wdt = msecs;
+	return ret;
+}
+
+int wdt_stop(void)
+{
+	last_wdt = -1;
+	return wdt_control(0);
+}
+
+int wdt_kick(void)
+{
+	wdt_reg_write(kick_lock, KICK_LOCK_1);
+	if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
+		return -1;
+
+	wdt_reg_write(kick_lock, KICK_LOCK_2);
+	if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
+		return -1;
+
+	wdt_reg_write(kick, 1);
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	clk_enable(TNETV107X_LPSC_WDT_ARM);
+	wdt_start(1);
+	wdt_kick();
+}
--- a/arch/arm/cpu/arm1176/u-boot.lds
+++ b/arch/arm/cpu/arm1176/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/arm/cpu/arm1176/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
--- a/arch/arm/cpu/arm720t/Makefile
+++ b/arch/arm/cpu/arm720t/Makefile
--- a/arch/arm/cpu/arm720t/config.mk
+++ b/arch/arm/cpu/arm720t/config.mk
--- a/arch/arm/cpu/arm720t/cpu.c
+++ b/arch/arm/cpu/arm720t/cpu.c
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+#include <asm/proc-armv/ptrace.h>
+#include <asm/hardware.h>
+
+#ifndef CONFIG_NETARM
+/* we always count down the max. */
+#define TIMER_LOAD_VAL 0xffff
+/* macro to read the 16 bit timer */
+#define READ_TIMER (IO_TC1D & 0xffff)
+
+#ifdef CONFIG_LPC2292
+#undef READ_TIMER
+#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
+#endif
+
+#else
+#define IRQEN	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
+#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
+#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
+#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
+#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
+#endif
+
+#ifdef CONFIG_S3C4510B
+/* require interrupts for the S3C4510B */
+# ifndef CONFIG_USE_IRQ
+#  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
+# else
+static struct _irq_handler IRQ_HANDLER[N_IRQS];
+# endif
+#endif	/* CONFIG_S3C4510B */
+
+#ifdef CONFIG_USE_IRQ
+void do_irq (struct pt_regs *pt_regs)
+{
+#if defined(CONFIG_S3C4510B)
+	unsigned int pending;
+
+	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
+		IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
+
+		/* clear pending interrupt */
+		PUT_REG( REG_INTPEND, (1<<(pending>>2)));
+	}
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No do_irq() for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+
+    void (*pfnct)(void);
+
+    pfnct = (void (*)(void))VICVectAddr;
+
+    (*pfnct)();
+#else
+#error do_irq() not defined for this CPU type
+#endif
+}
+#endif
+
+#ifdef CONFIG_S3C4510B
+static void default_isr( void *data) {
+	printf ("default_isr():  called for IRQ %d\n", (int)data);
+}
+
+static void timer_isr( void *data) {
+	unsigned int *pTime = (unsigned int *)data;
+
+	(*pTime)++;
+	if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
+		/* toggle LED 0 */
+		PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
+	}
+
+}
+#endif
+
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* Use IntegratorAP routines in board/integratorap.c */
+#else
+
+static ulong timestamp;
+static ulong lastdec;
+
+#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
+int arch_interrupt_init (void)
+{
+	int i;
+
+	/* install default interrupt handlers */
+	for ( i = 0; i < N_IRQS; i++) {
+		IRQ_HANDLER[i].m_data = (void *)i;
+		IRQ_HANDLER[i].m_func = default_isr;
+	}
+
+	/* configure interrupts for IRQ mode */
+	PUT_REG( REG_INTMODE, 0x0);
+	/* clear any pending interrupts */
+	PUT_REG( REG_INTPEND, 0x1FFFFF);
+
+	lastdec = 0;
+
+	/* install interrupt handler for timer */
+	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
+	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
+
+	return 0;
+}
+#endif
+
+int timer_init (void)
+{
+#if defined(CONFIG_NETARM)
+	/* disable all interrupts */
+	IRQEN = 0;
+
+	/* operate timer 2 in non-prescale mode */
+	TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
+		    NETARM_GEN_TCTL_ENABLE |
+		    NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
+
+	/* set timer 2 counter */
+	lastdec = TIMER_LOAD_VAL;
+#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+	/* disable all interrupts */
+	IO_INTMR1 = 0;
+
+	/* operate timer 1 in prescale mode */
+	IO_SYSCON1 |= SYSCON1_TC1M;
+
+	/* select 2kHz clock source for timer 1 */
+	IO_SYSCON1 &= ~SYSCON1_TC1S;
+
+	/* set timer 1 counter */
+	lastdec = IO_TC1D = TIMER_LOAD_VAL;
+#elif defined(CONFIG_S3C4510B)
+	/* configure free running timer 0 */
+	PUT_REG( REG_TMOD, 0x0);
+	/* Stop timer 0 */
+	CLR_REG( REG_TMOD, TM0_RUN);
+
+	/* Configure for interval mode */
+	CLR_REG( REG_TMOD, TM1_TOGGLE);
+
+	/*
+	 * Load Timer data register with count down value.
+	 * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
+	 */
+	PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
+
+	/*
+	 * Enable global interrupt
+	 * Enable timer0 interrupt
+	 */
+	CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
+
+	/* Start timer */
+	SET_REG( REG_TMOD, TM0_RUN);
+#elif defined(CONFIG_LPC2292)
+	PUT32(T0IR, 0);		/* disable all timer0 interrupts */
+	PUT32(T0TCR, 0);	/* disable timer0 */
+	PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
+	PUT32(T0MCR, 0);
+	PUT32(T0TC, 0);
+	PUT32(T0TCR, 1);	/* enable timer0 */
+
+#else
+#error No timer_init() defined for this CPU type
+#endif
+	timestamp = 0;
+
+	return (0);
+}
+
+#endif /* ! IntegratorAP */
+
+/*
+ * timer without interrupts
+ */
+
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void __udelay (unsigned long usec)
+{
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CONFIG_SYS_HZ;
+	tmo /= 1000;
+
+	tmo += get_timer (0);
+
+	while (get_timer_masked () < tmo)
+#ifdef CONFIG_LPC2292
+		/* GJ - not sure whether this is really needed or a misunderstanding */
+		__asm__ __volatile__(" nop");
+#else
+		/*NOP*/;
+#endif
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	} else {
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+#elif defined(CONFIG_S3C4510B)
+
+ulong get_timer (ulong base)
+{
+	return timestamp - base;
+}
+
+void __udelay (unsigned long usec)
+{
+	u32 ticks;
+
+	ticks = (usec * CONFIG_SYS_HZ) / 1000000;
+
+	ticks += get_timer (0);
+
+	while (get_timer (0) < ticks)
+		/*NOP*/;
+
+}
+
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No timer routines for IntegratorAP/CM720T as yet */
+#else
+#error Timer routines not defined for this CPU type
+#endif
--- a/arch/arm/cpu/arm720t/lpc2292/Makefile
+++ b/arch/arm/cpu/arm720t/lpc2292/Makefile
--- a/arch/arm/cpu/arm720t/lpc2292/flash.c
+++ b/arch/arm/cpu/arm720t/lpc2292/flash.c
--- a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
+++ b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
--- a/arch/arm/cpu/arm720t/lpc2292/mmc.c
+++ b/arch/arm/cpu/arm720t/lpc2292/mmc.c
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
+++ b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
+++ b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
--- a/arch/arm/cpu/arm720t/lpc2292/spi.c
+++ b/arch/arm/cpu/arm720t/lpc2292/spi.c
--- a/arch/arm/cpu/arm720t/s3c4510b/Makefile
+++ b/arch/arm/cpu/arm720t/s3c4510b/Makefile
--- a/arch/arm/cpu/arm720t/s3c4510b/cache.c
+++ b/arch/arm/cpu/arm720t/s3c4510b/cache.c
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -0,0 +1,612 @@
+/*
+ *  armboot - Startup Code for ARM720 CPU-core
+ *
+ *  Copyright (c) 2001	Marius Gr<EFBFBD>ger <mag@sysgo.de>
+ *  Copyright (c) 2002	Alex Z<EFBFBD>pke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start: b	reset
+	ldr	pc, _undefined_instruction
+	ldr	pc, _software_interrupt
+	ldr	pc, _prefetch_abort
+	ldr	pc, _data_abort
+#ifdef CONFIG_LPC2292
+	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
+#else
+	ldr	pc, _not_used
+#endif
+	ldr	pc, _irq
+	ldr	pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt:	.word software_interrupt
+_prefetch_abort:	.word prefetch_abort
+_data_abort:		.word data_abort
+_not_used:		.word not_used
+_irq:			.word irq
+_fiq:			.word fiq
+
+	.balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from RAM!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+	.word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+	.word __bss_start
+
+.globl _bss_end
+_bss_end:
+	.word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+	.word	0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+	.word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+	/*
+	 * set the cpu to SVC32 mode
+	 */
+	mrs	r0,cpsr
+	bic	r0,r0,#0x1f
+	orr	r0,r0,#0x13
+	msr	cpsr,r0
+
+	/*
+	 * we do sys-critical inits only at reboot,
+	 * not when booting from ram!
+	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	bl	cpu_init_crit
+#endif
+
+#ifdef CONFIG_LPC2292
+	bl	lowlevel_init
+#endif
+
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+relocate:				/* relocate U-Boot to RAM	    */
+	adr	r0, _start		/* r0 <- current position of code   */
+	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
+	cmp	r0, r1			/* don't reloc during debug	    */
+	beq	stack_setup
+
+#if TEXT_BASE
+#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
+	ldr	r2, =0x0		/* Relocate the exception vectors   */
+	cmp	r1, r2			/* and associated data to address   */
+	ldmneia r0!, {r3-r10}		/* 0x0. Do nothing if TEXT_BASE is  */
+	stmneia r2!, {r3-r10}		/* 0x0. Copy the first 15 words.    */
+	ldmneia r0, {r3-r9}
+	stmneia r2, {r3-r9}
+	adrne	r0, _start		/* restore r0			    */
+#endif	/* !CONFIG_LPC2292 */
+#endif
+
+	ldr	r2, _armboot_start
+	ldr	r3, _bss_start
+	sub	r2, r3, r2		/* r2 <- size of armboot	    */
+	add	r2, r0, r2		/* r2 <- source end address	    */
+
+copy_loop:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */
+	ble	copy_loop
+
+#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
+
+	/* Set up the stack						    */
+stack_setup:
+	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area			    */
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo			    */
+#ifdef CONFIG_USE_IRQ
+	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
+	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
+
+clear_bss:
+	ldr	r0, _bss_start		/* find start of bss segment	    */
+	ldr	r1, _bss_end		/* stop here			    */
+	mov	r2, #0x00000000		/* clear			    */
+
+clbss_l:str	r2, [r0]		/* clear loop...		    */
+	add	r0, r0, #4
+	cmp	r0, r1
+	ble	clbss_l
+
+	ldr	pc, _start_armboot
+
+_start_armboot: .word start_armboot
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+
+/* Interupt-Controller base addresses */
+INTMR1:		.word	0x80000280 @ 32 bit size
+INTMR2:		.word	0x80001280 @ 16 bit size
+INTMR3:		.word	0x80002280 @  8 bit size
+
+/* SYSCONs */
+SYSCON1:	.word	0x80000100
+SYSCON2:	.word	0x80001100
+SYSCON3:	.word	0x80002200
+
+#define CLKCTL	       0x6  /* mask */
+#define CLKCTL_18      0x0  /* 18.432 MHz */
+#define CLKCTL_36      0x2  /* 36.864 MHz */
+#define CLKCTL_49      0x4  /* 49.152 MHz */
+#define CLKCTL_73      0x6  /* 73.728 MHz */
+
+#elif defined(CONFIG_LPC2292)
+PLLCFG_ADR:	.word	PLLCFG
+PLLFEED_ADR:	.word	PLLFEED
+PLLCON_ADR:	.word	PLLCON
+PLLSTAT_ADR:	.word	PLLSTAT
+VPBDIV_ADR:	.word	VPBDIV
+MEMMAP_ADR:	.word	MEMMAP
+
+#endif
+
+cpu_init_crit:
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+
+	/*
+	 * mask all IRQs by clearing all bits in the INTMRs
+	 */
+	mov	r1, #0x00
+	ldr	r0, INTMR1
+	str	r1, [r0]
+	ldr	r0, INTMR2
+	str	r1, [r0]
+	ldr	r0, INTMR3
+	str	r1, [r0]
+
+	/*
+	 * flush v4 I/D caches
+	 */
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+
+	/*
+	 * disable MMU stuff and caches
+	 */
+	mrc	p15,0,r0,c1,c0
+	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
+	bic	r0, r0, #0x0000008f	@ clear bits 7, 3:0 (B--- WCAM)
+	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
+	mcr	p15,0,r0,c1,c0
+#elif defined(CONFIG_NETARM)
+	/*
+	 * prior to software reset : need to set pin PORTC4 to be *HRESET
+	 */
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
+			NETARM_GEN_PORT_DIR(0x10))
+	str	r1, [r0, #+NETARM_GEN_PORTC]
+	/*
+	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
+	 *		    for an explanation of this process
+	 */
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
+	/*
+	 * setup PLL and System Config
+	 */
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+
+	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
+			NETARM_GEN_SYS_CFG_BUSFULL | \
+			NETARM_GEN_SYS_CFG_USER_EN | \
+			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
+			NETARM_GEN_SYS_CFG_BUSARB_INT | \
+			NETARM_GEN_SYS_CFG_BUSMON_EN )
+
+	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
+
+#ifndef CONFIG_NETARM_PLL_BYPASS
+	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
+			NETARM_GEN_PLL_CTL_POLTST_DEF | \
+			NETARM_GEN_PLL_CTL_INDIV(1) | \
+			NETARM_GEN_PLL_CTL_ICP_DEF | \
+			NETARM_GEN_PLL_CTL_OUTDIV(2) )
+	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
+#endif
+
+	/*
+	 * mask all IRQs by clearing all bits in the INTMRs
+	 */
+	mov	r1, #0
+	ldr	r0, =NETARM_GEN_MODULE_BASE
+	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
+
+#elif defined(CONFIG_S3C4510B)
+
+	/*
+	 * Mask off all IRQ sources
+	 */
+	ldr	r1, =REG_INTMASK
+	ldr	r0, =0x3FFFFF
+	str	r0, [r1]
+
+	/*
+	 * Disable Cache
+	 */
+	ldr r0, =REG_SYSCFG
+	ldr r1, =0x83ffffa0	/* cache-disabled  */
+	str r1, [r0]
+
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No specific initialisation for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+	/* Set-up PLL */
+	mov	r3, #0xAA
+	mov	r4, #0x55
+	/* First disconnect and disable the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x00
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Set new M and P values */
+	ldr	r0, PLLCFG_ADR
+	mov	r1, #0x23	/* M=4 and P=2 */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Then enable the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x01	/* PLL enable bit */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Wait for the lock */
+	ldr	r0, PLLSTAT_ADR
+	mov	r1, #0x400	/* lock bit */
+lock_loop:
+	ldr	r2, [r0]
+	and	r2, r1, r2
+	cmp	r2, #0
+	beq	lock_loop
+	/* And finally connect the PLL */
+	ldr	r0, PLLCON_ADR
+	mov	r1, #0x03	/* PLL enable bit and connect bit */
+	str	r1, [r0]
+	ldr	r0, PLLFEED_ADR /* start feed sequence */
+	str	r3, [r0]
+	str	r4, [r0]	/* feed sequence done */
+	/* Set-up VPBDIV register */
+	ldr	r0, VPBDIV_ADR
+	mov	r1, #0x01	/* VPB clock is same as process clock */
+	str	r1, [r0]
+#else
+#error No cpu_init_crit() defined for current CPU type
+#endif
+
+#ifdef CONFIG_ARM7_REVD
+	/* set clock speed */
+	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
+	/* !!! not doing DRAM refresh properly! */
+	ldr	r0, SYSCON3
+	ldr	r1, [r0]
+	bic	r1, r1, #CLKCTL
+	orr	r1, r1, #CLKCTL_36
+	str	r1, [r0]
+#endif
+
+#ifndef CONFIG_LPC2292
+	mov	ip, lr
+	/*
+	 * before relocating, we have to setup RAM timing
+	 * because memory timing is board-dependent, you will
+	 * find a lowlevel_init.S in your board directory.
+	 */
+	bl	lowlevel_init
+	mov	lr, ip
+#endif
+
+	mov	pc, lr
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE	72
+
+#define S_OLD_R0	68
+#define S_PSR		64
+#define S_PC		60
+#define S_LR		56
+#define S_SP		52
+
+#define S_IP		48
+#define S_FP		44
+#define S_R10		40
+#define S_R9		36
+#define S_R8		32
+#define S_R7		28
+#define S_R6		24
+#define S_R5		20
+#define S_R4		16
+#define S_R3		12
+#define S_R2		8
+#define S_R1		4
+#define S_R0		0
+
+#define MODE_SVC 0x13
+#define I_BIT	 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+	.macro	bad_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC
+
+	ldr	r2, _armboot_start
+	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)	@ set base 2 words into abort stack
+	ldmia	r2, {r2 - r4}			@ get pc, cpsr, old_r0
+	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
+
+	add	r5, sp, #S_SP
+	mov	r1, lr
+	stmia	r5, {r0 - r4}			@ save sp_SVC, lr_SVC, pc, cpsr, old_r
+	mov	r0, sp
+	.endm
+
+	.macro	irq_save_user_regs
+	sub	sp, sp, #S_FRAME_SIZE
+	stmia	sp, {r0 - r12}			@ Calling r0-r12
+	add	r8, sp, #S_PC
+	stmdb	r8, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r8, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r8, #4]			@ Save CPSR
+	str	r0, [r8, #8]			@ Save OLD_R0
+	mov	r0, sp
+	.endm
+
+	.macro	irq_restore_user_regs
+	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
+	mov	r0, r0
+	ldr	lr, [sp, #S_PC]			@ Get PC
+	add	sp, sp, #S_FRAME_SIZE
+	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	.endm
+
+	.macro get_bad_stack
+	ldr	r13, _armboot_start		@ setup our mode stack
+	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+
+	str	lr, [r13]			@ save caller lr / spsr
+	mrs	lr, spsr
+	str	lr, [r13, #4]
+
+	mov	r13, #MODE_SVC			@ prepare SVC-Mode
+	msr	spsr_c, r13
+	mov	lr, pc
+	movs	pc, lr
+	.endm
+
+	.macro get_irq_stack			@ setup IRQ stack
+	ldr	sp, IRQ_STACK_START
+	.endm
+
+	.macro get_fiq_stack			@ setup FIQ stack
+	ldr	sp, FIQ_STACK_START
+	.endm
+
+/*
+ * exception handlers
+ */
+	.align	5
+undefined_instruction:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_undefined_instruction
+
+	.align	5
+software_interrupt:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_software_interrupt
+
+	.align	5
+prefetch_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_prefetch_abort
+
+	.align	5
+data_abort:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_data_abort
+
+	.align	5
+not_used:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+	.align	5
+irq:
+	get_irq_stack
+	irq_save_user_regs
+	bl	do_irq
+	irq_restore_user_regs
+
+	.align	5
+fiq:
+	get_fiq_stack
+	/* someone ought to write a more effiction fiq_save_user_regs */
+	irq_save_user_regs
+	bl	do_fiq
+	irq_restore_user_regs
+
+#else
+
+	.align	5
+irq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_irq
+
+	.align	5
+fiq:
+	get_bad_stack
+	bad_save_user_regs
+	bl	do_fiq
+
+#endif
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	mov	ip, #0
+	mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
+	mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
+	mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
+	bic	ip, ip, #0x000f			@ ............wcam
+	bic	ip, ip, #0x2100			@ ..v....s........
+	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
+	mov	pc, r0
+#elif defined(CONFIG_NETARM)
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, =NETARM_MEM_MODULE_BASE
+	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
+	ldr	r1, =0xFFFFF000
+	and	r0, r1, r0
+	ldr	r1, =(relocate-TEXT_BASE)
+	add	r0, r1, r0
+	ldr	r4, =NETARM_GEN_MODULE_BASE
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
+	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
+	mov	pc, r0
+#elif defined(CONFIG_S3C4510B)
+/* Nothing done here as reseting the CPU is board specific, depending
+ * on external peripherals such as watchdog timers, etc. */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+	/* No specific reset actions for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_LPC2292)
+	.align	5
+.globl reset_cpu
+reset_cpu:
+	mov	pc, r0
+#else
+#error No reset_cpu() defined for current CPU type
+#endif
--- a/arch/arm/cpu/arm720t/u-boot.lds
+++ b/arch/arm/cpu/arm720t/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		arch/arm/cpu/arm720t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+	_end = .;
+}
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
--- a/arch/arm/cpu/arm920t/a320/Makefile
+++ b/arch/arm/cpu/arm920t/a320/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+SOBJS	+= reset.o
+COBJS	+= timer.o
+COBJS	+= ftsmc020.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/arch/arm/cpu/arm920t/a320/ftsmc020.c
+++ b/arch/arm/cpu/arm920t/a320/ftsmc020.c
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ftsmc020.h>
+
+struct ftsmc020_config {
+	unsigned int	config;
+	unsigned int	timing;
+};
+
+static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
+
+static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
+
+static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config *cfg)
+{
+	if (bank > 3) {
+		printf("bank # %u invalid\n", bank);
+		return;
+	}
+
+	writel(cfg->config, &smc->bank[bank].cr);
+	writel(cfg->timing, &smc->bank[bank].tpr);
+}
+
+void ftsmc020_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(config); i++)
+		ftsmc020_setup_bank(i, &config[i]);
+}
--- a/arch/arm/cpu/arm920t/a320/reset.S
+++ b/arch/arm/cpu/arm920t/a320/reset.S
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+.global reset_cpu
+reset_cpu:
+	b	reset_cpu
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ b/arch/arm/cpu/arm920t/a320/timer.c
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ftpmu010.h>
+#include <asm/arch/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+
+#define TIMER_CLOCK	32768
+#define TIMER_LOAD_VAL	0xffffffff
+
+int timer_init(void)
+{
+	unsigned int oscc;
+	unsigned int cr;
+
+	debug("%s()\n", __func__);
+
+	/* disable timers */
+	writel(0, &tmr->cr);
+
+	/*
+	 * use 32768Hz oscillator for RTC, WDT, TIMER
+	 */
+
+	/* enable the 32768Hz oscillator */
+	oscc = readl(&pmu->OSCC);
+	oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
+	writel(oscc, &pmu->OSCC);
+
+	/* wait until ready */
+	while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
+		;
+
+	/* select 32768Hz oscillator */
+	oscc = readl(&pmu->OSCC);
+	oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
+	writel(oscc, &pmu->OSCC);
+
+	/* setup timer */
+	writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+	writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+	writel(0, &tmr->timer3_match1);
+	writel(0, &tmr->timer3_match2);
+
+	/* we don't want timer to issue interrupts */
+	writel(FTTMR010_TM3_MATCH1 |
+	       FTTMR010_TM3_MATCH2 |
+	       FTTMR010_TM3_OVERFLOW,
+	       &tmr->interrupt_mask);
+
+	cr = readl(&tmr->cr);
+	cr |= FTTMR010_TM3_CLOCK;	/* use external clock */
+	cr |= FTTMR010_TM3_ENABLE;
+	writel(cr, &tmr->cr);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+	/* capure current decrementer value time */
+	lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+
+	debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+	debug("%s()\n", __func__);
+	reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+	debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+	if (lastdec >= now) {
+		/*
+		 * normal mode (non roll)
+		 * move stamp fordward with absoulte diff ticks
+		 */
+		timestamp += lastdec - now;
+	} else {
+		/*
+		 * we have overflow of the count down timer
+		 *
+		 * nts = ts + ld + (TLV - now)
+		 * ts=old stamp, ld=time that passed before passing through -1
+		 * (TLV-now) amount of time after passing though -1
+		 * nts = new "advancing time stamp"...it could also roll and
+		 * cause problems.
+		 */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+
+	lastdec = now;
+
+	debug("%s() returns %lx\n", __func__, timestamp);
+
+	return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+	debug("%s(%lx)\n", __func__, base);
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	debug("%s(%lx)\n", __func__, t);
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	unsigned long now, last = readl(&tmr->timer3_counter);
+
+	debug("%s(%lu)\n", __func__, usec);
+	while (tmo > 0) {
+		now = readl(&tmr->timer3_counter);
+		if (now > last) /* count down timer overflow */
+			tmo -= TIMER_LOAD_VAL + last - now;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	debug("%s()\n", __func__);
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	debug("%s()\n", __func__);
+	return CONFIG_SYS_HZ;
+}
--- a/arch/arm/cpu/arm920t/at91/Makefile
+++ b/arch/arm/cpu/arm920t/at91/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+SOBJS	+= lowlevel_init.o
+COBJS	+= reset.o
+COBJS	+= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/at91/lowlevel_init.S
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+#define ARM920T_CONTROL	0xC0000000	/* @ set bit 31 (iA) and 30 (nF) */
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+	.word	TEXT_BASE-PHYS_FLASH_1
+#else
+	.word	TEXT_BASE
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr     r1, =AT91_ASM_PMC_MOR
+	/* Main oscillator Enable register */
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
+	ldr     r0, =0x0000FF01		/* Enable main oscillator */
+#else
+	ldr     r0, =0x0000FF00		/* Disable main oscillator */
+#endif
+	str     r0, [r1] /*AT91C_CKGR_MOR] */
+	/* Add loop to compensate Main Oscillator startup time */
+	ldr     r0, =0x00000010
+LoopOsc:
+	subs    r0, r0, #1
+	bhi     LoopOsc
+
+	/* memory control configuration */
+	/* this isn't very elegant, but	 what the heck */
+	ldr	r0, =SMRDATA
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #80
+pllloop:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	pllloop
+	/* delay - this is all done by guess */
+	ldr	r0, =0x00010000
+	/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
+lock:
+	subs	r0, r0, #1
+	bhi	lock
+	ldr	r0, =SMRDATA1
+	ldr	r1, _MTEXT_BASE
+	sub	r0, r0, r1
+	add	r2, r0, #176
+sdinit:
+	/* the address */
+	ldr	r1, [r0], #4
+	/* the value */
+	ldr	r3, [r0], #4
+	str	r3, [r1]
+	cmp	r2, r0
+	bne	sdinit
+
+	/* switch from FastBus to Asynchronous clock mode */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #ARM920T_CONTROL
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/* everything is fine now */
+	mov	pc, lr
+
+	.ltorg
+
+SMRDATA:
+	.word AT91_ASM_MC_EBI_CFG
+	.word CONFIG_SYS_EBI_CFGR_VAL
+	.word AT91_ASM_MC_SMC_CSR0
+	.word CONFIG_SYS_SMC_CSR0_VAL
+	.word AT91_ASM_PMC_PLLAR
+	.word CONFIG_SYS_PLLAR_VAL
+	.word AT91_ASM_PMC_PLLBR
+	.word CONFIG_SYS_PLLBR_VAL
+	.word AT91_ASM_PMC_MCKR
+	.word CONFIG_SYS_MCKR_VAL
+	/* here there's a delay */
+SMRDATA1:
+	.word AT91_ASM_PIOC_ASR
+	.word CONFIG_SYS_PIOC_ASR_VAL
+	.word AT91_ASM_PIOC_BSR
+	.word CONFIG_SYS_PIOC_BSR_VAL
+	.word AT91_ASM_PIOC_PDR
+	.word CONFIG_SYS_PIOC_PDR_VAL
+	.word AT91_ASM_MC_EBI_CSA
+	.word CONFIG_SYS_EBI_CSA_VAL
+	.word AT91_ASM_MC_SDRAMC_CR
+	.word CONFIG_SYS_SDRC_CR_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL1
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL2
+	.word CONFIG_SYS_SDRAM1
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_TR
+	.word CONFIG_SYS_SDRC_TR_VAL
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	.word AT91_ASM_MC_SDRAMC_MR
+	.word CONFIG_SYS_SDRC_MR_VAL3
+	.word CONFIG_SYS_SDRAM
+	.word CONFIG_SYS_SDRAM_VAL
+	/* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
--- a/arch/arm/cpu/arm920t/at91/reset.c
+++ b/arch/arm/cpu/arm920t/at91/reset.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_st.h>
+
+void board_reset(void) __attribute__((__weak__));
+
+void reset_cpu(ulong ignored)
+{
+	at91_st_t *st = (at91_st_t *) AT91_ST_BASE;
+#if defined(CONFIG_AT91RM9200_USART)
+	/*shutdown the console to avoid strange chars during reset */
+	serial_exit();
+#endif
+
+	if (board_reset)
+		board_reset();
+
+	/* Reset the cpu by setting up the watchdog timer */
+	writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
+		&st->wdmr);
+	writel(AT91_ST_CR_WDRST, &st->cr);
+	/* and let it timeout */
+	while (1)
+		;
+	/* Never reached */
+}
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ b/arch/arm/cpu/arm920t/at91/timer.c
@@ -0,0 +1,163 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/arch/at91_tc.h>
+#include <asm/arch/at91_pmc.h>
+
+/* the number of clocks per CONFIG_SYS_HZ */
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+
+static u32 timestamp;
+static u32 lastinc;
+
+int timer_init(void)
+{
+	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
+	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+	/* enables TC1.0 clock */
+	writel(1 << AT91_ID_TC0, &pmc->pcer);	/* enable clock */
+
+	writel(0, &tc->bcr);
+	writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
+		AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
+
+	writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
+	/* set to MCLK/2 and restart the timer
+	when the value in TC_RC is reached */
+	writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
+
+	writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
+	writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
+
+	writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
+	lastinc = 0;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
+	lastinc = readl(&tc->tc[0].cv) & 0x0000ffff;
+	timestamp = 0;
+}
+
+ulong get_timer_raw(void)
+{
+	at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE;
+	u32 now;
+
+	now = readl(&tc->tc[0].cv) & 0x0000ffff;
+
+	if (now >= lastinc) {
+		/* normal mode */
+		timestamp += now - lastinc;
+	} else {
+		/* we have an overflow ... */
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
+	}
+	lastinc = now;
+
+	return timestamp;
+}
+
+ulong get_timer_masked(void)
+{
+	return get_timer_raw()/TIMER_LOAD_VAL;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	u32 tmo;
+	u32 endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= 1000;
+
+	endtime = get_timer_raw() + tmo;
+
+	do {
+		u32 now = get_timer_raw();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
--- a/arch/arm/cpu/arm920t/at91rm9200/Makefile
+++ b/arch/arm/cpu/arm920t/at91rm9200/Makefile
--- a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
@@ -0,0 +1,232 @@
+/*
+ * Broadcom BCM5221 Ethernet PHY
+ *
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#ifdef CONFIG_DRIVER_ETHER
+
+#include <bcm5221.h>
+
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ *	bcm5221_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+	unsigned short Id1, Id2;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1);
+	at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) &&
+		((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK)))
+		return TRUE;
+
+	return FALSE;
+}
+
+/*
+ * Name:
+ *	bcm5221_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+	unsigned short stat1, stat2;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1))
+		return FALSE;
+
+	if (!(stat1 & BCM5221_LINK_STATUS))	/* link status up? */
+		return FALSE;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2))
+		return FALSE;
+
+	if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
+		/*set Emac for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
+		/*set MII for 100BaseTX and Half Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_SPD;
+		return TRUE;
+	}
+
+	if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
+		/*set MII for 10BaseT and Half Duplex  */
+		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	bcm5221_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac)
+{
+	unsigned char ret = TRUE;
+	unsigned short IntValue;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+
+	if (!bcm5221_GetLinkSpeed (p_mac)) {
+		/* Try another time */
+		ret = bcm5221_GetLinkSpeed (p_mac);
+	}
+
+	/* Disable PHY Interrupts */
+	at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue);
+	/* clear FDX LED and INTR Enable */
+	IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE);
+	/* set FDX, SPD, Link, INTR masks */
+	IntValue |= (BCM5221_FDX_MASK  | BCM5221_SPD_MASK |
+		     BCM5221_LINK_MASK | BCM5221_INTR_MASK);
+	at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	return (ret);
+}
+
+
+/*
+ * Name:
+ *	bcm5221_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+	unsigned short value;
+	unsigned short PhyAnar;
+	unsigned short PhyAnalpar;
+
+	/* Set bcm5221 control register */
+	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
+		return FALSE;
+	value &= ~BCM5221_AUTONEG;	/* remove autonegotiation enable */
+	value |=  BCM5221_ISOLATE;	/* Electrically isolate PHY */
+	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
+		return FALSE;
+
+	/* Set the Auto_negotiation Advertisement Register */
+	/* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+	PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX |
+		  BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3;
+	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar))
+		return FALSE;
+
+	/* Read the Control Register     */
+	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
+		return FALSE;
+
+	value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE;
+	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
+		return FALSE;
+	/* Restart Auto_negotiation  */
+	value |= BCM5221_RESTART_AUTONEG;
+	value &= ~BCM5221_ISOLATE;
+	if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
+		return FALSE;
+
+	/*check AutoNegotiate complete */
+	udelay (10000);
+	at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value);
+	if (!(value & BCM5221_AUTONEG_COMP))
+		return FALSE;
+
+	/* Get the AutoNeg Link partner base page */
+	if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar))
+		return FALSE;
+
+	if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) {
+		/*set MII for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+	return FALSE;
+}
+
+#endif
+
+#endif	/* CONFIG_DRIVER_ETHER */
--- a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#ifdef CONFIG_DRIVER_ETHER
+#include <dm9161.h>
+
+#if defined(CONFIG_CMD_NET)
+
+/*
+ * Name:
+ *	dm9161_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+	unsigned short Id1, Id2;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
+		((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+		return TRUE;
+
+	return FALSE;
+}
+
+/*
+ * Name:
+ *	dm9161_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+	unsigned short stat1, stat2;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+		return FALSE;
+
+	if (!(stat1 & DM9161_LINK_STATUS))	/* link status up? */
+		return FALSE;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+		return FALSE;
+
+	if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+		/*set Emac for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) {
+		/*set MII for 100BaseTX and Half Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_SPD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+		/*set MII for 10BaseT and Half Duplex  */
+		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	dm9161_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+{
+	UCHAR ret = TRUE;
+	unsigned short IntValue;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+
+	if (!dm9161_GetLinkSpeed (p_mac)) {
+		/* Try another time */
+		ret = dm9161_GetLinkSpeed (p_mac);
+	}
+
+	/* Disable PHY Interrupts */
+	at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
+	/* set FDX, SPD, Link, INTR masks */
+	IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
+			DM9161_LINK_MASK | DM9161_INTR_MASK);
+	at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	return (ret);
+}
+
+
+/*
+ * Name:
+ *	dm9161_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+	unsigned short value;
+	unsigned short PhyAnar;
+	unsigned short PhyAnalpar;
+
+	/* Set dm9161 control register */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	value &= ~DM9161_AUTONEG;	/* remove autonegotiation enable */
+	value |= DM9161_ISOLATE;	/* Electrically isolate PHY */
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/* Set the Auto_negotiation Advertisement Register	*/
+	/* MII advertising for Next page, 100BaseTxFD and HD,	*/
+	/* 10BaseTFD and HD, IEEE 802.3 */
+	PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
+			DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+		return FALSE;
+
+	/* Read the Control Register     */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	/* Restart Auto_negotiation  */
+	value |= DM9161_RESTART_AUTONEG;
+	value &= ~DM9161_ISOLATE;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/*check AutoNegotiate complete */
+	udelay (10000);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
+	if (!(value & DM9161_AUTONEG_COMP))
+		return FALSE;
+
+	/* Get the AutoNeg Link partner base page */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+		return FALSE;
+
+	if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+		/*set MII for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+	return FALSE;
+}
+
+#endif
+
+#endif	/* CONFIG_DRIVER_ETHER */
--- a/arch/arm/cpu/arm920t/at91rm9200/ether.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/ether.c
--- a/arch/arm/cpu/arm920t/at91rm9200/i2c.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/i2c.c
--- a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
--- a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
--- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
--- a/arch/arm/cpu/arm920t/at91rm9200/reset.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/reset.c
--- a/arch/arm/cpu/arm920t/at91rm9200/spi.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/spi.c
--- a/arch/arm/cpu/arm920t/at91rm9200/timer.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/timer.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <asm/io.h>*/
+#include <asm/arch/hardware.h>
+/*#include <asm/proc/ptrace.h>*/
+
+/* the number of clocks per CONFIG_SYS_HZ */
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
+AT91PS_TC tmr;
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init (void)
+{
+	tmr = AT91C_BASE_TC0;
+
+	/* enables TC1.0 clock */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_TC0;  /* enable clock */
+
+	*AT91C_TCB0_BCR = 0;
+	*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
+	tmr->TC_CCR = AT91C_TC_CLKDIS;
+#define AT91C_TC_CMR_CPCTRG (1 << 14)
+	/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
+	tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
+
+	tmr->TC_IDR = ~0ul;
+	tmr->TC_RC = TIMER_LOAD_VAL;
+	lastinc = 0;
+	tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
+	timestamp = 0;
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void __udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_raw (void)
+{
+	ulong now = READ_TIMER;
+
+	if (now >= lastinc) {
+		/* normal mode */
+		timestamp += now - lastinc;
+	} else {
+		/* we have an overflow ... */
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
+	}
+	lastinc = now;
+
+	return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+	return get_timer_raw()/TIMER_LOAD_VAL;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= 1000;
+
+	endtime = get_timer_raw () + tmo;
+
+	do {
+		ulong now = get_timer_raw ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
--- a/arch/arm/cpu/arm920t/at91rm9200/usb.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/usb.c
--- a/arch/arm/cpu/arm920t/config.mk
+++ b/arch/arm/cpu/arm920t/config.mk
--- a/arch/arm/cpu/arm920t/cpu.c
+++ b/arch/arm/cpu/arm920t/cpu.c
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_AT91_LEGACY
+#warning Your board is using legacy AT91RM9200 SoC access. Please update!
+#endif
+
+static void cache_flush(void);
+
+int cleanup_before_linux (void)
+{
+	/*
+	 * this function is called just before we call linux
+	 * it prepares the processor for linux
+	 *
+	 * we turn off caches etc ...
+	 */
+
+	disable_interrupts ();
+
+	/* turn off I/D-cache */
+	icache_disable();
+	dcache_disable();
+	/* flush I/D-cache */
+	cache_flush();
+
+	return 0;
+}
+
+/* flush I/D-cache */
+static void cache_flush (void)
+{
+	unsigned long i = 0;
+
+	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+}
--- a/arch/arm/cpu/arm920t/ep93xx/Makefile
+++ b/arch/arm/cpu/arm920t/ep93xx/Makefile
@@ -0,0 +1,55 @@
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath@gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS   = cpu.o led.o speed.o timer.o
+SOBJS   = lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:    $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/arch/arm/cpu/arm920t/ep93xx/cpu.c
+++ b/arch/arm/cpu/arm920t/ep93xx/cpu.c
@@ -0,0 +1,51 @@
+/*
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.	See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	uint32_t value;
+
+	/* Unlock DeviceCfg and set SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value |= SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Unlock DeviceCfg and clear SWRST */
+	writel(0xAA, &syscon->sysswlock);
+	value = readl(&syscon->devicecfg);
+	value &= ~SYSCON_DEVICECFG_SWRST;
+	writel(value, &syscon->devicecfg);
+
+	/* Dying... */
+	while (1)
+		; /* noop */
+}
--- a/arch/arm/cpu/arm920t/ep93xx/led.c
+++ b/arch/arm/cpu/arm920t/ep93xx/led.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2010, 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/arch/ep93xx.h>
+#include <config.h>
+#include <status_led.h>
+
+static uint8_t saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+static uint32_t gpio_pin[2] = {1 << STATUS_LED_GREEN,
+			       1 << STATUS_LED_RED};
+
+inline void switch_LED_on(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) | gpio_pin[led], &gpio->pedr);
+	saved_state[led] = STATUS_LED_ON;
+}
+
+inline void switch_LED_off(uint8_t led)
+{
+	register struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
+
+	writel(readl(&gpio->pedr) & ~gpio_pin[led], &gpio->pedr);
+	saved_state[led] = STATUS_LED_OFF;
+}
+
+void red_LED_on(void)
+{
+	switch_LED_on(STATUS_LED_RED);
+}
+
+void red_LED_off(void)
+{
+	switch_LED_off(STATUS_LED_RED);
+}
+
+void green_LED_on(void)
+{
+	switch_LED_on(STATUS_LED_GREEN);
+}
+
+void green_LED_off(void)
+{
+	switch_LED_off(STATUS_LED_GREEN);
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+			red_LED_off();
+		else
+			red_LED_on();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_GREEN])
+			green_LED_off();
+		else
+			green_LED_on();
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
+			red_LED_on();
+		else
+			red_LED_off();
+	} else if (STATUS_LED_GREEN == mask) {
+		if (STATUS_LED_ON == state)
+			green_LED_on();
+		else
+			green_LED_off();
+	}
+}
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -0,0 +1,65 @@
+/*
+ * Low-level initialization for EP93xx
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <version.h>
+#include <asm/arch/ep93xx.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* backup return address */
+	ldr r1, =SYSCON_SCRATCH0
+	str lr, [r1]
+
+	/* Turn on both LEDs */
+	bl red_LED_on
+	bl green_LED_on
+
+	/* Configure flash wait states before we switch to the PLL */
+	bl flash_cfg
+
+	/* Set up PLL */
+	bl pll_cfg
+
+	/* Turn off the Green LED and leave the Red LED on */
+	bl green_LED_off
+
+	/* Setup SDRAM */
+	bl sdram_cfg
+
+	/* Turn on Green LED, Turn off the Red LED */
+	bl green_LED_on
+	bl red_LED_off
+
+	/* FIXME: we use async mode for now */
+	mrc p15, 0, r0, c1, c0, 0
+	orr r0, r0, #0xc0000000
+	mcr p15, 0, r0, c1, c0, 0
+
+	/* restore return address */
+	ldr r1, =SYSCON_SCRATCH0
+	ldr lr, [r1]
+
+	mov pc, lr
--- a/arch/arm/cpu/arm920t/ep93xx/speed.c
+++ b/arch/arm/cpu/arm920t/ep93xx/speed.c
@@ -0,0 +1,110 @@
+/*
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+/*
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+
+/*
+ * return the PLL output frequency
+ *
+ * PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * / (X2IPD + 1) / 2^PS
+ */
+static ulong get_PLLCLK(uint32_t *pllreg)
+{
+	uint8_t i;
+	const uint32_t clkset = readl(pllreg);
+	uint64_t rate = CONFIG_SYS_CLK_FREQ;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
+	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
+	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
+		rate >>= 1;
+
+	return (ulong)rate;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK()
+{
+	const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t fclk_div =
+		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
+	const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
+
+	return fclk_rate;
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t hclk_div =
+		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
+	const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
+
+	return hclk_rate;
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+
+	const uint32_t clkset1 = readl(&syscon->clkset1);
+	const uint8_t pclk_div =
+		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
+	const ulong pclk_rate = get_HCLK() / pclk_div;
+
+	return pclk_rate;
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
+	ulong uclk_rate;
+
+	const uint32_t value = readl(&syscon->pwrcnt);
+	if (value & SYSCON_PWRCNT_UART_BAUD)
+		uclk_rate = CONFIG_SYS_CLK_FREQ;
+	else
+		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+
+	return uclk_rate;
+}
--- a/arch/arm/cpu/arm920t/ep93xx/timer.c
+++ b/arch/arm/cpu/arm920t/ep93xx/timer.c
@@ -0,0 +1,143 @@
+/*
+ * Cirrus Logic EP93xx timer support.
+ *
+ * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define TIMER_CLKSEL	(1 << 3)
+#define TIMER_ENABLE	(1 << 7)
+
+#define TIMER_FREQ			508469		/* ticks / second */
+#define TIMER_MAX_VAL			0xFFFFFFFF
+
+static struct ep93xx_timer
+{
+	unsigned long long ticks;
+	unsigned long last_read;
+} timer;
+
+static inline unsigned long long usecs_to_ticks(unsigned long usecs)
+{
+	unsigned long long ticks = (unsigned long long)usecs * TIMER_FREQ;
+	do_div(ticks, 1000 * 1000);
+
+	return ticks;
+}
+
+static inline void read_timer(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+	const unsigned long now = TIMER_MAX_VAL - readl(&timer_regs->timer3.value);
+
+	if (now >= timer.last_read)
+		timer.ticks += now - timer.last_read;
+	else
+		/* an overflow occurred */
+		timer.ticks += TIMER_MAX_VAL - timer.last_read + now;
+
+	timer.last_read = now;
+}
+
+/*
+ * Get the number of ticks (in CONFIG_SYS_HZ resolution)
+ */
+unsigned long long get_ticks(void)
+{
+	unsigned long long sys_ticks;
+
+	read_timer();
+
+	sys_ticks = timer.ticks * CONFIG_SYS_HZ;
+	do_div(sys_ticks, TIMER_FREQ);
+
+	return sys_ticks;
+}
+
+unsigned long get_timer_masked(void)
+{
+	return get_ticks();
+}
+
+unsigned long get_timer(unsigned long base)
+{
+	return get_timer_masked() - base;
+}
+
+void reset_timer_masked(void)
+{
+	read_timer();
+	timer.ticks = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long target;
+
+	read_timer();
+
+	target = timer.ticks + usecs_to_ticks(usec);
+
+	while (timer.ticks < target)
+		read_timer();
+}
+
+int timer_init(void)
+{
+	struct timer_regs *timer_regs = (struct timer_regs *)TIMER_BASE;
+
+	/* use timer 3 with 508KHz and free running, not enabled now */
+	writel(TIMER_CLKSEL, &timer_regs->timer3.control);
+
+	/* set initial timer value */
+	writel(TIMER_MAX_VAL, &timer_regs->timer3.load);
+
+	/* Enable the timer */
+	writel(TIMER_ENABLE | TIMER_CLKSEL,
+		&timer_regs->timer3.control);
+
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  arch/arm/cpu/arm920t/start.o	(.text)
+		/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
+	  . = 0x1000;
+	  LONG(0x53555243)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/arch/arm/cpu/arm920t/imx/Makefile
+++ b/arch/arm/cpu/arm920t/imx/Makefile
--- a/arch/arm/cpu/arm920t/imx/generic.c
+++ b/arch/arm/cpu/arm920t/imx/generic.c
--- a/arch/arm/cpu/arm920t/imx/speed.c
+++ b/arch/arm/cpu/arm920t/imx/speed.c
--- a/arch/arm/cpu/arm920t/imx/timer.c
+++ b/arch/arm/cpu/arm920t/imx/timer.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined (CONFIG_IMX)
+
+#include <asm/arch/imx-regs.h>
+
+int timer_init (void)
+{
+	int i;
+	/* setup GP Timer 1 */
+	TCTL1 = TCTL_SWR;
+	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
+	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
+	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
+
+	reset_timer_masked();
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer (ulong t)
+{
+	/* nop */
+}
+
+void reset_timer_masked (void)
+{
+	TCTL1 &= ~TCTL_TEN;
+	TCTL1 |= TCTL_TEN; /* Enable timer */
+}
+
+ulong get_timer_masked (void)
+{
+	return TCN1;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime = get_timer_masked() + usec;
+	signed long diff;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+void __udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	/* Disable watchdog and set Time-Out field to 0 */
+	WCR = 0x00000000;
+
+	/* Write Service Sequence */
+	WSR = 0x00005555;
+	WSR = 0x0000AAAA;
+
+	/* Enable watchdog */
+	WCR = 0x00000001;
+
+	while (1);
+	/*NOTREACHED*/
+}
+
+#endif /* defined (CONFIG_IMX) */
--- a/arch/arm/cpu/arm920t/interrupts.c
+++ b/arch/arm/cpu/arm920t/interrupts.c
--- a/arch/arm/cpu/arm920t/ks8695/Makefile
+++ b/arch/arm/cpu/arm920t/ks8695/Makefile
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
--- a/arch/arm/cpu/arm920t/ks8695/timer.c
+++ b/arch/arm/cpu/arm920t/ks8695/timer.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/*
+ * Handy KS8695 register access functions.
+ */
+#define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
+#define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
+
+ulong timer_ticks;
+
+int timer_init (void)
+{
+	reset_timer();
+
+	return 0;
+}
+
+/*
+ * Initial timer set constants. Nothing complicated, just set for a 1ms
+ * tick.
+ */
+#define	TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_1)
+#define	TIMER_COUNT	(TIMER_INTERVAL / 2)
+#define	TIMER_PULSE	TIMER_COUNT
+
+void reset_timer_masked(void)
+{
+	/* Set the hadware timer for 1ms */
+	ks8695_write(KS8695_TIMER1, TIMER_COUNT);
+	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
+	ks8695_write(KS8695_TIMER_CTRL, 0x2);
+	timer_ticks = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	/* Check for timer wrap */
+	if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
+		/* Clear interrupt condition */
+		ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
+		timer_ticks++;
+	}
+	return timer_ticks;
+}
+
+ulong get_timer(ulong base)
+{
+       return (get_timer_masked() - base);
+}
+
+void set_timer(ulong t)
+{
+	timer_ticks = t;
+}
+
+void __udelay(ulong usec)
+{
+	ulong start = get_timer_masked();
+	ulong end;
+
+	/* Only 1ms resolution :-( */
+	end = usec / 1000;
+	while (get_timer(start) < end)
+		;
+}
+
+void reset_cpu (ulong ignored)
+{
+	ulong tc;
+
+	/* Set timer0 to watchdog, and let it timeout */
+	tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
+	ks8695_write(KS8695_TIMER_CTRL, tc);
+	ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
+	ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
+
+	/* Should only wait here till watchdog resets */
+	for (;;)
+		;
+}
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
--- a/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/interrupts.c
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/proc-armv/ptrace.h>
+
+void do_irq (struct pt_regs *pt_regs)
+{
+	struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
+	u_int32_t intpnd = readl(&irq->INTPND);
+
+}
--- a/arch/arm/cpu/arm920t/s3c24x0/speed.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2001-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This code should work for both the S3C2400 and the S3C2410
+ * as they seem to have the same PLL and clock machinery inside.
+ * The different address mapping is handled by the s3c24xx.h files below.
+ */
+
+#include <common.h>
+#ifdef CONFIG_S3C24X0
+
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+#define MPLL 0
+#define UPLL 1
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	ulong r, m, p, s;
+
+	if (pllreg == MPLL)
+		r = readl(&clk_power->MPLLCON);
+	else if (pllreg == UPLL)
+		r = readl(&clk_power->UPLLCON);
+	else
+		hang();
+
+	m = ((r & 0xFF000) >> 12) + 8;
+	p = ((r & 0x003F0) >> 4) + 2;
+	s = r & 0x3;
+
+	return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+	return get_PLLCLK(MPLL);
+}
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+
+	return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+
+	return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
+}
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	return get_PLLCLK(UPLL);
+}
+
+#endif /* CONFIG_S3C24X0 */
--- a/arch/arm/cpu/arm920t/s3c24x0/timer.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/timer.c
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#ifdef CONFIG_S3C24X0
+
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+int timer_load_val = 0;
+static ulong timer_clk;
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+
+	return readl(&timers->TCNTO4) & 0xffff;
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+	ulong tmr;
+
+	/* use PWM Timer 4 because it has no output */
+	/* prescaler for Timer 4 is 16 */
+	writel(0x0f00, &timers->TCFG0);
+	if (timer_load_val == 0) {
+		/*
+		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
+		 * (default) and prescaler = 16. Should be 10390
+		 * @33.25MHz and 15625 @ 50 MHz
+		 */
+		timer_load_val = get_PCLK() / (2 * 16 * 100);
+		timer_clk = get_PCLK() / (2 * 16);
+	}
+	/* load value for 10 ms timeout */
+	lastdec = timer_load_val;
+	writel(timer_load_val, &timers->TCNTB4);
+	/* auto load, manual update of Timer 4 */
+	tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
+	writel(tmr, &timers->TCON);
+	/* auto load, start Timer 4 */
+	tmr = (tmr & ~0x0700000) | 0x0500000;
+	writel(tmr, &timers->TCON);
+	timestamp = 0;
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+void __udelay (unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_ticks();
+
+	tmo = usec / 1000;
+	tmo *= (timer_load_val * 100);
+	tmo /= 1000;
+
+	while ((ulong) (get_ticks() - start) < tmo)
+		/*NOP*/;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong tmr = get_ticks();
+
+	return tmr / (timer_clk / CONFIG_SYS_HZ);
+}
+
+void udelay_masked(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= (timer_load_val * 100);
+		tmo /= 1000;
+	} else {
+		tmo = usec * (timer_load_val * 100);
+		tmo /= (1000 * 1000);
+	}
+
+	endtime = get_ticks() + tmo;
+
+	do {
+		ulong now = get_ticks();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	ulong now = READ_TIMER();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + timer_load_val - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
+	tbclk = timer_load_val * 100;
+#elif defined(CONFIG_SBC2410X) || \
+      defined(CONFIG_SMDK2410) || \
+      defined(CONFIG_VCMA9)
+	tbclk = CONFIG_SYS_HZ;
+#else
+#	error "tbclk not configured"
+#endif
+
+	return tbclk;
+}
+
+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu(ulong ignored)
+{
+	struct s3c24x0_watchdog *watchdog;
+
+#ifdef CONFIG_TRAB
+	extern void disable_vfd(void);
+
+	disable_vfd();
+#endif
+
+	watchdog = s3c24x0_get_base_watchdog();
+
+	/* Disable watchdog */
+	writel(0x0000, &watchdog->WTCON);
+
+	/* Initialize watchdog timer count register */
+	writel(0x0001, &watchdog->WTCNT);
+
+	/* Enable watchdog timer; assert reset at timer timeout */
+	writel(0x0021, &watchdog->WTCON);
+
+	while (1)
+		/* loop forever and wait for reset to happen */;
+
+	/*NOTREACHED*/
+}
+
+#endif /* CONFIG_S3C24X0 */
--- a/arch/arm/cpu/arm920t/s3c24x0/usb.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2006
+ * DENX Software Engineering <mk@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && \
+    defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+    defined(CONFIG_S3C24X0)
+
+#include <asm/arch/s3c24x0_cpu.h>
+#include <asm/io.h>
+
+int usb_cpu_init(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
+
+	/*
+	 * Set the 48 MHz UPLL clocking. Values are taken from
+	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
+	 */
+	writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+	/* 1 = use pads related USB for USB host */
+	writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
+
+	/*
+	 * Enable USB host clock.
+	 */
+	writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
+
+	return 0;
+}
+
+int usb_cpu_stop(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	/* may not want to do this */
+	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+	writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
+	return 0;
+}
+
+#endif /* defined(CONFIG_USB_OHCI_NEW) && \
+	   defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+	   defined(CONFIG_S3C24X0) */
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
+++ b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
--- a/Show More
+++ b/Show More