e27f2dd721
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD registers. In EMIF_PHY_CTRL: Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the read latency expected will be CL+3 as per tests from HW folks. Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug purpose. With out this resume is not working(Still waiting for PHY team to come back for better explanation). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
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am43xx | ||
am335x | ||
am3517crane | ||
beagle | ||
dra7xx | ||
evm | ||
omap5_uevm | ||
omap5912osk | ||
panda | ||
sdp3430 | ||
sdp4430 | ||
ti814x | ||
ti816x | ||
tnetv107xevm |