leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
da84f33b04
u-boot/arch/mips/cpu/mips32
History
Gabor Juhos da84f33b04 MIPS: mips32/cache.S: remove superfluous register assignment 
The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
2013-07-24 09:51:05 -04:00
..
au1x00 Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
incaip Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
cache.S MIPS: mips32/cache.S: remove superfluous register assignment 2013-07-24 09:51:05 -04:00
config.mk Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
cpu.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
interrupts.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
Makefile Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
start.S MIPS: start.S: emulate REVISION register for qemu-malta 2013-07-24 09:51:03 -04:00
time.c MIPS: mips32/time.c: fix checkpatch errors/warnings 2013-07-24 09:51:04 -04:00