aa30aae8b4
tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> |
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| .. | ||
| mediatek | ||
| rockchip | ||
| stm32mp1 | ||
| bmips_ram.c | ||
| k3-am654-ddrss.c | ||
| k3-am654-ddrss.h | ||
| Kconfig | ||
| Makefile | ||
| mpc83xx_sdram.c | ||
| ram-uclass.c | ||
| sandbox_ram.c | ||
| stm32_sdram.c | ||