Siva Durga Prasad Paladugu 71723aaec5 fpga: zynq: Add delay after PCFG_PROG_B change ...

There is delay needed after PCFG_PROGB change if
AES key source is efuse. This fixes the issue of
encrypted bitstream loading with AES efuse as key
source.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

2018-04-09 12:14:50 +02:00

12 KiB

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