Wenyou Yang fed0509c92 clk: at91: add PLLADIV driver ...

As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

2018-03-16 07:30:04 -04:00

1.9 KiB

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