a46dce2817
Add support for new compatible "st,stm32mp13-ddr" to manage the DDR sub system (Controller and PHY) in STM32MP13x SOC: - only one AXI port - support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2) The STM32MP15x SOC have 2 AXI ports and 32 bits support. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| stm32mp1_ddr_regs.h | ||
| stm32mp1_ddr.c | ||
| stm32mp1_ddr.h | ||
| stm32mp1_interactive.c | ||
| stm32mp1_ram.c | ||
| stm32mp1_tests.c | ||
| stm32mp1_tests.h | ||