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ram: stm32mp1: Conditionally enable ASR

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Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL
register bits. While ASR does save considerable amount of power at
runtime automatically, it also causes LTDC underruns on large panels.
Let user select whether or not ASR is required or not, generally ASR
should be enabled on portable and battery operated devices.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Marek Vasut 2022-04-26 16:37:41 +02:00 committed by Patrice Chotard
parent 189ec2fee6
commit 221869efc3
1 changed files with 11 additions and 3 deletions
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14
drivers/ram/stm32mp1/stm32mp1_ddr.c
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@ -653,10 +653,14 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
wait_sw_done_ack(ctl);
}
static void stm32mp1_asr_enable(struct ddr_info *priv)
static void stm32mp1_asr_enable(struct ddr_info *priv, const u32 pwrctl)
{
struct stm32mp1_ddrctl *ctl = priv->ctl;
/* SSR is the best we can do. */
if (!(pwrctl & DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE))
return;
clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK,
RCC_DDRITFCR_DDRCKMOD_ASR);
@ -666,8 +670,12 @@ static void stm32mp1_asr_enable(struct ddr_info *priv)
writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) |
DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01),
&ctl->pwrtmg);
/* HSR we can do. */
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
if (pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) /* ASR we can do. */
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
wait_sw_done_ack(ctl);
@ -845,7 +853,7 @@ start:
config->c_reg.pwrctl);
/* Enable auto-self-refresh, which saves a bit of power at runtime. */
stm32mp1_asr_enable(priv);
stm32mp1_asr_enable(priv, config->c_reg.pwrctl);
/* enable uMCTL2 AXI port 0 and 1 */
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);