u-boot

History

Trent Piepho f62fb99941 Fix all linker script to handle all rodata sections A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata" to get all rodata linker section gcc has now and might add in the future. However, '(.rodata)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: (.text) . = ALIGN(16); (.rodata) (.rodata.str1.4) (.eh_frame) I change this to: (.text) . = ALIGN(16); (.eh_frame) (SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>		2009-03-20 22:39:12 +01:00
..
config.mk	ppc4xx: Netstal HCU4 board. Added POST. Various fixes	2008-01-17 13:49:51 +01:00
hcu4.c	rename CFG_ macros to CONFIG_SYS	2008-10-18 21:54:03 +02:00
Makefile	Cleanup out-or-tree building for some boards (.depend)	2008-07-02 23:49:18 +02:00
README.txt	Add PPC4xx-HCU4 and HCU5 boards: READMEs	2007-08-10 09:09:19 +02:00
u-boot.lds	Fix all linker script to handle all rodata sections	2009-03-20 22:39:12 +01:00

README.txt

HCU4 Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

Chip-Select 2: Flash Memory
---------------------------

0x70000000

Chip-Select 3: CAN Interface
----------------------------
0x7800000


Chip-Select 4: IMC-bus standard
-------------------------------

Our IO-Bus (slow version)


Chip-Select 5: IMC-bus fast (inactive)
--------------------------------------

Our IO-Bus (fast, but not yet use)


Memory Bank 1 -- SDRAM
-------------------------------------

0x00000000 - 0x1ffffff   # Default 32 MB