Add PPC4xx-HCU4 and HCU5 boards: READMEs
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
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Niklaus Giger
Stefan Roese
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59
board/netstal/hcu4/README.txt
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59
board/netstal/hcu4/README.txt
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HCU4 Configuration Details
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Memory Bank 0 -- Flash chip
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---------------------------
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0xfff00000 - 0xffffffff
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The flash chip is really only 512Kbytes, but the high address bit of
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the 1Meg region is ignored, so the flash is replicated through the
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region. Thus, this is consistent with a flash base address 0xfff80000.
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The placement at the end is to be consistent with reset behavior,
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where the processor itself initially uses this bus to load the branch
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vector and start running.
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On-Chip Memory
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--------------
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0xf4000000 - 0xf4000fff
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The 405GPr includes a 4K on-chip memory that can be placed however
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software chooses. I choose to place the memory at this address, to
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keep it out of the cachable areas.
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Internal Peripherals
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--------------------
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0xef600300 - 0xef6008ff
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These are scattered various peripherals internal to the PPC405GPr
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chip.
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Chip-Select 2: Flash Memory
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---------------------------
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0x70000000
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Chip-Select 3: CAN Interface
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----------------------------
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0x7800000
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Chip-Select 4: IMC-bus standard
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-------------------------------
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Our IO-Bus (slow version)
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Chip-Select 5: IMC-bus fast (inactive)
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--------------------------------------
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Our IO-Bus (fast, but not yet use)
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Memory Bank 1 -- SDRAM
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-------------------------------------
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0x00000000 - 0x1ffffff # Default 32 MB
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174
board/netstal/hcu5/README.txt
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174
board/netstal/hcu5/README.txt
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HCU5 configuration details and startup sequence
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(C) Copyright 2007 Netstal Maschinen AG
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Niklaus Giger (Niklaus.Giger@netstal.com)
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TODO:
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-----
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- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
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- Does not occur if both EMAC are connected
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- Fix RTS/CTS problem (HW?)
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CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
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Switching to interrupt driven serial input mode
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- Make vxWorks start from u-boot. Possible reasons
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- Does vxWorks need an entry for the Machine Check interrupt like this
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tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
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Caveats:
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--------
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Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
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see hcu5.c.
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Memory Bank 0 -- Flash chip
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---------------------------
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0xfff00000 - 0xffffffff
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The flash chip is really only 512Kbytes, but the high address bit of
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the 1Meg region is ignored, so the flash is replicated through the
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region. Thus, this is consistent with a flash base address 0xfff80000.
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The placement at the end is to be consistent with reset behavior,
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where the processor itself initially uses this bus to load the branch
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vector and start running.
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On-Chip Memory
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--------------
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0xe0010000- 0xe0013fff CFG_OCM_BASE
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The 440EPx includes a 16K on-chip memory that can be placed however
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software chooses.
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Internal Peripherals
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--------------------
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0xef600300 - 0xef6008ff
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These are scattered various peripherals internal to the PPC440EPX
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chip.
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Chip-Select 2: Flash Memory
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---------------------------
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Not used
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Chip-Select 3: CAN Interface
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----------------------------
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0xc800000: 2 Intel 82527 CAN-Controller
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Chip-Select 4: IMC-bus standard
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-------------------------------
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0xcc00000: Netstal specific IO-Bus
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Chip-Select 5: IMC-bus fast (inactive)
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--------------------------------------
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0xce00000: Netstal specific IO-Bus (fast, but not yet used)
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Memory Bank 1 -- DDR2
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-------------------------------------
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0x00000000 - 0xfffffff # Default 256 MB
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PCI ??
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USB ??
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Only USB_STORAGE is enabled to load vxWorks
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from a memory stick.
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System-LEDs ??? (Analog zu HCU4 ???)
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Startup sequence
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----------------
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(cpu/ppc4xx/resetvec.S)
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depending on configs option
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call _start_440 _start_pci oder _start
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(cpu/ppc4xx/start.S)
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_start_440:
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initialize register like
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CCR0
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debug
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setup interrupt vectors
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configure cache regions
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clear and setup TLB
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enable internal RAM
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jump start_ram
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which in turn will jump to start
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_start:
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Clear and set up some registers.
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Debug setup
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Setup the internal SRAM
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Setup the stack in internal SRAM
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setup stack pointer (r1)
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setup GOT
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call cpu_init_f /* run low-level CPU init code (from Flash) */
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call cpu_init_f
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board_init_f: (lib_ppc\board.c)
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init_sequence defines a list of function to be called
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board_early_init_f: (board/netstal/hcu5/hcu5.c)
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We are using Bootstrap-Option A
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if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
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Setup the GPIO pins
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Setup the interrupt controller polarities, triggers, etc.
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Ethernet, PCI, USB enable
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setup BOOT FLASH (Chip timing)
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init_baudrate,
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serial_init
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checkcpu
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misc_init_f #ifdef
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init_func_i2c #ifdef
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post_init_f #ifdef
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init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
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(EYE function removed!!)
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test_dram call
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* Reserve memory at end of RAM for (top down in that order):
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* - kernel log buffer
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* - protected RAM
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* - LCD framebuffer
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* - monitor code
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* - board info struct
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Save local variables to board info struct
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call relocate_code() does not return
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relocate_code: (cpu/ppc4xx/start.S)
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-------------------------------------------------------
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From now on our copy is in RAM and we will run from there,
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starting with board_init_r
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-------------------------------------------------------
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board_init_r: (lib_ppc\board.c)
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setup bd function pointers
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trap_init
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flash_init: (board/netstal/hcu5/flash.c)
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/* setup for u-boot erase, update */
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setup bd flash info
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cpu_init_r: (cpu/ppc4xx/cpu_init.c)
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peripheral chip select in using defines like
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CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h
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mem_malloc_init
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malloc_bin_reloc
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spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
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env_relocated
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misc_init_r(bd): (board/netstal/hcu5.c)
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ethaddr mit serial number ergänzen
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Then we will somehow go into the command loop
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Most of the HW specific code for the HCU5 may be found in
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include/configs/hcu5.h
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board/netstal/hcu5/*
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cpu/ppc4xx/*
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lib_ppc/*
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include/ppc440.h
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Drivers for serial etc are found under drivers/
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Don't ask question if you did not look at the README !!
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Most CFG_* and CONFIG_* switches are mentioned/explained there.
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