exynos9820(dtsi): minimal dtsi

arch/arm/dts/Makefile

@@ -36,6 +36,8 @@ dtb-$(CONFIG_ARCH_APPLE) += \
 	t8103-j274.dtb \
 	t8103-j293.dtb
 
+dtb-$(CONFIG_EXYNOS9820) += exynos9820-beyond1lte.dtb
+
 dtb-$(CONFIG_ARCH_DAVINCI) += \
 	da850-evm.dtb \
 	da850-lcdk.dtb \

arch/arm/dts/exynos7420.dtsi

@@ -1,82 +1,217 @@
-// SPDX-License-Identifier: GPL-2.0+
 /*
- * Samsung Exynos7420 SoC device tree source
+ * SAMSUNG EXYNOS9820 SoC device tree source
  *
- * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2018 Samsung Electronics Co., Ltd.
- *		http://www.samsung.com
+ *             http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS9820 SoC device nodes are listed in this file.
+ * EXYNOS based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
  */
 
 /dts-v1/;
-#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/exynos7420-clk.h>
-/ {
-	compatible = "samsung,exynos7420";
 
-	fin_pll: xxti {
+#include "exynos9820-pinctrl.dtsi"
+
+/ {
+	compatible = "samsung,armv8", "samsung,exynos9820";
+	dtb-hw_rev = <0>;
+	dtb-hw_rev_end = <255>;
+
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	xxti: clock {
+		/* XXTI */
 		compatible = "fixed-clock";
-		clock-output-names = "fin_pll";
+		clock-output-names = "oscclk";
-		u-boot,dm-pre-reloc;
 		#clock-cells = <0>;
 	};
 
-	clock_topc: clock-controller@10570000 {
+	cpus {
-		compatible = "samsung,exynos7-clock-topc";
+		#address-cells = <2>;
-		reg = <0x10570000 0x10000>;
+		#size-cells = <0>;
-		u-boot,dm-pre-reloc;
-		#clock-cells = <1>;
-		clocks = <&fin_pll>;
-		clock-names = "fin_pll";
-	};
 
-	clock_top0: clock-controller@105d0000 {
+		cpu-map {
-		compatible = "samsung,exynos7-clock-top0";
+			cluster0 {
-		reg = <0x105d0000 0xb000>;
+				coregroup0 {
-		u-boot,dm-pre-reloc;
+					core0 {
-		#clock-cells = <1>;
+						cpu = <&cpu0>;
-		clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+					};
-			 <&clock_topc DOUT_SCLK_BUS1_PLL>,
+					core1 {
-			 <&clock_topc DOUT_SCLK_CC_PLL>,
+						cpu = <&cpu1>;
-			 <&clock_topc DOUT_SCLK_MFC_PLL>;
+					};
-		clock-names = "fin_pll", "dout_sclk_bus0_pll",
+					core2 {
-			      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+						cpu = <&cpu2>;
-			      "dout_sclk_mfc_pll";
+					};
-	};
+					core3 {
+						cpu = <&cpu3>;
+					};
+				};
 
-	clock_peric1: clock-controller@14c80000 {
+				coregroup1 {
-		compatible = "samsung,exynos7-clock-peric1";
+					core0 {
-		reg = <0x14c80000 0xd00>;
+						cpu = <&cpu4>;
-		u-boot,dm-pre-reloc;
+					};
-		#clock-cells = <1>;
+					core1 {
-		clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+						cpu = <&cpu5>;
-			 <&clock_top0 CLK_SCLK_UART1>,
+					};
-			 <&clock_top0 CLK_SCLK_UART2>,
+				};
-			 <&clock_top0 CLK_SCLK_UART3>;
+			};
-		clock-names = "fin_pll", "dout_aclk_peric1_66",
-			      "sclk_uart1", "sclk_uart2", "sclk_uart3";
-	};
 
-	pinctrl@13470000 {
+			cluster1 {
-		compatible = "samsung,exynos7420-pinctrl";
+				coregroup0 {
-		reg = <0x13470000 0x1000>;
+					core0 {
-		u-boot,dm-pre-reloc;
+						cpu = <&cpu6>;
+					};
+					core1 {
+						cpu = <&cpu7>;
+					};
+				};
+			};
 
-		serial2_bus: serial2-bus {
+		};
-			samsung,pins = "gpd1-4", "gpd1-5";
+
-			samsung,pin-function = <2>;
+		cpu0: cpu@0 {
-			samsung,pin-pud = <3>;
+			device_type = "cpu";
-			samsung,pin-drv = <0>;
+			compatible = "arm,cortex-a55", "arm,armv8";
-			u-boot,dm-pre-reloc;
+			reg = <0x0 0x0000>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55", "arm,armv8";
+			reg = <0x0 0x0001>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55", "arm,armv8";
+			reg = <0x0 0x0002>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55", "arm,armv8";
+			reg = <0x0 0x0003>;
+			enable-method = "psci";
+		};
+
+		cpu4: cpu@4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a75", "arm,armv8";
+			reg = <0x0 0x0004>;
+			enable-method = "psci";
+		};
+
+		cpu5: cpu@5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a75", "arm,armv8";
+			reg = <0x0 0x0005>;
+			enable-method = "psci";
+		};
+
+		cpu6: cpu@100 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m4", "arm,armv8";
+			reg = <0x0 0x0100>;
+			enable-method = "psci";
+		};
+
+		cpu7: cpu@101 {
+			device_type = "cpu";
+			compatible = "samsung,mongoose-m4", "arm,armv8";
+			reg = <0x0 0x0101>;
+			enable-method = "psci";
 		};
 	};
 
-	serial@14C30000 {
+	psci {
-		compatible = "samsung,exynos4210-uart";
+		compatible = "arm,psci";
-		reg = <0x14C30000 0x100>;
+		method = "smc";
-		u-boot,dm-pre-reloc;
+		cpu_suspend = <0xC4000001>;
-		clocks = <&clock_peric1 PCLK_UART2>,
+		cpu_off = <0x84000002>;
-			 <&clock_peric1 SCLK_UART2>;
+		cpu_on = <0xC4000003>;
-		clock-names = "uart", "clk_uart_baud0";
+	};
-		pinctrl-names = "default";
+
-		pinctrl-0 = <&serial2_bus>;
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		ramoops@92000000 {
+			compatible = "ramoops";
+			reg = <0 0x92000000 0 0x8000>;
+			record-size = <0x4000>;
+			console-size = <0x4000>;
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0x18000000>;
+
+		gic: interrupt-controller@10200000 {
+			compatible = "arm,cortex-a15-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x10201000 0x1000>,
+			      <0x10202000 0x1000>,
+			      <0x10204000 0x2000>,
+			      <0x10206000 0x2000>;
+			interrupts = <GIC_PPI 9 0xf04>;
+		};
+
+		mct: mct@10040000 {
+			compatible = "samsung,exynos4210-mct";
+			reg = <0x10040000 0x800>;
+			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+
+			// TODO clocks
+			//clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
+			//clock-names = "fin_pll", "mct";
+		};
+	};
+
+	chipid@10000000 {
+		compatible = "samsung,exynos850-chipid";
+		reg = <0x0 0x10000000 0x100>;
+	};
+
+	timer {
+	        compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	        clock-frequency = <26000000>;
+		use-clocksource-only;
+		use-physical-timer;
 	};
 };

arch/arm/dts/exynos9820-beyond1lte.dts

@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung Exynos9820 SoC device tree source
+ *
+ */
+
+/dts-v1/;
+
+#include "exynos9820.dtsi"
+
+/ {
+	compatible = "samsung,exynos9820";
+
+	aliases {
+		console = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+	};
+};
+
+&fin_pll {
+	clock-frequency = <26000000>;
+};

arch/arm/dts/exynos9820.dtsi

@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung Exynos 9820 SoC device tree source
+ *
+ * Copyright (C) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ * Copyright (C) 2020 Ivaylo Ivanov <ivo.ivanov@null.net>
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "samsung,exynos9820";
+
+	aliases {
+		pinctrl6 = &pinctrl_6;
+	};
+
+	fin_pll: xxti {
+		compatible = "fixed-clock";
+		clock-output-names = "fin_pll";
+		u-boot,dm-pre-reloc;
+		#clock-cells = <0>;
+	};
+
+	gic: interrupt-controller@10100000 {
+		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x10101000 0x1000 0x0 0x10102000 0x1000 0x0 0x10104000 0x2000 0x0 0x10106000 0x2000>;
+		interrupts = <0x1 0x9 0xf04>;
+		#linux,phandle = <0x1>;
+		#phandle = <0x1>;
+	};
+
+	/* PERIC0 */
+	pinctrl_6: pinctrl@10830000 {
+		compatible = "samsung,exynos9820-pinctrl";
+		reg = <0x0 0x10830000 0x1000>;
+		interrupts = <0x0 0x197 0x0>;
+
+		gpp4: gpp4 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpp5: gpp5 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpp6: gpp6 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpc0: gpc0 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpc1: gpc1 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpd0: gpd0 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gpg3: gpg3 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gph0: gph0 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+
+		gph1: gph1 {
+			gpio-controller;
+			#gpio-cells = <0x2>;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+		};
+	};
+
+	/* UART_DEBUG */
+	uart0: serial@10430000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x10430000 0x100>;
+		u-boot,dm-pre-reloc;
+	};
+};

arch/arm/mach-exynos/Kconfig

@@ -45,6 +45,16 @@ config ARCH_EXYNOS7
 	  Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
 	  multiple SoCs in this family including Exynos7420.
 
+config ARCH_EXYNOS9
+	bool "Exynos9 SoC family"
+	select ARM64
+	select BLK
+	select DM_MMC
+	help
+	  Samsung Exynos9 SoC family are based on ARM Cortex-A77 CPU,
+	  Cortex-A73 CPU, Cortex-A55 CPU, Cortex-A53 CPU or Custom Mongoose CPU.
+	  There are multiple SoCs in this family including Exynos8995 and Exynos9820.
+
 endchoice
 
 if ARCH_EXYNOS4
@@ -181,6 +191,24 @@ config  TARGET_A3Y17LTE
 endchoice
 endif
 
+if ARCH_EXYNOS9
+
+choice
+	prompt "EXYNOS9 board select"
+
+config  TARGET_BEYOND
+	bool "BEYOND board"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select CLK_EXYNOS
+	select OF_CONTROL
+	select PINCTRL
+	select PINCTRL_EXYNOS9
+	select SUPPORT_SPL
+
+endchoice
+endif
+
 config SYS_SOC
 	default "exynos"
 
@@ -195,6 +223,7 @@ source "board/samsung/smdk5250/Kconfig"
 source "board/samsung/smdk5420/Kconfig"
 source "board/samsung/espresso7420/Kconfig"
 source "board/samsung/axy17lte/Kconfig"
+source "board/samsung/beyond/Kconfig"
 
 config SPL_LDSCRIPT
 	default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4

arch/arm/mach-exynos/mmu-arm64.c

@@ -95,4 +95,42 @@ static struct mm_region exynos7880_mem_map[] = {
 };
 
 struct mm_region *mem_map = exynos7880_mem_map;
+
+#elif CONFIG_IS_ENABLED(EXYNOS9820)
+static struct mm_region exynos9820_mem_map[] = {
+	{
+		.virt	= 0x10000000UL,
+		.phys	= 0x10000000UL,
+		.size	= 0x10000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	},
+	{
+		.virt	= 0x80000000UL,
+		.phys	= 0x80000000UL,
+		.size	= 0x3C800000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	},
+	{
+		.virt	= 0xC0000000UL,
+		.phys	= 0xC0000000UL,
+		.size	= 0x40000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	},
+	{
+		.virt	= 0x80000000UL,
+		.phys	= 0x80000000UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	},
+	{
+		/* List terminator */
+	},
+};
+
+struct mm_region *mem_map = exynos9820_mem_map;
 #endif

arch/arm/mach-exynos/soc.c

@@ -10,7 +10,7 @@
 #include <asm/io.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_TARGET_ESPRESSO7420
+#if defined(CONFIG_TARGET_ESPRESSO7420) || defined (CONFIG_EXYNOS9820)
 /*
  * Exynos7420 uses CPU0 of Cluster-1 as boot CPU. Due to this, branch_if_master
  * fails to identify as the boot CPU as the master CPU. As temporary workaround,

board/samsung/axy17lte/Kconfig

@@ -1,6 +1,6 @@
 config SYS_CONFIG_NAME
 	string "Board configuration name"
-	default "exynos78x0-common.h"
+	default "exynos78x0-common"
 	help
 	  This option contains information about board configuration name.
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header

board/samsung/beyond/Kconfig

@@ -0,0 +1,18 @@
+if TARGET_BEYOND
+
+config SYS_BOARD
+	default "beyond"
+	help
+	  BEYOND is a production board for Galaxy S10/S10e/S10+ phones on Exynos9820 SoC.
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "BEYOND"
+
+config EXYNOS9820
+    bool "Exynos 9820 SOC support"
+    default "y"
+
+endif

board/samsung/beyond/MAINTAINERS

@@ -0,0 +1,7 @@
+Samsung S10/S10e/S10+ (beyond1lte)/(beyond2lte)/(beyond0lte) Board
+M:	Dani Shum <dani.shum@null.net>
+M:	Kreato <kreato@null.net>
+S:	Maintained
+F:	board/samsung/beyond/
+F:	include/configs/beyond.h
+F:	configs/beyond_defconfig.h

board/samsung/beyond/Makefile

@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_TARGET_BEYOND) += beyond.o

board/samsung/beyond/beyond.c

@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Samsung DREAM board based on Exynos 8895 board file
+ */
+
+#include <common.h>
+
+int exynos_init(void)
+{
+	return 0;
+}

configs/beyond1lte_defconfig

@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS9=y
+CONFIG_S5P=y
+CONFIG_TARGET_BEYOND=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos9820-beyond1lte"
+# TODO fix the address since sboot is causing issues
+CONFIG_SYS_TEXT_BASE=0x80001000
+CONFIG_BOARD_EARLY_INIT_F=n
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_DISPLAY_CPUINFO=n
+CONFIG_STANDALONE_LOAD_ADDR=0x10008000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_SYS_LOAD_ADDR=0x81ad7fff
+CONFIG_PSCI_RESET=n

configs/exynos9820.h

@@ -0,0 +1,34 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS9820_H
+#define __CONFIG_EXYNOS9820_H
+
+#include <configs/exynos9820-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_EXYNOS9820
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define CONFIG_SPL_STACK		CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING	" for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
+#endif	/* __CONFIG_EXYNOS9820_H */

configs/exynos9820_defconfig

@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS9820=y
+CONFIG_TARGET_EXYNOS9820=y
+CONFIG_DEFAULT_DEVICE_TREE="exynos9820"
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_PROMPT="EXYNOS9820 # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set

drivers/pinctrl/exynos/Kconfig

@@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0
 	help
 	  Support pin multiplexing and pin configuration control on
 	  Samsung's Exynos78x0 SoC.
+
+config PINCTRL_EXYNOS9
+	bool "Samsung Exynos9 pinctrl driver"
+	depends on ARCH_EXYNOS && PINCTRL_FULL
+	select PINCTRL_EXYNOS
+	help
+	  Support pin multiplexing and pin configuration control on
+	  Samsung's Exynos9 Family.

drivers/pinctrl/exynos/Makefile

@@ -6,3 +6,4 @@
 obj-$(CONFIG_PINCTRL_EXYNOS)		+= pinctrl-exynos.o
 obj-$(CONFIG_PINCTRL_EXYNOS7420)	+= pinctrl-exynos7420.o
 obj-$(CONFIG_PINCTRL_EXYNOS78x0)	+= pinctrl-exynos78x0.o
+obj-$(CONFIG_PINCTRL_EXYNOS9)		+= pinctrl-exynos9.o

drivers/pinctrl/exynos/pinctrl-exynos9.c

@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ * Copyright (C) 2020 Ivaylo Ivanov <ivo.ivanov@null.net>
+ */
+
+#include <log.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <fdtdec.h>
+#include <asm/arch/pinmux.h>
+
+#include "pinctrl-exynos.h"
+
+#define DEBUG
+
+static struct pinctrl_ops exynos9_pinctrl_ops = {
+	.set_state	= exynos_pinctrl_set_state
+};
+
+/* pin banks of exynos9820 pin-controller 6 (PERIC0) */
+static const struct samsung_pin_bank_data exynos9820_pin_banks6[] = {
+	EXYNOS_PIN_BANK(4, 0x080, "gpb1"),
+	EXYNOS_PIN_BANK(8, 0x000, "gpd0"),
+	EXYNOS_PIN_BANK(8, 0x020, "gpd1"),
+	EXYNOS_PIN_BANK(4, 0x040, "gpd2"),
+	EXYNOS_PIN_BANK(5, 0x060, "gpd3"),
+	EXYNOS_PIN_BANK(8, 0x0A0, "gpe7"),
+	EXYNOS_PIN_BANK(8, 0x0C0, "gpf1"),
+};
+
+static const struct samsung_pin_ctrl exynos9820_pin_ctrl[] = {
+	{
+		/* pin-controller instance 6 PERIC0 data */
+		.pin_banks	= exynos9820_pin_banks6,
+		.nr_banks	= ARRAY_SIZE(exynos9820_pin_banks6),
+	}, {
+		/* list terminator */
+	}
+};
+
+static const struct udevice_id exynos9_pinctrl_ids[] = {
+	{
+		.compatible = "samsung,exynos9820-pinctrl",
+		.data = (ulong)exynos9820_pin_ctrl
+	}, {
+		/* list terminator */
+	}
+};
+
+U_BOOT_DRIVER(pinctrl_exynos9) = {
+	.name		= "pinctrl_exynos9",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= exynos9_pinctrl_ids,
+	.priv_auto = sizeof(struct exynos_pinctrl_priv),
+	.ops		= &exynos9_pinctrl_ops,
+	.probe		= exynos_pinctrl_probe,
+};

drivers/serial/serial_s5p.c

@@ -273,6 +273,7 @@ U_BOOT_DRIVER(serial_s5p) = {
 
 static inline void _debug_uart_init(void)
 {
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
 	if (IS_ENABLED(CONFIG_DEBUG_UART_SKIP_INIT))
 		return;
 
@@ -284,6 +285,8 @@ static inline void _debug_uart_init(void)
 #else
 	s5p_serial_baud(uart, 1, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 #endif
+
+#endif
 }
 
 static inline void _debug_uart_putc(int ch)

include/configs/beyond.h

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the SAMSUNG A5 2017 (A520F)(a5y17lte) board.
+ *
+ * Copyright (C) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ * Copyright (C) 2020 Ivaylo Ivanov <ivo.ivanov@null.net>
+ * based on configs/espresso7420.h
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ */
+
+#ifndef __CONFIG_BEYOND_H
+#define __CONFIG_BEYOND_H
+
+#include <configs/exynos9820-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_2M - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		0x80001000
+
+/* select serial console configuration */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+		"console=ttySAC2,115200n8\0" \
+
+/* DRAM Memory Banks */
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
+#endif	/* __CONFIG_BEYOND_H */

include/configs/exynos9820-common.h

@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Configuration settings for the EXYNOS 9820 boards.
+ *
+ * Copyright (C) 2020 Dzmitry Sankouski (dsankouski@gmail.com)
+ * Copyright (C) 2020 Ivaylo Ivanov <ivo.ivanov@null.net>
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * Based on include/configs/exynos7420-common.h
+ */
+
+#ifndef __CONFIG_EXYNOS9820_COMMON_H
+#define __CONFIG_EXYNOS9820_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <linux/sizes.h>
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		1024	/* Print Buffer Size */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY		26000000
+
+/* Device Tree */
+#define CONFIG_DEVICE_TREE_LIST		"exynos9820-beyond"
+
+#define CPU_RELEASE_ADDR		secondary_boot_addr
+
+#define CONFIG_NR_DRAM_BANKS		12
+
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2			(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3			(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4			(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5			(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6			(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7			(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8			(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_9			(CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_9_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_10			(CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_10_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_11			(CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_11_SIZE		SDRAM_BANK_SIZE
+#define PHYS_SDRAM_12			(CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_12_SIZE		SDRAM_BANK_SIZE
+
+/* Configuration of ENV Blocks */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+
+// TODO fix addresses
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x42000000\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x43300000\0" \
+	"scriptaddr=0x50000000\0" \
+	"pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS \
+	EXYNOS_FDTFILE_SETTING \
+	MEM_LAYOUT_ENV_SETTINGS
+
+#endif	/* __CONFIG_EXYNOS9820_COMMON_H */