dts: use minimal dts
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@ -1,82 +1,217 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Samsung Exynos7420 SoC device tree source
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* SAMSUNG EXYNOS9820 SoC device tree source
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS9820 SoC device nodes are listed in this file.
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* EXYNOS based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/exynos7420-clk.h>
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/ {
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compatible = "samsung,exynos7420";
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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fin_pll: xxti {
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#include "exynos9820-pinctrl.dtsi"
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/ {
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compatible = "samsung,armv8", "samsung,exynos9820";
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dtb-hw_rev = <0>;
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dtb-hw_rev_end = <255>;
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <1>;
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xxti: clock {
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/* XXTI */
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compatible = "fixed-clock";
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clock-output-names = "fin_pll";
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u-boot,dm-pre-reloc;
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clock-output-names = "oscclk";
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#clock-cells = <0>;
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};
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clock_topc: clock-controller@10570000 {
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compatible = "samsung,exynos7-clock-topc";
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reg = <0x10570000 0x10000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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clocks = <&fin_pll>;
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clock-names = "fin_pll";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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clock_top0: clock-controller@105d0000 {
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compatible = "samsung,exynos7-clock-top0";
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reg = <0x105d0000 0xb000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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<&clock_topc DOUT_SCLK_BUS1_PLL>,
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<&clock_topc DOUT_SCLK_CC_PLL>,
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<&clock_topc DOUT_SCLK_MFC_PLL>;
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clock-names = "fin_pll", "dout_sclk_bus0_pll",
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"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
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"dout_sclk_mfc_pll";
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};
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cpu-map {
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cluster0 {
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coregroup0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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clock_peric1: clock-controller@14c80000 {
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compatible = "samsung,exynos7-clock-peric1";
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reg = <0x14c80000 0xd00>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
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<&clock_top0 CLK_SCLK_UART1>,
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<&clock_top0 CLK_SCLK_UART2>,
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<&clock_top0 CLK_SCLK_UART3>;
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clock-names = "fin_pll", "dout_aclk_peric1_66",
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"sclk_uart1", "sclk_uart2", "sclk_uart3";
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};
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coregroup1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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};
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};
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pinctrl@13470000 {
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compatible = "samsung,exynos7420-pinctrl";
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reg = <0x13470000 0x1000>;
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u-boot,dm-pre-reloc;
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cluster1 {
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coregroup0 {
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core0 {
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cpu = <&cpu6>;
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};
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core1 {
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cpu = <&cpu7>;
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};
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};
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};
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serial2_bus: serial2-bus {
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samsung,pins = "gpd1-4", "gpd1-5";
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samsung,pin-function = <2>;
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samsung,pin-pud = <3>;
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samsung,pin-drv = <0>;
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u-boot,dm-pre-reloc;
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55", "arm,armv8";
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reg = <0x0 0x0000>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55", "arm,armv8";
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reg = <0x0 0x0001>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a55", "arm,armv8";
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reg = <0x0 0x0002>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a55", "arm,armv8";
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reg = <0x0 0x0003>;
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enable-method = "psci";
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};
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cpu4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a75", "arm,armv8";
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reg = <0x0 0x0004>;
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enable-method = "psci";
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};
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cpu5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a75", "arm,armv8";
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reg = <0x0 0x0005>;
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enable-method = "psci";
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};
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cpu6: cpu@100 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m4", "arm,armv8";
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reg = <0x0 0x0100>;
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enable-method = "psci";
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};
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cpu7: cpu@101 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m4", "arm,armv8";
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reg = <0x0 0x0101>;
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enable-method = "psci";
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};
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};
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serial@14C30000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x14C30000 0x100>;
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u-boot,dm-pre-reloc;
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clocks = <&clock_peric1 PCLK_UART2>,
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<&clock_peric1 SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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pinctrl-names = "default";
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pinctrl-0 = <&serial2_bus>;
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_suspend = <0xC4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xC4000003>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ramoops@92000000 {
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compatible = "ramoops";
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reg = <0 0x92000000 0 0x8000>;
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record-size = <0x4000>;
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console-size = <0x4000>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0x18000000>;
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gic: interrupt-controller@10200000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10201000 0x1000>,
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<0x10202000 0x1000>,
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<0x10204000 0x2000>,
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<0x10206000 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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mct: mct@10040000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10040000 0x800>;
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interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
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// TODO clocks
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//clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
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//clock-names = "fin_pll", "mct";
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};
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};
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chipid@10000000 {
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compatible = "samsung,exynos850-chipid";
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reg = <0x0 0x10000000 0x100>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <26000000>;
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use-clocksource-only;
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use-physical-timer;
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};
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};
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