Prepare v2019.10-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>
Merge branch '2019-08-26-master-imports'
2019-08-26 20:16:42 -04:00 · 2019-08-26 17:45:20 -04:00 · 2019-08-26 11:46:30 -04:00 · 2019-08-26 11:46:30 -04:00 · 2019-08-26 11:46:29 -04:00 · 2019-08-26 11:46:29 -04:00
805 changed files with 4590 additions and 5461 deletions
@@ -4,10 +4,18 @@
 # and/or not always written the same way, making contributions from the
 # same person appearing not to be so or badly displayed.
 #
+# This file is also used by scripts/get_maintainer.pl.
+#
 # This file can be modified by hand or updated by the following command:
 #  scripts/mailmapper > tmp; mv tmp .mailmap
 #
+# Entries in this file take one of the following forms:
+# Proper Name <commit@email.xx>
+# <proper@email.xx> <commit@email.xx>
+# Proper Name <proper@email.xx> <commit@email.xx>
+# Proper Name <proper@email.xx> Commit Name <commit@email.xx>

+Alexander Graf <agraf@csgraf.de> <agraf@suse.de>
 Allen Martin <amartin@nvidia.com>
 Andreas Bießmann <andreas.devel@googlemail.com>
 Andreas Bießmann <andreas@biessmann.org>
@@ -23,8 +31,8 @@ Markus Klotzbuecher <mk@denx.de>
 Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
 Prabhakar Kushwaha <prabhakar@freescale.com>
 Rajeshwari Shinde <rajeshwari.s@samsung.com>
-Ricardo Ribalda <ricardo.ribalda@uam.es>
-Ricardo Ribalda <ricardo.ribalda@gmail.com>
+Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
+Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
 Sandeep Paulraj <s-paulraj@ti.com>
 Shaohui Xie <Shaohui.Xie@freescale.com>
 Stefan Roese <stroese>
@@ -156,14 +156,15 @@ config SYS_MALLOC_F_LEN

 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
-	depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP
+	depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
+	default 0x2000000 if ARCH_ROCKCHIP
 	help
 	  This defines memory to be allocated for Dynamic allocation
 	  TODO: Use for other architectures

 config SPL_SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool in SPL before relocation"
-	depends on SYS_MALLOC_F
+	depends on SYS_MALLOC_F && SPL
 	default 0x2800 if RCAR_GEN3
 	default SYS_MALLOC_F_LEN
 	help
@@ -174,7 +175,7 @@ config SPL_SYS_MALLOC_F_LEN

 config TPL_SYS_MALLOC_F_LEN
 	hex "Size of malloc() pool in TPL before relocation"
-	depends on SYS_MALLOC_F
+	depends on SYS_MALLOC_F && TPL
 	default SYS_MALLOC_F_LEN
 	help
 	  Before relocation, memory is very limited on many platforms. Still,
@@ -238,6 +239,7 @@ config SPL_IMAGE
 	string "SPL image used in the combined SPL+U-Boot image"
 	default "spl/boot.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "spl/u-boot-spl.bin"
+	depends on SPL
 	help
 	  Select the SPL build target that shall be generated by the SPL
 	  build process (default spl/u-boot-spl.bin). This image will be
@@ -250,7 +252,8 @@ config BUILD_TARGET
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
 	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
-	default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI)
+	default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || \
+				ARCH_SUNXI || RISCV)
 	default "u-boot.kwb" if KIRKWOOD
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	help
@@ -463,6 +466,7 @@ config SPL_FIT_GENERATOR
 	depends on SPL_FIT
 	default "board/sunxi/mksunxi_fit_atf.sh" if SPL_LOAD_FIT && ARCH_SUNXI
 	default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
+	default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
 	help
 	  Specifies a (platform specific) script file to generate the FIT
 	  source file used to build the U-Boot FIT image file. This gets
@@ -3,7 +3,7 @@
 VERSION = 2019
 PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 NAME =

 # *DOCUMENTATION*
@@ -1257,7 +1257,9 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 		-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage

 u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
-		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin dts/dt.dtb,u-boot.bin) FORCE
+		$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
+			$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+		,u-boot.bin) FORCE
 	$(call if_changed,mkimage)
 	$(BOARD_SIZE_CHECK)

@@ -1267,7 +1269,9 @@ else
 MKIMAGEFLAGS_u-boot.itb = -E
 endif

-u-boot.itb: u-boot-nodtb.bin dts/dt.dtb $(U_BOOT_ITS) FORCE
+u-boot.itb: u-boot-nodtb.bin \
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+		$(U_BOOT_ITS) FORCE
 	$(call if_changed,mkfitimage)
 	$(BOARD_SIZE_CHECK)

@@ -267,6 +267,13 @@ board_init_f():
 	- preloader_console_init() can be called here in extremis
 	- should set up SDRAM, and anything needed to make the UART work
 	- these is no need to clear BSS, it will be done by crt0.S
+	- for specific scenarios on certain architectures an early BSS *can*
+	  be made available (via CONFIG_SPL_EARLY_BSS by moving the clearing
+	  of BSS prior to entering board_init_f()) but doing so is discouraged.
+	  Instead it is strongly recommended to architect any code changes
+	  or additions such to not depend on the availability of BSS during
+	  board_init_f() as indicated in other sections of this README to
+	  maintain compatibility and consistency across the entire code base.
 	- must return normally from this function (don't call board_init_r()
 		directly)

@@ -76,6 +76,12 @@ config RISCV
 	imply MTD
 	imply TIMER
 	imply CMD_DM
+	imply SPL_DM
+	imply SPL_OF_CONTROL
+	imply SPL_LIBCOMMON_SUPPORT
+	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_SERIAL_SUPPORT
+	imply SPL_TIMER

 config SANDBOX
 	bool "Sandbox"
@@ -329,6 +329,12 @@ config SYS_CACHELINE_SIZE
 	default 64 if SYS_CACHE_SHIFT_6
 	default 32 if SYS_CACHE_SHIFT_5

+config ARCH_CPU_INIT
+	bool "Enable ARCH_CPU_INIT"
+	help
+	  Some architectures require a call to arch_cpu_init()
+	  Say Y here to enable it
+
 config SYS_ARCH_TIMER
 	bool "ARM Generic Timer support"
 	depends on CPU_V7A || ARM64
@@ -367,7 +373,7 @@ config SYS_THUMB_BUILD
 config SPL_SYS_THUMB_BUILD
 	bool "Build SPL using the Thumb instruction set"
 	default y if SYS_THUMB_BUILD
-	depends on !ARM64
+	depends on !ARM64 && SPL
 	help
 	   Use this flag to build SPL using the Thumb instruction set for
 	   ARM architectures. Thumb instruction set provides better code
@@ -414,7 +420,7 @@ config USE_ARCH_MEMCPY
 config SPL_USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy for SPL"
 	default y if USE_ARCH_MEMCPY
-	depends on !ARM64
+	depends on !ARM64 && SPL
 	help
 	  Enable the generation of an optimized version of memcpy.
 	  Such implementation may be faster under some conditions
@@ -423,7 +429,7 @@ config SPL_USE_ARCH_MEMCPY
 config TPL_USE_ARCH_MEMCPY
 	bool "Use an assembly optimized implementation of memcpy for TPL"
 	default y if USE_ARCH_MEMCPY
-	depends on !ARM64
+	depends on !ARM64 && TPL
 	help
 	  Enable the generation of an optimized version of memcpy.
 	  Such implementation may be faster under some conditions
@@ -441,7 +447,7 @@ config USE_ARCH_MEMSET
 config SPL_USE_ARCH_MEMSET
 	bool "Use an assembly optimized implementation of memset for SPL"
 	default y if USE_ARCH_MEMSET
-	depends on !ARM64
+	depends on !ARM64 && SPL
 	help
 	  Enable the generation of an optimized version of memset.
 	  Such implementation may be faster under some conditions
@@ -450,7 +456,7 @@ config SPL_USE_ARCH_MEMSET
 config TPL_USE_ARCH_MEMSET
 	bool "Use an assembly optimized implementation of memset for TPL"
 	default y if USE_ARCH_MEMSET
-	depends on !ARM64
+	depends on !ARM64 && TPL
 	help
 	  Enable the generation of an optimized version of memset.
 	  Such implementation may be faster under some conditions
@@ -458,7 +464,8 @@ config TPL_USE_ARCH_MEMSET

 config ARM64_SUPPORT_AARCH32
 	bool "ARM64 system support AArch32 execution state"
-	default y if ARM64 && !TARGET_THUNDERX_88XX
+	depends on ARM64
+	default y if !TARGET_THUNDERX_88XX
 	help
 	  This ARM64 system supports AArch32 execution state.

@@ -1093,6 +1100,7 @@ config TARGET_LS2080A_SIMU
 	select ARCH_MISC_INIT
 	select ARM64
 	select ARMV8_MULTIENTRY
+	select BOARD_LATE_INIT
 	help
 	  Support for Freescale LS2080A_SIMU platform
 	  The LS2080A Development System (QDS) is a pre silicon
@@ -1306,6 +1314,8 @@ config TARGET_LS1028AQDS
 	select ARM64
 	select ARMV8_MULTIENTRY
 	select ARCH_SUPPORT_TFABOOT
+	select BOARD_LATE_INIT
+	select ARCH_MISC_INIT
 	help
 	  Support for Freescale LS1028AQDS platform
 	  The LS1028A Development System (QDS) is a high-performance
@@ -40,14 +40,6 @@ config ARCH_LS1028A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
-	select SYS_I2C_MXC_I2C1
-	select SYS_I2C_MXC_I2C2
-	select SYS_I2C_MXC_I2C3
-	select SYS_I2C_MXC_I2C4
-	select SYS_I2C_MXC_I2C5
-	select SYS_I2C_MXC_I2C6
-	select SYS_I2C_MXC_I2C7
-	select SYS_I2C_MXC_I2C8
 	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_ERRATUM_A008514 if !TFABOOT
@@ -155,10 +147,10 @@ config ARCH_LS1088A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
-	select SYS_I2C_MXC_I2C1
-	select SYS_I2C_MXC_I2C2
-	select SYS_I2C_MXC_I2C3
-	select SYS_I2C_MXC_I2C4
+	select SYS_I2C_MXC_I2C1 if !TFABOOT
+	select SYS_I2C_MXC_I2C2 if !TFABOOT
+	select SYS_I2C_MXC_I2C3 if !TFABOOT
+	select SYS_I2C_MXC_I2C4 if !TFABOOT
 	imply SCSI
 	imply PANIC_HANG

@@ -205,10 +197,10 @@ config ARCH_LS2080A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
-	select SYS_I2C_MXC_I2C1
-	select SYS_I2C_MXC_I2C2
-	select SYS_I2C_MXC_I2C3
-	select SYS_I2C_MXC_I2C4
+	select SYS_I2C_MXC_I2C1 if !TFABOOT
+	select SYS_I2C_MXC_I2C2 if !TFABOOT
+	select SYS_I2C_MXC_I2C3 if !TFABOOT
+	select SYS_I2C_MXC_I2C4 if !TFABOOT
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG

@@ -235,14 +227,6 @@ config ARCH_LX2160A
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
 	select SYS_I2C_MXC
-	select SYS_I2C_MXC_I2C1
-	select SYS_I2C_MXC_I2C2
-	select SYS_I2C_MXC_I2C3
-	select SYS_I2C_MXC_I2C4
-	select SYS_I2C_MXC_I2C5
-	select SYS_I2C_MXC_I2C6
-	select SYS_I2C_MXC_I2C7
-	select SYS_I2C_MXC_I2C8
 	imply DISTRO_DEFAULTS
 	imply PANIC_HANG
 	imply SCSI
@@ -513,6 +497,10 @@ config SYS_FSL_DUART_CLK_DIV
 config SYS_FSL_I2C_CLK_DIV
 	int "I2C clock divider"
 	default 1 if ARCH_LS1043A
+	default 4 if ARCH_LS1012A
+	default 4 if ARCH_LS1028A
+	default 8 if ARCH_LX2160A
+	default 8 if ARCH_LS1088A
 	default 2
 	help
 	  This is the divider that is used to derive I2C clock from Platform
@@ -47,8 +47,10 @@ endif

 ifneq ($(CONFIG_ARCH_LS1088A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
+obj-y += icid.o ls1088_ids.o
 endif

 ifneq ($(CONFIG_ARCH_LS1028A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
+obj-y += icid.o ls1028_ids.o
 endif
@@ -17,7 +17,10 @@ static void set_icid(struct icid_id_table *tbl, int size)
 	int i;

 	for (i = 0; i < size; i++)
-		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+		if (tbl[i].le)
+			out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+		else
+			out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
 }

 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+struct icid_id_table icid_tbl[] = {
+	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+	SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+	SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
+	SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
+	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+	SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
+	SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
+	SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+	SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+	SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+struct icid_id_table icid_tbl[] = {
+	SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
+	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+	SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
+	SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+	SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+	SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
+	SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
+	SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
+	SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
@@ -340,6 +340,10 @@ void fsl_lsch3_early_init_f(void)
 	if (fsl_check_boot_mode_secure() == 1)
 		bypass_smmu();
 #endif
+
+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
+	set_icids();
+#endif
 }

 /* Get VDD in the unit mV from voltage ID */
@@ -81,7 +81,6 @@ dtb-$(CONFIG_ROCKCHIP_RK322X) += \

 dtb-$(CONFIG_ROCKCHIP_RK3288) += \
 	rk3288-evb.dtb \
-	rk3288-fennec.dtb \
 	rk3288-firefly.dtb \
 	rk3288-miqi.dtb \
 	rk3288-phycore-rdk.dtb \
@@ -807,4 +806,4 @@ PHONY += dtbs
 dtbs: $(addprefix $(obj)/, $(dtb-y))
 	@:

-clean-files := *.dtb
+clean-files := *.dtb *_HS
@@ -37,10 +37,23 @@

 &i2c0 {
 	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
 };

 &i2c1 {
 	status = "okay";
+
+	rtc@51 {
+		compatible = "pcf2127-rtc";
+		reg = <0x51>;
+	};
 };

 &i2c2 {
@@ -37,6 +37,26 @@

 &i2c0 {
 	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	 i2c-mux@77 {
+
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			rtc@51 {
+				compatible = "pcf2127-rtc";
+				reg = <0x51>;
+			};
+		};
+	};
 };

 &i2c1 {
@@ -18,6 +18,29 @@
 	};
 };

+&i2c0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			rtc@51 {
+				compatible = "pcf2127-rtc";
+				reg = <0x51>;
+			};
+		};
+	};
+};
+
 &ifc {
 	#address-cells = <2>;
 	#size-cells = <1>;
@@ -17,6 +17,29 @@
 	};
 };

+&i2c0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			rtc@51 {
+				compatible = "pcf2127-rtc";
+				reg = <0x51>;
+			};
+		};
+	};
+};
+
 &qspi {
 	bus-num = <0>;
 	status = "okay";
@@ -34,6 +34,38 @@
 			     <1 10 0x8>; /* Hypervisor PPI, active-low */
 	};

+	i2c0: i2c@2000000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2000000 0x0 0x10000>;
+		interrupts = <0 34 4>;
+	};
+
+	i2c1: i2c@2010000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2010000 0x0 0x10000>;
+		interrupts = <0 34 4>;
+	};
+
+	i2c2: i2c@2020000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2020000 0x0 0x10000>;
+		interrupts = <0 35 4>;
+	};
+
+	i2c3: i2c@2030000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2030000 0x0 0x10000>;
+		interrupts = <0 35 4>;
+	};
+
 	serial0: serial@21c0500 {
 		device_type = "serial";
 		compatible = "fsl,ns16550", "ns16550a";
@@ -19,6 +19,25 @@
 	};
 };

+&i2c0 {
+	status = "okay";
+	pca9547@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00>;
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+			};
+		};
+	};
+};
+
 &dspi {
 	bus-num = <0>;
 	status = "okay";
@@ -56,6 +56,42 @@
 		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 	};

+	i2c0: i2c@2000000 {
+		status = "disabled";
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2000000 0x0 0x10000>;
+		interrupts = <0 34 0x4>; /* Level high type */
+	};
+
+	i2c1: i2c@2010000 {
+		status = "disabled";
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2010000 0x0 0x10000>;
+		interrupts = <0 34 0x4>; /* Level high type */
+	};
+
+	i2c2: i2c@2020000 {
+		status = "disabled";
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2020000 0x0 0x10000>;
+		interrupts = <0 35 0x4>; /* Level high type */
+	};
+
+	i2c3: i2c@2030000 {
+		status = "disabled";
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2030000 0x0 0x10000>;
+		interrupts = <0 35 0x4>; /* Level high type */
+	};
+
 	dspi: dspi@2100000 {
 		compatible = "fsl,vf610-dspi";
 		#address-cells = <1>;
@@ -57,6 +57,28 @@
 	};
 };

+&i2c0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	pca9547@75 {
+		compatible = "nxp,pca9547";
+		reg = <0x75>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		 i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x01>;
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+			};
+		};
+	};
+};
+
 &sata {
 	status = "okay";
 };
@@ -23,6 +23,29 @@
 	status = "okay";
 };

+&i2c0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	i2c-mux@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			rtc@51 {
+				compatible = "pcf2127-rtc";
+				reg = <0x51>;
+			};
+		};
+	};
+};
+
 &sata0 {
 	status = "okay";
 };
@@ -27,6 +27,20 @@
 	status = "okay";
 };

+&i2c0 {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+};
+
+&i2c4 {
+	status = "okay";
+
+	rtc@51 {
+		compatible = "pcf2127-rtc";
+		reg = <0x51>;
+	};
+};
+
 &sata0 {
 	status = "okay";
 };
@@ -49,6 +49,80 @@
 			     <1 10 0x8>; /* Hypervisor PPI, active-low */
 	};

+	i2c0: i2c@2000000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2000000 0x0 0x10000>;
+		interrupts = <0 34 4>;
+		scl-gpio = <&gpio2 15 0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@2010000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2010000 0x0 0x10000>;
+		interrupts = <0 34 4>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@2020000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2020000 0x0 0x10000>;
+		interrupts = <0 35 4>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@2030000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2030000 0x0 0x10000>;
+		interrupts = <0 35 4>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@2040000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2040000 0x0 0x10000>;
+		interrupts = <0 74 4>;
+		scl-gpio = <&gpio2 16 0>;
+		status = "disabled";
+	};
+
+	i2c5: i2c@2050000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2050000 0x0 0x10000>;
+		interrupts = <0 74 4>;
+		status = "disabled";
+	};
+
+	i2c6: i2c@2060000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2060000 0x0 0x10000>;
+		interrupts = <0 75 4>;
+		status = "disabled";
+	};
+
+	i2c7: i2c@2070000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2070000 0x0 0x10000>;
+		interrupts = <0 75 4>;
+		status = "disabled";
+	};
+
 	uart0: serial@21c0000 {
 		compatible = "arm,pl011";
 		reg = <0x0 0x21c0000 0x0 0x1000>;
@@ -102,6 +176,17 @@
 		num-cs = <6>;
 	};

+	gpio2: gpio@2320000 {
+		compatible = "fsl,qoriq-gpio";
+		reg = <0x0 0x2320000 0x0 0x10000>;
+		interrupts = <0 37 4>;
+		gpio-controller;
+		little-endian;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	usb0: usb3@3100000 {
 		compatible = "fsl,layerscape-dwc3";
 		reg = <0x0 0x3100000 0x0 0x10000>;
@@ -228,6 +228,20 @@
 		>;
 	};

+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */
+			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */
+		>;
+	};
+
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */
+			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */
+		>;
+	};
+
 	tsc2004_pins: pinmux_tsc2004_pins {
 		pinctrl-single,pins = <
 			OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4)	/* mcbsp4_dr.gpio_153 */
@@ -249,18 +263,6 @@
 			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */
 		>;
 	};
-	i2c2_pins: pinmux_i2c2_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0)	/* i2c2_scl */
-			OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0)	/* i2c2_sda */
-		>;
-	};
-	i2c3_pins: pinmux_i2c3_pins {
-		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0)	/* i2c3_scl */
-			OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0)	/* i2c3_sda */
-		>;
-	};
 };

 &omap3_pmx_core2 {
@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Rockchip Electronics Co., Ltd
- */
-
-#include "rk3288-u-boot.dtsi"
-
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
-	u-boot,dm-pre-reloc;
-};
-
-&pcfg_pull_none_drv_8ma {
-	u-boot,dm-spl;
-};
-
-&pcfg_pull_up_drv_8ma {
-	u-boot,dm-spl;
-};
-
-&sdmmc_bus4 {
-	u-boot,dm-spl;
-};
-
-&sdmmc_clk {
-	u-boot,dm-spl;
-};
-
-&sdmmc_cmd {
-	u-boot,dm-spl;
-};
-
-&sdmmc_pwr {
-	u-boot,dm-spl;
-};
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include "rk3288-fennec.dtsi"
-
-/ {
-	model = "Rockchip RK3288 Fennec Board";
-	compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
-
-	chosen {
-		stdout-path = &uart2;
-	};
-};
-
-&dmc {
-	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
-		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
-		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
-		0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
-		0x8 0x1f4>;
-	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
-		0x0 0xc3 0x6 0x2>;
-	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
-};
-
-&pwm1 {
-	status = "okay";
-};
@@ -1,421 +0,0 @@
-/*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "rk3288.dtsi"
-
-/ {
-	memory {
-		reg = <0x0 0x80000000>;
-		device_type = "memory";
-	};
-
-	ext_gmac: external-gmac-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <125000000>;
-		clock-output-names = "ext_gmac";
-	};
-
-	vcc_sys: vsys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_sys";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-};
-
-&cpu0 {
-	cpu0-supply = <&vdd_cpu>;
-};
-
-&emmc {
-	bus-width = <8>;
-	cap-mmc-highspeed;
-	disable-wp;
-	non-removable;
-	num-slots = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	card-detect-delay = <200>;
-	disable-wp;
-	num-slots = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
-	status = "okay";
-	vmmc-supply = <&vcc_sd>;
-	vqmmc-supply = <&vccio_sd>;
-};
-
-&gmac {
-	assigned-clocks = <&cru SCLK_MAC>;
-	assigned-clock-parents = <&ext_gmac>;
-	clock_in_out = "input";
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
-	phy-supply = <&vcc_lan>;
-	phy-mode = "rgmii";
-	snps,reset-active-low;
-	snps,reset-delays-us = <0 10000 1000000>;
-	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
-	tx_delay = <0x30>;
-	rx_delay = <0x10>;
-	status = "okay";
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&hdmi {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <400000>;
-
-	rk808: pmic@1b {
-		compatible = "rockchip,rk808";
-		reg = <0x1b>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		clock-output-names = "xin32k", "rk808-clkout2";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int &global_pwroff>;
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vcc_sys>;
-		vcc2-supply = <&vcc_sys>;
-		vcc3-supply = <&vcc_sys>;
-		vcc4-supply = <&vcc_sys>;
-		vcc6-supply = <&vcc_sys>;
-		vcc7-supply = <&vcc_sys>;
-		vcc8-supply = <&vcc_io>;
-		vcc9-supply = <&vcc_io>;
-		vcc10-supply = <&vcc_io>;
-		vcc11-supply = <&vcc_io>;
-		vcc12-supply = <&vcc_io>;
-		vddio-supply = <&vcc_io>;
-
-		regulators {
-			vdd_cpu: DCDC_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-name = "vdd_arm";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <1250000>;
-				regulator-name = "vdd_gpu";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc_ddr";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_io: DCDC_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc_io";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vccio_pmu: LDO_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vccio_pmu";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_33: LDO_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcca_33";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_10: LDO_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
-				regulator-name = "vdd_10";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-
-			vcc_wl: LDO_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc_wl";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vccio_sd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vdd10_lcd: LDO_REG6 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
-				regulator-name = "vdd10_lcd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-
-			vcc_18: LDO_REG7 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc_18";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc18_lcd: LDO_REG8 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc18_lcd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc_sd: SWITCH_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc_sd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_lan: SWITCH_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc_lan";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-&pinctrl {
-	pcfg_output_high: pcfg-output-high {
-		output-high;
-	};
-
-	pcfg_output_low: pcfg-output-low {
-		output-low;
-	};
-
-	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
-		drive-strength = <8>;
-	};
-
-	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
-		bias-pull-up;
-		drive-strength = <8>;
-	};
-
-	gmac {
-		phy_int: phy-int {
-			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-
-		phy_pmeb: phy-pmeb {
-			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-
-		phy_rst: phy-rst {
-			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic-int {
-			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	sdmmc {
-		sdmmc_bus4: sdmmc-bus4 {
-			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
-		};
-
-		sdmmc_clk: sdmmc-clk {
-			rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
-		};
-
-		sdmmc_cmd: sdmmc-cmd {
-			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
-		};
-
-		sdmmc_pwr: sdmmc-pwr {
-			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	usbphy {
-		host_drv: host-drv {
-			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&host_drv>;
-	vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host1 {
-	status = "okay";
-};
-
-&usb_otg {
-	status = "okay";
-};
-
-&usb_hsic {
-	status = "okay";
-};
-
-&vopb {
-	status = "okay";
-};
-
-&vopb_mmu {
-	status = "okay";
-};
-
-&vopl {
-	status = "okay";
-};
-
-&vopl_mmu {
-	status = "okay";
-};
-
-&vpu {
-	status = "okay";
-};
@@ -1,33 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd
 */

+#include "rk3328-u-boot.dtsi"
 #include "rk3328-sdram-ddr3-666.dtsi"

-/ {
-	aliases {
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		u-boot,spl-boot-order = &emmc, &sdmmc;
-	};
-};
-
-&cru {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
+&usb_host0_xhci {
+	vbus-supply = <&vcc5v0_host_xhci>;
+	status = "okay";
 };
@@ -116,11 +116,6 @@
 	status = "okay";
 };

-&usb_host0_xhci {
-	vbus-supply = <&vcc5v0_host_xhci>;
-	status = "okay";
-};
-
 &i2c1 {
 	clock-frequency = <400000>;
 	i2c-scl-rising-time-ns = <168>;
@@ -1,34 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2018 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
 */

+#include "rk3328-u-boot.dtsi"
 #include "rk3328-sdram-lpddr3-1600.dtsi"

-/ {
-	aliases {
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		u-boot,spl-boot-order = &emmc, &sdmmc;
-	};
-};
-
-&cru {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
+&usb_host0_xhci {
+	status = "okay";
 };
@@ -34,23 +34,10 @@

 	vcc_host_5v: vcc-host-5v-regulator {
 		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&usb30_host_drv>;
-		regulator-name = "vcc_host_5v";
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&usb20_host_drv>;
-		regulator-name = "vcc_host1_5v";
+		regulator-name = "vcc_host_5v";
 		regulator-always-on;
 		regulator-boot-on;
 		vin-supply = <&vcc_sys>;
@@ -244,12 +231,6 @@
 			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
-
-	usb3 {
-		usb30_host_drv: usb30-host-drv {
-			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
 };

 &sdmmc {
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+/ {
+	aliases {
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		u-boot,spl-boot-order = &emmc, &sdmmc;
+	};
+
+	dmc: dmc {
+		u-boot,dm-pre-reloc;
+		compatible = "rockchip,rk3328-dmc";
+		reg = <0x0 0xff400000 0x0 0x1000
+		       0x0 0xff780000 0x0 0x3000
+		       0x0 0xff100000 0x0 0x1000
+		       0x0 0xff440000 0x0 0x1000
+		       0x0 0xff720000 0x0 0x1000
+		       0x0 0xff798000 0x0 0x1000>;
+	};
+
+	usb_host0_xhci: usb@ff600000 {
+		compatible = "rockchip,rk3328-xhci";
+		reg = <0x0 0xff600000 0x0 0x100000>;
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		snps,dis-enblslpm-quirk;
+		snps,phyif-utmi-bits = <16>;
+		snps,dis-u2-freeclk-exists-quirk;
+		snps,dis-u2-susphy-quirk;
+		status = "disabled";
+	};
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+	clock-frequency = <24000000>;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};
@@ -186,7 +186,6 @@
 	};

 	grf: syscon@ff100000 {
-		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff100000 0x0 0x1000>;

@@ -232,7 +231,6 @@
 		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		clock-names = "baudclk", "apb_pclk";
-		clock-frequency = <24000000>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		dmas = <&dmac 6>, <&dmac 7>;
@@ -351,17 +349,6 @@
 		status = "disabled";
 	};

-	dmc: dmc {
-		u-boot,dm-pre-reloc;
-		compatible = "rockchip,rk3328-dmc";
-		reg = <0x0 0xff400000 0x0 0x1000
-		       0x0 0xff780000 0x0 0x3000
-		       0x0 0xff100000 0x0 0x1000
-		       0x0 0xff440000 0x0 0x1000
-		       0x0 0xff720000 0x0 0x1000
-		       0x0 0xff798000 0x0 0x1000>;
-	};
-
 	cru: clock-controller@ff440000 {
 		compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 		reg = <0x0 0xff440000 0x0 0x1000>;
@@ -512,17 +499,6 @@
 		status = "disabled";
 	};

-	usb_host0_xhci: usb@ff600000 {
-		compatible = "rockchip,rk3328-xhci";
-		reg = <0x0 0xff600000 0x0 0x100000>;
-		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-		snps,dis-enblslpm-quirk;
-		snps,phyif-utmi-bits = <16>;
-		snps,dis-u2-freeclk-exists-quirk;
-		snps,dis-u2-susphy-quirk;
-		status = "disabled";
-	};
-
 	gic: interrupt-controller@ffb70000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;
@@ -178,8 +178,10 @@
 #elif defined(CONFIG_ARCH_LX2160A)
 #define TZPC_BASE				0x02200000
 #define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#if !defined(CONFIG_DM_I2C)
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_EARLY_INIT
+#endif
 #define SRDS_MAX_LANES  8
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT		6
@@ -17,6 +17,7 @@ struct icid_id_table {
 	u32 reg;
 	phys_addr_t compat_addr;
 	phys_addr_t reg_addr;
+	bool le;
 };

 struct fman_icid_id_table {
@@ -30,18 +31,35 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
 void set_icids(void);
 void fdt_fixup_icid(void *blob);

-#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
+#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
 	{ .compat = name, \
 	  .id = idA, \
 	  .reg = regA, \
 	  .compat_addr = compataddr, \
 	  .reg_addr = addr, \
+	  .le = _le \
 	}

+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define SEC_IS_LE true
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define SEC_IS_LE false
+#endif
+
+#ifdef CONFIG_FSL_LSCH2
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define SCFG_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define SCFG_IS_LE false
+#endif
+
+#define QDMA_IS_LE false
+
 #define SET_SCFG_ICID(compat, streamid, name, compataddr) \
 	SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
 		offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
-		compataddr)
+		compataddr, SCFG_IS_LE)

 #define SET_USB_ICID(usb_num, compat, streamid) \
 	SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
@@ -55,14 +73,6 @@ void fdt_fixup_icid(void *blob);
 	SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
 		CONFIG_SYS_FSL_ESDHC_ADDR)

-#define SET_QDMA_ICID(compat, streamid) \
-	SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
-		QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
-		QDMA_BASE_ADDR), \
-	SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
-		QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
-		QDMA_BASE_ADDR)
-
 #define SET_EDMA_ICID(streamid) \
 	SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
 		EDMA_BASE_ADDR)
@@ -81,22 +91,78 @@ void fdt_fixup_icid(void *blob);
 	SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
 		offsetof(struct ccsr_qman, liodnr) + \
 		CONFIG_SYS_FSL_QMAN_ADDR, \
-		CONFIG_SYS_FSL_QMAN_ADDR)
+		CONFIG_SYS_FSL_QMAN_ADDR, false)

 #define SET_BMAN_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
 		offsetof(struct ccsr_bman, liodnr) + \
 		CONFIG_SYS_FSL_BMAN_ADDR, \
-		CONFIG_SYS_FSL_BMAN_ADDR)
+		CONFIG_SYS_FSL_BMAN_ADDR, false)

 #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
 	{ .port_id = (_port_id), .icid = (streamid) }

+#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
+
 #define SET_SEC_QI_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
 		0, offsetof(ccsr_sec_t, qilcr_ls) + \
 		CONFIG_SYS_FSL_SEC_ADDR, \
-		CONFIG_SYS_FSL_SEC_ADDR)
+		CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+
+extern struct fman_icid_id_table fman_icid_tbl[];
+extern int fman_icid_tbl_sz;
+
+#else /* CONFIG_FSL_LSCH2 */
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define GUR_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define GUR_IS_LE false
+#endif
+
+#define QDMA_IS_LE true
+
+#define SET_GUR_ICID(compat, streamid, name, compataddr) \
+	SET_ICID_ENTRY(compat, streamid, streamid, \
+		offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+		compataddr, GUR_IS_LE)
+
+#define SET_USB_ICID(usb_num, compat, streamid) \
+	SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
+		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(sata_num, compat, streamid) \
+	SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
+		AHCI_BASE_ADDR##sata_num)
+
+#define SET_SDHC_ICID(sdhc_num, streamid) \
+	SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
+		FSL_ESDHC##sdhc_num##_BASE_ADDR)
+
+#define SET_EDMA_ICID(streamid) \
+	SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
+		EDMA_BASE_ADDR)
+
+#define SET_GPU_ICID(compat, streamid) \
+	SET_GUR_ICID(compat, streamid, misc1_amqr,\
+		GPU_BASE_ADDR)
+
+#define SET_DISPLAY_ICID(streamid) \
+	SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
+		DISPLAY_BASE_ADDR)
+
+#define SEC_ICID_REG_VAL(streamid) (streamid)
+
+#endif /* CONFIG_FSL_LSCH2 */
+
+#define SET_QDMA_ICID(compat, streamid) \
+	SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
+		QDMA_BASE_ADDR, QDMA_IS_LE), \
+	SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
+		QDMA_BASE_ADDR, QDMA_IS_LE)

 #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
 	SET_ICID_ENTRY( \
@@ -106,24 +172,22 @@ void fdt_fixup_icid(void *blob);
 			? NULL \
 			: "fsl,sec-v4.0-job-ring"), \
 		streamid, \
-		(((streamid) << 16) | (streamid)), \
+		SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
 		CONFIG_SYS_FSL_SEC_ADDR, \
-		FSL_SEC_JR##jr_num##_BASE_ADDR)
+		FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)

 #define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
-	SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, 0)
+		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)

 #define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
-	SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
+	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, 0)
+		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)

 extern struct icid_id_table icid_tbl[];
-extern struct fman_icid_id_table fman_icid_tbl[];
 extern int icid_tbl_sz;
-extern int fman_icid_tbl_sz;

 #endif
@@ -25,6 +25,8 @@
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR			CONFIG_SYS_FSL_ESDHC_ADDR
+#define FSL_ESDHC2_BASE_ADDR			(CONFIG_SYS_IMMR + 0x01150000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #endif
@@ -79,20 +81,41 @@
 #define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
 #define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)

+/* EDMA */
+#define EDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x012c0000)
+
 /* SATA */
 #define AHCI_BASE_ADDR1				(CONFIG_SYS_IMMR + 0x02200000)
 #define AHCI_BASE_ADDR2				(CONFIG_SYS_IMMR + 0x02210000)

+/* QDMA */
+#define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG				0x20a80
+
+/* DISPLAY */
+#define DISPLAY_BASE_ADDR			(CONFIG_SYS_IMMR + 0x0e080000)
+
+/* GPU */
+#define GPU_BASE_ADDR				(CONFIG_SYS_IMMR + 0x0e0c0000)
+
 /* SFP */
 #define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)

 /* SEC */
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
 #define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
+#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define FSL_SEC_JR1_OFFSET			0x07020000ull
+#define FSL_SEC_JR2_OFFSET			0x07030000ull
+#define FSL_SEC_JR3_OFFSET			0x07040000ull
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)

 #ifdef CONFIG_TFABOOT
 #ifdef CONFIG_NXP_LSCH3_2
@@ -417,7 +440,8 @@ struct ccsr_gur {
 	u32	usb2_amqr;
 	u8	res_528[0x530-0x528];	/* add more registers when needed */
 	u32	sdmm1_amqr;
-	u8	res_534[0x550-0x534];	/* add more registers when needed */
+	u32	sdmm2_amqr;
+	u8	res_538[0x550 - 0x538];	/* add more registers when needed */
 	u32	sata1_amqr;
 	u32	sata2_amqr;
 	u8	res_558[0x570-0x558];	/* add more registers when needed */
@@ -425,7 +449,8 @@ struct ccsr_gur {
 	u8	res_574[0x590-0x574];	/* add more registers when needed */
 	u32	spare1_amqr;
 	u32	spare2_amqr;
-	u8	res_598[0x620-0x598];	/* add more registers when needed */
+	u32	spare3_amqr;
+	u8	res_59c[0x620 - 0x59c];	/* add more registers when needed */
 	u32	gencr[7];	/* General Control Registers */
 	u8	res_63c[0x640-0x63c];	/* add more registers when needed */
 	u32	cgensr1;	/* Core General Status Register */
@@ -76,7 +76,7 @@

 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
 #define FSL_DMA_STREAM_ID		6
-#elif defined(CONFIG_ARCH_LS1088A)
+#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
 #define FSL_DMA_STREAM_ID		5
 #endif

@@ -98,4 +98,15 @@
 #define FSL_DPAA2_STREAM_ID_START	23
 #define FSL_DPAA2_STREAM_ID_END		63

+#define FSL_SEC_STREAM_ID		64
+#define FSL_SEC_JR1_STREAM_ID		65
+#define FSL_SEC_JR2_STREAM_ID		66
+#define FSL_SEC_JR3_STREAM_ID		67
+#define FSL_SEC_JR4_STREAM_ID		68
+
+#define FSL_SDMMC2_STREAM_ID		69
+#define FSL_EDMA_STREAM_ID		70
+#define FSL_GPU_STREAM_ID		71
+#define FSL_DISPLAY_STREAM_ID		72
+
 #endif
@@ -10,7 +10,6 @@


 /* Basic CPU architecture */
-#define CONFIG_ARCH_CPU_INIT

 /* UART configuration */
 #if	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ *      Rohan Garg <rohan.garg@collabora.com>
+ */
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+			      const u32 cpuid_length,
+			      u8 *cpuid);
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
+int rockchip_setup_macaddr(void);
@@ -1,6 +1,8 @@
 #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
 	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
-	!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
+	!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
+	!defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \
+	!defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A)
 #include <asm/arch/gpio.h>
 #endif
 #include <asm-generic/gpio.h>
@@ -5,7 +5,6 @@
 #ifndef __AT91RM9200_H__
 #define __AT91RM9200_H__

-#define CONFIG_ARCH_CPU_INIT	/* we need arch_cpu_init() for hw timers */
 #define CONFIG_AT91_GPIO	/* and require always gpio features */

 /* Periperial Identifiers */
@@ -201,7 +201,9 @@ static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
 	int offs, node_offs, ret, i;
 	uint32_t phandle;

-	offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
+	offs = fdt_path_offset(fdt, "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks");
+	if (offs < 0)
+		offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
 	if (offs < 0) {
 		debug("Could not find cm_core_aon clocks node path offset : %s\n",
 		      fdt_strerror(offs));
@@ -25,6 +25,10 @@ endif

 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o

+ifdef CONFIG_MISC_INIT_R
+obj-y += misc.o
+endif
+
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
 ifndef CONFIG_TPL_BUILD
@@ -11,6 +11,7 @@
 #include <asm/arch-rockchip/boot_mode.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
 #include <power/regulator.h>

 DECLARE_GLOBAL_DATA_PTR;
@@ -102,3 +103,25 @@ int fastboot_set_reboot_flag(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_MISC_INIT_R
+__weak int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	ret = rockchip_setup_macaddr();
+
+	return ret;
+}
+#endif
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ *      Rohan Garg <rohan.garg@collabora.com>
+ *
+ * Based on puma-rk3399.c:
+ *      (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <common.h>
+#include <env.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <misc.h>
+#include <u-boot/sha256.h>
+
+#include <asm/arch-rockchip/misc.h>
+
+int rockchip_setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+	int ret;
+	const char *cpuid = env_get("cpuid#");
+	u8 hash[SHA256_SUM_LEN];
+	int size = sizeof(hash);
+	u8 mac_addr[6];
+
+	/* Only generate a MAC address, if none is set in the environment */
+	if (env_get("ethaddr"))
+		return -1;
+
+	if (!cpuid) {
+		debug("%s: could not retrieve 'cpuid#'\n", __func__);
+		return -1;
+	}
+
+	ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+	if (ret) {
+		debug("%s: failed to calculate SHA256\n", __func__);
+		return -1;
+	}
+
+	/* Copy 6 bytes of the hash to base the MAC address on */
+	memcpy(mac_addr, hash, 6);
+
+	/* Make this a valid MAC address and set it */
+	mac_addr[0] &= 0xfe;  /* clear multicast bit */
+	mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
+	eth_env_set_enetaddr("ethaddr", mac_addr);
+#endif
+	return 0;
+}
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+			      const u32 cpuid_length,
+			      u8 *cpuid)
+{
+#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+	struct udevice *dev;
+	int ret;
+
+	/* retrieve the device */
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_GET_DRIVER(rockchip_efuse), &dev);
+	if (ret) {
+		debug("%s: could not find efuse device\n", __func__);
+		return -1;
+	}
+
+	/* read the cpu_id range from the efuses */
+	ret = misc_read(dev, cpuid_offset, cpuid, sizeof(cpuid));
+	if (ret) {
+		debug("%s: reading cpuid from the efuses failed\n",
+		      __func__);
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
+{
+	u8 low[cpuid_length / 2], high[cpuid_length / 2];
+	char cpuid_str[cpuid_length * 2 + 1];
+	u64 serialno;
+	char serialno_str[17];
+	int i;
+
+	memset(cpuid_str, 0, sizeof(cpuid_str));
+	for (i = 0; i < 16; i++)
+		sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
+
+	debug("cpuid: %s\n", cpuid_str);
+
+	/*
+	 * Mix the cpuid bytes using the same rules as in
+	 *   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
+	 */
+	for (i = 0; i < 8; i++) {
+		low[i] = cpuid[1 + (i << 1)];
+		high[i] = cpuid[i << 1];
+	}
+
+	serialno = crc32_no_comp(0, low, 8);
+	serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+	snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
+
+	env_set("cpuid#", cpuid_str);
+	env_set("serial#", serialno_str);
+
+	return 0;
+}
@@ -191,8 +191,6 @@ source "board/radxa/rock2/Kconfig"

 source "board/rockchip/evb_rk3288/Kconfig"

-source "board/rockchip/fennec_rk3288/Kconfig"
-
 source "board/rockchip/tinker_rk3288/Kconfig"

 endif
@@ -113,6 +113,23 @@ config RISCV_SMODE

 endchoice

+choice
+	prompt "SPL Run Mode"
+	default SPL_RISCV_MMODE
+	depends on SPL
+
+config SPL_RISCV_MMODE
+	bool "Machine"
+	help
+	  Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+	bool "Supervisor"
+	help
+	  Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
 	bool "Emit compressed instructions"
 	default y
@@ -132,34 +149,40 @@ config 64BIT

 config SIFIVE_CLINT
 	bool
-	depends on RISCV_MMODE
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
 	select REGMAP
 	select SYSCON
+	select SPL_REGMAP if SPL
+	select SPL_SYSCON if SPL
 	help
 	  The SiFive CLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.

 config ANDES_PLIC
 	bool
-	depends on RISCV_MMODE
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
 	select REGMAP
 	select SYSCON
+	select SPL_REGMAP if SPL
+	select SPL_SYSCON if SPL
 	help
 	  The Andes PLIC block holds memory-mapped claim and pending registers
 	  associated with software interrupt.

 config ANDES_PLMT
 	bool
-	depends on RISCV_MMODE
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
 	select REGMAP
 	select SYSCON
+	select SPL_REGMAP if SPL
+	select SPL_SYSCON if SPL
 	help
 	  The Andes PLMT block holds memory-mapped mtime register
 	  associated with timer tick.

 config RISCV_RDTIME
 	bool
-	default y if RISCV_SMODE
+	default y if RISCV_SMODE || SPL_RISCV_SMODE
 	help
 	  The provides the riscv_get_time() API that is implemented using the
 	  standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -189,7 +212,7 @@ config NR_CPUS

 config SBI_IPI
 	bool
-	default y if RISCV_SMODE
+	default y if RISCV_SMODE || SPL_RISCV_SMODE
 	depends on SMP

 config XIP
@@ -203,4 +226,7 @@ config STACK_SIZE_SHIFT
 	int
 	default 13

+config SPL_LDSCRIPT
+	default "arch/riscv/cpu/u-boot-spl.lds"
+
 endmenu
@@ -4,8 +4,8 @@ config RISCV_NDS
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER
-	imply ANDES_PLIC if RISCV_MMODE
-	imply ANDES_PLMT if RISCV_MMODE
+	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
 	help
 	  Run U-Boot on AndeStar V5 platforms and use some specific features
 	  which are provided by Andes Technology AndeStar V5 families.
@@ -14,7 +14,7 @@ if RISCV_NDS

 config RISCV_NDS_CACHE
 	bool "AndeStar V5 families specific cache support"
-	depends on RISCV_MMODE
+	depends on RISCV_MMODE || SPL_RISCV_MMODE
 	help
 	  Provide Andes Technology AndeStar V5 families specific cache support.

@@ -46,13 +46,13 @@ static inline bool supports_extension(char ext)

 	return false;
 #else  /* !CONFIG_CPU */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
 	return csr_read(CSR_MISA) & (1 << (ext - 'a'));
-#else  /* !CONFIG_RISCV_MMODE */
+#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
 	return false;
-#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /* CONFIG_CPU */
 }

@@ -8,5 +8,8 @@ config GENERIC_RISCV
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER
-	imply SIFIVE_CLINT if RISCV_MMODE
+	imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply CMD_CPU
+	imply SPL_CPU_SUPPORT
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
@@ -39,7 +39,7 @@ secondary_harts_relocation_error:
 .section .text
 .globl _start
 _start:
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
 	csrr	a0, CSR_MHARTID
 #endif

@@ -62,7 +62,7 @@ _start:

 #ifdef CONFIG_SMP
 	/* set xSIE bit to receive IPIs */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
 	li	t0, MIE_MSIE
 #else
 	li	t0, SIE_SSIE
@@ -75,7 +75,11 @@ _start:
 */
 call_board_init_f:
 	li	t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	li	t1, CONFIG_SPL_STACK
+#else
 	li	t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
 	and	sp, t1, t0		/* force 16 byte alignment */

 call_board_init_f_0:
@@ -159,7 +163,57 @@ wait_for_gd_init:

 	mv	a0, zero		/* a0 <-- boot_flags = 0 */
 	la	t5, board_init_f
-	jr	t5			/* jump to board_init_f() */
+	jalr	t5			/* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+	la	t0, __bss_start
+	la	t1, __bss_end
+	beq	t0, t1, spl_stack_gd_setup
+
+spl_clear_bss_loop:
+	SREG	zero, 0(t0)
+	addi	t0, t0, REGBYTES
+	bne	t0, t1, spl_clear_bss_loop
+
+spl_stack_gd_setup:
+	jal	spl_relocate_stack_gd
+
+	/* skip setup if we did not relocate */
+	beqz	a0, spl_call_board_init_r
+	mv	s0, a0
+
+	/* setup stack on main hart */
+#ifdef CONFIG_SMP
+	/* tp: hart id */
+	slli	t0, tp, CONFIG_STACK_SIZE_SHIFT
+	sub	sp, s0, t0
+#else
+	mv	sp, s0
+#endif
+
+	/* set new stack and global data pointer on secondary harts */
+spl_secondary_hart_stack_gd_setup:
+	la	a0, secondary_hart_relocate
+	mv	a1, s0
+	mv	a2, s0
+	jal	smp_call_function
+
+	/* hang if relocation of secondary harts has failed */
+	beqz	a0, 1f
+	mv	a1, a0
+	la	a0, secondary_harts_relocation_error
+	jal	printf
+	jal	hang
+
+	/* set new global data pointer on main hart */
+1:	mv	gp, s0
+
+spl_call_board_init_r:
+	mv	a0, zero
+	mv	a1, zero
+	jal	board_init_r
+#endif

 /*
 * void relocate_code (addr_sp, gd, addr_moni)
@@ -344,7 +398,7 @@ secondary_hart_loop:

 #ifdef CONFIG_SMP
 	csrr	t0, MODE_PREFIX(ip)
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
 	andi	t0, t0, MIE_MSIE
 #else
 	andi	t0, t0, SIE_SSIE
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/riscv/cpu/u-boot.lds, which is
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * and arch/mips/cpu/u-boot-spl.lds.
+ */
+MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		    LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+SECTIONS
+{
+	. = ALIGN(4);
+	.text : {
+		arch/riscv/cpu/start.o	(.text)
+		*(.text*)
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	} > .spl_mem
+	. = ALIGN(4);
+
+	.got : {
+		__got_start = .;
+		*(.got.plt) *(.got)
+		__got_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	.binman_sym_table : {
+		__binman_sym_start = .;
+		KEEP(*(SORT(.binman_sym*)));
+		__binman_sym_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	/DISCARD/ : { *(.rela.plt*) }
+	.rela.dyn : {
+		__rel_dyn_start = .;
+		*(.rela*)
+		__rel_dyn_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	.dynsym : {
+		__dyn_sym_start = .;
+		*(.dynsym)
+		__dyn_sym_end = .;
+	} > .spl_mem
+
+	. = ALIGN(4);
+
+	_end = .;
+
+	.bss : {
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .bss_mem
+}
@@ -9,7 +9,7 @@

 #include <asm/csr.h>

-#ifdef CONFIG_RISCV_SMODE
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
 #define MODE_PREFIX(__suffix)	s##__suffix
 #else
 #define MODE_PREFIX(__suffix)	m##__suffix
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/mips/include/asm/spl.h.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _ASM_RISCV_SPL_H_
+#define _ASM_RISCV_SPL_H_
+
+enum {
+	BOOT_DEVICE_RAM,
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+	BOOT_DEVICE_NAND,
+	BOOT_DEVICE_ONENAND,
+	BOOT_DEVICE_NOR,
+	BOOT_DEVICE_UART,
+	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_USB,
+	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
+	BOOT_DEVICE_DFU,
+	BOOT_DEVICE_XIP,
+	BOOT_DEVICE_BOOTROM,
+	BOOT_DEVICE_NONE
+};
+
+#endif
@@ -10,15 +10,19 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y	+= cache.o
-obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
+ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
+else
+obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
+obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
+endif
 obj-y	+= interrupts.o
 obj-y	+= reset.o
-obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 obj-y   += setjmp.o
 obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o

 # For building EFI apps
 CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
@@ -0,0 +1,100 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0+
+#
+# script to generate FIT image source for RISC-V boards with OpenSBI
+# and, optionally, multiple device trees (given on the command line).
+#
+# usage: $0 [<dt_name> [<dt_name] ...]
+
+[ -z "$OPENSBI" ] && OPENSBI="fw_dynamic.bin"
+
+if [ -z "$UBOOT_LOAD_ADDR" ]; then
+	UBOOT_LOAD_ADDR="$(grep "^CONFIG_SYS_TEXT_BASE=" .config | awk 'BEGIN{FS="="} {print $2}')"
+fi
+
+if [ -z "$OPENSBI_LOAD_ADDR" ]; then
+	OPENSBI_LOAD_ADDR="$(grep "^CONFIG_SPL_OPENSBI_LOAD_ADDR=" .config | awk 'BEGIN{FS="="} {print $2}')"
+fi
+
+if [ ! -f $OPENSBI ]; then
+	echo "WARNING: OpenSBI binary \"$OPENSBI\" not found, resulting binary is not functional." >&2
+	OPENSBI=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+	description = "Configuration to load OpenSBI before U-Boot";
+
+	images {
+		uboot {
+			description = "U-Boot";
+			data = /incbin/("u-boot-nodtb.bin");
+			type = "standalone";
+			os = "U-Boot";
+			arch = "riscv";
+			compression = "none";
+			load = <$UBOOT_LOAD_ADDR>;
+		};
+		opensbi {
+			description = "RISC-V OpenSBI";
+			data = /incbin/("$OPENSBI");
+			type = "firmware";
+			os = "opensbi";
+			arch = "riscv";
+			compression = "none";
+			load = <$OPENSBI_LOAD_ADDR>;
+			entry = <$OPENSBI_LOAD_ADDR>;
+		};
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+	cat << __FDT_IMAGE_EOF
+		fdt_$cnt {
+			description = "$(basename $dtname .dtb)";
+			data = /incbin/("$dtname");
+			type = "flat_dt";
+			compression = "none";
+		};
+__FDT_IMAGE_EOF
+cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+	};
+	configurations {
+		default = "config_1";
+
+__CONF_HEADER_EOF
+
+if [ $# -eq 0 ]; then
+cat << __CONF_SECTION_EOF
+		config_1 {
+			description = "U-Boot FIT";
+			firmware = "opensbi";
+			loadables = "uboot";
+		};
+__CONF_SECTION_EOF
+else
+cnt=1
+for dtname in $*
+do
+cat << __CONF_SECTION_EOF
+		config_$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "opensbi";
+			loadables = "uboot";
+			fdt = "fdt_$cnt";
+		};
+__CONF_SECTION_EOF
+cnt=$((cnt+1))
+done
+fi
+
+cat << __ITS_EOF
+	};
+};
+__ITS_EOF
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+#include <common.h>
+#include <spl.h>
+#include <asm/smp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak void board_init_f(ulong dummy)
+{
+	int ret;
+
+	ret = spl_early_init();
+	if (ret)
+		panic("spl_early_init() failed: %d\n", ret);
+
+	arch_cpu_init_dm();
+
+	preloader_console_init();
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb);
+	void *fdt_blob;
+	int ret;
+
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+	fdt_blob = spl_image->fdt_addr;
+#else
+	fdt_blob = (void *)gd->fdt_blob;
+#endif
+
+	image_entry_riscv_t image_entry =
+		(image_entry_riscv_t)spl_image->entry_point;
+	invalidate_icache_all();
+
+	debug("image entry point: 0x%lX\n", spl_image->entry_point);
+#ifdef CONFIG_SMP
+	ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0);
+	if (ret)
+		hang();
+#endif
+	image_entry(gd->arch.boot_hart, fdt_blob);
+}
@@ -33,8 +33,6 @@ config MAC_ADDR_IN_EEPROM

 endif

-source "board/ti/common/Kconfig"
-
 endif

 if TARGET_OMAPL138_LCDK
@@ -234,8 +234,7 @@ const struct pinmux_resource pinmuxes[] = {
 	PINMUX_ITEM(emifa_pins_cs3),
 	PINMUX_ITEM(emifa_pins_cs4),
 	PINMUX_ITEM(emifa_pins_nand),
-#endif
-#ifdef CONFIG_USE_NOR
+#elif defined(CONFIG_USE_NOR)
 	PINMUX_ITEM(emifa_pins_cs2),
 	PINMUX_ITEM(emifa_pins_nor),
 #endif
@@ -227,10 +227,6 @@ int board_init(void)
 	return 0;
 }

-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
 #define CFG_MAC_ADDR_SPI_BUS	0
 #define CFG_MAC_ADDR_SPI_CS	0
 #define CFG_MAC_ADDR_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
@@ -13,13 +13,22 @@ config SYS_CONFIG_NAME
 	default "qemu-riscv"

 config SYS_TEXT_BASE
+	default 0x81200000 if SPL
 	default 0x80000000 if !RISCV_SMODE
 	default 0x80200000 if RISCV_SMODE && ARCH_RV64I
 	default 0x80400000 if RISCV_SMODE && ARCH_RV32I

+config SPL_TEXT_BASE
+	default 0x80000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	hex
+	default 0x81000000
+
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select GENERIC_RISCV
+	select SUPPORT_SPL
 	imply SYS_NS16550
 	imply VIRTIO_MMIO
 	imply VIRTIO_NET
@@ -43,5 +52,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	imply CMD_PCI
 	imply E1000
 	imply NVME
+	imply SPL_RAM_SUPPORT
+	imply SPL_RAM_DEVICE

 endif
@@ -5,5 +5,7 @@ F:	board/emulation/qemu-riscv/
 F:	include/configs/qemu-riscv.h
 F:	configs/qemu-riscv32_defconfig
 F:	configs/qemu-riscv32_smode_defconfig
+F:	configs/qemu-riscv32_spl_defconfig
 F:	configs/qemu-riscv64_defconfig
 F:	configs/qemu-riscv64_smode_defconfig
+F:	configs/qemu-riscv64_spl_defconfig
@@ -7,6 +7,7 @@
 #include <dm.h>
 #include <env.h>
 #include <fdtdec.h>
+#include <spl.h>
 #include <virtio_types.h>
 #include <virtio.h>

@@ -88,3 +89,19 @@ int ft_board_setup(void *blob, bd_t *bd)

 	return 0;
 }
+
+#ifdef CONFIG_SPL
+u32 spl_boot_device(void)
+{
+	/* RISC-V QEMU only supports RAM as SPL boot device */
+	return BOOT_DEVICE_RAM;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
@@ -24,10 +24,22 @@ void set_fan_speed(u8 data)
 			       I2C_EMC2305_FAN5};

 	for (index = 0; index < NUM_OF_FANS; index++) {
+#ifndef CONFIG_DM_I2C
 		if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {
 			printf("Error: failed to change fan speed @%x\n",
 			       Fan[index]);
 		}
+#else
+		struct udevice *dev;
+
+		if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+			continue;
+
+		if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) {
+			printf("Error: failed to change fan speed @%x\n",
+			       Fan[index]);
+		}
+#endif
 	}
 }

@@ -36,6 +48,15 @@ void emc2305_init(void)
 	u8 data;

 	data = I2C_EMC2305_CMD;
+#ifndef CONFIG_DM_I2C
 	if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)
 		printf("Error: failed to configure EMC2305\n");
+#else
+	struct udevice *dev;
+
+	if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
+		if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1))
+			printf("Error: failed to configure EMC2305\n");
+#endif
+
 }
@@ -21,16 +21,40 @@
 #define QIXIS_LBMAP_BRDCFG_REG 0x00
 #endif

+#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#endif
+#ifndef QIXIS_RCFG_CTL_RECONFIG_START
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
+#ifndef CONFIG_DM_I2C
 	return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+#else
+	struct udevice *dev;
+
+	if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+		return 0xff;
+
+	return dm_i2c_reg_read(dev, reg);
+#endif
 }

 void qixis_write_i2c(unsigned int reg, u8 value)
 {
 	u8 val = value;
+#ifndef CONFIG_DM_I2C
 	i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+#else
+	struct udevice *dev;
+
+	if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
+		dm_i2c_reg_write(dev, reg, val);
+#endif
+
 }
 #endif

@@ -142,11 +166,13 @@ static void qixis_reset(void)
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
 }

+#ifdef QIXIS_LBMAP_ALTBANK
 static void qixis_bank_reset(void)
 {
 	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
 	QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 }
+#endif

 static void __maybe_unused set_lbmap(int lbmap)
 {
@@ -159,12 +185,16 @@ static void __maybe_unused set_lbmap(int lbmap)

 static void __maybe_unused set_rcw_src(int rcw_src)
 {
+#ifdef CONFIG_NXP_LSCH3_2
+	QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
+#else
 	u8 reg;

 	reg = QIXIS_READ(dutcfg[1]);
 	reg = (reg & ~1) | (rcw_src & 1);
 	QIXIS_WRITE(dutcfg[1], reg);
 	QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
+#endif
 }

 static void qixis_dump_regs(void)
@@ -210,16 +240,20 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 		set_lbmap(QIXIS_LBMAP_DFLTBANK);
 		qixis_reset();
 	} else if (strcmp(argv[1], "altbank") == 0) {
+#ifdef QIXIS_LBMAP_ALTBANK
 		set_lbmap(QIXIS_LBMAP_ALTBANK);
 		qixis_bank_reset();
+#else
+		printf("No Altbank!\n");
+#endif
 	} else if (strcmp(argv[1], "nand") == 0) {
 #ifdef QIXIS_LBMAP_NAND
 		QIXIS_WRITE(rst_ctl, 0x30);
 		QIXIS_WRITE(rcfg_ctl, 0);
 		set_lbmap(QIXIS_LBMAP_NAND);
 		set_rcw_src(QIXIS_RCW_SRC_NAND);
-		QIXIS_WRITE(rcfg_ctl, 0x20);
-		QIXIS_WRITE(rcfg_ctl, 0x21);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
 		printf("Not implemented\n");
 #endif
@@ -233,8 +267,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 		set_lbmap(QIXIS_LBMAP_SD);
 		set_rcw_src(QIXIS_RCW_SRC_SD);
 #endif
-		QIXIS_WRITE(rcfg_ctl, 0x20);
-		QIXIS_WRITE(rcfg_ctl, 0x21);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
 		printf("Not implemented\n");
 #endif
@@ -244,8 +278,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 		QIXIS_WRITE(rcfg_ctl, 0);
 		set_lbmap(QIXIS_LBMAP_IFC);
 		set_rcw_src(QIXIS_RCW_SRC_IFC);
-		QIXIS_WRITE(rcfg_ctl, 0x20);
-		QIXIS_WRITE(rcfg_ctl, 0x21);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
 		printf("Not implemented\n");
 #endif
@@ -255,8 +289,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 		QIXIS_WRITE(rcfg_ctl, 0);
 		set_lbmap(QIXIS_LBMAP_EMMC);
 		set_rcw_src(QIXIS_RCW_SRC_EMMC);
-		QIXIS_WRITE(rcfg_ctl, 0x20);
-		QIXIS_WRITE(rcfg_ctl, 0x21);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
 #else
 		printf("Not implemented\n");
 #endif
@@ -266,8 +300,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 		QIXIS_WRITE(rcfg_ctl, 0);
 		set_lbmap(QIXIS_LBMAP_SD_QSPI);
 		set_rcw_src(QIXIS_RCW_SRC_SD);
-		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_START);
 #else
 		printf("Not implemented\n");
 #endif
@@ -277,8 +313,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
 		QIXIS_WRITE(rcfg_ctl, 0);
 		set_lbmap(QIXIS_LBMAP_QSPI);
 		set_rcw_src(QIXIS_RCW_SRC_QSPI);
-		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
-		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_IDLE);
+		qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
+				QIXIS_RCFG_CTL_RECONFIG_START);
 #else
 		printf("Not implemented\n");
 #endif
@@ -149,23 +149,42 @@ static int read_eeprom(void)
 {
 	int ret;
 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
 	unsigned int bus;
+#endif
 #endif

 	if (has_been_read)
 		return 0;

 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
 	bus = i2c_get_bus_num();
 	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
 #endif
+#endif

-	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
-		(void *)&e, sizeof(e));
+#ifndef CONFIG_DM_I2C
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+		       CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+		       (void *)&e, sizeof(e));
+#else
+	struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+#else
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
+#endif
+	if (!ret)
+		ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
+#endif

 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
 	i2c_set_bus_num(bus);
 #endif
+#endif

 #ifdef DEBUG
 	show_eeprom();
@@ -199,7 +218,9 @@ static int prog_eeprom(void)
 	int i;
 	void *p;
 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
+#ifndef CONFIG_DM_I2C
 	unsigned int bus;
+#endif
 #endif

 	/* Set the reserved values to 0xFF   */
@@ -211,9 +232,11 @@ static int prog_eeprom(void)
 #endif
 	update_crc();

+#ifndef CONFIG_DM_I2C
 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	bus = i2c_get_bus_num();
 	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
 #endif

 	/*
@@ -222,8 +245,26 @@ static int prog_eeprom(void)
 	 * complete a given write.
 	 */
 	for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
-		ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+#ifndef CONFIG_DM_I2C
+		ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i,
+				CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 				p, min((int)(sizeof(e) - i), 8));
+#else
+		struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+		ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+					      CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#else
+		ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#endif
+		if (!ret)
+			ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i),
+							  8));
+#endif
 		if (ret)
 			break;
 		udelay(5000);	/* 5ms write cycle timing */
@@ -233,14 +274,33 @@ static int prog_eeprom(void)
 		/* Verify the write by reading back the EEPROM and comparing */
 		struct eeprom e2;

+#ifndef CONFIG_DM_I2C
 		ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-			CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
+			       CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+			       (void *)&e2, sizeof(e2));
+#else
+		struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+		ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+					      CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#else
+		ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+					      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+					      &dev);
+#endif
+		if (!ret)
+			ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));
+#endif
 		if (!ret && memcmp(&e, &e2, sizeof(e)))
 			ret = -1;
 	}

+#ifndef CONFIG_DM_I2C
 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	i2c_set_bus_num(bus);
+#endif
 #endif

 	if (ret) {
@@ -529,8 +589,24 @@ unsigned int get_cpu_board_revision(void)
 		u8 minor;         /* 0x05        Board revision, minor */
 	} be;

+#ifndef CONFIG_DM_I2C
 	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 		(void *)&be, sizeof(be));
+#else
+	struct udevice *dev;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+	ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
+				      CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				      &dev);
+#else
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
+				      CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
+				      &dev)
+#endif
+	if (!ret)
+		dm_i2c_read(dev, 0, (void *)&be, sizeof(be));
+#endif

 	if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
 		return MPC85XX_CPU_BOARD_REV(0, 0);
@@ -61,13 +61,23 @@ static int find_ir_chip_on_i2c(void)
 	u8 byte;
 	int i;
 	const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+#endif

 	/* Check all the address */
 	for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
 		i2caddress = ir_i2c_addr[i];
+#ifndef CONFIG_DM_I2C
 		ret = i2c_read(i2caddress,
 			       IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
 			       sizeof(byte));
+#else
+		ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+		if (!ret)
+			ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
+					  (void *)&byte, sizeof(byte));
+#endif
 		if ((ret >= 0) && (byte == IR36021_MFR_ID))
 			return i2caddress;
 	}
@@ -103,11 +113,21 @@ static int read_voltage_from_INA220(int i2caddress)
 	int i, ret, voltage_read = 0;
 	u16 vol_mon;
 	u8 buf[2];
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+#endif

 	for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
 		ret = i2c_read(I2C_VOL_MONITOR_ADDR,
 			       I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
 			       (void *)&buf, 2);
+#else
+		ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+		if (!ret)
+			ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
+					  (void *)&buf, 2);
+#endif
 		if (ret) {
 			printf("VID: failed to read core voltage\n");
 			return ret;
@@ -136,11 +156,21 @@ static int read_voltage_from_IR(int i2caddress)
 	int i, ret, voltage_read = 0;
 	u16 vol_mon;
 	u8 buf;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+#endif

 	for (i = 0; i < NUM_READINGS; i++) {
+#ifndef CONFIG_DM_I2C
 		ret = i2c_read(i2caddress,
 			       IR36021_LOOP1_VOUT_OFFSET,
 			       1, (void *)&buf, 1);
+#else
+		ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+		if (!ret)
+			ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
+					  (void *)&buf, 1);
+#endif
 		if (ret) {
 			printf("VID: failed to read vcpu\n");
 			return ret;
@@ -179,17 +209,33 @@ static int read_voltage_from_LTC(int i2caddress)
 	int  ret, vcode = 0;
 	u8 chan = PWM_CHANNEL0;

+#ifndef CONFIG_DM_I2C
 	/* select the PAGE 0 using PMBus commands PAGE for VDD*/
 	ret = i2c_write(I2C_VOL_MONITOR_ADDR,
 			PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
+#endif
 	if (ret) {
 		printf("VID: failed to select VDD Page 0\n");
 		return ret;
 	}

+#ifndef CONFIG_DM_I2C
 	/*read the output voltage using PMBus command READ_VOUT*/
 	ret = i2c_read(I2C_VOL_MONITOR_ADDR,
 		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+	ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+	if (ret) {
+		printf("VID: failed to read the volatge\n");
+		return ret;
+	}
+#endif
 	if (ret) {
 		printf("VID: failed to read the volatge\n");
 		return ret;
@@ -294,8 +340,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd)
 	vid = DIV_ROUND_UP(vdd - 245, 5);
 #endif

+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
 			1, (void *)&vid, sizeof(vid));
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
+				   (void *)&vid, sizeof(vid));
+
+#endif
 	if (ret) {
 		printf("VID: failed to write VID\n");
 		return -1;
@@ -331,8 +387,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
 			vdd & 0xFF, (vdd & 0xFF00) >> 8};

 	/* Write the desired voltage code to the regulator */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_VOL_MONITOR_ADDR,
 			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+				   (void *)&buff, 5);
+#endif
 	if (ret) {
 		printf("VID: I2C failed to write to the volatge regulator\n");
 		return -1;
@@ -516,14 +581,24 @@ int adjust_vdd(ulong vdd_override)
 	}

 	/* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
 	ret = i2c_read(i2caddress,
 		       IR36021_INTEL_MODE_OOFSET,
 		       1, (void *)&buf, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+				  (void *)&buf, 1);
+#endif
 	if (ret) {
 		printf("VID: failed to read IR chip mode.\n");
 		ret = -1;
 		goto exit;
 	}
+
 	if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
 		printf("VID: IR Chip is not used in Intel mode.\n");
 		ret = -1;
@@ -688,9 +763,18 @@ int adjust_vdd(ulong vdd_override)
 	}

 	/* check IR chip work on Intel mode*/
+#ifndef CONFIG_DM_I2C
 	ret = i2c_read(i2caddress,
 		       IR36021_INTEL_MODE_OOFSET,
 		       1, (void *)&buf, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
+				  (void *)&buf, 1);
+#endif
 	if (ret) {
 		printf("VID: failed to read IR chip mode.\n");
 		ret = -1;
@@ -13,6 +13,7 @@
 #include <linux/libfdt.h>
 #include <env_internal.h>
 #include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include <i2c.h>
 #include <asm/arch/soc.h>
 #ifdef CONFIG_FSL_LS_PPA
@@ -73,7 +74,15 @@ int board_init(void)
 #if defined(CONFIG_TARGET_LS1028ARDB)
 	u8 val = I2C_MUX_CH_DEFAULT;

+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
+#else
+	struct udevice *dev;
+
+	if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
+		dm_i2c_write(dev, 0x0b, &val, 1);
+#endif
+
 #endif
 	return 0;
 }
@@ -135,6 +144,8 @@ int ft_board_setup(void *blob, bd_t *bd)

 	fdt_fixup_memory_banks(blob, base, size, 2);

+	fdt_fixup_icid(blob);
+
 	return 0;
 }
 #endif
@@ -81,11 +81,16 @@ struct ls1088a_qds_mdio {
 	struct mii_dev *realbus;
 };

+struct reg_pair {
+	uint addr;
+	u8 *val;
+};
+
 static void sgmii_configure_repeater(int dpmac)
 {
 	struct mii_dev *bus;
 	uint8_t a = 0xf;
-	int i, j, ret;
+	int i, j, k, ret;
 	unsigned short value;
 	const char *dev = "LS1088A_QDS_MDIO2";
 	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -97,8 +102,28 @@ static void sgmii_configure_repeater(int dpmac)
 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};

+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+		{6, &reg_val[0]}, {4, &reg_val[1]},
+		{8, &reg_val[2]}, {0xf, NULL},
+		{0x11, NULL}, {0x16, NULL},
+		{0x18, NULL}, {0x23, &reg_val[3]},
+		{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+#ifdef CONFIG_DM_I2C
+	struct udevice *udev;
+#endif
+
 	/* Set I2c to Slot 1 */
-	i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;

 	switch (dpmac) {
 	case 1:
@@ -144,31 +169,34 @@ static void sgmii_configure_repeater(int dpmac)
 		return;
 	}

+#ifdef CONFIG_DM_I2C
+	i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
 	for (i = 0; i < 4; i++) {
 		for (j = 0; j < 4; j++) {
-			a = 0x18;
-			i2c_write(i2c_phy_addr, 6, 1, &a, 1);
-			a = 0x38;
-			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
-			a = 0x4;
-			i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+			reg_pair[3].val = &ch_a_eq[i];
+			reg_pair[4].val = &ch_a_ctl2[j];
+			reg_pair[5].val = &ch_b_eq[i];
+			reg_pair[6].val = &ch_b_ctl2[j];
+			for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+				ret = i2c_write(i2c_phy_addr,
+						reg_pair[k].addr,
+						1, reg_pair[k].val, 1);
+#else
+				ret = i2c_get_chip_for_busnum(0,
+							      i2c_phy_addr,
+							      1, &udev);
+				if (!ret)
+					ret = dm_i2c_write(udev,
+							   reg_pair[k].addr,
+							   reg_pair[k].val, 1);
+#endif
+				if (ret)
+					goto error;
+			}

-			i2c_write(i2c_phy_addr, 0xf, 1,
-				  &ch_a_eq[i], 1);
-			i2c_write(i2c_phy_addr, 0x11, 1,
-				  &ch_a_ctl2[j], 1);
-
-			i2c_write(i2c_phy_addr, 0x16, 1,
-				  &ch_b_eq[i], 1);
-			i2c_write(i2c_phy_addr, 0x18, 1,
-				  &ch_b_ctl2[j], 1);
-
-			a = 0x14;
-			i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
-			a = 0xb5;
-			i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
-			a = 0x20;
-			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
 			mdelay(100);
 			ret = miiphy_read(dev, phy_addr, 0x11, &value);
 			if (ret > 0)
@@ -203,7 +231,7 @@ error:
 static void qsgmii_configure_repeater(int dpmac)
 {
 	uint8_t a = 0xf;
-	int i, j;
+	int i, j, k;
 	int i2c_phy_addr = 0;
 	int phy_addr = 0;
 	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -213,12 +241,32 @@ static void qsgmii_configure_repeater(int dpmac)
 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};

+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+		{6, &reg_val[0]}, {4, &reg_val[1]},
+		{8, &reg_val[2]}, {0xf, NULL},
+		{0x11, NULL}, {0x16, NULL},
+		{0x18, NULL}, {0x23, &reg_val[3]},
+		{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+
 	const char *dev = mdio_names[EMI1_SLOT1];
 	int ret = 0;
 	unsigned short value;
+#ifdef CONFIG_DM_I2C
+	struct udevice *udev;
+#endif

 	/* Set I2c to Slot 1 */
-	i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;

 	switch (dpmac) {
 	case 7:
@@ -252,28 +300,35 @@ static void qsgmii_configure_repeater(int dpmac)
 		return;
 	}

+#ifdef CONFIG_DM_I2C
+	i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
+#endif
+
 	for (i = 0; i < 4; i++) {
 		for (j = 0; j < 4; j++) {
-			a = 0x18;
-			i2c_write(i2c_phy_addr, 6, 1, &a, 1);
-			a = 0x38;
-			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
-			a = 0x4;
-			i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+			reg_pair[3].val = &ch_a_eq[i];
+			reg_pair[4].val = &ch_a_ctl2[j];
+			reg_pair[5].val = &ch_b_eq[i];
+			reg_pair[6].val = &ch_b_ctl2[j];

-			i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
-			i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
+			for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+				ret = i2c_write(i2c_phy_addr,
+						reg_pair[k].addr,
+						1, reg_pair[k].val, 1);
+#else
+				ret = i2c_get_chip_for_busnum(0,
+							      i2c_addr[dpmac],
+							      1, &udev);
+				if (!ret)
+					ret = dm_i2c_write(udev,
+							   reg_pair[k].addr,
+							   reg_pair[k].val, 1);
+#endif
+				if (ret)
+					goto error;
+			}

-			i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
-			i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
-
-			a = 0x14;
-			i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
-			a = 0xb5;
-			i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
-			a = 0x20;
-			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
-			mdelay(100);
 			ret = miiphy_read(dev, phy_addr, 0x11, &value);
 			if (ret > 0)
 				goto error;
@@ -21,6 +21,7 @@
 #include <hwconfig.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>

 #include "../common/qixis.h"
 #include "ls1088a_qixis.h"
@@ -374,7 +375,15 @@ int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;

+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -393,38 +402,89 @@ void board_retimer_init(void)

 	/* Access to Control/Shared register */
 	reg = 0x0;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+#else
+	struct udevice *dev;
+
+	i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif

 	/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 1, &reg, 1);
+#endif
 	debug("Retimer version id = 0x%x\n", reg);

 	/* Enable Broadcast. All writes target all channel register sets */
 	reg = 0x0c;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif

 	/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0, &reg, 1);
+#endif
 	reg |= 0x4;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0, &reg, 1);
+#endif

 	/* Set data rate as 10.3125 Gbps */
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x60, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x61, &reg, 1);
+#endif
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x62, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x63, &reg, 1);
+#endif
 	reg = 0xcd;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x64, &reg, 1);
+#endif

 	/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0x2F, &reg, 1);
+#endif
 	reg &= 0x0f;
 	reg |= 0x70;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x2F, &reg, 1);
+#endif

 #ifdef	CONFIG_TARGET_LS1088AQDS
 	/* Retimer is connected to I2C1_CH5 */
@@ -432,38 +492,88 @@ void board_retimer_init(void)

 	/* Access to Control/Shared register */
 	reg = 0x0;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
+#else
+	i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif

 	/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 1, &reg, 1);
+#endif
 	debug("Retimer version id = 0x%x\n", reg);

 	/* Enable Broadcast. All writes target all channel register sets */
 	reg = 0x0c;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0xff, &reg, 1);
+#endif

 	/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0, &reg, 1);
+#endif
 	reg |= 0x4;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0, &reg, 1);
+#endif

 	/* Set data rate as 10.3125 Gbps */
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x60, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x61, &reg, 1);
+#endif
 	reg = 0x90;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x62, &reg, 1);
+#endif
 	reg = 0xb3;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x63, &reg, 1);
+#endif
 	reg = 0xcd;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x64, &reg, 1);
+#endif

 	/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
 	i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_read(dev, 0x2F, &reg, 1);
+#endif
 	reg &= 0x0f;
 	reg |= 0x70;
+#ifndef CONFIG_DM_I2C
 	i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
+#else
+	dm_i2c_write(dev, 0x2F, &reg, 1);
+#endif
+
 #endif
 	/*return the default channel*/
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -482,6 +592,32 @@ int misc_init_r(void)
 		QIXIS_WRITE(brdcfg[5], brdcfg5);
 	}
 #endif
+
+#ifdef CONFIG_TARGET_LS1088AQDS
+	 u8 brdcfg4, brdcfg5;
+
+	if (hwconfig("dspi-on-board")) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
+		brdcfg4 |= BRDCFG4_SPI;
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+		brdcfg5 = QIXIS_READ(brdcfg[5]);
+		brdcfg5 &= ~BRDCFG5_SPR_MASK;
+		brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
+		QIXIS_WRITE(brdcfg[5], brdcfg5);
+	} else if (hwconfig("dspi-off-board")) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
+		brdcfg4 |= BRDCFG4_SPI;
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+
+		brdcfg5 = QIXIS_READ(brdcfg[5]);
+		brdcfg5 &= ~BRDCFG5_SPR_MASK;
+		brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
+		QIXIS_WRITE(brdcfg[5], brdcfg5);
+	}
+#endif
 	return 0;
 }
 #endif
@@ -500,16 +636,30 @@ int get_serdes_volt(void)
 	u8 chan = PWM_CHANNEL0;

 	/* Select the PAGE 0 using PMBus commands PAGE for VDD */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 			PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
+				   &chan, 1);
+#endif
+
 	if (ret) {
 		printf("VID: failed to select VDD Page 0\n");
 		return ret;
 	}

 	/* Read the output voltage using PMBus command READ_VOUT */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 		       PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+	dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+#endif
 	if (ret) {
 		printf("VID: failed to read the volatge\n");
 		return ret;
@@ -525,8 +675,17 @@ int set_serdes_volt(int svdd)
 			svdd & 0xFF, (svdd & 0xFF00) >> 8};

 	/* Write the desired voltage code to the SVDD regulator */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 			PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+				   (void *)&buff, 5);
+#endif
 	if (ret) {
 		printf("VID: I2C failed to write to the volatge regulator\n");
 		return -1;
@@ -557,8 +716,18 @@ int set_serdes_volt(int svdd)
 	printf("SVDD changing of RDB\n");

 	/* Read the BRDCFG54 via CLPD */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 		       QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
+				  (void *)&brdcfg4, 1);
+#endif
+
 	if (ret) {
 		printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 		return -1;
@@ -567,8 +736,14 @@ int set_serdes_volt(int svdd)
 	brdcfg4 = brdcfg4 | 0x08;

 	/* Write to the BRDCFG4 */
+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 			QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+	ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
+			   (void *)&brdcfg4, 1);
+#endif
+
 	if (ret) {
 		debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 		return -1;
@@ -739,11 +914,26 @@ void fsl_fdt_fixup_flash(void *fdt)
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int i;
-	u64 base[CONFIG_NR_DRAM_BANKS];
-	u64 size[CONFIG_NR_DRAM_BANKS];
+	u16 mc_memory_bank = 0;
+
+	u64 *base;
+	u64 *size;
+	u64 mc_memory_base = 0;
+	u64 mc_memory_size = 0;
+	u16 total_memory_banks;

 	ft_cpu_setup(blob, bd);

+	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+	if (mc_memory_base != 0)
+		mc_memory_bank++;
+
+	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+	base = calloc(total_memory_banks, sizeof(u64));
+	size = calloc(total_memory_banks, sizeof(u64));
+
 	/* fixup DT for the two GPP DDR banks */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		base[i] = gd->bd->bi_dram[i].start;
@@ -760,7 +950,17 @@ int ft_board_setup(void *blob, bd_t *bd)
 		size[1] = gd->arch.resv_ram - base[1];
 #endif

-	fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+	if (mc_memory_base != 0) {
+		for (i = 0; i <= total_memory_banks; i++) {
+			if (base[i] == 0 && size[i] == 0) {
+				base[i] = mc_memory_base;
+				size[i] = mc_memory_size;
+				break;
+			}
+		}
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);

 	fdt_fsl_mc_fixup_iommu_map_entry(blob);

@@ -769,6 +969,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
 #endif
+
+	fdt_fixup_icid(blob);
+
 	if (is_pb_board())
 		fixup_ls1088ardb_pb_banner(blob);

@@ -41,4 +41,15 @@
 #define BRDCFG5_SPISDHC_MASK		0x0C
 #define BRDCFG5_FORCE_SD		0x08

+/* Definitions of QIXIS Registers for LS1088AQDS */
+
+/* BRDCFG4 */
+#define BRDCFG4_USBOSC_MASK   0x01
+#define BRDCFG4_SPI 0x01
+
+/* BRDCFG5 */
+#define BRDCFG5_SPR_MASK 0x0f
+#define BRDCFG5_SPI_ON_BOARD 0x0a
+#define BRDCFG5_SPI_OFF_BOARD 0x0f
+
 #endif
@@ -90,11 +90,16 @@ struct ls2080a_qds_mdio {
 	struct mii_dev *realbus;
 };

+struct reg_pair {
+	uint addr;
+	u8 *val;
+};
+
 static void sgmii_configure_repeater(int serdes_port)
 {
 	struct mii_dev *bus;
 	uint8_t a = 0xf;
-	int i, j, ret;
+	int i, j, k, ret;
 	int dpmac_id = 0, dpmac, mii_bus = 0;
 	unsigned short value;
 	char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
@@ -105,10 +110,30 @@ static void sgmii_configure_repeater(int serdes_port)
 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};

+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+			{6, &reg_val[0]}, {4, &reg_val[1]},
+			{8, &reg_val[2]}, {0xf, NULL},
+			{0x11, NULL}, {0x16, NULL},
+			{0x18, NULL}, {0x23, &reg_val[3]},
+			{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+
 	int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
+#ifdef CONFIG_DM_I2C
+	struct udevice *udev;
+#endif

 	/* Set I2c to Slot 1 */
-	i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;

 	for (dpmac = 0; dpmac < 8; dpmac++) {
 		/* Check the PHY status */
@@ -121,7 +146,15 @@ static void sgmii_configure_repeater(int serdes_port)
 			mii_bus = 1;
 			dpmac_id = dpmac + 9;
 			a = 0xb;
-			i2c_write(0x76, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+			ret = i2c_write(0x76, 0, 0, &a, 1);
+#else
+			ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
+			if (!ret)
+				ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+			if (ret)
+				goto error;
 			break;
 		}

@@ -154,29 +187,29 @@ static void sgmii_configure_repeater(int serdes_port)

 		for (i = 0; i < 4; i++) {
 			for (j = 0; j < 4; j++) {
-				a = 0x18;
-				i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
-				a = 0x38;
-				i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
-				a = 0x4;
-				i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
+				reg_pair[3].val = &ch_a_eq[i];
+				reg_pair[4].val = &ch_a_ctl2[j];
+				reg_pair[5].val = &ch_b_eq[i];
+				reg_pair[6].val = &ch_b_ctl2[j];

-				i2c_write(i2c_addr[dpmac], 0xf, 1,
-					  &ch_a_eq[i], 1);
-				i2c_write(i2c_addr[dpmac], 0x11, 1,
-					  &ch_a_ctl2[j], 1);
+				for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+					ret = i2c_write(i2c_addr[dpmac],
+							reg_pair[k].addr,
+							1, reg_pair[k].val, 1);
+#else
+					ret = i2c_get_chip_for_busnum(0,
+							    i2c_addr[dpmac],
+							    1, &udev);
+					if (!ret)
+						ret = dm_i2c_write(udev,
+							  reg_pair[k].addr,
+							  reg_pair[k].val, 1);
+#endif
+					if (ret)
+						goto error;
+				}

-				i2c_write(i2c_addr[dpmac], 0x16, 1,
-					  &ch_b_eq[i], 1);
-				i2c_write(i2c_addr[dpmac], 0x18, 1,
-					  &ch_b_ctl2[j], 1);
-
-				a = 0x14;
-				i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
-				a = 0xb5;
-				i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
-				a = 0x20;
-				i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
 				mdelay(100);
 				ret = miiphy_read(dev[mii_bus],
 						  riser_phy_addr[dpmac],
@@ -217,7 +250,7 @@ error:
 static void qsgmii_configure_repeater(int dpmac)
 {
 	uint8_t a = 0xf;
-	int i, j;
+	int i, j, k;
 	int i2c_phy_addr = 0;
 	int phy_addr = 0;
 	int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@@ -227,12 +260,32 @@ static void qsgmii_configure_repeater(int dpmac)
 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};

+	u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
+	struct reg_pair reg_pair[10] = {
+		{6, &reg_val[0]}, {4, &reg_val[1]},
+		{8, &reg_val[2]}, {0xf, NULL},
+		{0x11, NULL}, {0x16, NULL},
+		{0x18, NULL}, {0x23, &reg_val[3]},
+		{0x2d, &reg_val[4]}, {4, &reg_val[5]},
+	};
+
 	const char *dev = "LS2080A_QDS_MDIO0";
 	int ret = 0;
 	unsigned short value;
+#ifdef CONFIG_DM_I2C
+	struct udevice *udev;
+#endif

 	/* Set I2c to Slot 1 */
-	i2c_write(0x77, 0, 0, &a, 1);
+#ifndef CONFIG_DM_I2C
+	ret = i2c_write(0x77, 0, 0, &a, 1);
+#else
+	ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
+	if (!ret)
+		ret = dm_i2c_write(udev, 0, &a, 1);
+#endif
+	if (ret)
+		goto error;

 	switch (dpmac) {
 	case 1:
@@ -283,25 +336,29 @@ static void qsgmii_configure_repeater(int dpmac)

 	for (i = 0; i < 4; i++) {
 		for (j = 0; j < 4; j++) {
-			a = 0x18;
-			i2c_write(i2c_phy_addr, 6, 1, &a, 1);
-			a = 0x38;
-			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
-			a = 0x4;
-			i2c_write(i2c_phy_addr, 8, 1, &a, 1);
+			reg_pair[3].val = &ch_a_eq[i];
+			reg_pair[4].val = &ch_a_ctl2[j];
+			reg_pair[5].val = &ch_b_eq[i];
+			reg_pair[6].val = &ch_b_ctl2[j];

-			i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
-			i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
+			for (k = 0; k < 10; k++) {
+#ifndef CONFIG_DM_I2C
+				ret = i2c_write(i2c_phy_addr,
+						reg_pair[k].addr,
+						1, reg_pair[k].val, 1);
+#else
+				ret = i2c_get_chip_for_busnum(0,
+							      i2c_phy_addr,
+							      1, &udev);
+				if (!ret)
+					ret = dm_i2c_write(udev,
+							   reg_pair[k].addr,
+							   reg_pair[k].val, 1);
+#endif
+				if (ret)
+					goto error;
+			}

-			i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
-			i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
-
-			a = 0x14;
-			i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
-			a = 0xb5;
-			i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
-			a = 0x20;
-			i2c_write(i2c_phy_addr, 4, 1, &a, 1);
 			mdelay(100);
 			ret = miiphy_read(dev, phy_addr, 0x11, &value);
 			if (ret > 0)
@@ -161,8 +161,16 @@ unsigned long get_board_ddr_clk(void)
 int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;

+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+
+#else
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -225,7 +233,15 @@ int board_init(void)
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+#ifdef CONFIG_DM_I2C
+	rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
+#else
 	rtc_enable_32khz_output();
+#endif
+#endif
+
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
 #endif
@@ -164,7 +164,16 @@ int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;

+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
+
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -410,11 +419,27 @@ void fsl_fdt_fixup_flash(void *fdt)

 int ft_board_setup(void *blob, bd_t *bd)
 {
-	u64 base[CONFIG_NR_DRAM_BANKS];
-	u64 size[CONFIG_NR_DRAM_BANKS];
+	int i;
+	u16 mc_memory_bank = 0;
+
+	u64 *base;
+	u64 *size;
+	u64 mc_memory_base = 0;
+	u64 mc_memory_size = 0;
+	u16 total_memory_banks;

 	ft_cpu_setup(blob, bd);

+	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+	if (mc_memory_base != 0)
+		mc_memory_bank++;
+
+	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+	base = calloc(total_memory_banks, sizeof(u64));
+	size = calloc(total_memory_banks, sizeof(u64));
+
 	/* fixup DT for the two GPP DDR banks */
 	base[0] = gd->bd->bi_dram[0].start;
 	size[0] = gd->bd->bi_dram[0].size;
@@ -431,7 +456,17 @@ int ft_board_setup(void *blob, bd_t *bd)
 		size[1] = gd->arch.resv_ram - base[1];
 #endif

-	fdt_fixup_memory_banks(blob, base, size, 2);
+	if (mc_memory_base != 0) {
+		for (i = 0; i <= total_memory_banks; i++) {
+			if (base[i] == 0 && size[i] == 0) {
+				base[i] = mc_memory_base;
+				size[i] = mc_memory_size;
+				break;
+			}
+		}
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);

 	fdt_fsl_mc_fixup_iommu_map_entry(blob);

@@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;

+#ifndef CONFIG_DM_I2C
 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+	struct udevice *dev;
+
+	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
 	if (ret) {
 		puts("PCA: failed to select proper channel\n");
 		return ret;
@@ -402,6 +410,26 @@ int config_board_mux(void)

 	return 0;
 }
+#elif defined(CONFIG_TARGET_LX2160ARDB)
+int config_board_mux(void)
+{
+	u8 brdcfg;
+
+	brdcfg = QIXIS_READ(brdcfg[4]);
+	/* The BRDCFG4 register controls general board configuration.
+	 *|-------------------------------------------|
+	 *|Field  | Function                          |
+	 *|-------------------------------------------|
+	 *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
+	 *|CAN_EN | 0= CAN transceivers are disabled. |
+	 *|       | 1= CAN transceivers are enabled.  |
+	 *|-------------------------------------------|
+	 */
+	brdcfg |= BIT_MASK(5);
+	QIXIS_WRITE(brdcfg[4], brdcfg);
+
+	return 0;
+}
 #else
 int config_board_mux(void)
 {
@@ -529,11 +557,26 @@ void board_quiesce_devices(void)
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int i;
-	u64 base[CONFIG_NR_DRAM_BANKS];
-	u64 size[CONFIG_NR_DRAM_BANKS];
+	u16 mc_memory_bank = 0;
+
+	u64 *base;
+	u64 *size;
+	u64 mc_memory_base = 0;
+	u64 mc_memory_size = 0;
+	u16 total_memory_banks;

 	ft_cpu_setup(blob, bd);

+	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
+
+	if (mc_memory_base != 0)
+		mc_memory_bank++;
+
+	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+	base = calloc(total_memory_banks, sizeof(u64));
+	size = calloc(total_memory_banks, sizeof(u64));
+
 	/* fixup DT for the three GPP DDR banks */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		base[i] = gd->bd->bi_dram[i].start;
@@ -553,7 +596,17 @@ int ft_board_setup(void *blob, bd_t *bd)
 		size[2] = gd->arch.resv_ram - base[2];
 #endif

-	fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+	if (mc_memory_base != 0) {
+		for (i = 0; i <= total_memory_banks; i++) {
+			if (base[i] == 0 && size[i] == 0) {
+				base[i] = mc_memory_base;
+				size[i] = mc_memory_size;
+				break;
+			}
+		}
+	}
+
+	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);

 #ifdef CONFIG_USB
 	fsl_fdt_fixup_dr_usb(blob, bd);
@@ -1,15 +0,0 @@
-if TARGET_FENNEC_RK3288
-
-config SYS_BOARD
-	default "fennec_rk3288"
-
-config SYS_VENDOR
-	default "rockchip"
-
-config SYS_CONFIG_NAME
-	default "fennec_rk3288"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif
@@ -1,6 +0,0 @@
-FENNEC-RK3288
-M:	Lin Huang <hl@rock-chips.com>
-S:	Maintained
-F:	board/rockchip/fennec_rk3288
-F:	include/configs/fennec_rk3288.h
-F:	configs/fennec-rk3288_defconfig
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= fennec-rk3288.o
@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
@@ -1,5 +1,5 @@
 DRACO BOARD
-M:	Roger Meier <r.meier@siemens.com>
+M:	Samuel Egli <samuel.egli@siemens.com>
 S:	Maintained
 F:	board/siemens/draco/
 F:	include/configs/draco.h
@@ -1,5 +1,5 @@
 PXM2 BOARD
-M:	Roger Meier <r.meier@siemens.com>
+M:	Samuel Egli <samuel.egli@siemens.com>
 S:	Maintained
 F:	board/siemens/pxm2/
 F:	include/configs/pxm2.h
@@ -1,5 +1,5 @@
 RUT BOARD
-M:	Roger Meier <r.meier@siemens.com>
+M:	Samuel Egli <samuel.egli@siemens.com>
 S:	Maintained
 F:	board/siemens/rut/
 F:	include/configs/rut.h
@@ -18,97 +18,10 @@
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/grf_rk3399.h>
 #include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
 #include <power/regulator.h>
 #include <u-boot/sha256.h>

-static void setup_macaddr(void)
-{
-#if CONFIG_IS_ENABLED(CMD_NET)
-	int ret;
-	const char *cpuid = env_get("cpuid#");
-	u8 hash[SHA256_SUM_LEN];
-	int size = sizeof(hash);
-	u8 mac_addr[6];
-
-	/* Only generate a MAC address, if none is set in the environment */
-	if (env_get("ethaddr"))
-		return;
-
-	if (!cpuid) {
-		debug("%s: could not retrieve 'cpuid#'\n", __func__);
-		return;
-	}
-
-	ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
-	if (ret) {
-		debug("%s: failed to calculate SHA256\n", __func__);
-		return;
-	}
-
-	/* Copy 6 bytes of the hash to base the MAC address on */
-	memcpy(mac_addr, hash, 6);
-
-	/* Make this a valid MAC address and set it */
-	mac_addr[0] &= 0xfe;  /* clear multicast bit */
-	mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
-	eth_env_set_enetaddr("ethaddr", mac_addr);
-#endif
-}
-
-static void setup_serial(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
-	const u32 cpuid_offset = 0x7;
-	const u32 cpuid_length = 0x10;
-
-	struct udevice *dev;
-	int ret, i;
-	u8 cpuid[cpuid_length];
-	u8 low[cpuid_length/2], high[cpuid_length/2];
-	char cpuid_str[cpuid_length * 2 + 1];
-	u64 serialno;
-	char serialno_str[17];
-
-	/* retrieve the device */
-	ret = uclass_get_device_by_driver(UCLASS_MISC,
-					  DM_GET_DRIVER(rockchip_efuse), &dev);
-	if (ret) {
-		debug("%s: could not find efuse device\n", __func__);
-		return;
-	}
-
-	/* read the cpu_id range from the efuses */
-	ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid));
-	if (ret) {
-		debug("%s: reading cpuid from the efuses failed\n",
-		      __func__);
-		return;
-	}
-
-	memset(cpuid_str, 0, sizeof(cpuid_str));
-	for (i = 0; i < 16; i++)
-		sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
-
-	debug("cpuid: %s\n", cpuid_str);
-
-	/*
-	 * Mix the cpuid bytes using the same rules as in
-	 *   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
-	 */
-	for (i = 0; i < 8; i++) {
-		low[i] = cpuid[1 + (i << 1)];
-		high[i] = cpuid[i << 1];
-	}
-
-	serialno = crc32_no_comp(0, low, 8);
-	serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
-	snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
-
-	env_set("cpuid#", cpuid_str);
-	env_set("serial#", serialno_str);
-#endif
-}
-
 static void setup_iodomain(void)
 {
 	const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
@@ -198,8 +111,23 @@ static int setup_boottargets(void)

 int misc_init_r(void)
 {
-	setup_serial();
-	setup_macaddr();
+       const u32 cpuid_offset = 0x7;
+       const u32 cpuid_length = 0x10;
+       u8 cpuid[cpuid_length];
+       int ret;
+
+       ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+       if (ret)
+               return ret;
+
+       ret = rockchip_cpuid_set(cpuid, cpuid_length);
+       if (ret)
+               return ret;
+
+       ret = rockchip_setup_macaddr();
+       if (ret)
+               return ret;
+
 	setup_iodomain();
 	setup_boottargets();

@@ -288,15 +288,15 @@ int ft_board_setup(void *blob, bd_t *bd)
 	mac_addr[5] = header.MAC1[5];


-	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
+	node = fdt_path_offset(blob, "ethernet0");
 	if (node < 0) {
-		printf("no /soc/fman/ethernet path offset\n");
+		printf("no ethernet0 path offset\n");
 		return -ENODEV;
 	}

 	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
 	if (ret) {
-		printf("error setting local-mac-address property\n");
+		printf("error setting mac-address property\n");
 		return -ENODEV;
 	}

@@ -308,15 +308,15 @@ int ft_board_setup(void *blob, bd_t *bd)
 	mac_addr[4] = header.MAC2[4];
 	mac_addr[5] = header.MAC2[5];

-	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
+	node = fdt_path_offset(blob, "ethernet1");
 	if (node < 0) {
-		printf("no /soc/fman/ethernet path offset\n");
+		printf("no ethernet1 path offset\n");
 		return -ENODEV;
 	}

 	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
 	if (ret) {
-		printf("error setting local-mac-address property\n");
+		printf("error setting mac-address property\n");
 		return -ENODEV;
 	}

@@ -611,6 +611,20 @@ config CMD_MEMORY
 	    base - print or set address offset
 	    loop - initialize loop on address range

+config MX_CYCLIC
+	bool "Enable cyclic md/mw commands"
+	depends on CMD_MEMORY
+	help
+          Add the "mdc" and "mwc" memory commands. These are cyclic
+          "md/mw" commands.
+          Examples:
+
+	  => mdc.b 10 4 500
+	  This command will print 4 bytes (10,11,12,13) each 500 ms.
+
+	  => mwc.l 100 12345678 10
+	  This command will write 12345678 to address 100 all 10 ms.
+
 config CMD_RANDOM
 	bool "random"
 	default y
@@ -7,51 +7,70 @@
 #include <clk.h>
 #if defined(CONFIG_DM) && defined(CONFIG_CLK)
 #include <dm.h>
+#include <dm/device.h>
+#include <dm/root.h>
 #include <dm/device-internal.h>
+#include <linux/clk-provider.h>
 #endif

+#if defined(CONFIG_DM) && defined(CONFIG_CLK)
+static void show_clks(struct udevice *dev, int depth, int last_flag)
+{
+	int i, is_last;
+	struct udevice *child;
+	struct clk *clkp;
+	u32 rate;
+
+	clkp = dev_get_clk_ptr(dev);
+	if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+		rate = clk_get_rate(clkp);
+
+	printf(" %-12u  %8d        ", rate, clkp->enable_count);
+
+	for (i = depth; i >= 0; i--) {
+		is_last = (last_flag >> i) & 1;
+		if (i) {
+			if (is_last)
+				printf("    ");
+			else
+				printf("|   ");
+		} else {
+			if (is_last)
+				printf("`-- ");
+			else
+				printf("|-- ");
+		}
+	}
+
+	printf("%s\n", dev->name);
+	}
+
+	list_for_each_entry(child, &dev->child_head, sibling_node) {
+		is_last = list_is_last(&child->sibling_node, &dev->child_head);
+		show_clks(child, depth + 1, (last_flag << 1) | is_last);
+	}
+}
+
 int __weak soc_clk_dump(void)
 {
-#if defined(CONFIG_DM) && defined(CONFIG_CLK)
-	struct udevice *dev;
-	struct uclass *uc;
-	struct clk clk;
-	int ret;
-	ulong rate;
+	struct udevice *root;

-	/* Device addresses start at 1 */
-	ret = uclass_get(UCLASS_CLK, &uc);
-	if (ret)
-		return ret;
-
-	uclass_foreach_dev(dev, uc) {
-		memset(&clk, 0, sizeof(clk));
-		ret = device_probe(dev);
-		if (ret)
-			goto noclk;
-
-		ret = clk_request(dev, &clk);
-		if (ret)
-			goto noclk;
-
-		rate = clk_get_rate(&clk);
-		clk_free(&clk);
-
-		if (rate == -ENODEV)
-			goto noclk;
-
-		printf("%-30.30s : %lu Hz\n", dev->name, rate);
-		continue;
-	noclk:
-		printf("%-30.30s : ? Hz\n", dev->name);
+	root = dm_root();
+	if (root) {
+		printf(" Rate               Usecnt      Name\n");
+		printf("------------------------------------------\n");
+		show_clks(root, -1, 0);
 	}

 	return 0;
+}
 #else
+int __weak soc_clk_dump(void)
+{
 	puts("Not implemented\n");
 	return 1;
-#endif
 }
+#endif

 static int do_clk_dump(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char *const argv[])
@@ -91,7 +91,7 @@ static int do_gpio_status(bool all, const char *gpio_name)

 		if (!gpio_name || !bank_name ||
 		    !strncasecmp(gpio_name, bank_name, banklen)) {
-			const char *p = NULL;
+			const char *p;
 			int offset;

 			p = gpio_name + banklen;
@@ -148,7 +148,7 @@ int pci_bar_show(struct udevice *dev)

 		if ((!is_64 && size_low) || (is_64 && size)) {
 			size = ~size + 1;
-			printf(" %d   %#016llx  %#016llx  %d     %s   %s\n",
+			printf(" %d   %#018llx  %#018llx  %d     %s   %s\n",
 			       bar_id, (unsigned long long)base,
 			       (unsigned long long)size, is_64 ? 64 : 32,
 			       is_io ? "I/O" : "MEM",
@@ -629,10 +629,10 @@ static void pci_show_regions(struct udevice *bus)
 		return;
 	}

-	printf("#   %-16s %-16s %-16s  %s\n", "Bus start", "Phys start", "Size",
+	printf("#   %-18s %-18s %-18s  %s\n", "Bus start", "Phys start", "Size",
 	       "Flags");
 	for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
-		printf("%d   %#016llx %#016llx %#016llx  ", i,
+		printf("%d   %#018llx %#018llx %#018llx  ", i,
 		       (unsigned long long)reg->bus_start,
 		       (unsigned long long)reg->phys_start,
 		       (unsigned long long)reg->size);
@@ -467,12 +467,29 @@ static int reserve_uboot(void)
 	return 0;
 }

+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+static int reserve_noncached(void)
+{
+	/* round down to SECTION SIZE (typicaly 1MB) limit */
+	gd->start_addr_sp &= ~(MMU_SECTION_SIZE - 1);
+	gd->start_addr_sp -= CONFIG_SYS_NONCACHED_MEMORY;
+	debug("Reserving %dM for noncached_alloc() at: %08lx\n",
+	      CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
+
+	return 0;
+}
+#endif
+
 /* reserve memory for malloc() area */
 static int reserve_malloc(void)
 {
 	gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
 	debug("Reserving %dk for malloc() at: %08lx\n",
 	      TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+	reserve_noncached();
+#endif
+
 	return 0;
 }

@@ -132,6 +132,7 @@ static const table_entry_t uimage_os[] = {
 #if defined(CONFIG_BOOTM_OPENRTOS) || defined(USE_HOSTCC)
 	{	IH_OS_OPENRTOS,	"openrtos",	"OpenRTOS",		},
 #endif
+	{	IH_OS_OPENSBI,	"opensbi",	"RISC-V OpenSBI",	},

 	{	-1,		"",		"",			},
 };
@@ -208,6 +208,7 @@ config SPL_SYS_MALLOC_SIMPLE
 config TPL_SYS_MALLOC_SIMPLE
 	bool
 	prompt "Only use malloc_simple functions in the TPL"
+	depends on TPL
 	help
 	  Say Y here to only use the *_simple malloc functions from
 	  malloc_simple.c, rather then using the versions from dlmalloc.c;
@@ -261,6 +262,7 @@ config SPL_BANNER_PRINT

 config TPL_BANNER_PRINT
 	bool "Enable output of the TPL banner 'U-Boot TPL ...'"
+	depends on TPL
 	default y
 	help
 	  If this option is enabled, SPL will not print the banner with version
@@ -433,6 +435,7 @@ config SPL_HASH_SUPPORT

 config TPL_HASH_SUPPORT
 	bool "Support hashing drivers in TPL"
+	depends on TPL
 	select SHA1
 	select SHA256
 	help
@@ -1000,6 +1003,14 @@ config SPL_SPI_LOAD

 endif # SPL_SPI_FLASH_SUPPORT

+config SYS_SPI_U_BOOT_OFFS
+	hex "address of u-boot payload in SPI flash"
+	default 0x0
+	depends on SPL_SPI_LOAD || SPL_SPI_SUNXI
+	help
+	 Address within SPI-Flash from where the u-boot payload is fetched
+	 from.
+
 config SPL_SPI_SUPPORT
 	bool "Support SPI drivers"
 	help
@@ -1146,6 +1157,23 @@ config SPL_OPTEE
 	  OP-TEE is an open source Trusted OS  which is loaded by SPL.
 	  More detail at: https://github.com/OP-TEE/optee_os

+config SPL_OPENSBI
+	bool "Support RISC-V OpenSBI"
+	depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+	help
+	  OpenSBI is an open-source implementation of the RISC-V Supervisor Binary
+	  Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC
+	  firmware. It is loaded and started by U-Boot SPL.
+
+	  More details are available at https://github.com/riscv/opensbi and
+	  https://github.com/riscv/riscv-sbi-doc
+
+config SPL_OPENSBI_LOAD_ADDR
+	hex "OpenSBI load address"
+	depends on SPL_OPENSBI
+	help
+	  Load address of the OpenSBI binary.
+
 config TPL
 	bool
 	depends on SUPPORT_TPL
@@ -22,6 +22,7 @@ obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
 obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
 obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
+obj-$(CONFIG_$(SPL_TPL_)OPENSBI) += spl_opensbi.o
 obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
 obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
 obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
@@ -659,6 +659,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 				(void *)spl_image.entry_point);
 		break;
 #endif
+#if CONFIG_IS_ENABLED(OPENSBI)
+	case IH_OS_OPENSBI:
+		debug("Jumping to U-Boot via RISC-V OpenSBI\n");
+		spl_invoke_opensbi(&spl_image);
+		break;
+#endif
 #ifdef CONFIG_SPL_OS_BOOT
 	case IH_OS_LINUX:
 		debug("Jumping to Linux\n");
@@ -775,7 +781,7 @@ ulong spl_relocate_stack_gd(void)
 #if CONFIG_IS_ENABLED(DM)
 	dm_fixup_for_gd_move(new_gd);
 #endif
-#if !defined(CONFIG_ARM)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_RISCV)
 	gd = new_gd;
 #endif
 	return ptr;
@@ -12,6 +12,8 @@
 #include <linux/libfdt.h>
 #include <spl.h>

+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SYS_BOOTM_LEN
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)
 #endif
@@ -279,26 +281,35 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 			      void *fit, int images, ulong base_offset)
 {
 	struct spl_image_info image_info;
-	int node, ret;
+	int node, ret = 0;
+
+	/*
+	 * Use the address following the image as target address for the
+	 * device tree.
+	 */
+	image_info.load_addr = spl_image->load_addr + spl_image->size;

 	/* Figure out which device tree the board wants to use */
 	node = spl_fit_get_image_node(fit, images, FIT_FDT_PROP, 0);
 	if (node < 0) {
 		debug("%s: cannot find FDT node\n", __func__);
-		return node;
+
+		/*
+		 * U-Boot did not find a device tree inside the FIT image. Use
+		 * the U-Boot device tree instead.
+		 */
+		if (gd->fdt_blob)
+			memcpy((void *)image_info.load_addr, gd->fdt_blob,
+			       fdt_totalsize(gd->fdt_blob));
+		else
+			return node;
+	} else {
+		ret = spl_load_fit_image(info, sector, fit, base_offset, node,
+					 &image_info);
+		if (ret < 0)
+			return ret;
 	}

-	/*
-	 * Read the device tree and place it after the image.
-	 * Align the destination address to ARCH_DMA_MINALIGN.
-	 */
-	image_info.load_addr = spl_image->load_addr + spl_image->size;
-	ret = spl_load_fit_image(info, sector, fit, base_offset, node,
-				 &image_info);
-
-	if (ret < 0)
-		return ret;
-
 	/* Make the load-address of the FDT available for the SPL framework */
 	spl_image->fdt_addr = (void *)image_info.load_addr;
 #if !CONFIG_IS_ENABLED(FIT_IMAGE_TINY)
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ *
+ * Based on common/spl/spl_atf.c
+ */
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/smp.h>
+#include <opensbi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct fw_dynamic_info opensbi_info;
+
+static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node)
+{
+	int fit_images_node, node;
+	const char *fit_os;
+
+	fit_images_node = fdt_path_offset(blob, "/fit-images");
+	if (fit_images_node < 0)
+		return -ENODEV;
+
+	fdt_for_each_subnode(node, blob, fit_images_node) {
+		fit_os = fdt_getprop(blob, node, FIT_OS_PROP, NULL);
+		if (!fit_os)
+			continue;
+
+		if (genimg_get_os_id(fit_os) == IH_OS_U_BOOT) {
+			*uboot_node = node;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+void spl_invoke_opensbi(struct spl_image_info *spl_image)
+{
+	int ret, uboot_node;
+	ulong uboot_entry;
+	void (*opensbi_entry)(ulong hartid, ulong dtb, ulong info);
+
+	if (!spl_image->fdt_addr) {
+		pr_err("No device tree specified in SPL image\n");
+		hang();
+	}
+
+	/* Find U-Boot image in /fit-images */
+	ret = spl_opensbi_find_uboot_node(spl_image->fdt_addr, &uboot_node);
+	if (ret) {
+		pr_err("Can't find U-Boot node, %d", ret);
+		hang();
+	}
+
+	/* Get U-Boot entry point */
+	uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node,
+				      "entry-point");
+	if (uboot_entry == FDT_ERROR)
+		uboot_entry = fdt_getprop_u32(spl_image->fdt_addr, uboot_node,
+					      "load-addr");
+
+	/* Prepare obensbi_info object */
+	opensbi_info.magic = FW_DYNAMIC_INFO_MAGIC_VALUE;
+	opensbi_info.version = FW_DYNAMIC_INFO_VERSION;
+	opensbi_info.next_addr = uboot_entry;
+	opensbi_info.next_mode = FW_DYNAMIC_INFO_NEXT_MODE_S;
+	opensbi_info.options = SBI_SCRATCH_NO_BOOT_PRINTS;
+
+	opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point;
+	invalidate_icache_all();
+
+#ifdef CONFIG_SMP
+	ret = smp_call_function((ulong)spl_image->entry_point,
+				(ulong)spl_image->fdt_addr,
+				(ulong)&opensbi_info);
+	if (ret)
+		hang();
+#endif
+	opensbi_entry(gd->arch.boot_hart, (ulong)spl_image->fdt_addr,
+		      (ulong)&opensbi_info);
+}
@@ -15,6 +15,7 @@ CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_USE_PREBOOT=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -7,6 +7,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
 # CONFIG_AUTOBOOT is not set
 CONFIG_CMD_IMLS=y
 CONFIG_LOOPW=y
+CONFIG_MX_CYCLIC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_CACHE=y
 CONFIG_DEFAULT_DEVICE_TREE="M5249EVB"
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x00600000
 CONFIG_TARGET_SBx81LIFKW=y
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
 CONFIG_KIRKWOOD=y
 CONFIG_SYS_TEXT_BASE=0x00600000
 CONFIG_TARGET_SBx81LIFXCAT=y