* Patch by Stefan Roese, 5 Jul 2005:

Update uc100 board PHY setup
* Patch by Detlev Zundel, 30 Jun 2005:
2005-07-05 11:35:27 +00:00 · 2005-07-04 00:03:16 +00:00 · 2005-07-01 15:53:57 +00:00 · 2005-06-30 13:06:07 +00:00 · 2005-06-27 13:30:03 +00:00 · 2005-06-20 10:28:38 +00:00
173 changed files with 16127 additions and 4394 deletions
--- a/177
+++ b/177
@@ -2,7 +2,180 @@
 Changes for U-Boot 1.1.3:
 ======================================================================

-* Add support for TQM8560 board
+* Patch by Stefan Roese, 5 Jul 2005:
+  Update uc100 board PHY setup
+
+* Patch by Stefan Roese, 1 Jul 2005:
+  Fix PHY address for CATcenter board (now correct!)
+
+* Patch by Stefan Roese, 30 Jun 2005:
+  Fix PHY addresses for PPChameleon and CATcenter boards
+  Change MAINTAINER for most esd boards
+
+* Patch by Detlev Zundel, 30 Jun 2005:
+  Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
+
+* Fix baudrate calculation problem on MPC5200 systems
+
+* Add EEPROM and RTC support for HMI1001 board
+
+* Patch by Detlev Zundel, 20 Jun 2005:
+  Fix initialization of low active GPIO pins on inka4x0 board
+
+* Enable redundant environment, disable HW flash protection of
+  HMI1001 board
+
+* Patch by Travis Sawyer, 10 Jun 2005:
+  Initialize allocated dev and private hw structures
+  after their respective allocation in 440gx_enet.c
+
+* Patch by Steven Scholz, 10 Jun 2005:
+  Fix byteorder problems with second argument of "bootm" with
+  standalone images;
+
+* Add support for HMI1001 board
+
+* Disable "date" and "sntp" commands on TQM866M
+
+* Fix watchdog reset problems on LWMON board
+
+* Patch by Juergen Selent, 17 May 2005:
+  Add support for Funkwerk VoVPN gateway module.
+
+* Cleanup debug code for MPC8220 FEC driver
+
+* Extend burst mode RAM test program to take a loop count
+  (0 = infinite)
+
+* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
+  those boards that use it.
+
+* Patches by Greg Ungerer, 19 May 2005:
+  - add support for the KS8695P (ARM 922 based) CPU
+  - add support for the OpenGear CM4008, CM4116 and CM4148 boards
+
+* Patch by Steven Scholz, 19 May 2005:
+  Add support for CONFIG_SERIAL_TAG on ARM boards
+
+* Add PCI support for Sorcery board.
+  Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
+
+* Fix compile problems caused by new burst mode SDRAM test;
+  make port pins to trigger logic analyzer configurable
+
+* Fix timer handling on MPC85xx systems
+
+* Fix debug code in omap5912osk flash driver
+
+* Add support for MPC8247 based "IDS8247" board.
+
+* Add support for 2 x TSEC interfaces on the TQM8540 board.
+
+* On LWMON we must use the watchdog to reset the board as the CPU
+  genereated HRESET pulse is too short to reset the external
+  circuitry.
+
+* Add test tool to exercise SDRAM accesses in burst mode
+  (as standalone program, MPC8xx/PowerPC only)
+
+* Increase CFG_MONITOR_LEN for Rattler board to match actual code
+  size.
+
+* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
+  March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
+  added to support LZO and LZARI compression modes (undefined by
+  default).
+
+* Fix problem with symbolic links in JFFS2 code.
+
+* Use linker ASSERT statement to prevent undetected overlapping of
+  sections on PPChameleon board; other boards might use this, too.
+
+* Patch by Stefan Roese, 03 May 2005:
+  Update for P3G4
+  Fix problems in cmd_universe.c
+
+* Patch by Matthias Fuchs, 03 May 2005:
+  Added missing variable declaration in cmd_nand.c
+  Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
+
+* Fix INKA4x0: use CS1 as gpio_wkup_6 output
+
+* Fix bug in the SDRAM initialization code for canmb, IceCube and
+  PM520 boards.
+  Fix PHY address for canmb board.
+
+* Cleanup serial console baudrate calculation on AT91RM9200;
+  get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
+
+* Patch by Matthias Fuchs, 18 Apr 2005:
+  Make PCI target address spaces on PMC405 and CPCI405 boards
+  configurable via environment variables
+
+* Auto-size RAM on canmb board.
+
+* Add support for canmb board
+
+* Patch by Stefan Roese, 13 Apr 2005:
+  Update for esd apc405
+
+* Fixes for TQM8560 board:
+  - fix clock rates
+  - remove debug messages
+  - fix flash sector protection
+
+* Patch by Steven Scholz, 07 Apr 2005:
+  Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
+
+* Patches by Steven Scholz, 07 Apr 2005:
+  Fix compiler warning in altera.c
+  Fix warning in cpu/arm920t/at91rm9200/i2c.c
+
+* Patch by Ladislav Michl, 06 Apr 2005:
+  Fix voiceblue configuration.
+
+* Patch by Stefan Roese, 06 Apr 2005:
+  Updates for OCOTEA board:
+  - Changed U-Boot size from 512kByte to 256kByte
+  - Fixed flash driver to support boot from soldered user flash
+  - Added README for switch from PIBS firmware to U-Boot
+
+* Patch by Travis Sawyer, 05 Apr 2005:
+  - Change timer frequency for ppc 440 from 10 ms to 1 ms.
+    Problem found by Andrew Wozniak.
+
+* Patch by Steven Scholz, 06 Apr 2005:
+  - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+  - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
+* Patches by Robert Whaley, 29 Nov 2004:
+  - update the pxa-regs.h file for PXA27x chips
+  - add PXA27x based ADSVIX board
+  - add support for MMC on PXA27x processors
+
+* Patch by Andrew E. Mileski, 28 Nov 2004:
+  Fix PPC4xx SPD SDRAM detection bug
+
+* Patch by Hiroshi Ito, 26 Nov 2004:
+  Fix logic of "test -z" and "test -n" commands
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Add support for VoiceBlue board.
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Fix netboot_common() prototypes.
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Use i.MX watchdog timer for reset_cpu()
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
+  subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
+  (now in interupts.c)
+
+* Add support for MPC8220 based "sorcery" board.
+
+* Add support for TQM8560 board.

 * Add FEC support for TQM8540 board.
  Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
@@ -26,7 +199,7 @@ Changes for U-Boot 1.1.3:

 * Patch by Tolunay Orkun, 16 November 2004:
  fix incorrect onboard Xilinx CPLD base address
-  
+
 * Patch by Jerry Van Baren, 08 Nov 2004:
  - Add low-boot option for MPC8260ADS board (if lowboot is selected,
    the jumper for the HRCW source should select flash. If lowboot is
--- a/8
+++ b/8
@@ -394,6 +394,10 @@ N: Rune Torgersen
 E: <runet@innovsys.com>
 D: Support for Motorola MPC8266ADS board

+N: Greg Ungerer
+E: greg.ungerer@opengear.com
+D: Support for ks8695 CPU, and OpenGear cmXXXX boards
+
 N: David Updegraff
 E: dave@cray.com
 D: Port to Cray L1 board; DHCP vendor extensions
@@ -402,6 +406,10 @@ N: Christian Vejlbo
 E: christian.vejlbo@tellabs.com
 D: FADS860T ethernet support

+N: Robert Whaley
+E: rwhaley@applieddata.net
+D: Port to ARM PXA27x adsvix SBC
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board
--- a/12
+++ b/12
@@ -230,7 +230,7 @@ Daniel Poirot <dan.poirot@windriver.com>
 	sbc8240			MPC8240
 	sbc405			PPC405GP

-Stefan Roese <stefan.roese@esd-electronics.com>
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>

 	ADCIOP			IOP480 (PPC401)
 	APC405			PPC405GP
@@ -298,6 +298,8 @@ Jon Loeliger <jdl@freescale.com>

 	MPC8540ADS		MPC8540
 	MPC8560ADS		MPC8560
+	MPC8541CDS		MPC8541
+	MPC8555CDS		MPC8555

 Dan Malek <dan@embeddededge.com>

@@ -413,6 +415,12 @@ Andrea Scian <andrea.scian@dave-tech.it>

 	B2				ARM7TDMI (S3C44B0X)

+Greg Ungerer <greg.ungerer@opengear.com>
+
+	cm4008			ks8695p
+	cm4116			ks8695p
+	cm4148			ks8695p
+
 Alex Z<>pke <azu@sysgo.de>

 	lart			SA1100
@@ -490,7 +498,7 @@ Yasushi Shoji <yashi@atmark-techno.com>
 #	Board			CPU					#
 #########################################################################

-Stefan Roese <stefan.roese@esd-electronics.com>
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>

 	TASREG			MCF5249

--- a/18
+++ b/18
@@ -129,11 +129,11 @@ LIST_7xx="	\
 	BAB7xx		CPCI750		ELPPC				\
 "

-LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
-	  ${LIST_8xx}  \
-	  ${LIST_824x} ${LIST_8260} \
-	  ${LIST_85xx}	\
-	  ${LIST_4xx}		    \
+LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
+	  ${LIST_8xx}				\
+	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
+	  ${LIST_85xx}				\
+	  ${LIST_4xx}				\
 	  ${LIST_74xx} ${LIST_7xx}"

 #########################################################################
@@ -157,7 +157,7 @@ LIST_ARM9="	\
 	lpd7a400	mx1ads		mx1fs2		omap1510inn	\
 	omap1610h2	omap1610inn	omap730p2	scb9328		\
 	smdk2400	smdk2410	trab		VCMA9		\
-	versatile							\
+	versatile	voiceblue					\
 "

 #########################################################################
@@ -170,9 +170,9 @@ LIST_ARM11="omap2420h4"
 #########################################################################

 LIST_pxa="	\
-	cerf250		cradle		csb226		innokom		\
-	lubbock		wepep250	xaeniax		xm250		\
-	xsengine							\
+	adsvix		cerf250		cradle		csb226		\
+	innokom		lubbock		wepep250	xaeniax		\
+	xm250		xsengine							\
 "

 LIST_ixp="ixdp425"
--- a/61
+++ b/61
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -215,6 +215,9 @@ unconfig:
 ## MPC5xx Systems
 #########################################################################

+canmb_config:	unconfig
+	@./mkconfig -a canmb ppc mpc5xxx canmb
+
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi

@@ -224,6 +227,10 @@ PATI_config:		unconfig
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
+
+hmi1001_config:         unconfig
+	@./mkconfig hmi1001 ppc mpc5xxx hmi1001
+
 Lite5200_config				\
 Lite5200_LOWBOOT_config			\
 Lite5200_LOWBOOT08_config		\
@@ -864,6 +871,9 @@ XPEDITE1K_config:	unconfig
 Alaska8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 alaska

+sorcery_config:		unconfig
+	@./mkconfig $(@:_config=) ppc mpc8220 sorcery
+
 Yukon8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 yukon

@@ -981,6 +991,9 @@ gw8260_config:	unconfig
 hymod_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 hymod

+IDS8247_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 ids8247
+
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539

@@ -1143,6 +1156,11 @@ TQM8265_AA_config:  unconfig
 	fi
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260

+VoVPN-GW_66MHz_config	\
+VoVPN-GW_100MHz_config:		unconfig
+	@echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > include/config.h
+	@./mkconfig -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk
+
 ZPC1900_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900

@@ -1282,6 +1300,12 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$

 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))

+at91rm9200dk_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+
+cmc_pu2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap

@@ -1379,6 +1403,25 @@ VCMA9_config	:	unconfig
 versatile_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs versatile

+voiceblue_smallflash_config	\
+voiceblue_config:	unconfig
+	@if [ "$(findstring _smallflash_,$@)" ] ; then \
+		echo "... boot from lower flash bank" ; \
+		echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \
+	else \
+		echo "... boot from upper flash bank" ; \
+		>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \
+	fi
+	@./mkconfig -a voiceblue arm arm925t voiceblue
+
+cm4008_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cm4008 NULL ks8695
+
+cm41xx_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
+
 #########################################################################
 ## S3C44B0 Systems
 #########################################################################
@@ -1402,20 +1445,13 @@ modnet50_config :	unconfig
 evb4510_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t evb4510

-#########################################################################
-## AT91RM9200 Systems
-#########################################################################
-
-at91rm9200dk_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
-
-cmc_pu2_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
-
 #########################################################################
 ## XScale Systems
 #########################################################################

+adsvix_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa adsvix
+
 cerf250_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa cerf250

@@ -1633,7 +1669,8 @@ clean:
 		| xargs rm -f
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
-	      examples/mem_to_mem_idma2intr examples/82559_eeprom
+	      examples/mem_to_mem_idma2intr examples/82559_eeprom \
+	      examples/test_burst
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
 	rm -f tools/mpc86x_clk tools/ncb
 	rm -f tools/easylogo/easylogo tools/bmp_logo
--- a/25
+++ b/25
@@ -126,12 +126,12 @@ Directory Hierarchy:
  - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
  - arm720t	Files specific to ARM 720 CPUs
  - arm920t	Files specific to ARM 920 CPUs
+    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
    - imx	Files specific to Freescale MC9328 i.MX CPUs
    - s3c24x0	Files specific to Samsung S3C24X0 CPUs
  - arm925t	Files specific to ARM 925 CPUs
  - arm926ejs	Files specific to ARM 926 CPUs
  - arm1136	Files specific to ARM 1136 CPUs
-  - at91rm9200	Files specific to Atmel AT91RM9200 CPUs
  - i386	Files specific to i386 CPUs
  - ixp		Files specific to Intel XScale IXP CPUs
  - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
@@ -2132,14 +2132,14 @@ Low Level (hardware related) configuration options:
 - CONFIG_SKIP_LOWLEVEL_INIT
 - CONFIG_SKIP_RELOCATE_UBOOT

-                [ARM only] If these variables are defined, then
-                certain low level initializations (like setting up
-                the memory controller) are omitted and/or U-Boot does
-                not relocate itself into RAM.
-                Normally these variables MUST NOT be defined. The
-                only exception is when U-Boot is loaded (to RAM) by
-                some other boot loader or by a debugger which
-                performs these intializations itself.
+		[ARM only] If these variables are defined, then
+		certain low level initializations (like setting up
+		the memory controller) are omitted and/or U-Boot does
+		not relocate itself into RAM.
+		Normally these variables MUST NOT be defined. The
+		only exception is when U-Boot is loaded (to RAM) by
+		some other boot loader or by a debugger which
+		performs these intializations itself.


 Building the Software:
@@ -3081,8 +3081,7 @@ Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
-meantime, send mail to bruno@exet-ag.de and/or wd@denx.de for
-details.
+meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz


 Implementation Internals:
@@ -3382,6 +3381,7 @@ Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.

+Patches shall be sent to the u-boot-users mailing list.

 When you send a patch, please include the following information with
 it:
@@ -3439,3 +3439,6 @@ Notes:
  (using #ifdef), and the resulting code with the new feature
  disabled must not need more memory than the old code without your
  modification.
+
+* Remember that there is a size limit of 40 kB per message on the
+  u-boot-users mailing list. Compression may help.
--- a/board/adsvix/Makefile
+++ b/board/adsvix/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= adsvix.o pcmcia.o
+SOBJS	:= lowlevel_init.o pxavoltage.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/adsvix/adsvix.c
+++ b/board/adsvix/adsvix.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of ADSVIX-Board */
+	gd->bd->bi_arch_number = 620;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa000003c;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
--- a/board/adsvix/config.mk
+++ b/board/adsvix/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1700000
--- a/board/adsvix/lowlevel_init.S
+++ b/board/adsvix/lowlevel_init.S
@@ -0,0 +1,466 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc	p15,0,\reg,c2,c0,0
+   mov	\reg,\reg
+   sub	pc,pc,#4
+   .endm
+
+
+/*
+ *	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR3
+	ldr		r1,	=CFG_GPSR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR3
+	ldr		r1,	=CFG_GPCR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR3
+	ldr		r1,	=CFG_GPDR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_L
+	ldr		r1,	=CFG_GAFR3_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_U
+	ldr		r1,	=CFG_GAFR3_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface					    */
+	/*								    */
+	/* The sequence below is based on the recommended init steps	    */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.							    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
+	/*	   clocks to settle. Only necessary after hard reset...	    */
+	/*	   FIXME: can be optimized later			    */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller	    */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type			    */
+
+	/* MSC0: nCS(0,1)						    */
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
+						/* that data latches	    */
+	/* MSC1: nCS(2,3)						    */
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)						    */
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface				    */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register				    */
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing				    */
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing				    */
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
+	/* ---------------------------------------------------------------- */
+	ldr	r2,  =CFG_FLYCNFG_VAL
+	str	r2,  [r1, #FLYCNFG_OFFSET]
+	str	r2,	[r1, #FLYCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
+	/* this to power on defaults + DRI field.			    */
+
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+	ldr	r2,	=0xFFF
+	bic	r4,	r4, r2
+
+	ldr	r3,	=CFG_MDREFR_VAL
+	and	r3,	r3,  r2
+
+	orr	r4,	r4, r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+
+	orr	r4,  r4, #MDREFR_K0RUN
+	orr	r4,  r4, #MDREFR_K0DB4
+	orr	r4,  r4, #MDREFR_K0FREE
+	orr	r4,  r4, #MDREFR_K0DB2
+	orr	r4,  r4, #MDREFR_K1DB2
+	bic	r4,  r4, #MDREFR_K1FREE
+	bic	r4,  r4, #MDREFR_K2FREE
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4			    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits		    */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.						    */
+
+	ldr	r2,  =CFG_SXCNFG_VAL
+	str	r2,  [r1, #SXCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM					    */
+	/* ---------------------------------------------------------------- */
+
+	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+	orr	r4, r4, #MDREFR_K1RUN
+	bic	r4, r4, #MDREFR_K2DB2
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	bic	r4, r4, #MDREFR_SLFRSH
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	orr	r4, r4, #MDREFR_E1PIN
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	nop
+	nop
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*	    configure but not enable each SDRAM partition pair.	    */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+
+	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
+	ldr	r4,	[r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
+	/*	    100..200 <20>sec.					    */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
+	/*	    attempting non-burst read or write accesses to disabled */
+	/*	    SDRAM, as commonly specified in the power up sequence   */
+	/*	    documented in SDRAM data sheets. The address(es) used   */
+	/*	    for this purpose must not be cacheable.		    */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted		    */
+	/*	    (MDCNFG:DEx set to 1).				    */
+
+	ldr	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r4, r3
+	orr	r3,	r3,	#MDCNFG_DE0
+	str	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r0, r3
+
+	/* Step 4h: Write MDMRS.					    */
+
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	/* enable APD */
+	ldr	r3,  [r1, #MDREFR_OFFSET]
+	orr	r3,  r3,  #MDREFR_APD
+	str	r3,  [r1, #MDREFR_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+setvoltage:
+
+	mov	r10,	lr
+	bl	initPXAvoltage	/* In case the board is rebooting with a    */
+	mov	lr,	r10	/* low voltage raise it up to a good one.   */
+
+wakeup:
+	/* Are we waking from sleep? */
+	ldr	r0,	=RCSR
+	ldr	r1,	[r0]
+	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r1,	[r0]
+	teq	r1,	#RCSR_SMR
+
+	bne	initirqs
+
+	ldr	r0,	=PSSR
+	mov	r1,	#PSSR_PH
+	str	r1,	[r0]
+
+	/* if so, resume at PSPR */
+	ldr	r0,	=PSPR
+	ldr	r1,	[r0]
+	mov	pc,	r1
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller	    */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
+	str	r1,  [r2]
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation						    */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off on-chip peripheral clocks (except for memory)	    */
+	/* for re-configuration.					    */
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN
+	str	r2,  [r1]
+
+	/* ... and write the core clock config register			    */
+	ldr	r2,  =CFG_CCCR
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+	/* Turn on turbo mode */
+	mrc	p14, 0, r2, c6, c0, 0
+	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
+	mcr	p14, 0, r2, c6, c0, 0
+
+	/* Re-write MDREFR */
+	ldr	r1, =MEMC_BASE
+	ldr	r2, [r1, #MDREFR_OFFSET]
+	str	r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager		    */
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
+	/* has settled.							    */
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#else
+#error "RTC not defined"
+#endif
+
+	/* Interrupt init: Mask all interrupts				    */
+    ldr r0, =ICMR /* enable no sources */
+	mov r1, #0
+    str r1, [r0]
+	/* FIXME */
+
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init							    */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+	mov	pc, lr
--- a/board/adsvix/pcmcia.c
+++ b/board/adsvix/pcmcia.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+void pcmcia_power_on(void)
+{
+#if 0
+	if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
+		GPCR(81) = GPIO_bit(81);
+		GPSR(82) = GPIO_bit(82);
+	}
+	else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
+		GPCR(81) = GPIO_bit(81);
+		GPCR(82) = GPIO_bit(82);
+	}
+#else
+#warning "Board will only supply 5V, wait for next HW spin for selectable power"
+	/* 5.0V */
+	GPCR(81) = GPIO_bit(81);
+	GPCR(82) = GPIO_bit(82);
+#endif
+
+	udelay(300000);
+
+	/* reset the card */
+	GPSR(52) = GPIO_bit(52);
+
+	/* enable PCMCIA */
+	GPCR(83) = GPIO_bit(83);
+
+	/* clear reset */
+	udelay(10);
+	GPCR(52) = GPIO_bit(52);
+
+	udelay(20000);
+}
+
+void pcmcia_power_off(void)
+{
+	/* 0V */
+	GPSR(81) = GPIO_bit(81);
+	GPSR(82) = GPIO_bit(82);
+	/* disable PCMCIA */
+	GPSR(83) = GPIO_bit(83);
+}
--- a/board/adsvix/pxavoltage.S
+++ b/board/adsvix/pxavoltage.S
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+#define LTC1663_ADDR    0x20
+
+#define LTC1663_SY	0x01	/* Sync ACK */
+#define LTC1663_SD	0x04	/* shutdown */
+#define LTC1663_BG	0x04	/* Internal Voltage Ref */
+
+#define VOLT_1_55         18    /* DAC value for 1.55V */
+
+		.global	initPXAvoltage
+
+@ Set the voltage to 1.55V early in the boot process so we can run
+@ at a high clock speed and boot quickly.  Note that this is necessary
+@ because the reset button does not reset the CPU voltage, so if the
+@ voltage was low (say 0.85V) then the CPU would crash without this
+@ routine
+
+@ This routine clobbers r0-r4
+
+initializei2c:
+
+		ldr	r2, =CKEN
+		ldr	r3, [r2]
+		orr	r3, r3, #CKEN15_PWRI2C
+		str	r3, [r2]
+
+		ldr	r2, =PCFR
+		ldr	r3, [r2]
+		orr	r3, r3, #PCFR_PI2C_EN
+		str	r3, [r2]
+
+		/* delay for about 250msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0000
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		ldr	r0, =PWRICR
+		ldr	r1, [r0]
+		bic	r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		ldr	r2, =PWRISR
+		ldr	r3, =0x7ff
+		str	r3, [r2]
+
+		bic	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		mov	r1, #(ICR_GCD | ICR_SCLE)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_IUE
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_FM
+		str	r1, [r0]
+
+		/* delay for about 1msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC00
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, lr
+
+sendbytei2c:
+		ldr	r3, =PWRIDBR
+		str	r0, [r3]
+		ldr	r3, =PWRICR
+		ldr	r0, [r3]
+		orr	r0, r0, r1
+		bic	r0, r0, r2
+		str	r0, [r3]
+		orr	r0, r0, #ICR_TB
+		str	r0, [r3]
+
+		mov	r2, #0x100000
+
+waitfortxemptyi2c:
+
+		ldr	r0, =PWRISR
+		ldr	r1, [r0]
+
+		/* take it from the top if we don't get empty after a while */
+		subs	r2, r2, #1
+		moveq	lr, r4
+		beq	initPXAvoltage
+
+		tst	r1, #ISR_ITE
+
+		beq	waitfortxemptyi2c
+
+		orr	r1, r1, #ISR_ITE
+		str	r1, [r0]
+
+		mov	pc, lr
+
+initPXAvoltage:
+
+		mov	r4, lr
+
+		bl	setleds
+
+		bl	initializei2c
+
+		bl	setleds
+
+		/* now send the real message to set the correct voltage */
+		ldr	r0, =LTC1663_ADDR
+		mov	r0, r0, LSL #1
+		mov	r1, #ICR_START
+		ldr	r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		mov	r0, #LTC1663_BG
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		and	r0, r0, #0xff
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		mov	r0, r0, ASR #8
+		and	r0, r0, #0xff
+		mov	r1, #ICR_STOP
+		mov	r2, #ICR_START
+		bl	sendbytei2c
+
+		bl	setleds
+
+		@ delay a little for the volatage to stablize
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, r4
+
+setleds:
+	mov		pc, lr
+
+	ldr		r5, =0x40e00058
+	ldr		r3, [r5]
+	bic		r3, r3, #0x3
+	str		r3, [r5]
+	ldr		r5, =0x40e0000c
+	ldr		r3, [r5]
+	orr		r3, r3, #0x00010000
+	str		r3, [r5]
+
+	@ inner loop
+	mov		r0, #0x2
+1:
+
+	ldr		r5, =0x40e00018
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+2:
+	subs		r3, r3, #1
+	bne		2b
+
+	ldr		r5, =0x40e00024
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+3:
+	subs		r3, r3, #1
+	bne		3b
+
+	subs		r0, r0, #1
+	bne		1b
+
+	mov		pc, lr
--- a/board/adsvix/u-boot.lds
+++ b/board/adsvix/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/alaska/Makefile
+++ b/board/alaska/Makefile
@@ -1,4 +1,4 @@
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	:= $(BOARD).o flash.o extserial.o serial.o
+OBJS	:= $(BOARD).o flash.o

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/alaska/extserial.c
+++ b/board/alaska/extserial.c
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-#   include <ns16550.h>
-
-#   define PADSERIAL_BAUD_115200   0x40
-#   define PADSERIAL_BAUD_57600    0x20
-#   define PADSERIAL_BAUD_9600     0
-#   define PADCARD_FREQ            18432000
-
-const NS16550_t com_port = (NS16550_t) CFG_NS16550_COM1;
-
-int ext_serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_init (com_port, baud_divisor);
-
-	return (0);
-}
-
-void ext_serial_putc (const char c)
-{
-	if (c == '\n')
-		NS16550_putc (com_port, '\r');
-
-	NS16550_putc (com_port, c);
-}
-
-void ext_serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int ext_serial_getc (void)
-{
-	return NS16550_getc (com_port);
-}
-
-int ext_serial_tstc (void)
-{
-	return NS16550_tstc (com_port);
-}
-
-void ext_serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_reinit (com_port, baud_divisor);
-}
-#endif /* CONFIG_EXTUART_CONSOLE */
--- a/board/alaska/serial.c
+++ b/board/alaska/serial.c
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-int serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-	volatile uchar *cpld = (volatile uchar *) CFG_CPLD_BASE;
-#endif
-
-	/* Check CPLD Switch 2 whether is external or internal */
-#if defined (CONFIG_EXTUART_CONSOLE)
-	if ((*cpld & 0x02) == 0x02) {
-		gd->bExtUart = 1;
-		return ext_serial_init ();
-	} else
-#endif
-	{
-#if defined(CONFIG_PSC_CONSOLE)
-		gd->bExtUart = 0;
-		return psc_serial_init ();
-#endif
-	}
-
-	return (0);
-}
-
-void serial_putc (const char c)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_putc (c);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_putc (c);
-#endif
-	}
-}
-
-void serial_puts (const char *s)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_puts (s);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_puts (s);
-#endif
-	}
-}
-
-int serial_getc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_getc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_getc ();
-#endif
-	}
-}
-
-int serial_tstc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_tstc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_tstc ();
-#endif
-	}
-}
-
-void serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_setbrg ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_setbrg ();
-#endif
-	}
-}
--- a/board/at91rm9200dk/u-boot.lds
+++ b/board/at91rm9200dk/u-boot.lds
@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}

--- a/board/canmb/Makefile
+++ b/board/canmb/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+#../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/canmb/canmb.c
+++ b/board/canmb/canmb.c
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m32s2-75.h"
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+	puts ("Board: CANMB\n");
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}
--- a/board/canmb/config.mk
+++ b/board/canmb/config.mk
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CANMB board
+#
+# allowed and functional TEXT_BASE values:
+#
+#   0xfe000000		low boot at 0x00000100 (default board setting)
+#	0x00100000		RAM load and test
+#
+
+TEXT_BASE = 0xFE000000
+#TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- a/board/canmb/mt48lc16m32s2-75.h
+++ b/board/canmb/mt48lc16m32s2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
--- a/board/canmb/u-boot.lds
+++ b/board/canmb/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/cm4008/Makefile
+++ b/board/cm4008/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm4008.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cm4008/cm4008.c
+++ b/board/cm4008/cm4008.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM4008 */
+	gd->bd->bi_arch_number = 624;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
--- a/board/cm4008/config.mk
+++ b/board/cm4008/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000
--- a/board/cm4008/flash.c
+++ b/board/cm4008/flash.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
--- a/board/cm4008/u-boot.lds
+++ b/board/cm4008/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/cm41xx/Makefile
+++ b/board/cm41xx/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm41xx.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cm41xx/cm41xx.c
+++ b/board/cm41xx/cm41xx.c
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM41xx */
+	gd->bd->bi_arch_number = 672;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
--- a/board/cm41xx/config.mk
+++ b/board/cm41xx/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000
--- a/board/cm41xx/flash.c
+++ b/board/cm41xx/flash.c
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
--- a/board/cm41xx/u-boot.lds
+++ b/board/cm41xx/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/cmc_pu2/u-boot.lds
+++ b/board/cmc_pu2/u-boot.lds
@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}

--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -140,6 +140,7 @@ SECTIONS
   *(COMMON)
  }

+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
  . = 0xFFFF8000;
  .ppcenv :
  {
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -63,10 +63,56 @@ unsigned char logo_bmp[] =
 */
 #include "../common/lcd.c"

-#include "../common/"CFG_LCD_HEADER_NAME
+#include CFG_LCD_HEADER_NAME
 #endif /* CONFIG_LCD_USED */


+int board_revision(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version <= 1.2 */
+		return 2;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 1.4 */
+		return 4;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 1.5 */
+		return 5;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
 int board_early_init_f (void)
 {
 	/*
@@ -120,8 +166,12 @@ int misc_init_f (void)

 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned short *fpga_ctrl2 =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
 	volatile unsigned char *duart0_mcr =
 		(unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr =
@@ -204,6 +254,11 @@ int misc_init_r (void)
 	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 	udelay(1000); /* wait 1ms */

+	/*
+	 * Write board revision in FPGA
+	 */
+	*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
+
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
@@ -228,8 +283,11 @@ int misc_init_r (void)
 		 logo_bmp, sizeof(logo_bmp));

 	/*
-	 * Enable microcontroller and setup backlight PWM controller
+	 * Reset microcontroller and setup backlight PWM controller
 	 */
+	*fpga_mode |= 0x0014;
+	for (i=0;i<10;i++)
+		udelay(1000);
 	*fpga_mode |= 0x001c;
 	*fuji_lcdbl_pwm = 0x00ff;

@@ -243,6 +301,8 @@ int misc_init_r (void)

 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));

@@ -254,7 +314,8 @@ int checkboard (void)
 		puts(str);
 	}

-	putc ('\n');
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld\n", gd->board_type);

 	/*
 	 * Disable sleep mode in LXT971
--- a/board/esd/apc405/fpgadata.c
+++ b/board/esd/apc405/fpgadata.c
--- a/board/esd/pmc405/fpgadata.c
+++ b/board/esd/pmc405/fpgadata.c
@@ -6,26 +6,26 @@
  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
  0x08,0xea,0x08,0x00,0x00,0x00,0x22,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,
  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x00,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
+  0x00,0x04,0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x00,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x38,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x00,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x2c,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
+  0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00,
  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,0x80,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x00,0x84,0x38,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
  0x09,0x00,0x00,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x8c,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x00,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
-  0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
  0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x00,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
  0x00,0x00,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
@@ -128,34 +128,34 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x04,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x04,0xd0,0x00,0x03,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x05,0x00,0x80,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x05,0x00,0xc0,0x11,0x00,0x00,
  0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x05,0x04,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x05,0x08,0x00,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x0c,0x80,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x05,0x20,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x24,0x04,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x28,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x05,0x2c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x30,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x40,0xa0,0x11,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x05,0x44,0xe8,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
-  0x48,0x40,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x4c,0x80,0x11,0x00,0x00,
+  0x05,0x04,0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x05,0x08,0x40,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x0c,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x10,0x80,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x05,0x20,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x24,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x28,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x05,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x30,
+  0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x40,0x20,0x19,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x05,0x44,0x20,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
+  0x48,0x48,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x4c,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x05,0x50,0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
-  0x00,0x05,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x84,0x04,0x31,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x88,0xc0,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x05,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x90,
+  0x05,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
+  0x00,0x05,0x80,0x00,0x21,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x84,0x00,0x11,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x88,0x80,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x05,0x8c,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x90,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xa0,0x04,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x05,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
-  0xa8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x01,0x00,0x00,
+  0xa8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x11,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x05,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x05,0xc0,0x08,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc4,0x00,0x09,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc8,0x80,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x05,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
+  0x05,0xc0,0xc8,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc4,0x08,0x09,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x05,0xcc,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
  0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,0x03,0x02,0x01,0x00,0x00,0x00,0x00,
  0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x07,
-  0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,
+  0x42,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,
  0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x0f,0x02,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x06,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x06,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x27,0x03,0x01,0x00,
@@ -165,8 +165,8 @@
  0x09,0x00,0x06,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x48,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x50,
-  0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,
-  0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
+  0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,
+  0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
  0x00,0x00,0x00,0x09,0x00,0x06,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
  0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x06,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x90,0x00,0x01,
@@ -175,10 +175,10 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xac,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x06,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc0,
  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc4,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x06,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,
-  0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x06,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,
+  0xcc,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
  0x00,0x00,0x00,0x09,0x00,0x06,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
+  0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
  0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x07,0x02,0x01,
  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x0b,0x02,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x0f,0x02,0x01,0x00,0x00,0x00,0x00,
@@ -207,7 +207,7 @@
  0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x04,0x00,0x01,0x00,0x00,
  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x08,0x00,0x01,0x00,
  0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x0e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x08,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x22,0x01,0x01,
+  0x00,0x08,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x23,0x01,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x08,0x28,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x2e,0x01,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
@@ -258,8 +258,8 @@
  0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x0a,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x10,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x20,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x0a,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x28,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x2e,0x00,0x01,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x0a,0x26,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x28,
+  0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x2c,0x01,0x01,0x00,0x00,0x00,
  0x00,0x01,0x09,0x00,0x0a,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,
  0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x44,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x09,0x00,0x0a,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
@@ -278,13 +278,13 @@
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
  0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0xd0,0x00,
  0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0b,0x00,
-  0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
  0x00,0x00,0x09,0x00,0x0b,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,
  0x00,0x00,0x00,0x09,0x00,0x0b,0x0a,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
  0x0b,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x10,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x20,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x22,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
  0x00,0x0b,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x28,0x01,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x2c,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x2e,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
  0x09,0x00,0x0b,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x40,0x00,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x44,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0b,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x4c,
@@ -327,12 +327,12 @@
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0c,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0c,0xd0,0x00,0x03,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0d,0x03,0x46,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0d,0x03,0x02,0x01,0x00,0x00,
  0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,
  0x0d,0x07,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
  0x00,0x0d,0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x0f,0x02,0x01,
  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x0d,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x27,0x03,
+  0x09,0x00,0x0d,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x27,0x07,
  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0d,0x2f,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x30,
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@@ -340,7 +340,7 @@
  0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x4c,0x00,0x01,0x00,0x00,
  0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
  0x0d,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
-  0x00,0x0d,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x0d,0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x88,0x00,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x0d,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x90,
@@ -354,27 +354,27 @@
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-  0x40,0x11,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,
-  0x08,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x0c,0x80,0x01,0x00,0x00,
+  0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,
+  0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x0c,0x80,0x01,0x00,0x00,
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-  0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x4c,0x80,0x11,0x00,0x00,0x00,0x00,
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-  0x80,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
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-  0xa0,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc4,0xc8,0x11,0x00,0x00,0x00,
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@@ -403,17 +403,17 @@
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@@ -427,31 +427,31 @@
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@@ -493,7 +493,7 @@
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@@ -503,8 +503,8 @@
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@@ -528,55 +528,55 @@
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@@ -593,7 +593,7 @@
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@@ -618,9 +618,9 @@
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@@ -658,16 +658,16 @@
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+  0x00,0x01,0x09,0x00,0x1a,0x90,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
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@@ -1006,7 +1006,7 @@
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-  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x30,0x00,0x11,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x28,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x44,
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@@ -1015,7 +1015,7 @@
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-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x90,0x80,0x01,0x00,0x00,0x00,0x00,
  0x01,0x09,0x00,0x28,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xa4,
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@@ -1023,30 +1023,30 @@
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-  0x00,0x28,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x29,0x00,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x04,0x84,0x31,0x00,0x00,0x00,0x00,
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@@ -1485,8 +1485,8 @@
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@@ -1494,10 +1494,10 @@
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@@ -1520,8 +1520,8 @@
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-  0x00,0x08,0x22,0x01,0x01,0x09,0x00,0x08,0x28,0x01,0x03,0x00,0x08,0x26,0x01,0x01,
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@@ -1562,9 +1562,9 @@
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@@ -1578,14 +1578,14 @@
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@@ -1619,19 +1619,19 @@
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@@ -1641,26 +1641,26 @@
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@@ -1839,8 +1839,8 @@
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@@ -1861,9 +1861,9 @@
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+  0x00,0x18,0xa6,0x00,0x03,0x00,0x18,0xa0,0x00,0x01,0x09,0x00,0x18,0xa8,0x01,0x03,
+  0x00,0x18,0xa6,0x00,0x01,0x09,0x00,0x18,0xac,0x01,0x03,0x00,0x18,0xa8,0x01,0x01,
+  0x09,0x00,0x18,0xb0,0x00,0x03,0x00,0x18,0xac,0x01,0x01,0x09,0x00,0x18,0xc0,0x00,
  0x03,0x00,0x18,0xb0,0x00,0x01,0x09,0x00,0x18,0xc4,0x00,0x03,0x00,0x18,0xc0,0x00,
  0x01,0x09,0x00,0x18,0xc8,0x00,0x03,0x00,0x18,0xc4,0x00,0x01,0x09,0x00,0x18,0xcc,
  0x00,0x03,0x00,0x18,0xc8,0x00,0x01,0x09,0x00,0x18,0xd0,0x00,0x03,0x00,0x18,0xcc,
@@ -1894,15 +1894,15 @@
  0x0c,0x00,0x01,0x09,0x00,0x1a,0x20,0x00,0x13,0x00,0x1a,0x10,0x00,0x01,0x09,0x00,
  0x1a,0x24,0x00,0x13,0x00,0x1a,0x20,0x00,0x11,0x09,0x00,0x1a,0x28,0x00,0x13,0x00,
  0x1a,0x24,0x00,0x11,0x09,0x00,0x1a,0x2c,0x00,0x13,0x00,0x1a,0x28,0x00,0x11,0x09,
-  0x00,0x1a,0x30,0x00,0x03,0x00,0x1a,0x2c,0x00,0x11,0x09,0x00,0x1a,0x40,0x00,0x13,
-  0x00,0x1a,0x30,0x00,0x01,0x09,0x00,0x1a,0x44,0x00,0x13,0x00,0x1a,0x40,0x00,0x11,
+  0x00,0x1a,0x30,0x00,0x13,0x00,0x1a,0x2c,0x00,0x11,0x09,0x00,0x1a,0x40,0x00,0x13,
+  0x00,0x1a,0x30,0x00,0x11,0x09,0x00,0x1a,0x44,0x00,0x13,0x00,0x1a,0x40,0x00,0x11,
  0x09,0x00,0x1a,0x48,0x00,0x13,0x00,0x1a,0x44,0x00,0x11,0x09,0x00,0x1a,0x4c,0x00,
-  0x13,0x00,0x1a,0x48,0x00,0x11,0x09,0x00,0x1a,0x50,0x00,0x03,0x00,0x1a,0x4c,0x00,
-  0x11,0x09,0x00,0x1a,0x82,0x81,0x03,0x00,0x1a,0x50,0x00,0x01,0x09,0x00,0x1a,0x84,
+  0x13,0x00,0x1a,0x48,0x00,0x11,0x09,0x00,0x1a,0x50,0x00,0x13,0x00,0x1a,0x4c,0x00,
+  0x11,0x09,0x00,0x1a,0x82,0x81,0x03,0x00,0x1a,0x50,0x00,0x11,0x09,0x00,0x1a,0x84,
  0x80,0x03,0x00,0x1a,0x82,0x81,0x01,0x09,0x00,0x1a,0x88,0x80,0x03,0x00,0x1a,0x84,
  0x80,0x01,0x09,0x00,0x1a,0x8c,0x80,0x03,0x00,0x1a,0x88,0x80,0x01,0x09,0x00,0x1a,
-  0x90,0x00,0x03,0x00,0x1a,0x8c,0x80,0x01,0x09,0x00,0x1a,0xa0,0x00,0x03,0x00,0x1a,
-  0x90,0x00,0x01,0x09,0x00,0x1a,0xa4,0x00,0x03,0x00,0x1a,0xa0,0x00,0x01,0x09,0x00,
+  0x90,0x80,0x03,0x00,0x1a,0x8c,0x80,0x01,0x09,0x00,0x1a,0xa0,0x00,0x03,0x00,0x1a,
+  0x90,0x80,0x01,0x09,0x00,0x1a,0xa4,0x00,0x03,0x00,0x1a,0xa0,0x00,0x01,0x09,0x00,
  0x1a,0xa8,0x00,0x03,0x00,0x1a,0xa4,0x00,0x01,0x09,0x00,0x1a,0xac,0x00,0x03,0x00,
  0x1a,0xa8,0x00,0x01,0x09,0x00,0x1a,0xb0,0x00,0x03,0x00,0x1a,0xac,0x00,0x01,0x09,
  0x00,0x1a,0xc0,0x00,0x03,0x00,0x1a,0xb0,0x00,0x01,0x09,0x00,0x1a,0xc4,0x00,0x03,
@@ -2183,41 +2183,41 @@
  0x00,0x28,0x20,0x00,0x13,0x00,0x28,0x10,0x00,0x01,0x09,0x00,0x28,0x24,0x00,0x13,
  0x00,0x28,0x20,0x00,0x11,0x09,0x00,0x28,0x28,0x00,0x13,0x00,0x28,0x24,0x00,0x11,
  0x09,0x00,0x28,0x2c,0x00,0x13,0x00,0x28,0x28,0x00,0x11,0x09,0x00,0x28,0x30,0x00,
-  0x03,0x00,0x28,0x2c,0x00,0x11,0x09,0x00,0x28,0x40,0x00,0x03,0x00,0x28,0x30,0x00,
-  0x01,0x09,0x00,0x28,0x44,0x00,0x03,0x00,0x28,0x40,0x00,0x01,0x09,0x00,0x28,0x48,
+  0x13,0x00,0x28,0x2c,0x00,0x11,0x09,0x00,0x28,0x40,0x00,0x03,0x00,0x28,0x30,0x00,
+  0x11,0x09,0x00,0x28,0x44,0x00,0x03,0x00,0x28,0x40,0x00,0x01,0x09,0x00,0x28,0x48,
  0x00,0x03,0x00,0x28,0x44,0x00,0x01,0x09,0x00,0x28,0x4c,0x00,0x03,0x00,0x28,0x48,
  0x00,0x01,0x09,0x00,0x28,0x50,0x00,0x03,0x00,0x28,0x4c,0x00,0x01,0x09,0x00,0x28,
  0x80,0x80,0x03,0x00,0x28,0x50,0x00,0x01,0x09,0x00,0x28,0x84,0x80,0x03,0x00,0x28,
  0x80,0x80,0x01,0x09,0x00,0x28,0x88,0x80,0x03,0x00,0x28,0x84,0x80,0x01,0x09,0x00,
-  0x28,0x8c,0x80,0x03,0x00,0x28,0x88,0x80,0x01,0x09,0x00,0x28,0x90,0x00,0x03,0x00,
-  0x28,0x8c,0x80,0x01,0x09,0x00,0x28,0xa0,0x00,0x03,0x00,0x28,0x90,0x00,0x01,0x09,
+  0x28,0x8c,0x80,0x03,0x00,0x28,0x88,0x80,0x01,0x09,0x00,0x28,0x90,0x80,0x03,0x00,
+  0x28,0x8c,0x80,0x01,0x09,0x00,0x28,0xa0,0x00,0x03,0x00,0x28,0x90,0x80,0x01,0x09,
  0x00,0x28,0xa4,0x00,0x03,0x00,0x28,0xa0,0x00,0x01,0x09,0x00,0x28,0xa8,0x00,0x03,
  0x00,0x28,0xa4,0x00,0x01,0x09,0x00,0x28,0xac,0x00,0x03,0x00,0x28,0xa8,0x00,0x01,
  0x09,0x00,0x28,0xb0,0x00,0x03,0x00,0x28,0xac,0x00,0x01,0x09,0x00,0x28,0xc0,0x00,
  0x13,0x00,0x28,0xb0,0x00,0x01,0x09,0x00,0x28,0xc4,0x00,0x13,0x00,0x28,0xc0,0x00,
  0x11,0x09,0x00,0x28,0xc8,0x00,0x13,0x00,0x28,0xc4,0x00,0x11,0x09,0x00,0x28,0xcc,
-  0x00,0x13,0x00,0x28,0xc8,0x00,0x11,0x09,0x00,0x28,0xd0,0x00,0x03,0x00,0x28,0xcc,
-  0x00,0x11,0x09,0x00,0x29,0x00,0x80,0x33,0x00,0x28,0xd0,0x00,0x01,0x09,0x00,0x29,
-  0x04,0x84,0x33,0x00,0x29,0x00,0x80,0x31,0x09,0x00,0x29,0x08,0xc0,0x03,0x00,0x29,
-  0x04,0x84,0x31,0x09,0x00,0x29,0x0c,0x00,0x03,0x00,0x29,0x08,0xc0,0x01,0x09,0x00,
-  0x29,0x10,0x00,0x03,0x00,0x29,0x0c,0x00,0x01,0x09,0x00,0x29,0x20,0x04,0x13,0x00,
-  0x29,0x10,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x13,0x00,0x29,0x20,0x04,0x11,0x09,
-  0x00,0x29,0x28,0x00,0x13,0x00,0x29,0x24,0x00,0x11,0x09,0x00,0x29,0x2c,0x00,0x03,
-  0x00,0x29,0x28,0x00,0x11,0x09,0x00,0x29,0x30,0x00,0x03,0x00,0x29,0x2c,0x00,0x01,
-  0x09,0x00,0x29,0x40,0xe8,0x1b,0x00,0x29,0x30,0x00,0x01,0x09,0x00,0x29,0x44,0xe8,
-  0x1b,0x00,0x29,0x40,0xe8,0x19,0x09,0x00,0x29,0x48,0xc0,0x13,0x00,0x29,0x44,0xe8,
-  0x19,0x09,0x00,0x29,0x4c,0x00,0x03,0x00,0x29,0x48,0xc0,0x11,0x09,0x00,0x29,0x50,
-  0x80,0x03,0x00,0x29,0x4c,0x00,0x01,0x09,0x00,0x29,0x80,0x00,0x03,0x00,0x29,0x50,
-  0x80,0x01,0x09,0x00,0x29,0x84,0x40,0x03,0x00,0x29,0x80,0x00,0x01,0x09,0x00,0x29,
-  0x88,0x00,0x33,0x00,0x29,0x84,0x40,0x01,0x09,0x00,0x29,0x8c,0x80,0x03,0x00,0x29,
-  0x88,0x00,0x31,0x09,0x00,0x29,0x90,0x00,0x03,0x00,0x29,0x8c,0x80,0x01,0x09,0x00,
-  0x29,0xa0,0x00,0x03,0x00,0x29,0x90,0x00,0x01,0x09,0x00,0x29,0xa4,0x04,0x03,0x00,
-  0x29,0xa0,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x03,0x00,0x29,0xa4,0x04,0x01,0x09,
-  0x00,0x29,0xac,0x00,0x13,0x00,0x29,0xa8,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,0x03,
-  0x00,0x29,0xac,0x00,0x11,0x09,0x00,0x29,0xc0,0x00,0x03,0x00,0x29,0xb0,0x00,0x01,
-  0x09,0x00,0x29,0xc4,0x00,0x03,0x00,0x29,0xc0,0x00,0x01,0x09,0x00,0x29,0xc8,0x00,
-  0x0b,0x00,0x29,0xc4,0x00,0x01,0x09,0x00,0x29,0xcc,0x80,0x13,0x00,0x29,0xc8,0x00,
-  0x09,0x09,0x00,0x29,0xd0,0x00,0x03,0x00,0x29,0xcc,0x80,0x11,0x09,0x00,0x2a,0x00,
+  0x00,0x13,0x00,0x28,0xc8,0x00,0x11,0x09,0x00,0x28,0xd0,0x00,0x13,0x00,0x28,0xcc,
+  0x00,0x11,0x09,0x00,0x29,0x00,0x00,0x03,0x00,0x28,0xd0,0x00,0x11,0x09,0x00,0x29,
+  0x04,0x00,0x03,0x00,0x29,0x00,0x00,0x01,0x09,0x00,0x29,0x08,0x00,0x03,0x00,0x29,
+  0x04,0x00,0x01,0x09,0x00,0x29,0x0c,0x00,0x03,0x00,0x29,0x08,0x00,0x01,0x09,0x00,
+  0x29,0x10,0x00,0x03,0x00,0x29,0x0c,0x00,0x01,0x09,0x00,0x29,0x20,0x00,0x03,0x00,
+  0x29,0x10,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x03,0x00,0x29,0x20,0x00,0x01,0x09,
+  0x00,0x29,0x28,0x00,0x03,0x00,0x29,0x24,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x03,
+  0x00,0x29,0x28,0x00,0x01,0x09,0x00,0x29,0x30,0x00,0x03,0x00,0x29,0x2c,0x00,0x01,
+  0x09,0x00,0x29,0x40,0x00,0x03,0x00,0x29,0x30,0x00,0x01,0x09,0x00,0x29,0x44,0x00,
+  0x03,0x00,0x29,0x40,0x00,0x01,0x09,0x00,0x29,0x48,0x00,0x03,0x00,0x29,0x44,0x00,
+  0x01,0x09,0x00,0x29,0x4c,0x00,0x03,0x00,0x29,0x48,0x00,0x01,0x09,0x00,0x29,0x50,
+  0x00,0x03,0x00,0x29,0x4c,0x00,0x01,0x09,0x00,0x29,0x80,0x00,0x03,0x00,0x29,0x50,
+  0x00,0x01,0x09,0x00,0x29,0x84,0x00,0xc3,0x00,0x29,0x80,0x00,0x01,0x09,0x00,0x29,
+  0x88,0x00,0x03,0x00,0x29,0x84,0x00,0xc1,0x09,0x00,0x29,0x8c,0x00,0x03,0x00,0x29,
+  0x88,0x00,0x01,0x09,0x00,0x29,0x90,0x00,0x03,0x00,0x29,0x8c,0x00,0x01,0x09,0x00,
+  0x29,0xa0,0x00,0x03,0x00,0x29,0x90,0x00,0x01,0x09,0x00,0x29,0xa4,0x80,0xe3,0x00,
+  0x29,0xa0,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x03,0x00,0x29,0xa4,0x80,0xe1,0x09,
+  0x00,0x29,0xac,0x00,0x03,0x00,0x29,0xa8,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,0x03,
+  0x00,0x29,0xac,0x00,0x01,0x09,0x00,0x29,0xc0,0x00,0x03,0x00,0x29,0xb0,0x00,0x01,
+  0x09,0x00,0x29,0xc4,0x00,0x63,0x00,0x29,0xc0,0x00,0x01,0x09,0x00,0x29,0xc8,0x00,
+  0x03,0x00,0x29,0xc4,0x00,0x61,0x09,0x00,0x29,0xcc,0x00,0x03,0x00,0x29,0xc8,0x00,
+  0x01,0x09,0x00,0x29,0xd0,0x00,0x03,0x00,0x29,0xcc,0x00,0x01,0x09,0x00,0x2a,0x00,
  0x00,0x03,0x00,0x29,0xd0,0x00,0x01,0x09,0x00,0x2a,0x04,0x00,0x03,0x00,0x2a,0x00,
  0x00,0x01,0x09,0x00,0x2a,0x08,0x00,0x03,0x00,0x2a,0x04,0x00,0x01,0x09,0x00,0x2a,
  0x0c,0x00,0x03,0x00,0x2a,0x08,0x00,0x01,0x09,0x00,0x2a,0x10,0x00,0x03,0x00,0x2a,
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
@@ -629,6 +629,7 @@ static void gt_setup_ide (struct pci_controller *hose,
 	}
 }

+#ifndef CONFIG_P3G4
 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 {
 	unsigned char pin, irq;
@@ -642,6 +643,7 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
 	}
 }
+#endif

 struct pci_config_table gt_config_table[] = {
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
@@ -651,12 +653,16 @@ struct pci_config_table gt_config_table[] = {
 };

 struct pci_controller pci0_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };

 struct pci_controller pci1_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };

@@ -692,8 +698,10 @@ void pci_init_board (void)

 	pci_register_hose (&pci0_hose);

+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST0);
 	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+#endif

 	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;
@@ -735,8 +743,10 @@ void pci_init_board (void)

 	pci_register_hose (&pci1_hose);

+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST1);
 	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+#endif

 	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;
--- a/board/funkwerk/vovpn-gw/Makefile
+++ b/board/funkwerk/vovpn-gw/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o m88e6060.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/funkwerk/vovpn-gw/config.mk
+++ b/board/funkwerk/vovpn-gw/config.mk
@@ -0,0 +1,21 @@
+# (C) Copyright 2004
+# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+#
+# Support for the Elmeg VoVPN Gateway Module
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+TEXT_BASE = 0xfff00000
--- a/board/funkwerk/vovpn-gw/flash.c
+++ b/board/funkwerk/vovpn-gw/flash.c
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
+ * and 28F128J3A flashs working in 8 Bit mode.
+ *
+ * Most of this code is taken from existing u-boot source code.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t				flash_info[CFG_MAX_FLASH_BANKS];
+
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xd0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_SUSPEND_ERASE		0xb0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_WRITE_BUFF		0xe8
+#define FLASH_CMD_PROG_RESUME		0xd0
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xd0
+#define FLASH_STATUS_DONE		0x80
+
+#define FLASH_WRITE_BUFFER_SIZE		32
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE			unsigned short
+#define FLASH_ID_MASK			0xffff
+#define FLASH_CMD_ADDR_SHIFT		0
+#else
+#define FLASH_WORD_SIZE			unsigned char
+#define FLASH_ID_MASK			0xff
+/* A0 is not used in either 8x or 16x for READ ID */
+#define FLASH_CMD_ADDR_SHIFT		1
+#endif
+
+
+static unsigned long
+flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	volatile FLASH_WORD_SIZE *p;
+	FLASH_WORD_SIZE value;
+	int i;
+
+	addr[0] = FLASH_CMD_READ_ID;
+
+	/* manufactor */
+	value = addr[0 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+
+	}
+
+	/* device */
+	value = addr[1 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+	}
+
+	/* setup sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count);
+	}
+
+	/* check protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		p = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1;
+	}
+
+	/* reset bank */
+	*addr = FLASH_CMD_RESET;
+	return (info->size);
+}
+
+unsigned long
+flash_init(void)
+{
+	unsigned long	size;
+	int		i;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+	size = flash_get((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH Size=0x%08lx\n", size);
+		return (0);
+	}
+
+	/* always protect 1 sector containing the HRCW */
+	flash_protect(FLAG_PROTECT_SET,
+		      flash_info[0].start[0],
+		      flash_info[0].start[1] - 1,
+		      &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_FLASH,
+		      CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+#ifdef	CFG_ENV_IS_IN_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+void
+flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320JA3 (32 Mbit)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640JA3 (64 Mbit)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128JA3 (128 Mbit)\n");
+				break;
+	default:		printf ("Unknown Chip Type");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long start, now, last;
+	int flag, prot, sect;
+	volatile FLASH_WORD_SIZE *addr;
+	FLASH_WORD_SIZE status;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return (1);
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Cannot erase unknown flash - aborted\n");
+		return (1);
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect]) {
+			continue;
+		}
+
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+#ifdef DEBUG
+		printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+		*addr = FLASH_CMD_CLEAR_STATUS;
+		*addr = FLASH_CMD_BLOCK_ERASE;
+		*addr = FLASH_CMD_ERASE_CONFIRM;
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+			if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf("Flash erase timeout at address %lx\n", info->start[sect]);
+				*addr = FLASH_CMD_SUSPEND_ERASE;
+				*addr = FLASH_CMD_RESET;
+				return (1);
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		*addr = FLASH_CMD_RESET;
+	}
+	printf (" done\n");
+	return (0);
+}
+
+static int
+write_buff2( volatile FLASH_WORD_SIZE *dst,
+	     volatile FLASH_WORD_SIZE *src,
+	     unsigned long cnt )
+{
+	unsigned long start;
+	FLASH_WORD_SIZE status;
+	int flag, i;
+
+	start = get_timer (0);
+	while (1) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		dst[0] = FLASH_CMD_WRITE_BUFF;
+		if ((status = *dst) & FLASH_STATUS_DONE) {
+			break;
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (-1);
+		}
+	}
+	dst[0] = (FLASH_WORD_SIZE)(cnt - 1);
+	for (i=0; i<cnt; i++) {
+		dst[i] = src[i];
+	}
+	dst[0] = FLASH_CMD_PROG_RESUME;
+
+	if (flag) {
+		enable_interrupts();
+	}
+
+	return( 0 );
+}
+
+static int
+poll_status( volatile FLASH_WORD_SIZE *addr )
+{
+	unsigned long start;
+
+	start = get_timer (0);
+	/* wait for error or finish */
+	while (1) {
+		if (*addr == FLASH_STATUS_DONE) {
+			if (*addr == FLASH_STATUS_DONE) {
+				break;
+			}
+		}
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = FLASH_CMD_RESET;
+			return (-1);
+		}
+	}
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*
+ * write_buff return values:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int
+write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt)
+{
+	volatile FLASH_WORD_SIZE *addr, *dst;
+	unsigned long bcnt;
+	int flag, i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return (4);
+	}
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+	dst = (volatile FLASH_WORD_SIZE *) udst;
+
+#ifdef CFG_FLASH_16BIT
+#error NYI
+#else
+	while (cnt > 0) {
+		/* Check if buffer write is possible */
+		if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) {
+			bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt;
+			/* Check if Flash is (sufficiently) erased */
+			for (i=0; i<bcnt; i++) {
+				if ((dst[i] & src[i]) != src[i]) {
+					return (2);
+				}
+			}
+			if (write_buff2( dst,src,bcnt ) != 0) {
+				addr[0] = FLASH_CMD_READ_STATUS;
+			}
+			if (poll_status( dst ) != 0) {
+				return (1);
+			}
+			cnt -= bcnt;
+			dst += bcnt;
+			src += bcnt;
+			continue;
+		}
+
+		/* Check if Flash is (sufficiently) erased */
+		if ((*dst & *src) != *src) {
+			return (2);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		addr[0] = FLASH_CMD_ERASE_CONFIRM;
+		addr[0] = FLASH_CMD_WRITE;
+		*dst++ = *src++;
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (poll_status( dst ) != 0) {
+			return (1);
+		}
+		cnt --;
+	}
+#endif
+	return (0);
+}
+
+int
+flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	volatile FLASH_WORD_SIZE *addr;
+	unsigned long start;
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]);
+	*addr = FLASH_CMD_CLEAR_STATUS;
+	*addr = FLASH_CMD_PROTECT;
+
+	if(prot) {
+		*addr = FLASH_CMD_PROTECT_SET;
+	} else {
+		*addr = FLASH_CMD_PROTECT_CLEAR;
+	}
+
+	/* wait for error or finish */
+	start = get_timer (0);
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+
+	/* Set software protect flag */
+	info->protect[sector] = prot;
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Support for flash file system (JFFS2)
+ *
+ * We use custom partition info function because we have to fit the
+ * file system image between first sector (containing hard reset
+ * configuration word) and the sector containing U-Boot image. Standard
+ * partition info function does not allow for last sector specification
+ * and assumes that the file system occupies flash bank up to and
+ * including bank's last sector.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
+#error TODO
+
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK 0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS 1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+#include <jffs2/jffs2.h>
+
+static struct part_info partition;
+
+struct part_info *jffs2_part_info(int part_num)
+{
+	int i;
+
+	if (part_num == 0) {
+		if (partition.usr_priv == 0) {
+			partition.offset =
+				(unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
+			for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
+				partition.size += flash_info[i].size;
+			partition.size -=
+				flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
+				flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#ifdef CFG_JFFS2_LAST_SECTOR
+			i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
+			partition.size -=
+				flash_info[CFG_JFFS2_LAST_BANK].start[i] -
+				flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
+#endif
+
+			partition.usr_priv = (void *)1;
+		}
+		return &partition;
+	}
+	return 0;
+}
+
+#endif /* JFFS2 */
--- a/board/funkwerk/vovpn-gw/m88e6060.c
+++ b/board/funkwerk/vovpn-gw/m88e6060.c
@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+static int		prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
+static int		phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
+
+static m88x_regCfg_t	prtCfg0[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001e },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg1[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001d },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg2[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001b },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg3[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x0017 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg4[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x000f },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*prtCfg[M88X_PRT_CNT] = {
+	prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
+};
+
+static m88x_regCfg_t	phyCfgX[] = {
+	{  4, 0xfa1f, 0x01e0 },
+	{  0, 0x213f, 0x1200 },
+	{ 24, 0x81ff, 0x1200 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*phyCfg[M88X_PHY_CNT] = {
+	phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
+};
+
+#if 0
+static void
+m88e6060_dump( int devAddr )
+{
+	int		i, j;
+	unsigned short	val[6];
+
+	printf( "M88E6060 Register Dump\n" );
+	printf( "====================================\n" );
+	printf( "PortNo    0    1    2    3    4    5\n" );
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
+	printf( "STAT   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
+	printf( "ID     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
+	printf( "CNTL   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
+	printf( "VLAN   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
+	printf( "PAV    %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
+	printf( "RX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
+	printf( "TX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	printf( "------------------------------------\n" );
+	printf( "PhyNo     0    1    2    3    4\n" );
+	for (i=0; i<9; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+	for (i=0x10; i<0x1d; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+}
+#endif
+
+int
+m88e6060_initialize( int devAddr )
+{
+	static char	*_f = "m88e6060_initialize:";
+	m88x_regCfg_t	*p;
+	int		err;
+	int		i;
+	unsigned short	val;
+
+	/*** reset all phys into powerdown ************************************/
+	for (i=0, err=0; i<M88X_PHY_CNT; i++) {
+		err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val );
+		/* keep SpeedLSB, Duplex */
+		val &= 0x2100;
+		/* set SWReset, AnegEn, PwrDwn, RestartAneg */
+		val |= 0x9a00;
+		err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] reset phys\n",_f );
+		return( -1 );
+	}
+
+	/*** disable all ports ************************************************/
+	for (i=0, err=0; i<M88X_PRT_CNT; i++) {
+		err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val );
+		val &= 0xfffc;
+		err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] disable ports\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize switch ************************************************/
+	/* set switch mac addr */
+#define ea eth_get_dev()->enetaddr
+	val = (ea[4] <<  8) | ea[5];
+	err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val );
+	val = (ea[2] <<  8) | ea[3];
+	err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val );
+	val = (ea[0] <<  8) | ea[1];
+#undef ea
+	val &= 0xfeff;		/* clear DiffAddr */
+	err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val );
+	if (err) {
+		printf( "%s [ERR] switch mac address register\n",_f );
+		return( -1 );
+	}
+
+	/* !DiscardExcessive, MaxFrameSize, CtrMode */
+	err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val );
+	val &= 0xd870;
+	val |= 0x0500;
+	err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] switch global control register\n",_f );
+		return( -1 );
+	}
+
+	/* LernDis off, ATUSize 1024, AgeTime 5min */
+	err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val );
+	val &= 0x000f;
+	val |= 0x2130;
+	err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] atu control register\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize ports *************************************************/
+	for (i=0; i<M88X_PRT_CNT; i++) {
+		if ((p = prtCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += miiphy_read( devAddr+prtTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += miiphy_write( devAddr+prtTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+
+	/*** initialize phys **************************************************/
+	for (i=0; i<M88X_PHY_CNT; i++) {
+		if ((p = phyCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += miiphy_read( devAddr+phyTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += miiphy_write( devAddr+phyTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+	udelay(100000);
+	return( 0 );
+}
+#endif
--- a/board/funkwerk/vovpn-gw/m88e6060.h
+++ b/board/funkwerk/vovpn-gw/m88e6060.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _INC_m88e6060_h_
+#define _INC_m88e6060_h_
+
+/* ************************************************************************** */
+/* *** DEFINES ************************************************************** */
+
+/* switch hw */
+#define M88X_PRT_CNT			6
+#define M88X_PHY_CNT			5
+
+/* phy register offsets */
+#define M88X_PHY_CNTL			0x00
+#define M88X_PHY_STAT			0x00
+#define M88X_PHY_ID0			0x02
+#define M88X_PHY_ID1			0x03
+#define M88X_PHY_ANEG_ADV		0x04
+#define M88X_PHY_LPA			0x05
+#define M88X_PHY_ANEG_EXP		0x06
+#define M88X_PHY_NPT			0x07
+#define M88X_PHY_LPNP			0x08
+
+/* port register offsets */
+#define M88X_PRT_STAT			0x00
+#define M88X_PRT_ID			0x03
+#define M88X_PRT_CNTL			0x04
+#define M88X_PRT_VLAN			0x06
+#define M88X_PRT_PAV			0x0b
+#define M88X_PRT_RX			0x10
+#define M88X_PRT_TX			0x11
+
+/* global/atu register offsets */
+#define M88X_GLB_STAT			0x00
+#define M88X_GLB_MAC01			0x01
+#define M88X_GLB_MAC23			0x02
+#define M88X_GLB_MAC45			0x03
+#define M88X_GLB_CNTL			0x04
+#define M88X_ATU_CNTL			0x0a
+#define M88X_ATU_OP			0x0b
+
+/* id0 register - 0x02 */
+#define M88X_PHY_ID0_VALUE		0x0141
+
+/* id1 register - 0x03 */
+#define M88X_PHY_ID1_VALUE		0x0c80		/* without revision ! */
+
+
+/* misc */
+#define M88E6060_ID		((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
+
+/* ************************************************************************** */
+/* *** TYPEDEFS ************************************************************* */
+
+typedef struct {
+	int		reg;
+	unsigned short	msk;
+	unsigned short	val;
+} m88x_regCfg_t;
+
+/* ************************************************************************** */
+/* *** PROTOTYPES *********************************************************** */
+
+extern int		m88e6060_initialize( int );
+
+#endif	/* _INC_m88e6060_h_ */
--- a/board/funkwerk/vovpn-gw/u-boot.lds
+++ b/board/funkwerk/vovpn-gw/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
--- a/board/funkwerk/vovpn-gw/vovpn-gw.c
+++ b/board/funkwerk/vovpn-gw/vovpn-gw.c
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A configuration */
+    {	/*	     conf ppar psor pdir podr pdat */
+	/* PA31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1252           */
+	/* PA30 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    BP_RES           */
+	/* PA29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1253           */
+	/* PA28 */ { 1,   1,   1,   1,   0,   0 }, /* FCC1   RMII TX_EN       */
+	/* PA27 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII CRS_DV      */
+	/* PA26 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII RX_ERR      */
+	/* PA25 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA24 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA23 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA22 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA21 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA20 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    LED STATUS       */
+	/* PA19 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[1]      */
+	/* PA18 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[0]      */
+	/* PA17 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[0]      */
+	/* PA16 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[1]      */
+	/* PA15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1255           */
+	/* PA14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP????           */
+	/* PA13 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    EN_BCTL1 XXX jse */
+	/* PA12 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    SWITCH RESET     */
+	/* PA11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL1 RESET    */
+	/* PA10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL2 RESET    */
+	/* PA9  */ { 1,   1,   0,   1,   0,   0 }, /* SMC2   TXD              */
+	/* PA8  */ { 1,   1,   0,   0,   0,   0 }, /* SMC2   RXD              */
+	/* PA7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exit       */
+    },
+
+    /* Port B configuration */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PB31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1257           */
+	/* PB30 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII CRS_DV      */
+	/* PB29 */ { 1,   1,   1,   1,   0,   0 }, /* FCC2   RMII TX_EN       */
+	/* PB28 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RX_ERR      */
+	/* PB27 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1TXD XXX val=0  */
+	/* PB26 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1RXD XXX val,dr */
+	/* PB25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1259           */
+	/* PB24 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_B2 L1RSYNC          */
+	/* PB23 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[1]      */
+	/* PB22 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[0]      */
+	/* PB21 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[0]      */
+	/* PB20 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[1]      */
+	/* PB19 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    PHY MDC          */
+	/* PB18 */ { 1,   0,   0,   0,   0,   0 }, /* GPIO   PHY MDIO         */
+	/* PB17 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB16 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB15 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB14 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    },
+
+    /* Port C */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PC31 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC30 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1183           */
+	/* PC28 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1184           */
+	/* PC27 */ { 1,   1,   0,   0,   0,   0 }, /* CLK5   TDM_A1 RX        */
+	/* PC26 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1185           */
+	/* PC25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1178           */
+	/* PC24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1186           */
+	/* PC23 */ { 1,   1,   0,   0,   0,   0 }, /* CLK9   TDM_B2 RX        */
+	/* PC22 */ { 1,   1,   0,   0,   0,   0 }, /* CLK10  FCC1 RMII REFCLK */
+	/* PC21 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1187           */
+	/* PC20 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1182           */
+	/* PC19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1188           */
+	/* PC18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    HW RESET         */
+	/* PC17 */ { 1,   1,   0,   1,   0,   0 }, /* BRG8   SWITCH CLKIN     */
+	/* PC16 */ { 1,   1,   0,   0,   0,   0 }, /* CLK16  FCC2 RMII REFCLK */
+	/* PC15 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_3      */
+	/* PC14 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_2      */
+	/* PC13 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_1      */
+	/* PC12 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_0      */
+	/* PC11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1176           */
+	/* PC10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1177           */
+	/* PC9  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_3      */
+	/* PC8  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_2      */
+	/* PC7  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_1      */
+	/* PC6  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_0      */
+	/* PC5  */ { 1,   1,   0,   1,   0,   0 }, /* SMC1   TXD              */
+	/* PC4  */ { 1,   1,   0,   0,   0,   0 }, /* SMC1   RXD              */
+	/* PC3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC1  */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1192           */
+	/* PC0  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    RACK             */
+    },
+
+    /* Port D */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PD31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1193           */
+	/* PD30 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1194           */
+	/* PD29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1195           */
+	/* PD28 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD27 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD26 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1179           */
+	/* PD24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1180           */
+	/* PD23 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1181           */
+	/* PD22 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1TXD            */
+	/* PD21 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1RXD            */
+	/* PD20 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_A2 L1RSYNC          */
+	/* PD19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1196           */
+	/* PD18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1197           */
+	/* PD17 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1198           */
+	/* PD16 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1199           */
+	/* PD15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1250           */
+	/* PD14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1251           */
+	/* PD13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD7  */ { 0,   0,   0,   1,   0,   0 }, /* GPO    FL_BYTE          */
+	/* PD6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    }
+};
+
+void reset_phy (void)
+{
+	volatile ioport_t *iop;
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	int i;
+	unsigned short val;
+#endif
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+
+	/* Reset the PHY */
+	iop->pdat &= 0xfff7ffff;	/* PA12 = |SWITCH_RESET */
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	udelay(20000);
+	iop->pdat |= 0x00080000;
+	for (i=0; i<100; i++) {
+		udelay(20000);
+		if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) {
+			break;
+		}
+	}
+	/* initialize switch */
+	m88e6060_initialize( CFG_PHY_ADDR );
+#endif
+}
+
+static unsigned long UPMATable[] = {
+	0x8fffec00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, //Words 0 to 3
+	0x0ffcfc04,  0x3ffdfc00,  0xfffffc01,  0xfffffc01, //Words 4 to 7
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, //Words 8 to 11
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 12 to 15
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 16 to 19
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 20 to 23
+	0x8fffec00,  0x00fffc00,  0x00fffc00,  0x00fffc00, //Words 24 to 27
+	0x0ffffc04,  0xfffffc01,  0xfffffc01,  0xfffffc01, //Words 28 to 31
+	0xfffffc00,  0xfffffc01,  0xfffffc01,  0xfffffc00, //Words 32 to 35
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 36 to 39
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 40 to 43
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 44 to 47
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, //Words 48 to 51
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 52 to 55
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 56 to 59
+	0xffffec00,  0xffffec04,  0xffffec00,  0xfffffc01  //Words 60 to 63
+};
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+#if 0
+	/* CS2-5 - DSP via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#else
+	/* CS7 - DPRAM via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	volatile ioport_t *iop;
+	unsigned char temp;
+#if 0
+	/* DUMP UPMA RAM */
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	unsigned char c;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_RARR;
+	for (i = 0; i < 64; i++) {
+		c = *dummy;
+		printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
+		        memctl->memc_mamr,
+		        memctl->memc_mar,
+		        memctl->memc_mdr );
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	/* enable buffers (DSP, DPRAM) */
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+	iop->pdat &= 0xfffbffff;	/* PA13 = |EN_M_BCTL1 */
+
+	/* destroy DPRAM magic */
+	*(volatile unsigned char *)0xf0500000 = 0x00;
+
+	/* clear any pending DPRAM irq */
+	temp = *(volatile unsigned char *)0xf05003ff;
+
+	/* write module-id into DPRAM */
+	*(volatile unsigned char *)0xf0500201 = 0x50;
+
+	return 0;
+}
+
+#if defined(CONFIG_HAVE_OWN_RESET)
+int
+do_reset (void *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile ioport_t *iop;
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 2);
+	iop->pdat |= 0x00002000;	/* PC18 = HW_RESET */
+	return 1;
+}
+#endif	/* CONFIG_HAVE_OWN_RESET */
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile uchar *ramaddr;
+	int i;
+	uchar c;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+	ramaddr = (uchar *) CFG_SDRAM_BASE;
+	c = 0xff;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
+	immap->im_siu_conf.sc_tescr1   = 0x00000000;
+	immap->im_siu_conf.sc_tescr2   = 0x00000000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM;
+
+	/* Precharge all banks */
+	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	*ramaddr = c;
+
+	/* CBR refresh */
+	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	/* Mode Register write */
+	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	*ramaddr = c;
+
+	/* Refresh enable */
+	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+	*ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+	return (CFG_SDRAM_SIZE);
+}
+
+int checkboard (void)
+{
+#ifdef CONFIG_CLKIN_66MHz
+	puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
+#else
+	puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
+#endif
+	return 0;
+}
--- a/board/hmi1001/Makefile
+++ b/board/hmi1001/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/hmi1001/config.mk
+++ b/board/hmi1001/config.mk
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# INKA 4X0 board:
+#
+#	Valid values for TEXT_BASE are:
+#
+#	0xFFE00000   boot high
+#
+#	0x00100000   boot from RAM (for testing only)
+#
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+#TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- a/board/hmi1001/hmi1001.c
+++ b/board/hmi1001/hmi1001.c
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+/*	return dramsize + dramsize2; */
+	return dramsize;
+}
+
+int checkboard (void)
+{
+	puts ("Board: HMI1001\n");
+	return 0;
+}
+
+int misc_init_f (void)
+{
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}
--- a/board/hmi1001/u-boot.lds
+++ b/board/hmi1001/u-boot.lds
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the sector layout of our flash chips!    XXX FIXME XXX   */
+
+    cpu/mpc5xxx/start.o          (.text)
+    cpu/mpc5xxx/traps.o          (.text)
+    lib_generic/crc32.o         (.text)
+    lib_ppc/cache.o             (.text)
+    lib_ppc/time.o              (.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o        (.ppcenv)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -133,10 +133,13 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

 	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize2 = test1;
--- a/board/ids8247/Makefile
+++ b/board/ids8247/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/ids8247/config.mk
+++ b/board/ids8247/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2005
+# Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IDS 8247 Board
+#
+
+# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
--- a/board/ids8247/flash.c
+++ b/board/ids8247/flash.c
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH8
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#elif FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#else /* FLASH_PORT_WIDTH8 */
+#define FLASH_PORT_WIDTH	uchar
+#define FLASH_PORT_WIDTHV	vu_char
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0;
+	int i;
+	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immr->im_memctl;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	memctl->memc_or0 = 0xff800060;
+	memctl->memc_br0 = 0xff800801;
+
+	flash_get_offsets (0xff800000, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	FPW value;
+
+	addr[0] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+#ifdef FLASH_PORT_WIDTH8
+	value = addr[2];			/* device ID        */
+#else
+	value = addr[1];			/* device ID        */
+#endif
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#elif defined(FLASH_PORT_WIDTH32)
+	wp = (addr & ~3);
+	port_width = 4;
+#else
+	wp = addr;
+	port_width = 1;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
+	/* PA30 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
+	/* PA29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
+	/* PA28 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
+	/* PA27 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
+	/* PA26 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
+	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
+	/* PA23 */ {   1,   0,	 0,   1,   1,	1   }, /* I2C_SCL2 */
+#else /* normal I/O port pins */
+	/* PA24 */ {   0,   0,	 0,   1,   0,	0   }, /* PA24 */
+	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
+#endif
+	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
+	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
+	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
+	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
+	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
+	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
+	/* PA10 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DSR */
+	/* PA9	*/ {   0,   1,	 0,   1,   0,	0   }, /* SMC2 TXD */
+	/* PA8	*/ {   0,   1,	 0,   0,   0,	0   }, /* SMC2 RXD */
+	/* PA7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA7 */
+	/* PA6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA6 */
+	/* PA5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA5 */
+	/* PA4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA4 */
+	/* PA3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA3 */
+	/* PA2	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA2 */
+	/* PA1	*/ {   0,   0,	 0,   1,   0,	0   }, /* PA1 */
+	/* PA0	*/ {   0,   0,	 0,   1,   0,	0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
+	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
+	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
+	/* PB14 */ {   0,   0,	 0,   0,   0,	0   }, /* PB14 */
+	/* PB13 */ {   0,   0,	 0,   0,   0,	0   }, /* PB13 */
+	/* PB12 */ {   0,   0,	 0,   0,   0,	0   }, /* PB12 */
+	/* PB11 */ {   0,   0,	 0,   0,   0,	0   }, /* PB11 */
+	/* PB10 */ {   0,   0,	 0,   0,   0,	0   }, /* PB10 */
+	/* PB9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB9 */
+	/* PB8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB8 */
+	/* PB7	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB7 */
+	/* PB6	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB6 */
+	/* PB5	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB5 */
+	/* PB4	*/ {   0,   0,	 0,   0,   0,	0   }, /* PB4 */
+	/* PB3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PB0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,	 0,   1,   0,	0   }, /* PC31 */
+	/* PC30 */ {   0,   0,	 0,   1,   0,	0   }, /* PC30 */
+	/* PC29 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_OUT */
+	/* PC27 */ {   0,   0,	 0,   1,   0,	0   }, /* PC27 */
+	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
+	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
+	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
+	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,	 0,   1,   0,	0   }, /* PC17 */
+	/* PC16 */ {   0,   0,	 0,   1,   0,	0   }, /* PC16 */
+	/* PC15 */ {   0,   0,	 0,   1,   0,	0   }, /* PC15 */
+	/* PC14 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,	 0,   1,   0,	0   }, /* PC13 */
+	/* PC12 */ {   0,   0,	 0,   1,   0,	0   }, /* PC12 */
+	/* PC11 */ {   0,   0,	 0,   1,   0,	0   }, /* PC11 */
+	/* PC10 */ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDC */
+	/* PC9	*/ {   0,   0,	 0,   1,   0,	0   }, /* FCC2 MDIO */
+	/* PC8	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC8 */
+	/* PC7	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC7 */
+	/* PC6	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC6 */
+	/* PC5	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC5 */
+	/* PC4	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC4 */
+	/* PC3	*/ {   0,   0,	 0,   1,   0,	0   }, /* PC3 */
+	/* PC2	*/ {   0,   0,	 0,   1,   0,	1   }, /* ENET FDE */
+	/* PC1	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET DSQE */
+	/* PC0	*/ {   0,   0,	 0,   1,   0,	0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   0,   1,	 1,   1,   0,	0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,	 0,   1,   0,	0   }, /* PD28 */
+	/* PD27 */ {   0,   0,	 0,   1,   0,	0   }, /* PD27 */
+	/* PD26 */ {   0,   0,	 0,   1,   0,	0   }, /* PD26 */
+	/* PD25 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC3_RX */
+	/* PD24 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_TX */
+	/* PD23 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC3_RTS */
+	/* PD22 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC4_RXD */
+	/* PD21 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_TXD */
+	/* PD20 */ {   0,   1,	 0,   1,   0,	0   }, /* SCC4_RTS */
+	/* PD19 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_SEL */
+	/* PD18 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_CLK */
+	/* PD17 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MOSI */
+	/* PD16 */ {   0,   1,	 1,   0,   0,	0   }, /* SPI_MISO */
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SDA1 */
+	/* PD14 */ {   1,   1,	 1,   0,   1,	0   }, /* I2C SCL1 */
+#else /* normal I/O port pins */
+	/* PD15 */ {   0,   1,	 1,   0,   1,	0   }, /* PD15 */
+	/* PD14 */ {   0,   1,	 1,   0,   1,	0   }, /* PD14 */
+#endif
+	/* PD13 */ {   0,   0,	 0,   0,   0,	0   }, /* PD13 */
+	/* PD12 */ {   0,   0,	 0,   0,   0,	0   }, /* PD12 */
+	/* PD11 */ {   0,   0,	 0,   0,   0,	0   }, /* PD11 */
+	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
+	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
+	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
+	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
+	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
+	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
+	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
+	/* PD3	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD2	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD1	*/ {   0,   0,	 0,   0,   0,	0   }, /* pin doesn't exist */
+	/* PD0	*/ {   0,   0,	 0,   0,   0,	0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	puts ("Board: IDS 8247\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+						  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+	long psize, lsize;
+
+	psize = 16 * 1024 * 1024;
+	lsize = 0;
+
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	psize = try_init (memctl, CFG_PSDMR, CFG_OR2,
+						  (uchar *) CFG_SDRAM_BASE);
+#endif /* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+int misc_init_r (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_flashstart = 0xff800000;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong
+nand_probe (ulong physadr);
+
+void
+nand_init (void)
+{
+	ulong totlen = 0;
+
+	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
+	totlen += nand_probe (CFG_NAND0_BASE);
+
+	printf ("%4lu MB\n", totlen >>20);
+}
+
+#endif	/* CFG_CMD_NAND */
--- a/board/ids8247/u-boot.lds
+++ b/board/ids8247/u-boot.lds
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/inka4x0/inka4x0.c
+++ b/board/inka4x0/inka4x0.c
@@ -173,6 +173,7 @@ void flash_preinit(void)
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 }

+#define GPIO_WKUP_7	0x80000000UL
 #define GPIO_PSC3_9	0x04000000UL

 int misc_init_f (void)
@@ -189,13 +190,13 @@ int misc_init_f (void)

 	/* Initialize GPIO output pins.
 	 */
-	/* Configure GPT as GPIO output */
+	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
 	*(vu_long *)MPC5XXX_GPT0_ENABLE =
 	*(vu_long *)MPC5XXX_GPT1_ENABLE =
 	*(vu_long *)MPC5XXX_GPT2_ENABLE =
 	*(vu_long *)MPC5XXX_GPT3_ENABLE =
 	*(vu_long *)MPC5XXX_GPT4_ENABLE =
-	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24;
+	*(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;

 	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
 	*(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
@@ -216,6 +217,8 @@ int misc_init_f (void)
 	*(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
 	*(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;

+	/* Set LR mirror bit because it is low-active */
+	*(vu_long *)MPC5XXX_WU_GPIO_DATA    |= GPIO_WKUP_7;
 	/*
 	 * Reset Coral-P graphics controller
 	 */
--- a/board/ocotea/config.mk
+++ b/board/ocotea/config.mk
@@ -30,7 +30,7 @@
 ifeq ($(ramsym),1)
 TEXT_BASE = 0x07FD0000
 else
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFC0000
 endif

 PLATFORM_CPPFLAGS += -DCONFIG_440=1
--- a/board/ocotea/flash.c
+++ b/board/ocotea/flash.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2004
+ * (C) Copyright 2004-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
@@ -43,7 +43,9 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */

-#define     BOOT_SMALL_FLASH        32	/* 00100000 */
+#define     BOOT_SMALL_FLASH        0x40 /* 01000000 */
+#define     FLASH_ONBD_N            2	/* 00000010 */
+#define     FLASH_SRAM_SEL          1	/* 00000001 */
 #define     FLASH_ONBD_N            2	/* 00000010 */
 #define     FLASH_SRAM_SEL          1	/* 00000001 */

@@ -55,8 +57,8 @@
 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */

 static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
-	{0xFF800000, 0xFF900000, 0xFFC00000},	/* 0:000: configuraton 4 */
-	{0xFF900000, 0xFF800000, 0xFFC00000},	/* 1:001: configuraton 3 */
+	{0xFF800000, 0xFF880000, 0xFFC00000},	/* 0:000: configuraton 4 */
+	{0xFF900000, 0xFF980000, 0xFFC00000},	/* 1:001: configuraton 3 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 3:011: configuraton 7 */
 	{0xFFE00000, 0xFFF00000, 0xFF800000},	/* 4:100: configuraton 2 */
@@ -131,6 +133,12 @@ unsigned long flash_init(void)
 		total_b += flash_info[i].size;
 	}

+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[2]);
+
 	return total_b;
 }

@@ -153,6 +161,9 @@ void flash_print_info(flash_info_t * info)
 	case FLASH_MAN_AMD:
 		printf("AMD ");
 		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
 	case FLASH_MAN_FUJ:
 		printf("FUJITSU ");
 		break;
@@ -300,6 +311,11 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
+	case (FLASH_WORD_SIZE) STM_ID_M29W040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;	/* => 512 ko */
+		break;
 	case (FLASH_WORD_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
@@ -312,8 +328,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)

 	/* set up sector start address table */
 	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040) ||
-	    (info->flash_id == FLASH_AMD016)) {
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
 		for (i = 0; i < info->sector_count; i++)
 			info->start[i] = base + (i * 0x00010000);
 	} else {
@@ -343,6 +359,15 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 		addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
+
+		/* For AMD29033C flash we need to resend the command of	*
+		 * reading flash protection for upper 8 Mb of flash	*/
+		if ( i == 32 ) {
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
+			addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
+		}
+
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
 		else
@@ -432,7 +457,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-			printf("Erasing sector %p\n", addr2);

 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
 				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
--- a/board/ocotea/ocotea.c
+++ b/board/ocotea/ocotea.c
@@ -37,6 +37,15 @@ void fpga_init (void);
 int board_early_init_f (void)
 {
 	unsigned long mfr;
+	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char switch_status;
+	unsigned long cs0_base;
+	unsigned long cs0_size;
+	unsigned long cs0_twt;
+	unsigned long cs2_base;
+	unsigned long cs2_size;
+	unsigned long cs2_twt;
+
 	/*-------------------------------------------------------------------------+
 	  | Initialize EBC CONFIG
 	  +-------------------------------------------------------------------------*/
@@ -47,17 +56,49 @@ int board_early_init_f (void)
 	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

 	/*-------------------------------------------------------------------------+
-	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  | FPGA. Initialize bank 7 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
+	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
-	      EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
+	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+
+	/* read FPGA base register FPGA_REG0 */
+	switch_status = *fpga_base;
+
+	if (switch_status & 0x40) {
+		cs0_base = 0xFFE00000;
+		cs0_size = EBC_BXCR_BS_2MB;
+		cs0_twt = 8;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_4MB;
+		cs2_twt = 10;
+	} else {
+		cs0_base = 0xFFC00000;
+		cs0_size = EBC_BXCR_BS_4MB;
+		cs0_twt = 10;
+		cs2_base = 0xFF800000;
+		cs2_size = EBC_BXCR_BS_2MB;
+		cs2_twt = 8;
+	}
+
+	/*-------------------------------------------------------------------------+
+	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
+	  +-------------------------------------------------------------------------*/
+	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
+	      EBC_BXAP_BCE_DISABLE|
+	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
+	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
+	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
+	      EBC_BXAP_BEM_WRITEONLY|
+	      EBC_BXAP_PEN_DISABLED);
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
+	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

 	/*-------------------------------------------------------------------------+
 	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
@@ -75,15 +116,15 @@ int board_early_init_f (void)
 	/*-------------------------------------------------------------------------+
 	  | 4 MB FLASH. Initialize bank 2 with default values.
 	  +-------------------------------------------------------------------------*/
-	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
+	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 	      EBC_BXAP_BCE_DISABLE|
 	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 	      EBC_BXAP_BEM_WRITEONLY|
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
-	      EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
+	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
+	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

 	/*-------------------------------------------------------------------------+
 	  | FPGA. Initialize bank 7 with default values.
--- a/board/omap5912osk/flash.c
+++ b/board/omap5912osk/flash.c
@@ -236,14 +236,14 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 		info->flash_id +=FLASH_28F256K3;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-			    printf ("\Intel StrataFlash 28F256K3C device initialized\n");
+		debug ("Intel StrataFlash 28F256K3C device initialized\n");
 		break;			/* => 32 MB	*/

 	case (FPW) (INTEL_ID_28F128J3A):
 		info->flash_id +=FLASH_28F128J3A;
 		info->sector_count = 259;
 		info->size = 0x02000000;
-			    printf ("\Micron StrataFlash MT28F128J3 device initialized\n");
+		debug ("Micron StrataFlash MT28F128J3 device initialized\n");
 		break;			/* => 32 MB	*/

 	default:
--- a/board/pm520/pm520.c
+++ b/board/pm520/pm520.c
@@ -133,10 +133,13 @@ long int initdram (int board_type)
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

 	/* find RAM size using SDRAM CS1 only */
-	sdram_start(0);
-	test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize2 = test1;
--- a/board/sorcery/Makefile
+++ b/board/sorcery/Makefile
@@ -0,0 +1,45 @@
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/cpu/at91rm9200/config.mk
+++ b/cpu/at91rm9200/config.mk
@@ -1,7 +1,6 @@
 #
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -21,7 +20,10 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-mshort-load-bytes -msoft-float

-PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
+#
+# sorcery board
+#
+
+TEXT_BASE = 0xfff00000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
--- a/board/sorcery/sorcery.c
+++ b/board/sorcery/sorcery.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2004, Freescale Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <pci.h>
+
+long int initdram (int board_type)
+{
+	ulong size;
+
+	size = dramSetup ();
+
+	return get_ram_size((ulong *)CFG_SDRAM_BASE, size);
+}
+
+int checkboard (void)
+{
+	puts ("Board: Sorcery-C MPC8220\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI devices, report devices found.
+ */
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+void pci_init_board (void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc8220_init (struct pci_controller *hose);
+	pci_mpc8220_init (&hose);
+#endif /* CONFIG_PCI */
+}
--- a/board/sorcery/u-boot.lds
+++ b/board/sorcery/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8220/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/uc100/uc100.c
+++ b/board/uc100/uc100.c
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 #include <i2c.h>
+#include <miiphy.h>


 /*********************************************************************/
@@ -252,6 +253,14 @@ int misc_init_r (void)
 	val |= 0x80;
 	i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);

+	/*
+	 * Configure PHY to setup LED's correctly and use 100MBit, FD
+	 */
+	mii_init();
+
+	miiphy_write(0, PHY_BMCR, 0x2100);    /* disable auto-negotiation, 100mbit, full-duplex */
+	miiphy_write(0, PHY_FCSCR, 0x4122);   /* set LED's to Link, Transmit, Receive           */
+
 	return 0;
 }

--- a/board/voiceblue/Makefile
+++ b/board/voiceblue/Makefile
@@ -0,0 +1,64 @@
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# (C) Copyright 2005
+# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= voiceblue.o
+SOBJS	:= setup.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+
+all:	$(LIB) eeprom.srec eeprom.bin
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+eeprom.srec:	eeprom.o
+	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \
+		-L../../examples -lstubs \
+		-L../../lib_generic -lgeneric \
+		-L$(gcclibdir) -lgcc
+	$(OBJCOPY) -O srec $(<:.o=) $@
+
+eeprom.bin:	eeprom.srec
+	$(OBJCOPY) -O binary $< $@ 2>/dev/null
+
+clean:
+	rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
+
+distclean:	clean
+	rm -f $(LIB) core config.tmp *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/voiceblue/config.mk
+++ b/board/voiceblue/config.mk
@@ -0,0 +1,16 @@
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifeq ($(VOICEBLUE_SMALL_FLASH),y)
+# We load ourself to internal SRAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+TEXT_BASE = 0x20012000
+else
+# Running in SDRAM...
+TEXT_BASE = 0x13000000
+endif
--- a/board/voiceblue/eeprom.c
+++ b/board/voiceblue/eeprom.c
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Some code shamelessly stolen back from Robin Getz.
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <exports.h>
+#include "../drivers/smc91111.h"
+
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+
+static int verify_macaddr(char *);
+static int set_mac(char *);
+
+int eeprom(int argc, char *argv[])
+{
+	app_startup(argv);
+	if (get_version() != XF_VERSION) {
+		printf("Wrong XF_VERSION.\n");
+		printf("Application expects ABI version %d\n", XF_VERSION);
+		printf("Actual U-Boot ABI version %d\n", (int)get_version());
+		return 1;
+	}
+
+	if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+		printf("SMSC91111 not found.\n");
+		return 2;
+	}
+
+	if (argc != 2) {
+		printf("VoiceBlue EEPROM writer\n");
+		printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+		printf("Usage:\n\t<mac_address>");
+		return 3;
+	}
+
+	set_mac(argv[1]);
+	if (verify_macaddr(argv[1])) {
+		printf("*** ERROR ***\n");
+		return 4;
+	}
+
+	return 0;
+}
+
+static u16 read_eeprom_reg(u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(2);
+	SMC_outw(reg, PTR_REG);
+
+	SMC_SELECT_BANK(1);
+	SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+		 CTL_REG);
+	timeout = 100;
+	while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+		udelay(100);
+	if (timeout == 0) {
+		printf("Timeout Reading EEPROM register %02x\n", reg);
+		return 0;
+	}
+
+	return SMC_inw (GP_REG);
+}
+
+static int write_eeprom_reg(u16 value, u16 reg)
+{
+	int timeout;
+
+	SMC_SELECT_BANK(2);
+	SMC_outw(reg, PTR_REG);
+
+	SMC_SELECT_BANK(1);
+	SMC_outw(value, GP_REG);
+	SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+	timeout = 100;
+	while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+		udelay (100);
+	if (timeout == 0) {
+		printf("Timeout Writing EEPROM register %02x\n", reg);
+		return 0;
+	}
+
+	return 1;
+}
+
+static int verify_macaddr(char *s)
+{
+	u16 reg;
+	int i, err = 0;
+
+	printf("Verifying MAC Address: ");
+	err = i = 0;
+	for (i = 0; i < 3; i++) {
+		reg = read_eeprom_reg(0x20 + i);
+		printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
+		err |= reg != ((u16 *)s)[i];
+	}
+
+	return err ? 0 : 1;
+}
+
+static int set_mac(char *s)
+{
+	int i;
+	char *e, eaddr[6];
+
+	/* turn string into mac value */
+	for (i = 0; i < 6; i++) {
+		eaddr[i] = simple_strtoul(s, &e, 16);
+		s = (*e) ? e+1 : e;
+	}
+
+	for (i = 0; i < 3; i++)
+		write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+
+	return 0;
+}
--- a/board/voiceblue/setup.S
+++ b/board/voiceblue/setup.S
@@ -0,0 +1,280 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
+ * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* SDRAM load addr from config.mk */
+
+OMAP5910_LPG1_BASE:		.word 0xfffbd000
+OMAP5910_TIPB_SWITCHES_BASE:	.word 0xfffbc800
+OMAP5910_MPU_TC_BASE:		.word 0xfffecc00
+OMAP5910_MPU_CLKM_BASE:		.word 0xfffece00
+OMAP5910_ULPD_PWR_MNG_BASE:	.word 0xfffe0800
+OMAP5910_DPLL1_BASE:		.word 0xfffecf00
+OMAP5910_GPIO_BASE:		.word 0xfffce000
+OMAP5910_MPU_WD_TIMER_BASE:	.word 0xfffec800
+OMAP5910_MPUI_BASE:		.word 0xfffec900
+
+_OMAP5910_ARM_CKCTL:		.word OMAP5910_ARM_CKCTL
+_OMAP5910_ARM_EN_CLK:		.word OMAP5910_ARM_EN_CLK
+
+OMAP5910_MPUI_CTRL:		.word 0x0000ff1b
+
+VAL_EMIFS_CS0_CONFIG:		.word 0x00009090
+VAL_EMIFS_CS1_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS2_CONFIG:		.word 0x00003031
+VAL_EMIFS_CS3_CONFIG:		.word 0x0000c0c0
+VAL_EMIFS_DYN_WAIT:		.word 0x00000000
+/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
+				/*     SLRF       SD_RET     ARE        SDRAM_TYPE   ARCV           SDRAM_FREQUENCY PWD     CLK */
+VAL_EMIFF_SDRAM_CONFIG:		.word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+VAL_EMIFF_SDRAM_CONFIG2:	.word 0x00000003
+VAL_EMIFF_MRS:			.word 0x00000037
+
+/*
+ * GPIO04 - D4 (Onboard LED)
+ * GPIO07 - LAN91C111 reset
+ */
+GPIO_DIRECTION:
+	.word 0x0000ff6f
+/*
+ * Disable everything, but D4 LED (connected through invertor)
+ */
+GPIO_OUTPUT:
+	.word 0x00000010
+
+MUX_CONFIG_BASE:
+	.word 0xfffe1000
+
+MUX_CONFIG_VALUES:
+	.align 4
+	.word 0x00000000	@ FUNC_MUX_CTRL_0
+	.word 0x00000000	@ FUNC_MUX_CTRL_1
+	.word 0x00000000	@ FUNC_MUX_CTRL_2
+	.word 0x00000000	@ FUNC_MUX_CTRL_3
+	.word 0x00000000	@ FUNC_MUX_CTRL_4
+	.word 0x12082480	@ FUNC_MUX_CTRL_5
+	.word 0x00000004	@ FUNC_MUX_CTRL_6
+	.word 0x00000003	@ FUNC_MUX_CTRL_7
+	.word 0x10001200	@ FUNC_MUX_CTRL_8
+	.word 0x01201012	@ FUNC_MUX_CTRL_9
+	.word 0x02081248	@ FUNC_MUX_CTRL_A
+	.word 0x00001248	@ FUNC_MUX_CTRL_B
+	.word 0x12240000	@ FUNC_MUX_CTRL_C
+	.word 0x00002000	@ FUNC_MUX_CTRL_D
+	.word 0x00000000	@ PULL_DWN_CTRL_0
+	.word 0x0000085f	@ PULL_DWN_CTRL_1
+	.word 0x01001000	@ PULL_DWN_CTRL_2
+	.word 0x00000000	@ PULL_DWN_CTRL_3
+	.word 0x00000000	@ GATE_INH_CTRL_0
+	.word 0x00000000	@ VOLTAGE_CTRL_0
+	.word 0x00000000	@ TEST_DBG_CTRL_0
+	.word 0x00000006	@ MOD_CONF_CTRL_0
+	.word 0x0000eaef	@ COMP_MODE_CTRL_0
+
+MUX_CONFIG_OFFSETS:
+	.align 1
+	.byte 0x00		@ FUNC_MUX_CTRL_0
+	.byte 0x04		@ FUNC_MUX_CTRL_1
+	.byte 0x08		@ FUNC_MUX_CTRL_2
+	.byte 0x10		@ FUNC_MUX_CTRL_3
+	.byte 0x14		@ FUNC_MUX_CTRL_4
+	.byte 0x18		@ FUNC_MUX_CTRL_5
+	.byte 0x1c		@ FUNC_MUX_CTRL_6
+	.byte 0x20		@ FUNC_MUX_CTRL_7
+	.byte 0x24		@ FUNC_MUX_CTRL_8
+	.byte 0x28		@ FUNC_MUX_CTRL_9
+	.byte 0x2c		@ FUNC_MUX_CTRL_A
+	.byte 0x30		@ FUNC_MUX_CTRL_B
+	.byte 0x34		@ FUNC_MUX_CTRL_C
+	.byte 0x38		@ FUNC_MUX_CTRL_D
+	.byte 0x40		@ PULL_DWN_CTRL_0
+	.byte 0x44		@ PULL_DWN_CTRL_1
+	.byte 0x48		@ PULL_DWN_CTRL_2
+	.byte 0x4c		@ PULL_DWN_CTRL_3
+	.byte 0x50		@ GATE_INH_CTRL_0
+	.byte 0x60		@ VOLTAGE_CTRL_0
+	.byte 0x70		@ TEST_DBG_CTRL_0
+	.byte 0x80		@ MOD_CONF_CTRL_0
+	.byte 0x0c		@ COMP_MODE_CTRL_0
+	.byte 0xff
+
+.globl platformsetup
+platformsetup:
+	/* Improve performance a bit... */
+	mrc	p15, 0, r1, c0, c0, 0		@ read C15 ID register
+	mrc	p15, 0, r1, c0, c0, 1		@ read C15 Cache information register
+	mrc	p15, 0, r1, c1, c0, 0		@ read C15 Control register
+	orr	r1, r1, #0x1000			@ enable I-cache, map interrupt vector 0xffff0000
+	mcr	p15, 0, r1, c1, c0, 0		@ write C15 Control register
+	mov	r1, #0x00
+	mcr	p15, 0, r1, c7, c5, 0		@ Flush I-cache
+	nop
+	nop
+	nop
+	nop
+
+	/* Setup clocking mode */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ prepare base of CLOCK unit
+	ldrh	r1, [r0, #0x18]			@ get reset status
+	bic	r1, r1, #(7 << 11)		@ clear clock select
+	orr	r1, r1, #(2 << 11)		@ set synchronous scalable
+	mov	r2, #0				@ set wait counter to 100 clock cycles
+
+icache_loop:
+	cmp	r2, #0x01
+	streqh	r1, [r0, #0x18]
+	add	r2, r2, #0x01
+	cmp	r2, #0x10
+	bne	icache_loop
+	nop
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	ldr	r1, _OMAP5910_ARM_CKCTL
+	orr	r1, r1, #0x2000			@ enable DSP clock
+	strh	r1, [r0, #0x00]			@ setup clock divisors
+
+	/* Setup DPLL to generate requested freq */
+	ldr	r0, OMAP5910_DPLL1_BASE		@ base of DPLL1 register
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	orr	r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+	orr	r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+	strh	r1, [r0]			@ write
+
+locking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #0x01
+	beq	locking				@ while LOCK not set
+
+	/* Enable clock */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ base of CLOCK unit
+	mov	r1, #(1 << 10)			@ disable idle mode do not check
+						@ nWAKEUP pin, other remain active
+	strh	r1, [r0, #0x04]
+	ldr	r1, _OMAP5910_ARM_EN_CLK
+	strh	r1, [r0, #0x08]
+	mov	r1, #0x003f			@ FLASH.RP not enabled in idle and
+						@ max delayed ( 32 x CLKIN )
+	strh	r1, [r0, #0x0c]
+
+	/* Configure 5910 pins functions to match our board. */
+	ldr     r0, MUX_CONFIG_BASE
+	adr	r1, MUX_CONFIG_VALUES
+	adr	r2, MUX_CONFIG_OFFSETS
+next_mux_cfg:
+	ldrb	r3, [r2], #1
+	ldr	r4, [r1], #4
+	cmp	r3, #0xff
+	strne	r4, [r0, r3]
+	bne	next_mux_cfg
+
+	/* Configure GPIO pins (also enables onboard LED) */
+	ldr	r0, OMAP5910_GPIO_BASE
+	ldr	r1, GPIO_OUTPUT
+	strh    r1, [r0, #0x04]
+	ldr	r1, GPIO_DIRECTION
+	strh	r1, [r0, #0x08]
+
+	/* EnablePeripherals */
+	ldr	r0, OMAP5910_MPU_CLKM_BASE	@ CLOCK unit
+	mov	r1, #0x0001			@ Peripheral enable
+	strh	r1, [r0, #0x14]
+
+	/* Program LED Pulse Generator */
+	ldr	r0, OMAP5910_LPG1_BASE		@ 1st LED Pulse Generator
+	mov	r1, #0x7F			@ Set obscure frequency in
+	strb	r1, [r0, #0x00]			@ LCR
+	mov	r1, #0x01			@ Enable clock (CLK_EN) in
+	strb    r1, [r0, #0x04]			@ PMR
+
+	/* TIPB Lock UART1 */
+	ldr	r0, OMAP5910_TIPB_SWITCHES_BASE	@ prepare base of TIPB switches
+	mov	r1, #1				@ ARM allocated
+	strh	r1, [r0,#0x04]			@ clear IRQ line and status bits
+	strh	r1, [r0,#0x00]
+	ldrh	r1, [r0,#0x04]
+
+	/* Disable watchdog */
+	ldr	r0, OMAP5910_MPU_WD_TIMER_BASE
+	mov	r1, #0xf5
+	strh	r1, [r0, #0x8]
+	mov	r1, #0xa0
+	strh	r1, [r0, #0x8]
+
+	/* Enable MCLK */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE
+	mov	r1, #0x6
+	strh	r1, [r0, #0x34]
+	strh	r1, [r0, #0x34]
+
+	/* Setup clock divisors */
+	ldr	r0, OMAP5910_ULPD_PWR_MNG_BASE	@ base of ULDPL DPLL1 register
+
+	mov	r1, #0x0010			@ set PLL_ENABLE
+	orr	r1, r1, #0x2000			@ set IOB to new locking
+	strh	r1, [r0]			@ write
+
+ulocking:
+	ldrh	r1, [r0]			@ get DPLL value
+	tst	r1, #1
+	beq	ulocking			@ while LOCK not set
+
+	/* EMIF init */
+	ldr	r0, OMAP5910_MPU_TC_BASE
+	ldrh	r1, [r0, #0x0c]			@ EMIFS_CONFIG_REG
+	bic	r1, r1, #0x0c			@ pwr down disabled, flash WP
+	orr	r1, r1, #0x01
+	str	r1, [r0, #0x0c]
+
+	ldr	r1, VAL_EMIFS_CS0_CONFIG
+	str	r1, [r0, #0x10]			@ EMIFS_CS0_CONFIG
+	ldr	r1, VAL_EMIFS_CS1_CONFIG
+	str	r1, [r0, #0x14]			@ EMIFS_CS1_CONFIG
+	ldr	r1, VAL_EMIFS_CS2_CONFIG
+	str	r1, [r0, #0x18]			@ EMIFS_CS2_CONFIG
+	ldr	r1, VAL_EMIFS_CS3_CONFIG
+	str	r1, [r0, #0x1c]			@ EMIFS_CS3_CONFIG
+	ldr	r1, VAL_EMIFS_DYN_WAIT
+	str	r1, [r0, #0x40]			@ EMIFS_CFG_DYN_WAIT
+
+	/* Setup SDRAM */
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG
+	str	r1, [r0, #0x20]			@ EMIFF_SDRAM_CONFIG
+	ldr	r1, VAL_EMIFF_SDRAM_CONFIG2
+	str	r1, [r0, #0x3c]			@ EMIFF_SDRAM_CONFIG2
+	ldr	r1, VAL_EMIFF_MRS
+	str	r1, [r0, #0x24]			@ EMIFF_MRS
+	/* SDRAM needs 100us to stabilize */
+	mov	r0, #0x4000
+sdelay:
+	subs	r0, r0, #0x1
+	bne 	sdelay
+
+	/* back to arch calling code */
+	mov	pc, lr
+.end
--- a/board/voiceblue/u-boot.lds
+++ b/board/voiceblue/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm925t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/voiceblue/voiceblue.c
+++ b/board/voiceblue/voiceblue.c
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa;
+
+	/* arch number of VoiceBlue board */
+	/* TODO: use define from asm/mach-types.h */
+	gd->bd->bi_arch_number = 218;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x10000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff;
+
+ 	/* Take the Ethernet controller out of reset and wait
+ 	 * for the EEPROM load to complete. */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
+	udelay(10);	/* doesn't work before interrupt_init call */
+	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
+	udelay(500);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifndef VOICEBLUE_SMALL_FLASH
+
+#include <jffs2/jffs2.h>
+
+extern flash_info_t flash_info[];
+static struct part_info partinfo;
+static int current_part = -1;
+
+/* Partition table (Linux MTD see it this way)
+ *
+ * 0 - U-Boot
+ * 1 - env
+ * 2 - redundant env
+ * 3 - data1 (jffs2)
+ * 4 - data2 (jffs2)
+ */
+
+static struct {
+	ulong offset;
+	ulong size;
+} part[5];
+
+static void partition_flash(flash_info_t *info)
+{
+	char mtdparts[128];
+	int i, n, size, psize;
+	const ulong plen[3] = { CFG_MONITOR_LEN, CFG_ENV_SIZE, CFG_ENV_SIZE };
+
+	size = n = 0;
+	for (i = 0; i < 4; i++) {
+		part[i].offset = info->start[n];
+		psize = i < 3 ? plen[i] : (info->size - size) / 2;
+		while (part[i].size < psize) {
+			if (++n > info->sector_count) {
+				printf("Partitioning error. System halted.\n");
+				while (1) ;
+			}
+			part[i].size += info->start[n] - info->start[n - 1];
+		}
+		size += part[i].size;
+	}
+	part[4].offset = info->start[n];
+	part[4].size = info->start[info->sector_count - 1] - info->start[n];
+
+	sprintf(mtdparts, "omapflash.0:"
+			"%dk(U-Boot)ro,%dk(env),%dk(r_env),%dk(data1),-(data2)",
+			part[0].size >> 10, part[1].size >> 10,
+			part[2].size >> 10, part[3].size >> 10);
+	setenv ("mtdparts", mtdparts);
+}
+
+struct part_info* jffs2_part_info(int part_num)
+{
+	void *jffs2_priv_saved = partinfo.jffs2_priv;
+
+	if (part_num != 3 && part_num != 4)
+		return NULL;
+
+	if (current_part != part_num) {
+		memset(&partinfo, 0, sizeof(partinfo));
+		current_part = part_num;
+		partinfo.offset = (char*) part[part_num].offset;
+		partinfo.size = part[part_num].size;
+		partinfo.usr_priv = &current_part;
+		partinfo.jffs2_priv = jffs2_priv_saved;
+	}
+
+	return &partinfo;
+}
+
+#endif
+
+int misc_init_r(void)
+{
+	*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55;
+
+#ifndef VOICEBLUE_SMALL_FLASH
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("Unknown flash. System halted.\n");
+		while (1) ;
+	}
+	partition_flash(&flash_info[0]);
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00;
+
+	return 0;
+}
--- a/common/altera.c
+++ b/common/altera.c
@@ -158,6 +158,7 @@ int altera_info( Altera_desc *desc )
 				/* Add new family types here */
 			default:
 				/* we don't need a message here - we give one up above */
+				break;
 			}
 		} else {
 			printf ("No Device Function Table.\n");
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -261,7 +261,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		name = "Standalone Application";
 		/* A second argument overwrites the load address */
 		if (argc > 2) {
-			hdr->ih_load = simple_strtoul(argv[2], NULL, 16);
+			hdr->ih_load = htonl(simple_strtoul(argv[2], NULL, 16));
 		}
 		break;
 	case IH_TYPE_KERNEL:
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -175,10 +175,9 @@ do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 int
 do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-   struct part_info* jffs2_part_info(int);
-   int jffs2_1pass_ls(struct part_info *,char *);
-
-   char *filename = "/";
+	struct part_info* jffs2_part_info(int);
+	int jffs2_1pass_ls(struct part_info *,char *);
+	char *filename = "/";
 	int ret;
 	struct part_info *part;

@@ -235,11 +234,11 @@ do_jffs2_chpart(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int tmp_part;
 	char str_part_num[3];
-   struct part_info* jffs2_part_info(int);
+	struct part_info* jffs2_part_info(int);

-   if (argc >= 2) {
+	if (argc >= 2) {
 		tmp_part = simple_strtoul(argv[1], NULL, 16);
-	}else{
+	} else {
 		puts ("Need partition number in argument list\n");
 		return 0;

--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -670,11 +670,12 @@ static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
 	id = READ_NAND(nand->IO_ADDR);

 	NAND_DISABLE_CE(nand);  /* set pin high */
-	/* No response - return failure */
-	if (mfr == 0xff || mfr == 0) {
+
 #ifdef NAND_DEBUG
-		printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
+	printf("NanD_Command (ReadID) got %x %x\n", mfr, id);
 #endif
+	if (mfr == 0xff || mfr == 0) {
+		/* No response - return failure */
 		return 0;
 	}

@@ -1218,6 +1219,8 @@ static int nand_write_page (struct nand_chip *nand,
 	}
 	if (nand->bus16) {
 		for (i = 0; i < nand->oobsize; i += 2) {
+			u16 val;
+
 			val = READ_NAND (nand->IO_ADDR);
 			nand->data_buf[i] = val & 0xff;
 			nand->data_buf[i + 1] = val >> 8;
--- a/common/cmd_net.c
+++ b/common/cmd_net.c
@@ -33,7 +33,7 @@

 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);

-static int netboot_common (int, cmd_tbl_t *, int , char *[]);
+static int netboot_common (proto_t, cmd_tbl_t *, int , char *[]);

 int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -152,7 +152,7 @@ static void netboot_update_env (void)
 }

 static int
-netboot_common (int proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
+netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
 {
 	char *s;
 	int   rcode = 0;
--- a/common/cmd_universe.c
+++ b/common/cmd_universe.c
@@ -72,6 +72,9 @@ int universe_init(void)
 	dev->busdevfn = busdevfn;

 	pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_1, &val);
+	if (val & 1) {
+		pci_read_config_dword(busdevfn, PCI_BASE_ADDRESS_0, &val);
+	}
 	val &= ~0xf;
 	dev->uregs = (UNIVERSE *)val;

@@ -102,7 +105,13 @@ int universe_init(void)
 	 *   Arbitration Mode
 	 *   DTACK Enable
 	 */
-	writel(0x15060000, &dev->uregs->misc_ctl);
+	writel(0x15040000 | (readl(&dev->uregs->misc_ctl) & 0x00020000), &dev->uregs->misc_ctl);
+
+	if (readl(&dev->uregs->misc_ctl) & 0x00020000) {
+		debug ("System Controller!\n"); /* test-only */
+	} else {
+		debug ("Not System Controller!\n"); /* test-only */
+	}

 	/*
 	 * Lets turn off interrupts
@@ -114,12 +123,14 @@ int universe_init(void)
 	writel(0x0000, &dev->uregs->lint_map1);  /* Map all ints to 0 */
 	eieio();

+	return 0;
+
 break_30:
 	free(dev);
 break_20:
 	lastError = result;

-	return 0;
+	return result;
 }


@@ -193,13 +204,13 @@ int universe_pci_slave_window(unsigned int pciAddr, unsigned int vmeAddr, int si

 	switch (pms & PCI_MS_Mxx) {
 	case PCI_MS_MEM:
-		ctl = 0x00000000;
+		ctl |= 0x00000000;
 		break;
 	case PCI_MS_IO:
-		ctl = 0x00000001;
+		ctl |= 0x00000001;
 		break;
 	case PCI_MS_CONFIG:
-		ctl = 0x00000002;
+		ctl |= 0x00000002;
 		break;
 	}

@@ -278,13 +289,13 @@ int universe_vme_slave_window(unsigned int vmeAddr, unsigned int pciAddr, int si

 	switch (pms & PCI_MS_Mxx) {
 	case PCI_MS_MEM:
-		ctl = 0x00000000;
+		ctl |= 0x00000000;
 		break;
 	case PCI_MS_IO:
-		ctl = 0x00000001;
+		ctl |= 0x00000001;
 		break;
 	case PCI_MS_CONFIG:
-		ctl = 0x00000002;
+		ctl |= 0x00000002;
 		break;
 	}

--- a/common/cmd_usb.c
+++ b/common/cmd_usb.c
@@ -609,7 +609,7 @@ U_BOOT_CMD(
 	"usb tree  - show USB device tree\n"
 	"usb info [dev] - show available USB devices\n"
 	"usb scan  - (re-)scan USB bus for storage devices\n"
-	"usb device [dev] - show or set current USB storage device\n"
+	"usb dev [dev] - show or set current USB storage device\n"
 	"usb part [dev] - print partition table of one or all USB storage devices\n"
 	"usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
 	"    to memory address `addr'\n"
--- a/common/command.c
+++ b/common/command.c
@@ -136,9 +136,9 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

 		if (adv == 2) {
 			if (strcmp(ap[0], "-z") == 0)
-				expr = strlen(ap[1]) == 0 ? 0 : 1;
-			else if (strcmp(ap[0], "-n") == 0)
 				expr = strlen(ap[1]) == 0 ? 1 : 0;
+			else if (strcmp(ap[0], "-n") == 0)
+				expr = strlen(ap[1]) == 0 ? 0 : 1;
 			else {
 				expr = 1;
 				break;
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -58,6 +58,15 @@
 /************************************************************************/
 #include <video_font.h>		/* Get font data, width and height	*/

+/************************************************************************/
+/* ** LOGO DATA								*/
+/************************************************************************/
+#ifdef CONFIG_LCD_LOGO
+# include <bmp_logo.h>		/* Get logo data, width and height	*/
+# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
+#  error Default Color Map overlaps with Logo Color Map
+# endif
+#endif

 ulong lcd_setmem (ulong addr);

@@ -269,7 +278,7 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count)

 static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)
 {
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
 	lcd_drawchars (x, y+BMP_LOGO_HEIGHT, s, strlen (s));
 #else
 	lcd_drawchars (x, y, s, strlen (s));
@@ -280,7 +289,7 @@ static inline void lcd_puts_xy (ushort x, ushort y, uchar *s)

 static inline void lcd_putc_xy (ushort x, ushort y, uchar c)
 {
-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
 	lcd_drawchars (x, y+BMP_LOGO_HEIGHT, &c, 1);
 #else
 	lcd_drawchars (x, y, &c, 1);
@@ -420,7 +429,7 @@ static int lcd_init (void *lcdbase)

 	/* Initialize the console */
 	console_col = 0;
-#ifdef LCD_INFO_BELOW_LOGO
+#ifdef CONFIG_LCD_INFO_BELOW_LOGO
 	console_row = 7 + BMP_LOGO_HEIGHT / VIDEO_FONT_HEIGHT;
 #else
 	console_row = 1;	/* leave 1 blank line below logo */
@@ -655,6 +664,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
 	for (i = 0; i < height; ++i) {
+		WATCHDOG_RESET();
 		for (j = 0; j < width ; j++)
 #if defined(CONFIG_PXA250)
 			*(fb++)=*(bmap++);
@@ -672,12 +682,12 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)

 static void *lcd_logo (void)
 {
-#ifdef LCD_INFO
+#ifdef CONFIG_LCD_INFO
 	DECLARE_GLOBAL_DATA_PTR;

 	char info[80];
 	char temp[32];
-#endif /* LCD_INFO */
+#endif /* CONFIG_LCD_INFO */

 #ifdef CONFIG_SPLASH_SCREEN
 	char *s;
@@ -699,7 +709,7 @@ static void *lcd_logo (void)
 #endif /* CONFIG_LCD_LOGO */

 #ifdef CONFIG_MPC823
-#ifdef LCD_INFO
+# ifdef CONFIG_LCD_INFO
 	sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__);
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, info, strlen(info));

@@ -710,7 +720,7 @@ static void *lcd_logo (void)
 	sprintf (info, "    Wolfgang DENK, wd@denx.de");
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2,
 					info, strlen(info));
-#ifdef LCD_INFO_BELOW_LOGO
+#  ifdef CONFIG_LCD_INFO_BELOW_LOGO
 	sprintf (info, "MPC823 CPU at %s MHz",
 		strmhz(temp, gd->cpu_clk));
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3,
@@ -720,7 +730,7 @@ static void *lcd_logo (void)
 		gd->bd->bi_flashsize >> 20 );
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
 					info, strlen(info));
-#else
+#  else
 	/* leave one blank line */

 	sprintf (info, "MPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash",
@@ -730,15 +740,15 @@ static void *lcd_logo (void)
 	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4,
 					info, strlen(info));

+#  endif /* CONFIG_LCD_INFO_BELOW_LOGO */
+# endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_MPC823 */
-#endif /* LCD_INFO_BELOW_LOGO */
-#endif /* LCD_INFO */

-#if defined(CONFIG_LCD_LOGO) && !defined(LCD_INFO_BELOW_LOGO)
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
 	return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length));
 #else
 	return ((void *)lcd_base);
-#endif /* CONFIG_LCD_LOGO */
+#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */
 }

 /************************************************************************/
--- a/cpu/arm920t/at91rm9200/Makefile
+++ b/cpu/arm920t/at91rm9200/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2003
+# (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -23,22 +23,20 @@

 include $(TOPDIR)/config.mk

-LIB	= lib$(CPU).a
+LIB	= lib$(SOC).a

-START	= start.o
-OBJS	= serial.o interrupts.o cpu.o \
-	  at91rm9200_ether.o i2c.o
-SOBJS	= lowlevel.o
+OBJS	= ether.o i2c.o interrupts.o serial.o
+SOBJS	= lowlevel_init.o

-all:	.depend $(START) $(LIB)
+all:	.depend $(LIB)

 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

 #########################################################################

-.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@

 sinclude .depend

--- a/cpu/at91rm9200/at91rm9200_ether.c
+++ b/cpu/at91rm9200/at91rm9200_ether.c
--- a/cpu/arm920t/at91rm9200/i2c.c
+++ b/cpu/arm920t/at91rm9200/i2c.c
@@ -138,12 +138,12 @@ i2c_read (unsigned char chip, unsigned int addr, int alen,

 int
 i2c_write(unsigned char chip, unsigned int addr, int alen,
-							unsigned char *buffer, int len)
+	  unsigned char *buffer, int len)
 {
+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 	int i;
 	unsigned char *buf;

-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 	/* we only allow one address byte */
 	if (alen > 1)
 		return 1;
@@ -189,4 +189,19 @@ i2c_init(int speed, int slaveaddr)
 	debug ("Found AT91 i2c\n");
 	return;
 }
+
+uchar i2c_reg_read(uchar i2c_addr, uchar reg)
+{
+	char buf;
+
+	i2c_read(i2c_addr, reg, 1, &buf, 1);
+
+	return(buf);
+}
+
+void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
+{
+	i2c_write(i2c_addr, reg, 1, &val, 1);
+}
+
 #endif /* CONFIG_HARD_I2C */
--- a/cpu/arm920t/at91rm9200/interrupts.c
+++ b/cpu/arm920t/at91rm9200/interrupts.c
@@ -31,9 +31,9 @@
 */

 #include <common.h>
-#include <asm/io.h>
+/*#include <asm/io.h>*/
 #include <asm/arch/hardware.h>
-#include <asm/proc/ptrace.h>
+/*#include <asm/proc/ptrace.h>*/

 /* the number of clocks per CFG_HZ */
 #define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
@@ -42,119 +42,11 @@
 #define READ_TIMER (tmr->TC_CV & 0x0000ffff)
 AT91PS_TC tmr;

-#ifdef CONFIG_USE_IRQ
-#error There is no IRQ support for AT91RM9200 in U-Boot yet.
-#else
-void enable_interrupts (void)
-{
-	return;
-}
-int disable_interrupts (void)
-{
-	return 0;
-}
-#endif
-
-
-void bad_mode (void)
-{
-	panic ("Resetting CPU ...\n");
-	reset_cpu (0);
-}
-
-void show_regs (struct pt_regs *regs)
-{
-	unsigned long flags;
-	const char *processor_modes[] = {
-	"USER_26",	"FIQ_26",	"IRQ_26",	"SVC_26",
-	"UK4_26",	"UK5_26",	"UK6_26",	"UK7_26",
-	"UK8_26",	"UK9_26",	"UK10_26",	"UK11_26",
-	"UK12_26",	"UK13_26",	"UK14_26",	"UK15_26",
-	"USER_32",	"FIQ_32",	"IRQ_32",	"SVC_32",
-	"UK4_32",	"UK5_32",	"UK6_32",	"ABT_32",
-	"UK8_32",	"UK9_32",	"UK10_32",	"UND_32",
-	"UK12_32",	"UK13_32",	"UK14_32",	"SYS_32",
-	};
-
-	flags = condition_codes (regs);
-
-	printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
-		"sp : %08lx  ip : %08lx  fp : %08lx\n",
-		instruction_pointer (regs),
-		regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
-	printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
-		regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
-	printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
-		regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
-	printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
-		regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
-	printf ("Flags: %c%c%c%c",
-		flags & CC_N_BIT ? 'N' : 'n',
-		flags & CC_Z_BIT ? 'Z' : 'z',
-		flags & CC_C_BIT ? 'C' : 'c',
-		flags & CC_V_BIT ? 'V' : 'v');
-	printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
-		interrupts_enabled (regs) ? "on" : "off",
-		fast_interrupts_enabled (regs) ? "on" : "off",
-		processor_modes[processor_mode (regs)],
-		thumb_mode (regs) ? " (T)" : "");
-}
-
-void do_undefined_instruction (struct pt_regs *pt_regs)
-{
-	printf ("undefined instruction\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_software_interrupt (struct pt_regs *pt_regs)
-{
-	printf ("software interrupt\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_prefetch_abort (struct pt_regs *pt_regs)
-{
-	printf ("prefetch abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_data_abort (struct pt_regs *pt_regs)
-{
-	printf ("data abort\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_not_used (struct pt_regs *pt_regs)
-{
-	printf ("not used\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_fiq (struct pt_regs *pt_regs)
-{
-	printf ("fast interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-	printf ("interrupt request\n");
-	show_regs (pt_regs);
-	bad_mode ();
-}
-
 static ulong timestamp;
 static ulong lastinc;

 int interrupt_init (void)
 {
-
 	tmr = AT91C_BASE_TC0;

 	/* enables TC1.0 clock */
@@ -266,3 +158,53 @@ ulong get_tbclk (void)
 	tbclk = CFG_HZ;
 	return tbclk;
 }
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ * or toggle a GPIO pin on the AT91RM9200DK board
+ */
+void reset_cpu (ulong ignored)
+{
+
+#ifdef CONFIG_DBGU
+	AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+	AT91PS_USART us = AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
+	AT91PS_USART us = AT91C_BASE_US1;
+#endif
+#ifdef CONFIG_AT91RM9200DK
+	AT91PS_PIO pio = AT91C_BASE_PIOA;
+#endif
+
+	/*shutdown the console to avoid strange chars during reset */
+	us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+
+#ifdef CONFIG_AT91RM9200DK
+	/* Clear PA19 to trigger the hard reset */
+	pio->PIO_CODR = 0x00080000;
+	pio->PIO_OER  = 0x00080000;
+	pio->PIO_PER  = 0x00080000;
+#endif
+
+	/* this is the way Linux does it */
+
+	/* FIXME:
+	 * These defines should be moved into
+	 * include/asm-arm/arch-at91rm9200/AT91RM9200.h
+	 * as soon as the whitespace fix gets applied.
+	 */
+	#define AT91C_ST_RSTEN (0x1 << 16)
+	#define AT91C_ST_EXTEN (0x1 << 17)
+	#define AT91C_ST_WDRST (0x1 <<  0)
+	#define ST_WDMR *((unsigned long *)0xfffffd08)	/* watchdog mode register */
+	#define ST_CR *((unsigned long *)0xfffffd00)	/* system clock control register */
+
+	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+	ST_CR = AT91C_ST_WDRST;
+
+	while (1);
+	/* Never reached */
+}
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
--- a/cpu/arm920t/at91rm9200/serial.c
+++ b/cpu/arm920t/at91rm9200/serial.c
@@ -55,11 +55,8 @@ void serial_setbrg (void)

 	if ((baudrate = gd->baudrate) <= 0)
 		baudrate = CONFIG_BAUDRATE;
-	if (baudrate == 0 || baudrate == CONFIG_BAUDRATE)
-		us->US_BRGR = CFG_AT91C_BRGR_DIVISOR;	/* hardcode so no __divsi3 */
-	else
-		/* MASTER_CLOCK/(16 * baudrate) */
-		us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
+	/* MASTER_CLOCK/(16 * baudrate) */
+	us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
 }

 int serial_init (void)
--- a/cpu/arm920t/imx/interrupts.c
+++ b/cpu/arm920t/imx/interrupts.c
@@ -117,4 +117,23 @@ ulong get_tbclk (void)
 	return tbclk;
 }

+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	/* Disable watchdog and set Time-Out field to 0 */
+	WCR = 0x00000000;
+
+	/* Write Service Sequence */
+	WSR = 0x00005555;
+	WSR = 0x0000AAAA;
+
+	/* Enable watchdog */
+	WCR = 0x00000001;
+
+	while (1);
+	/*NOTREACHED*/
+}
+
 #endif /* defined (CONFIG_IMX) */
--- a/cpu/arm920t/ks8695/Makefile
+++ b/cpu/arm920t/ks8695/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(SOC).a
+
+OBJS	= interrupts.o serial.o
+SOBJS	= lowlevel_init.o
+
+all:	.depend $(LIB)
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/cpu/arm920t/ks8695/interrupts.c
+++ b/cpu/arm920t/ks8695/interrupts.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/*
+ * Handy KS8695 register access functions.
+ */
+#define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
+#define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
+
+int timer_inited;
+ulong timer_ticks;
+
+int interrupt_init (void)
+{
+	/* nothing happens here - we don't setup any IRQs */
+	return (0);
+}
+
+/*
+ * Initial timer set constants. Nothing complicated, just set for a 1ms
+ * tick.
+ */
+#define	TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_1)
+#define	TIMER_COUNT	(TIMER_INTERVAL / 2)
+#define	TIMER_PULSE	TIMER_COUNT
+
+void reset_timer_masked(void)
+{
+	/* Set the hadware timer for 1ms */
+	ks8695_write(KS8695_TIMER1, TIMER_COUNT);
+	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
+	ks8695_write(KS8695_TIMER_CTRL, 0x2);
+	timer_ticks = 0;
+	timer_inited++;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	/* Check for timer wrap */
+	if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
+		/* Clear interrupt condition */
+		ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
+		timer_ticks++;
+	}
+	return timer_ticks;
+}
+
+ulong get_timer(ulong base)
+{
+       return (get_timer_masked() - base);
+}
+
+void set_timer(ulong t)
+{
+	timer_ticks = t;
+}
+
+void udelay(ulong usec)
+{
+	ulong start = get_timer_masked();
+	ulong end;
+
+	if (!timer_inited)
+		reset_timer();
+
+	/* Only 1ms resolution :-( */
+	end = usec / 1000;
+	while (get_timer(start) < end)
+		;
+}
+
+void reset_cpu (ulong ignored)
+{
+	ulong tc;
+
+	/* Set timer0 to watchdog, and let it timeout */
+	tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
+	ks8695_write(KS8695_TIMER_CTRL, tc);
+	ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
+	ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
+
+	/* Should only wait here till watchdog resets */
+	for (;;)
+		;
+}
--- a/cpu/arm920t/ks8695/lowlevel_init.S
+++ b/cpu/arm920t/ks8695/lowlevel_init.S
@@ -0,0 +1,205 @@
+/*
+ *  lowlevel_init.S - basic hardware initialization for the KS8695 CPU
+ *
+ *  Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/platform.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ *************************************************************************
+ *
+ * Handy dandy macros
+ *
+ *************************************************************************
+ */
+
+/* Delay a bit */
+.macro DELAY_FOR cycles, reg0
+	ldr     \reg0, =\cycles
+	subs    \reg0, \reg0, #1
+	subne   pc,  pc, #0xc
+.endm
+
+/*
+ *************************************************************************
+ *
+ * Some local storage.
+ *
+ *************************************************************************
+ */
+
+/* Should we boot with an interactive console or not */
+.globl serial_console
+
+/*
+ *************************************************************************
+ *
+ * Raw hardware initialization code. The important thing is to get
+ * SDRAM setup and running. We do some other basic things here too,
+ * like getting the PLL set for high speed, and init the LEDs.
+ *
+ *************************************************************************
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+#if DEBUG
+	/*
+	 * enable UART for early debug trace
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
+	mov	r2, #0xd9
+	str	r2, [r1]		/* 115200 baud */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
+	mov	r2, #0x03
+	str	r2, [r1]		/* 8 data bits, no parity, 1 stop */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
+	mov	r2, #0x41
+	str	r2, [r1]		/* write 'A' */
+#endif
+#if DEBUG
+	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
+	mov	r2, #0x42
+	str	r2, [r1]
+#endif
+
+	/*
+	 * remap the memory and flash regions. we want to end up with
+	 * ram from address 0, and flash at 32MB.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
+	ldr	r2, =0xbfc00040
+	str	r2, [r1]		/* large flash map */
+	ldr	pc, =(highflash+0x02000000-0x00f00000)	/* jump to high flash address */
+highflash:
+	ldr	r2, =0x8fe00040
+	str	r2, [r1]		/* remap flash range */
+
+	/*
+	 * remap the second select region to the 4MB immediately after
+	 * the first region. This way if you have a larger flash (say 8Mb)
+	 * then you can have it all mapped nicely. Has no effect if you
+	 * only have a 4Mb or smaller flash.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
+	ldr	r2, =0x9fe40040
+	str	r2, [r1]		/* remap flash2 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
+	ldr	r2, =0x30000005
+	str	r2, [r1]		/* enable both flash selects */
+
+#ifdef CONFIG_CM41xx
+	/*
+	 * map the second flash chip, using the external IO lines.
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
+	ldr	r2, =0xafe80b6d
+	str	r2, [r1]		/* remap io0 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
+	ldr	r2, =0xbfec0b6d
+	str	r2, [r1]		/* remap io1 region, contiguous */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
+	ldr	r2, =0x30050005
+	str	r2, [r1]		/* enable second flash */
+#endif
+
+	/*
+	 * before relocating, we have to setup RAM timing
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
+#if (PHYS_SDRAM_1_SIZE == 0x02000000)
+	ldr	r2, =0x7fc0000e		/* 32MB */
+#else
+	ldr	r2, =0x3fc0000e		/* 16MB */
+#endif
+	str	r2, [r1]		/* configure sdram bank0 setup */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
+	mov	r2, #0
+	str	r2, [r1]		/* configure sdram bank1 setup */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
+	ldr	r2, =0x0000000a
+	str	r2, [r1]		/* set RAS/CAS timing */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
+	ldr	r2, =0x00030000
+	str	r2, [r1]		/* send NOP command */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x00010000
+	str	r2, [r1]		/* send PRECHARGE-ALL */
+	DELAY_FOR 0x100, r0
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
+	ldr	r2, =0x00000020
+	str	r2, [r1]		/* set for fast refresh */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x00000190
+	str	r2, [r1]		/* set normal refresh timing */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
+	ldr	r2, =0x00020033
+	str	r2, [r1]		/* send mode command */
+	DELAY_FOR 0x100, r0
+	ldr	r2, =0x01f00000
+	str	r2, [r1]		/* enable sdram fifos */
+
+	/*
+	 * set pll to top speed
+	 */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
+	mov	r2, #0
+	str	r2, [r1]		/* set pll clock to 166MHz */
+
+	ldr	r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
+	ldr	r2, [r1]		/* Get switch ctrl0 register       */
+	and	r2, r2, #0x0fc00000	/* Mask out LED control bits       */
+	orr	r2, r2, #0x01800000	/* Set Link/activity/speed actions */
+	str	r2, [r1]
+
+#ifdef CONFIG_CM4008
+	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
+	ldr	r2, =0x0000fe30
+	str	r2, [r1]		/* enable LED's as outputs	    */
+	ldr	r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
+	ldr	r2, =0x0000fe20
+	str	r2, [r1]		/* turn on power LED		    */
+#endif
+#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
+	ldr	r2, [r1]		/* get current GPIO input data	    */
+	tst	r2, #0x8		/* check if "erase" depressed	    */
+	beq	nobutton
+	mov	r2, #0			/* be quiet on boot, no console	    */
+	ldr	r1, =serial_console
+	str	r2, [r1]
+nobutton:
+#endif
+
+	add	lr, lr, #0x02000000	/* flash is now mapped high */
+	add	ip, ip, #0x02000000	/* this is a hack */
+	mov	pc, lr			/* all done, return */
+
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
--- a/cpu/arm920t/ks8695/serial.c
+++ b/cpu/arm920t/ks8695/serial.c
@@ -0,0 +1,116 @@
+/*
+ * serial.c -- KS8695 serial driver
+ *
+ * (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+#ifndef CONFIG_SERIAL1
+#error "Bad: you didn't configure serial ..."
+#endif
+
+/*
+ *	Define the UART hardware register access structure.
+ */
+struct ks8695uart {
+	unsigned int	RX;		/* 0x00	- Receive data (r) */
+	unsigned int	TX;		/* 0x04	- Transmit data (w) */
+	unsigned int	FCR;		/* 0x08	- Fifo Control (r/w) */
+	unsigned int	LCR;		/* 0x0c	- Line Control (r/w) */
+	unsigned int	MCR;		/* 0x10	- Modem Control (r/w) */
+	unsigned int	LSR;		/* 0x14	- Line Status (r/w) */
+	unsigned int	MSR;		/* 0x18	- Modem Status (r/w) */
+	unsigned int	BD;		/* 0x1c	- Baud Rate (r/w) */
+	unsigned int	SR;		/* 0x20	- Status (r/w) */
+};
+
+#define	KS8695_UART_ADDR	((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
+#define	KS8695_UART_CLK		25000000
+
+
+/*
+ * Under some circumstances we want to be "quiet" and not issue any
+ * serial output - though we want u-boot to otherwise work and behave
+ * the same. By default be noisy.
+ */
+int serial_console = 1;
+
+
+void serial_setbrg(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+
+	/* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
+	uartp->BD = KS8695_UART_CLK / gd->baudrate;
+	uartp->LCR = KS8695_UART_LINEC_WLEN8;
+}
+
+int serial_init(void)
+{
+	serial_console = 1;
+	serial_setbrg();
+	return 0;
+}
+
+void serial_raw_putc(const char c)
+{
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+	int i;
+
+	for (i = 0; (i < 0x100000); i++) {
+		if (uartp->LSR & KS8695_UART_LINES_TXFE)
+			break;
+	}
+
+	uartp->TX = c;
+}
+
+void serial_putc(const char c)
+{
+	if (serial_console) {
+		serial_raw_putc(c);
+		if (c == '\n')
+			serial_raw_putc('\r');
+	}
+}
+
+int serial_tstc(void)
+{
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+	if (serial_console)
+		return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
+	return 0;
+}
+
+void serial_puts(const char *s)
+{
+	char c;
+	while ((c = *s++) != 0)
+		serial_putc(c);
+}
+
+int serial_getc(void)
+{
+	volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
+
+	while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
+		;
+	return (uartp->RX);
+}
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -185,4 +185,33 @@ ulong get_tbclk (void)
 	return tbclk;
 }

+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	volatile S3C24X0_WATCHDOG * watchdog;
+
+#ifdef CONFIG_TRAB
+	extern void disable_vfd (void);
+
+	disable_vfd();
+#endif
+
+	watchdog = S3C24X0_GetBase_WATCHDOG();
+
+	/* Disable watchdog */
+	watchdog->WTCON = 0x0000;
+
+	/* Initialize watchdog timer count register */
+	watchdog->WTCNT = 0x0001;
+
+	/* Enable watchdog timer; assert reset at timer timeout */
+	watchdog->WTCON = 0x0021;
+
+	while(1);	/* loop forever and wait for reset to happen */
+
+	/*NOTREACHED*/
+}
+
 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -433,39 +433,3 @@ fiq:
 	bl 	do_fiq

 #endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-#ifdef CONFIG_S3C2400
-	bl	disable_interrupts
-# ifdef CONFIG_TRAB
-	bl	disable_vfd
-# endif
-	ldr	r1, _rWTCON
-	ldr	r2, _rWTCNT
-	/* Disable watchdog */
-	mov	r3, #0x0000
-	str	r3, [r1]
-	/* Initialize watchdog timer count register */
-	mov	r3, #0x0001
-	str	r3, [r2]
-	/* Enable watchdog timer; assert reset at timer timeout */
-	mov	r3, #0x0021
-	str	r3, [r1]
-_loop_forever:
-	b	_loop_forever
-_rWTCON:
-	.word	0x15300000
-_rWTCNT:
-	.word	0x15300008
-#else /* ! CONFIG_S3C2400 */
-	mov     ip, #0
-	mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
-	mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)
-	mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
-	bic     ip, ip, #0x000f                 @ ............wcam
-	bic     ip, ip, #0x2100                 @ ..v....s........
-	mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-	mov     pc, r0
-#endif /* CONFIG_S3C2400 */
--- a/cpu/at91rm9200/cpu.c
+++ b/cpu/at91rm9200/cpu.c
@@ -1,200 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
-#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
-#endif
-
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
-    unsigned long value;
-
-    __asm__ __volatile__(
-	"mrc     p15, 0, %0, c1, c0, 0   @ read control reg\n"
-	: "=r" (value)
-	:
-	: "memory");
-    /*printf("p15/c1 is = %08lx\n", value); */
-    return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
-    /*printf("write %08lx to p15/c1\n", value); */
-    __asm__ __volatile__(
-	"mcr     p15, 0, %0, c1, c0, 0   @ write it back\n"
-	: "=r" (value)
-	:
-	: "memory");
-
-    read_p15_c1();
-}
-
-static void cp_delay(void)
-{
-    volatile int i;
-
-    /* copro seems to need some delay between reading and writing */
-    for (i=0; i<100; i++);
-}
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)	/* mmu off/on */
-#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
-#define C1_IDC		(1<<2)	/* icache and/or dcache off/on */
-#define C1_WRITE_BUFFER	(1<<3)	/* write buffer off/on */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)	/* system protection */
-#define C1_ROM_PROT	(1<<9)	/* ROM protection */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-
-int cpu_init(void)
-{
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	DECLARE_GLOBAL_DATA_PTR;
-
-	IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-	return 0;
-}
-
-int cleanup_before_linux(void)
-{
-    /*
-     * this function is called just before we call linux
-     * it prepares the processor for linux
-     *
-     * we turn off caches etc ...
-     * and we set the CPU-speed to 73 MHz - see start.S for details
-     */
-
-    disable_interrupts();
-    return 0;
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-
-#ifdef CFG_SOFT_RESET
-    disable_interrupts();
-    reset_cpu(0);
-#else
-#ifdef CONFIG_DBGU
-   AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
-#endif
-#ifdef CONFIG_USART0
-   AT91PS_USART us = AT91C_BASE_US0;
-#endif
-#ifdef CONFIG_USART1
-   AT91PS_USART us = AT91C_BASE_US1;
-#endif
-   AT91PS_PIO pio = AT91C_BASE_PIOA;
-
-   /*shutdown the console to avoid strange chars during reset */
-   us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
-
-#ifdef CONFIG_AT91RM9200DK
-   /* Clear PA19 to trigger the hard reset */
-   pio->PIO_CODR = 0x00080000;
-   pio->PIO_OER  = 0x00080000;
-   pio->PIO_PER  = 0x00080000;
-#endif
-#ifdef CONFIG_CMC_PU2
-/* this is the way Linux does it */
-#define AT91C_ST_RSTEN (0x1 << 16)
-#define AT91C_ST_EXTEN (0x1 << 17)
-#define AT91C_ST_WDRST (0x1 <<  0)
-/* watchdog mode register */
-#define ST_WDMR *((unsigned long *)0xfffffd08)
-/* system clock control register */
-#define ST_CR *((unsigned long *)0xfffffd00)
-	ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
-	ST_CR = AT91C_ST_WDRST;
-   /* Never reached */
-#endif
-#endif
-   return 0;
-}
-
-void icache_enable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg | C1_IDC);
-}
-
-void icache_disable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg & ~C1_IDC);
-}
-
-int icache_status(void)
-{
-    return (read_p15_c1() & C1_IDC) != 0;
-    return 0;
-}
-
-void dcache_enable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg | C1_IDC);
-}
-
-void dcache_disable(void)
-{
-    ulong reg;
-    reg = read_p15_c1();
-    cp_delay();
-    write_p15_c1(reg & ~C1_IDC);
-}
-
-int dcache_status(void)
-{
-    return (read_p15_c1() & C1_IDC) != 0;
-    return 0;
-}
--- a/cpu/at91rm9200/start.S
+++ b/cpu/at91rm9200/start.S
@@ -1,391 +0,0 @@
-/*
- *  armboot - Startup Code for ARM720 CPU-core
- *
- *  Copyright (c) 2001	Marius Gr<EFBFBD>ger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Z<EFBFBD>pke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include "config.h"
-#include "version.h"
-
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
-	.word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
-	.word __bss_start
-
-.globl _bss_end
-_bss_end:
-	.word _end
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs     r0,cpsr
-	bic     r0,r0,#0x1f
-	orr     r0,r0,#0xd3 /* was 13 */
-	msr     cpsr,r0
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	/* scratch stack */
-/****	ldr 	r1, =0x00204000		****/
-	/* Insure word alignment */
-/****	bic     r1, r1, #3		****/
-	/* Init stack SYS	 */
-/****	mov     sp, r1			****/
-	/*
-	 * This does a lot more than just set up the memory, which
-	 * is why it's called lowlevel_init
-	 */
-	bl	lowlevel_init /* in lowlevel.S */
-
-	/*
-	 * Read/modify/write CP15 control register
-	 * disable MMU, enable I-Cache, select Asychronous Clocking Mode
-	 */
-
-	mrc     p15, 0, r0, c1, c0, 0	@ read cp15 control register (cp15 r1) in r0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x0000008f	@ clear bits 7, 3:0 (B--- WCAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00000004	@ set bit 3 (C) D-Cache
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	orr	r0, r0, #0xC0000000	@ set bits 31:30 (iA, nF)
-	mcr     p15, 0, r0, c1, c0, 0	@ write r0 in cp15 control register (cp15 r1)
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-	/*
-	 * relocate exeception table
-	 */
-	ldr	r0, =_start
-	ldr	r1, =0x0
-	mov	r2, #16
-copyex:
-	subs	r2, r2, #1
-	ldr	r3, [r0], #4
-	str	r3, [r1], #4
-	bne	copyex
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl      cpu_init_crit
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
-relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
-	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
-	ldr	r2, _armboot_start
-	ldr	r3, _bss_start
-	sub	r2, r3, r2		/* r2 <- size of armboot            */
-	add	r2, r0, r2		/* r2 <- source end address         */
-
-copy_loop:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end addreee [r2]    */
-	ble	copy_loop
-#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */
-
-	/* Set up the stack						    */
-stack_setup:
-	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CFG_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
-#ifdef CONFIG_USE_IRQ
-	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
-#endif
-	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
-
-clear_bss:
-	ldr	r0, _bss_start		/* find start of bss segment        */
-	ldr	r1, _bss_end		/* stop here                        */
-	mov 	r2, #0x00000000		/* clear                            */
-
-clbss_l:str	r2, [r0]		/* clear loop...                    */
-	add	r0, r0, #4
-	cmp	r0, r1
-	ble	clbss_l
-
-	ldr pc,_start_armboot
-
-_start_armboot: .word start_armboot
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- *************************************************************************
- */
-
-cpu_init_crit:
-	/* do nothing for now */
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-
-	ldr	r2, _armboot_start
-	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
-	ldmia	r2, {r2 - r4}                   @ get pc, cpsr, old_r0
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r4}                   @ save sp_SVC, lr_SVC, pc, cpsr, old_r
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, _armboot_start		@ setup our mode stack
-	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
-	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str     lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	msr	spsr_c, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl 	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl 	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl 	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov     pc, r0
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2003
+ * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * This file is based on mpc4200fec.c,
@@ -869,9 +869,10 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#if defined(CONFIG_ICECUBE) || defined(CONFIG_PM520)   || \
-    defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200) || \
-    defined(CONFIG_INKA4X0)
+#if defined(CONFIG_CANMB)   || defined(CONFIG_HMI1001)	|| \
+    defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0)	|| \
+    defined(CONFIG_PM520)   || defined(CONFIG_TOP5200)	|| \
+    defined(CONFIG_TQM5200)
 # ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
 # else
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -154,11 +154,11 @@ serial_setbrg(void)
 #if defined(CONFIG_MGT5100)
 	baseclk = CFG_MPC5XXX_CLKIN / 32;
 #elif defined(CONFIG_MPC5200)
-	baseclk = gd->ipb_clk / 32;
+	baseclk = (gd->ipb_clk + 16) / 32;
 #endif

 	/* set up UART divisor */
-	div = baseclk / gd->baudrate;
+	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
 	psc->ctur = div >> 8;
 	psc->ctlr = div & 0xff;
 }
--- a/cpu/mpc8220/Makefile
+++ b/cpu/mpc8220/Makefile
@@ -27,8 +27,9 @@ LIB	= lib$(CPU).a

 START	= start.o
 ASOBJS	= io.o fec_dma_tasks.o
-OBJS	= i2c.o traps.o cpu.o cpu_init.o fec.o dramSetup.o interrupts.o \
-	  loadtask.o uart.o speed.o
+OBJS	= cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
+	  interrupts.o loadtask.o speed.o \
+	  traps.o uart.o pci.o

 all:	.depend $(START) $(ASOBJS) $(LIB)

--- a/cpu/mpc8220/cpu_init.c
+++ b/cpu/mpc8220/cpu_init.c
@@ -49,13 +49,19 @@ void cpu_init_f (void)
 	portcfg->pcfg1 = 0;
 	portcfg->pcfg2 = 0;
 	portcfg->pcfg3 = 0;
+	portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG;
+	portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG;

 	/*
 	 * Flexbus Controller: configure chip selects and enable them
 	 */
 #if defined (CFG_CS0_BASE)
 	flexbus->csar0 = CFG_CS0_BASE;
+
+/* Sorcery-C can hang-up after CTRL reg initialization */
+#if defined (CFG_CS0_CTRL)
 	flexbus->cscr0 = CFG_CS0_CTRL;
+#endif
 	flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
 	__asm__ volatile ("sync");
 #endif
@@ -97,15 +103,15 @@ void cpu_init_f (void)
 	/* This section of the code cannot place in cpu_init_r(),
 	   it will cause the system to hang */
 	/* enable timebase */
-	xlbarb->config = 0x00002000;
-
 	xlbarb->addrTenTimeOut = 0x1000;
 	xlbarb->dataTenTimeOut = 0x1000;
 	xlbarb->busActTimeOut = 0x2000;

+	xlbarb->config = 0x00002000;
+
 	/* Master Priority Enable */
-	xlbarb->mastPriEn = 0x1f;
 	xlbarb->mastPriority = 0;
+	xlbarb->mastPriEn = 0xff;
 }

 /*
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
stroese	cd5b2b9941	* Patch by Stefan Roese, 5 Jul 2005: Update uc100 board PHY setup	2005-07-05 11:35:27 +00:00
wdenk	88804d19e2	* Patch by Detlev Zundel, 30 Jun 2005: Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code	2005-07-04 00:03:16 +00:00
stroese	3c71f3e8aa	* Patch by Stefan Roese, 1 Jul 2005: Fix PHY address for CATcenter board (now correct!)	2005-07-01 15:53:57 +00:00
stroese	bf41886f9d	* Patch by Stefan Roese, 30 Jun 2005: Fix PHY addresses for PPChameleon and CATcenter boards Change MAINTAINER for most esd boards	2005-06-30 13:06:07 +00:00
wdenk	342717f72a	* Fix baudrate calculation problem on MPC5200 systems * Add MPC8220 boards to MAKEALL script * Add EEPROM and RTC support for HMI1001 board * Patch by Detlev Zundel, 20 Jun 2005: Fix initialization of low active GPIO pins on inka4x0 board	2005-06-27 13:30:03 +00:00
wdenk	024447b186	Enable redundant environment, disable HW flash protection of HMI1001 board	2005-06-20 10:28:38 +00:00
wdenk	b2532eff87	* Patch by Travis Sawyer, 10 Jun 2005: Initialize allocated dev and private hw structures after their respective allocation in 440gx_enet.c * Patch by Steven Scholz, 10 Jun 2005: Fix byteorder problems with second argument of "bootm" with standalone images;	2005-06-20 10:17:34 +00:00
wdenk	a87589da74	* Add support for HMI1001 board * Disable "date" and "sntp" commands on TQM866M which has no RTC	2005-06-10 10:00:19 +00:00
wdenk	51152c173d	Fix watchdog reset problems on LWMON board	2005-06-05 20:30:43 +00:00
wdenk	ba91e26a19	Patch by Juergen Selent, 17 May 2005: Add support for Funkwerk VoVPN gateway module.	2005-05-30 23:55:42 +00:00
wdenk	2eab48f511	* Extend burst mode RAM test program to take a loop count (0 = infinite) * Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on those boards that use it.	2005-05-23 10:49:50 +00:00
wdenk	16b013e750	Patch by Greg Ungerer, 19 May 2005: add support for the OpenGear CM4008 board	2005-05-19 22:46:33 +00:00
wdenk	121fc64022	Patch by Greg Ungerer, 19 May 2005: add support for the OpenGear CM4008 board	2005-05-19 22:46:33 +00:00
wdenk	3a574cbe72	* Patch by Greg Ungerer, 19 May 2005: add support for the KS8695P (ARM 922 based) CPU * Patch by Steven Scholz, 19 May 2005: Add support for CONFIG_SERIAL_TAG on ARM boards	2005-05-19 22:39:42 +00:00
wdenk	7680c140af	Add PCI support for Sorcery board. Code cleanup (especially Sorcery / Alaska / Yukon serial driver).	2005-05-16 15:23:22 +00:00
wdenk	c01766307c	Fix compile problems caused by new burst mode SDRAM test; make port pins to trigger logic analyzer configurable	2005-05-16 14:19:49 +00:00
wdenk	343117bf12	Fix timer handling on MPC85xx systems	2005-05-13 22:49:36 +00:00
wdenk	9dd41a7b0c	* Fix debug code in omap5912osk flash driver * Add support for MPC8247 based "IDS8247" board.	2005-05-12 22:48:09 +00:00
wdenk	d44e14b5fc	Add support for 2 x TSEC interfaces on the TQM8540 board.	2005-05-10 15:51:35 +00:00
wdenk	ed16fefcba	On LWMON we must use the watchdog to reset the board as the CPU genereated HRESET pulse is too short to reset the external circuitry.	2005-05-09 10:17:32 +00:00
wdenk	931da93e0f	Add test tool to exercise SDRAM accesses in burst mode (as standalone program, MPC8xx/PowerPC only)	2005-05-07 19:06:32 +00:00
wdenk	412babe304	It's better to handle LZO and LZARI compression mdoes for JFFS2 with a single #define.	2005-05-05 09:51:44 +00:00
wdenk	60fc6cbbb7	Increase CFG_MONITOR_LEN for Rattler board to match actual code size.	2005-05-05 09:13:21 +00:00
wdenk	07cc099941	Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of March 13, 2005); new configuration options CONFIG_JFFS2_LZO and CONFIG_JFFS2_LZARI are added. Both are undefined by default.	2005-05-05 00:04:14 +00:00
wdenk	cf8bc5773c	Fix problem with symbolic links in JFFS2 code.	2005-05-04 23:50:54 +00:00
wdenk	a710d4be80	Use linker ASSERT statement to prevent undetected overlapping of sections on PPChameleon board; other boards might use this, too.	2005-05-04 23:44:59 +00:00
wdenk	90dc67049d	README: add explanation about patch policy net/net.c: fix indentation	2005-05-03 14:12:25 +00:00
stroese	434cf850a4	* Patch by Stefan Roese, 03 May 2005: Update for P3G4 Fix problems in cmd_universe.c * Patch by Matthias Fuchs, 03 May 2005: Added missing variable declaration in cmd_nand.c Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram	2005-05-03 06:19:57 +00:00
stroese	81b83c9ecc	* Patch by Matthias Fuchs, 03 May 2005: Added missing variable declaration in cmd_nand.c Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram	2005-05-03 06:12:20 +00:00
stroese	dcb2f95a60	* Patch by Stefan Roese, 03 May 2005: Update for P3G4 Fix problems in cmd_universe.c	2005-05-03 06:06:41 +00:00
wdenk	9f709b6cee	Fix INKA4x0: use CS1 as gpio_wkup_6 output	2005-04-22 15:09:09 +00:00
wdenk	a63109281a	Fix bug in the SDRAM initialization code for canmb, IceCube and PM520 boards. Fix PHY address for canmb board.	2005-04-21 21:10:22 +00:00
wdenk	7cc1438d43	get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition	2005-04-20 14:38:59 +00:00
wdenk	ec0ca73190	Cleanup serial console baudrate calculation on AT91RM9200	2005-04-20 12:36:05 +00:00
wdenk	b2323ea6f9	Auto-size RAM on canmb board. Cleanup.	2005-04-20 09:28:54 +00:00
stroese	fddae7b811	* Patch by Matthias Fuchs, 18 Apr 2005: Make PCI target address spaces on PMC405 and CPCI405 boards configurable via environment variables	2005-04-20 06:52:40 +00:00
wdenk	5e5f9ed254	Add support for canmb board	2005-04-13 23:15:10 +00:00
stroese	4c2a366db3	* Patch by Stefan Roese, 13 Apr 2005: Update for esd apc405	2005-04-13 10:08:39 +00:00
stroese	04e93ec979	Update for esd apc405	2005-04-13 10:06:07 +00:00
wdenk	2a8af18738	* Fixes for TQM8560 board: - fix clock rates - remove debug messages - fix flash sector protection * Patch by Steven Scholz, 07 Apr 2005: Fix warning in cpu/arm920t/at91rm9200/i2c.c	2005-04-13 10:02:42 +00:00
wdenk	e694e08a8b	Cleanup	2005-04-07 22:41:05 +00:00
wdenk	b77fad3b25	* Patch by Steven Scholz, 07 Apr 2005: Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C * Patch by Steven Scholz, 07 Apr 2005: Fix compiler warning in altera.c * Patch by Ladislav Michl, 06 Apr 2005: Fix voiceblue configuration.	2005-04-07 22:36:40 +00:00
stroese	7ec2550238	* Patch by Stefan Roese, 06 Apr 2005: Updates for OCOTEA board: - Changed U-Boot size from 512kByte to 256kByte - Fixed flash driver to support boot from soldered user flash - Added README for switch from PIBS firmware to U-Boot	2005-04-07 05:35:12 +00:00
stroese	0a7c5391a0	Add PPC440GX Revision C	2005-04-07 05:33:41 +00:00
stroese	68e0236f7e	* Patch by Travis Sawyer, 05 Apr 2005: - Change timer frequency for ppc 440 from 10 ms to 1 ms. Problem found by Andrew Wozniak.	2005-04-07 05:32:44 +00:00
wdenk	a85f9f21aa	Patch by Steven Scholz, 06 Apr 2005: - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200	2005-04-06 13:52:31 +00:00
wdenk	20787e23b8	* Patches by Robert Whaley, 29 Nov 2004: - update the pxa-regs.h file for PXA27x chips - add PXA27x based ADSVIX board - add support for MMC on PXA27x processors * Patch by Andrew E. Mileski, 28 Nov 2004: Fix PPC4xx SPD SDRAM detection bug * Patch by Hiroshi Ito, 26 Nov 2004: Fix logic of "test -z" and "test -n" commands	2005-04-06 00:04:16 +00:00
wdenk	3c2b3d454d	* Patch by Ladislav Michl, 05 Apr 2005: Add support for VoiceBlue board. * Patch by Ladislav Michl, 05 Apr 2005: Fix netboot_common() prototypes. * Cleanup.	2005-04-05 23:32:21 +00:00
wdenk	b304c96871	Patches by Steven Scholz, 05 Apr 2005: - Use i.MX watchdog timer for reset_cpu() - Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ (now in interupts.c)	2005-04-05 22:30:50 +00:00
wdenk	12b43d515c	Add support for MPC8220 based "sorcery" board.	2005-04-05 21:57:18 +00:00