Use the new ACPI writer to write the base tables at the start of the area,
moving this code from the x86 implementation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use the new ACPI writer to write the ACPI tables. At present this is all
done in one monolithic function. Future work will split this out.
Unfortunately the QFW write_acpi_tables() function conflicts with the
'writer' version, so disable that for sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present acpi_setup_base_tables() both sets up the ACPI context and
writes out the base tables.
We want to use an ACPI writer to write the base tables, so split this
function into two, with acpi_setup_ctx() doing the context set, and
acpi_setup_base_tables() just doing the base tables.
Disable the writer's write_acpi_tables() function for now, to avoid
build errors. It is enabled in a following patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rather than keying everything off ACPIGEN, use the main
GENERATE_ACPI_TABLE option to determine whether the core ACPI code
is included. Make sure these option are not enabled in SPL/TPL since we
never generate tables there.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this option is missing a header file, a function prototype and
the qfw driver needs a header included.
Fix these problems so we can enable this option on sandbox. This will
increase the build coverage.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is enabled for quite a few boards which don't create ACPI tables.
Tidy this up by dropping the option for some boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some ARM boards are using ACPI now. It seems that U-Boot should support
this method. Add ARM to the list of archs which can generate ACPI tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow this to be used on any arch. Also convert to using macros so that
we can check the CONFIG option in C code.
Signed-off-by: Simon Glass <sjg@chromium.org>
These have sadly found their way to ARM now. Allow any arch to support
generating ACPI tables.
Disable this for the tools build.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since commit 9855034397 ("fdt: Don't call board_fdt_blob_setup()
without OF_BOARD") board_fdt_blob_setup() is no more called on
STM32MP platforms in trusted boot which hangs during boot process.
Enable OF_BOARD flag to fix this issue.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Add the partition name and remove the line number in error messages
of treat_partition_list() to provide correct information to user of
STM32CubeProgrammer.
The "line number" value was confusing because it is incorrect here;
the index in part_array[] is not aligned with the line number in
the parsed Layout file, because the empty lines and the lines beginning
by '#' are skipped during the first parsing in parse_flash_layout().
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias and
PHY reset GPIO are now reinstated in SoM u-boot dtsi.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Synchronize DH DHCOR DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias is
now reinstated in SoM u-boot dtsi, the PHY reset GPIO is reinstated in AV96
u-boot dtsi.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Device tree alignment with Linux kernel v5.16-rc5
- ARM: dts: stm32: set otg-rev on stm32mp151
- ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: fix SAI sub nodes register range
- ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkx
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Default value for CONFIG_SYS_BOOTCOUNT_SINGLEWORD and
CONFIG_SYS_BOOTCOUNT_ADDR are only needed when
CONFIG_BOOTCOUNT_GENERIC is used.
This patch avoids to define these configs when an other bootcount backend
is activated, for example for CONFIG_BOOTCOUNT_ENV.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Today the bootcount is not managed by the Linux kernel for STM32MP15 as
we don't have driver to update the used backup register in TAMP and the
recovery command still executes the normal bootcmd with
'altbootcmd=run bootcmd'.
So the bootcount feature is never used, the config CONFIG_BOOTCOUNT_LIMIT
and the associated environment variable 'altbootcmd' can be removed to
reduce the U-Boot size.
Each boards can re-enable this feature later in their defconfig, if it is
needed, with the expected backend, for example CONFIG_BOOTCOUNT_GENERIC
or CONFIG_BOOTCOUNT_ENV.
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This patch configures U-Boot SPL for DHCOR SoM to permit DFU upload of
SPL and subsequent u-boot.itb for recovery or commissioning purposes.
To start U-Boot on DHCOR based board, e.g. Avenger96, proceed as follows:
- Install dfu-util on the host PC (in debian this is package 'dfu-util')
- Power off the Avenger96 board.
- Connect both USB-serial console and USB-OTG microB ports to host PC.
- Switch Avenger96 to USB boot mode -- BOOT0..2 switches all set to 0.
- Power on the Avenger96 board.
- Verify using '$ dmesg' that a new device has been detected as follows:
New USB device found, idVendor=0483, idProduct=df11, bcdDevice= 2.00
New USB device strings: Mfr=1, Product=2, SerialNumber=3
Product: DFU in HS Mode @Device ID /0x500, @Revision ID /0x0000
Manufacturer: STMicroelectronics
- Upload U-Boot SPL:
$ dfu-util -a 1 -D u-boot-spl.stm32
- Upload U-Boot proper:
$ dfu-util -a 0 -D u-boot.itb
- At this point, SPL will wait for user to press "Ctrl-C" on serial
console. When ready to interact with U-Boot, press Ctrl-C to start
the bootloader.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
In case the SoC reports the boot device type is USB, it means the SPL was
loaded via BootROM DFU mode. Currently the spl_boot_device() returns boot
device as USB host, change it to DFU instead, so the SPL can continue the
DFU boot and load U-Boot via DFU.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
When booting from QSPI, the boot ROM appears to mux the QSPI
pins, but it's not guaranteed to be setup when booting from
eMMC. Fix this by explicitly configuring the pinmux.
Signed-off-by: Adam Ford <aford173@gmail.com>
Documentation:
* describe printf() format codes
UEFI
* enable more algorithms for UEFI image verification, e.g. SHA256-RSA2048
General
* simplify printing short texts for GUIDs
* provide a unit test for printing GUIDs
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Merge tag 'efi-2022-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-04-rc1-2
Documentation:
* describe printf() format codes
UEFI
* enable more algorithms for UEFI image verification, e.g. SHA256-RSA2048
General
* simplify printing short texts for GUIDs
* provide a unit test for printing GUIDs
This converts the following to Kconfig:
CONFIG_AT91_EFLASH
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Eugen Hristev <eugen.hristev@microchip.com>
- fdt_support: Add fdt_for_each_node_by_compatible() helper macro
(Marek)
- turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob (Pali)
- pci_mvebu: Add support for Kirkwood PCIe controllers (Pali)
- SPL: More verifications for kwbimage in SPL (Pali)
- mvebu: Remove comphy_update_map() (Pali)
- Minor misc stuff
Use the preferred
if (IS_ENABLED(X))
instead of
#ifdef X
where possible.
There are still places where this is not possible or is more complicated
to convert in this file. Leave those be for now.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Checkpatch warns about using uint32/16/8_t instead of u32/16/8.
Use the preferred types.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Print the wrong srcaddr (spl_image->offset) in error message also for
SATA case.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Last 4 bytes of kwbimage boot image is checksum. Verify it via the new
spl_check_board_image() function which is called by U-Boot SPL after
loading kwbimage.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Each boot mode has its own kwbimage specified by blockid. So check that
kwbimage is valid by blockid.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Add parameter spl_boot_device to spl_parse_board_header(), which allows
the implementations to see from which device we are booting and do
boot-device-specific checks of the image header.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
There are certain restrictions for kwbimage offset and blocksize.
Validate them.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base
address of PCIe mappings. Size of PCIe windows is not defined in any macro
yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE
macros.
Kirkwood arch code already maps mbus windows for io and mem, so avoid
calling mvebu_mbus_add_window_by_id() function which would try to do
duplicate window mapping.
Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible
string, so mark pci_mvebu.c driver as compatible for it.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Add macro fdt_for_each_node_by_compatible() to allow iterating over
fdt nodes by compatible string.
Convert various usages of
off = fdt_node_offset_by_compatible(fdt, start, compat);
while (off > 0) {
code();
off = fdt_node_offset_by_compatible(fdt, off, compat);
}
and similar, to
fdt_for_each_node_by_compatible(off, fdt, start, compat)
code();
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
gpio:
- Add modepin driver
net:
- Save random mac addresses to eth variable
zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses
zynqmp clk:
- Fix clock handling for gem and usb
phy:
- Add zynqmp phy/serdes driver
serial:
- Add one missing compatible string
microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups
zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver
versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain
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Merge tag 'xilinx-for-v2022.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.04-rc1
gpio:
- Add modepin driver
net:
- Save random mac addresses to eth variable
zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses
zynqmp clk:
- Fix clock handling for gem and usb
phy:
- Add zynqmp phy/serdes driver
serial:
- Add one missing compatible string
microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups
zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver
versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain
CONFIG_PARTITION_TYPE_GUID=y is needed for testing some GPT related
functionality.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
There are 4 MDIO bus controllers in AST2600 SOC. Each of them can
connect to one or more PHY chips and is flexible to work with the 4 MAC
devices in AST2600. On AST2600 EVB, MDIO 0,1,2,3 connect to the PHY
chips used by MAC 0,1,2,3 respectively.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This patch adds node for mmc/sd controller found on Action Semi OWL
S700 SoC.
Since, upstream Linux binding has not been merged for S700 MMC/SD
controller, Changes are put in u-boot specific dtsi file.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This Synchronizes the Actions Semi S700 SoC DT changes from
commit "g58e1100fdc59" ("Linux v5.16-rc3").
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
asm/mmu.h include is currently guarded by CONFIG_ADDR_MAP ifdef because
the header is only present on arm and powerpc. In order to remove the
dependency on this header and the associated ifdef, move init_addr_map()
declaration to init.h, since it is only called during the common init
sequence.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Add a return value to init_addr_map and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Commit 98f705c9ce ("powerpc: remove 4xx support") removed (in 2017) the
last code that made use of bedbug debugger support. Since there aren't
any boards left that define either CONFIG_CMD_BEDBUG or a real
bedbug_init(), drop this feature from u-boot.
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board
specific function designed for this purpose.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
- Let am335x_evm use the CPSW or PRUSS ethernet.
- Implement timer_get_boot_us in the omap timer driver
- gpmc bitflip, QSPI clock calculation on am437x, da8xx_gpio bugfixes
- Assorted K3 updates
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Merge tag 'u-boot-at91-2022.04-b' of https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-at91 features for the 2022.04 cycle:
This small feature set includes few changes for sama7g5 and sama7g5ek:
turn blue led on at boot, changes required for the Rev4 of the board,
better sync with the Linux DT with regards to the new DT nodes.
The rev4 of the board sama7g5ek has the eeproms on flexcom8 instead of
flexcom1.
Initialize flexcom8 with required pincontrol and move the eeproms accordingly.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add Flexcom8 node with required referenced nodes as phandles.
Since Flexcom8 is present in Linux, take the node exactly as-is from Linux.
Some nodes are referenced in Linux as phandles, the dma and the gic.
Add them as well to the file, even if they are unused by Uboot.
This is a step towards having the U-boot DT equivalent with the DT in Linux.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This driver supports power domains for the power management
controller found on Apple SoCs.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These are necessary to make sure the power domains needed for the
serial console are availble in the pre-relocation phase.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This synchronizes the device trees with those that are in the
process of being upstreamed into Linux. This is mostly the
current state of the device trees on the asahilinux branch
with a few extra bits used by OpenBSD. This includes device
trees for machines that were still missing.
There are still some differences that will hopefully be resolved
soon.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver
is enabled. Since driver is modeled as UCLASS_MISC, we need to
explicitly probe the driver. Use common misc_init_r() that entire
K3 family of SoCs.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed
in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image
directly on OSPI flash via MMIO window. So, copy the image to internal
on-chip RAM before parsing the image.
Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform
and thus cannot reside in OSPI/xSPI and needs to be copied over to
internal OCRAM.
This unblocks OSPI/xSPI boot on HS platforms
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Currently only the PADCFG registers of the main domain are unlocked.
Also unlock PADCFG registers of MCU domain, so MCU pin muxing can be configured by u-boot or Linux.
Signed-off-by: Michael Liebert <liebert@ibv-augsburg.de>
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Nishanth Menon <nm@ti.com>
Documentation:
* Fix building HTML documentation of readthedocs.io
* Add ARM Juno board documentation
* Build requirements for Alpine Linux
* Include DM headers in API documentation
UEFI:
* Fix section alignment of EFI binaries
* Fix header length of RISC-V EFI binaries allowing to run them on EDK II
* Remove kaslr-seed from device tree if the EFI_RNG_PROTOCOL is provided
Other:
* Let 'part list' show all 128 GPT partitions
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Merge tag 'efi-2022-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-04-rc1
Documentation:
* Fix building HTML documentation of readthedocs.io
* Add ARM Juno board documentation
* Build requirements for Alpine Linux
* Include DM headers in API documentation
UEFI:
* Fix section alignment of EFI binaries
* Fix header length of RISC-V EFI binaries allowing to run them on EDK II
* Remove kaslr-seed from device tree if the EFI_RNG_PROTOCOL is provided
Other:
* Let 'part list' show all 128 GPT partitions
At present some 32-bit settings are used with the 64-bit app. Fix this by
separating out the two cases.
Be careful not to break the 64-bit payload, which needs to build a 64-bit
EFI stub with a 32-bit U-Boot.
Signed-off-by: Christian Melki <christian.melki@t2data.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
That script is not intended for use with EFI, so update the logic to avoid
using it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Christian Melki <christian.melki@t2data.com>
Add an empty CPU init function to avoid fiddling with low-level CPU
features in the app. Set up the C runtime correctly for 64-bit use
and avoid clearing BSS, since this is done by EFI when U-Boot is loaded.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present this function requires a pointer to struct efi_entry_memmap
but the only field used in there is the desc_size. We want to be able
to use it from the app, so update it to use desc_size directly.
Signed-off-by: Simon Glass <sjg@chromium.org>
The alignment of sections in the EFI binaries generated by U-Boot is
incorrect.
According to the PE-COFF specification [1] the minimum value for
FileAlignment is 512. If the value of SectionAlignment is
less then the page size, it must equal FileAlignment.
Let's set both values to 512 for the ARM and RISC-V architectures.
[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
EDK II refuses to load the EFI binaries created by U-Boot.
The reason is an incorrect PE-COFF header. The number of
data directories does not match NumberOfRvaAndSizes.
This leads to a failed consistency check in
PeCoffLoaderGetPeHeader():
SizeOfOptionalHeader - HeaderWithoutDataDir) !=
NumberOfRvaAndSizes * sizeof(DATA_DIRECTORY))
Fixes: 9afaeec6ef ("riscv: Complete efi header for RV32/64")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Apple's ARMv8 cores don't implement EL3 and therefore don't
provide a PSCI implementation. So don't attempt to use
PSCI to reset on machines using Apple SoCs.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
BootROMs on pre-A38x SoCs enabled its output on UART by default, but A38x'
BootROM has its output on UART disabled by default.
To enable BootROM output on A38x SoC, it is required to set DEBUG flag
(which only enables BootROM output and nothing more) in kwbimage. For UART
images this DEBUG flag is ignored by BootROM.
Enable kwbimage DEBUG flag for all A38x boards.
With this change BootROM prints the following (success) information on UART
before booting U-Boot kwbimage:
BootROM - 1.73
Booting from SPI flash
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
U-Boot SPL for mvebu platform is not compiled as position independent.
Therefore it is required to instruct BootROM to load U-Boot SPL at the
correct address. Loading of kwbimage binary code at specific address can be
now achieved by the new LOAD_ADDRESS token as part of BINARY command in
kwbimage config file.
Update mvebu Makefile to put value of $(CONFIG_SPL_TEXT_BASE) into
LOAD_ADDRESS token when generating kwbimage.cfg from kwbimage.cfg.in.
It is required to update regex for sed to find replacement tokens at any
position on a line in kwbimage config file and not only at the beginning of
the line. This is because LOAD_ADDRESS is specified at the end of line
containing the BINARY command.
It looks like all Armada boards set CONFIG_SPL_TEXT_BASE to value
0x40004030 or 0x40000030. Why this value? It is because main kwbimage
header is at address 0x40004030 or 0x40000000 and it is 32 bytes long.
After the main header there is the binary header, which consist of 1 byte
for type, 3 bytes for size, 1 byte for number of arguments, 3 reserved
bytes and then 4 bytes for each argument. After these arguments comes the
executable code.
So arguments start at address 0x40004028 or 0x40000028. Before commit
e6571f38c9 ("arm: mvebu: Remove dummy BIN header arguments for SPL
binary") there were two (dummy) arguments, which resulted in load address
of 0x40004030 or 0x40000030, always. After that commit (which removed dummy
arguments), load address stayed same due to the 128-bit alignment done by
mkimage.
This patch now reflects the dependency between $(CONFIG_SPL_TEXT_BASE),
load address and dummy kwbimage arguments, and allows the user to adjust
$(CONFIG_SPL_TEXT_BASE) config option to some other value.
For unsupported values, when mkimage/kwbimage cannot set chosen load address
as specified by $(CONFIG_SPL_TEXT_BASE), the build process now fails,
instead of silently generating non-working kwbimage.
Removal of this alignment between $(CONFIG_SPL_TEXT_BASE) and LOAD_ADDRESS
can only be done by compiling U-Boot SPL as position independent. But this
currently is not possible for 32-bit ARM version of U-Boot SPL.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Usage of $(call cmd,...) is standard way to call other commands which
generate things.
It also has the advantage of printing build information in the form
KWBCFG arch/arm/mach-mvebu/kwbimage.cfg
if verbosity is disabled, and printing the build command otherwise.
Note that the '#' character needs to be escaped in Makefile when used as
value for make variable assignment.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
The DT properties for the "enable-arbiter" and "keep-config" config
knobs were previously named inconsistently:
- The u-boot driver used "nand-enable-arbiter" and "nand-keep-config"
names, without Marvell prefixes.
- The Linux driver uses "marvell,nand-keep-config" ("enable-arbiter"
does not exist anymore in recent kernels, but it also used to be
"marvell,nand-enable-arbiter").
- The device trees almost all use "marvell," prefixed names, except for
one single instance of "nand-enable-arbiter" without vendor prefix.
This commit standardizes on the vendor prefixed version, making the
u-boot driver read from DT props "marvell,nand-enable-arbiter" and
"marvell,nand-keep-config". The one device tree using the unprefixed
version is also changed to use the new naming.
This has the side effect of making the previously no-op "marvell,"
config knobs already present in some DTs actually do something. This was
likely the original intention of the DT authors, but note that this
commit was not tested on every single impacted board.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.
Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.
Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.
Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.
This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.
Signed-off-by: Pali Rohár <pali@kernel.org>
Enabling and disabling PCIe ports is done via address space of system
controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register
for enabling and disabling some or more PCIe ports. Correct mapping needs
to be set in particular DTS files.
DT API for mvebu-reset is prepared for implementing resets also for other
HW blocks, but currently only PCIe is implemented via index 0.
Currently this driver is not used as PCIe ports are automatically enabled
by SerDes code executed by U-Boot SPL. But this will change in followup
patches.
Signed-off-by: Pali Rohár <pali@kernel.org>
Do not call pci_set_region() for resources which were not properly mapped.
This prevents U-Boot to access unmapped memory space.
Update MBUS_PCI_MEM_SIZE and MBUS_PCI_IO_SIZE macros to cover all PCIe MEM
and IO ranges. Previously these macros covered only address ranges for the
first PCIe port. Between MBUS_PCI_IO_BASE and MBUS_PCI_MEM_BASE there is
space for six 128 MB long address ranges. So set MBUS_PCI_MEM_SIZE to value
of 6*128 MB. Similarly set MBUS_PCI_IO_SIZE to 6*64 KB.
Function resource_size() returns zero when start address is 0 and end
address is -1. So set invalid resources to these values to indicate that
resource has no mapping.
Split global PCIe MEM and IO resources (defined by MBUS_PCI_*_* macros)
into PCIe ports in mvebu_pcie_bind() function which allocates per-port
based struct mvebu_pcie, instead of using global state variables
mvebu_pcie_membase and mvebu_pcie_iobase. This makes pci_mvebu.c driver
independent of global static variables (which store the state of
allocation) and allows to bind and unbind the driver more times.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
The only user of board_pex_config() weak function is A385 controlcenterdc
board. It looks like that code in its board_pex_config() function needs to
be executed after PCIe link is up. Therefore put this code into
spl_board_init() function which is called after a38x serdes initialization,
and therefore it is after the serdes hws_pex_config() function finishes
(which is the state before this change).
With this change completely remove board_pex_config() function as it is not
used anymore.
Signed-off-by: Pali Rohár <pali@kernel.org>
U-Boot define loff_t as long long. But the header
/usr/include/linux/types.h may not define it.
This has lead to a build error on Alpine Linux.
So let's use long long instead of loff_t for
the size parameter of function os_get_filesize().
Reported-by: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rely on the new watchdog timer driver and the sysreset uclass to
reset the system. This gets rid of hard-coded addresses and
should work on systems based on the new M1 Pro and M1 Max SoCs
as well.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
Add a node for the watchdog timer based on the proposed Linux
device tree bindings.
Remove the old reboot node which was a watchdog timert node in
disguise using a preliminary device tree binding.
Signed-off-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
a7y17lte is called SM-A720F, and a3y17lte SM-A320F. a3y17lte also
should select PINCTRL_EXYNOS78x0, not the (non-existent)
PINCTRL_EXYNOS7880, and it has an Exynos 7870 SoC and not 7880.
Fixes: 3e2095e960 ("board: samsung: add support for Galaxy A series
of 2017 (a5y17lte)")
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
mcf5445x platform uses standard format of Config Address for PCI
Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS().
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
x86 platform uses standard format of Config Address for PCI Configuration
Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS().
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
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Merge tag 'u-boot-amlogic-20220107' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
All i.MX8MQ boards have been converted to binman, which makes it
necessary to flash both flash.bin and u-boot.itb to get a bootable
system. Prior to the conversion, only flash.bin was needed.
Such new requirement breaks existing distro mechanisms to generate the
final binary because the extra u-boot.itb is now required.
Generate a final flash.bin that can be used again as a single bootable
binary to keep the original behavior.
After this change the SPL binary is called spl.bin, which is a more
descriptive name for its purpose, and can still be used standalone (for
example, for secure boot purposes).
Also update imx8mq_evk.rst to remove the u-boot.itb copy step.
This is a cherry-pick of 028abfd9b1 ("imx8mm-evk: Generate a single
bootable flash.bin again") adjusted to apply to i.MX8MQ.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
CMD_DM is useful for showing the whole DM tree.
Enable it via "imply CMD_DM".
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
The binman node is part of the imx8mm-u-boot.dtsi file which
is duplicated in imx8mm-kontron-n801x-s-u-boot.dtsi and causes
a build error. Remove the duplicate.
Fixes: 3cbb31f0e848 ("arm64: dts: imx8mm: use common binman configuration")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
