Synchronise device tree with linux v6.1-rc3.
Note: Nowadays, the intent is for them regular device trees to just be
synchronised from them Linux kernel device trees and any and all U-Boot
specific changes need to go into the -u-boot.dtsi device tree include
files which BTW get included automatically by the U-Boot build system.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Migrate to using automatic build system included -u-boot.dtsi device
tree include files.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Tested-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
The IMX8M based Venice boards all have device-tree fec nodes that
use proper dt with a phy-handle pointing to a phy with reg assigned
to the proper phy address.
There is no need to keep using the CONFIG_FEC_MXC_PHYADDR hack when
a proper dt is used - remove it.
This was previously done in commit 400eebf10d
("configs: imx8m{m, n}_venice: remove unneeded CONFIG_FEC_MXC_PHYADDR")
but got clobbered by commit 6889412ad5
("Convert CONFIG_SYS_BARGSIZE to Kconfig")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
remove unused ifdef left behind after commit ca3369df71
("configs: drop CONFIG_SPL_ABORT_ON_RAW_IMAGE")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
commit 0543a1ed27 ("imx8m: fixup thermal trips") moved updating the
thermal trip points to all IMX8M so we can remove it from our board
specific dt config.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Enable insertion of version variable into U-Boot environment on DHSOM,
to make it possible to check U-Boot version e.g. in U-Boot scripts.
Signed-off-by: Marek Vasut <marex@denx.de>
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction
with the MSC SM2-MB-EP1 Mini-ITX Carrier Board.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
The description claims that the device is probed but it isn't.
Add the device_probe() call.
Also consolidate the iteration into one function.
Fixes: 8a5cbc065d ("dm: blk: Use uclass_find_first/next_device() in blk_first/next_device()")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Update the sandbox implementation to use UCLASS_HOST and adjust all
the pieces to continue to work:
- Update the 'host' command to use the new API
- Replace various uses of UCLASS_ROOT with UCLASS_HOST
- Disable test_eficonfig since it doesn't work (this should have a unit
test to allow this to be debugged)
- Update the blk test to use the new API
- Drop the old header file
Unfortunately it does not seem to be possible to split this change up
further.
Signed-off-by: Simon Glass <sjg@chromium.org>
Create a block driver for the new HOST uclass. This handles attaching and
detaching host files.
For now the uclass is not used but this will be plumbed in with future
patches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sandbox supports block devices which can access files on the host machine.
At present there is no uclass for this. The devices are attached to the
root devic. The block-device type is therefore set to UCLASS_ROOT which
is confusing.
Block devices should be attached to a 'media' device instead, something
which handles access to the actual media and provides the block driver
for the block device.
Create a new uclass to handle this. It supports two operations, to attach
and detach a file on the host machine.
For now this is not fully plumbed in.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function now finds its block-device child by looking for a child
device of the correct uclass (UCLASS_BLK). It cannot produce a device of
any other type, so drop the superfluous check.
Provide a version which does not probe the device, since that is often
needed when setting up the device's platdata.
Also fix up the function's comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
When running unit tests, some may have side effects which cause a
subsequent test to break. This can sometimes be seen when using 'ut dm'
or similar.
Add a new argument which allows a particular (failing) test to be run
immediately after a certain number of tests have run. This allows the
test causing the failure to be determined.
Update the documentation also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a 'ut info' command to show the number of suites and tests. This is
useful to get a feel for the scale of the tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sort this and put the command summary at the top instead of the bottom.
Adjust it so that the newlines are at the start of the strings, so that
there is not a blank line at the end.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some tests access data in block devices and so cause the cache to fill
up. This results in memory being allocated.
Some tests check the malloc usage at the beginning and then again at the
end, to ensure there is no memory leak caused by the test. The block cache
makes this difficult, since the any test may cause entries to be allocated
or even freed, if the cache becomes full.
It is simpler to clear the block cache after each test. This ensures that
it will not introduce noise in tests which check malloc usage.
Add the logic to clear the cache, using the existing blkcache_invalidate()
function. Drop the duplicate code at the same time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tidy this up so that pylint is happy. Use hex for the 1MB size and make
sure it is not a floating-point value.
Add a little main program to allow the code to be tried out, since at
present is only called from a long-running test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add the documentation to avoid a warning with 'make htmldocs'.
Fixes: 10107efedd ("sandbox: add SIGALRM-based watchdog device")
Signed-off-by: Simon Glass <sjg@chromium.org>
The support added later in this series tweaks the PMIC voltages in the
SPL. Enable support for the rn5t567 in SPL builds to allow this to be done
cleanly.
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Add support for the rn5t568 PMIC to the rn5t567 driver.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Jaehoon Chung <j80.chung@samsung.com>
The downstream U-Boot distributed by Beacon stores the environment
in the eMMC and the end of partition 2. This allow the environment
to stay on the SOM regardless of the boot source.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
In order to boot over USB, the device tree needs to enable
a few extra nodes in SPL. Since the USB driver has the
ability to detect host/device, the dr_mode can be removed
from the device tree since it needs to act as a device when
booting and OTG is the default mode. Add USB boot support
to spl_board_boot_device and enable the corresponding config
options.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
There are a few functions which are not essential for use in
SPL, but they take up enough space to make other preferred
features not fit. Remove the extras.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit before initializing LPDDR4
or it will be running out of spec.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
If the bd718x7 is required, but PMIC_CHILDREN is disabled, this
driver throws a compile error. Fix this by putting the function
to bind children into an if-statement checking for PMIC_CHILDREN.
Allowing PMIC_CHILDREN to be disabled in SPL saves some space and
still permits some read/write functions to access the PMIC in
early startup.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
The e10133 workaround was broken in two places:
- The code intended to temporarily mask all interrupts in GPC_IMRx_CORE0.
While the old register values were saved, the actual masking was
missing.
- imx_udelay() expects the system counter to run at its base frequency,
but the system counter is switched to a lower frequency earlier in
psci_system_suspend(), leading to a much longer delay than intended.
Replace the call with an equivalent loop (linux-imx 5.15 does the same)
This fixes the SoC hanging forever when there was already a wakeup IRQ
pending while suspending.
Fixes: 57b620255e ("imx: mx7: add system suspend/resume support")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
This enables armv8 crypto extension usage for SHA1/SHA256.
Which speed up sha1/sha256 operations, about 10x faster with
a imx8mm evk for a 20MiB kernel hash verification (12ms vs 165ms).
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
