arm: imx8mp: Initial MSC SM2S iMX8MP support
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Martyn Welch
Stefano Babic
parent
e055457759
commit
c8f3402ad2
@ -413,6 +413,15 @@ F: drivers/timer/atmel_tcb_timer.c
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F: include/dt-bindings/mfd/atmel-flexcom.h
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F: drivers/timer/mchp-pit64b-timer.c
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ARM MSC SM2S IMX8MP SOM
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M: Martyn Welch <martyn.welch@collabora.com>
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M: Ian Ray <ian.ray@ge.com>
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S: Maintained
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F: arch/arm/dts/imx8mp-msc-sm2s*
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F: board/msc/sm2s_imx8mp/
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F: configs/msc_sm2s_imx8mp_defconfig
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F: include/configs/msc_sm2s_imx8mp.h
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ARM NEXELL S5P4418
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M: Stefan Bosch <stefan_b@posteo.net>
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S: Maintained
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@ -979,6 +979,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mp-dhcom-pdk2.dtb \
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imx8mp-evk.dtb \
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imx8mp-icore-mx8mp-edimm2.2.dtb \
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imx8mp-msc-sm2s.dtb \
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imx8mp-phyboard-pollux-rdk.dtb \
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imx8mp-venice.dtb \
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imx8mp-venice-gw74xx.dtb \
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65
arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
Normal file
65
arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
Normal file
@ -0,0 +1,65 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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model = "MSC SM2S-IMX8MPLUS";
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compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp";
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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u-boot,dm-spl;
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};
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};
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®_usdhc2_vmmc {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&i2c1 {
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u-boot,dm-spl;
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};
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&i2c2 {
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u-boot,dm-spl;
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};
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&i2c3 {
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u-boot,dm-spl;
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};
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&i2c4 {
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u-boot,dm-spl;
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};
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&i2c5 {
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u-boot,dm-spl;
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};
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&i2c6 {
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u-boot,dm-spl;
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};
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&pinctrl_i2c6 {
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u-boot,dm-spl;
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};
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&pmic {
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u-boot,dm-spl;
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};
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820
arch/arm/dts/imx8mp-msc-sm2s.dts
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820
arch/arm/dts/imx8mp-msc-sm2s.dts
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@ -0,0 +1,820 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Avnet Embedded GmbH
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*/
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/dts-v1/;
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#include "imx8mp.dtsi"
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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aliases {
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rtc0 = &sys_rtc;
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rtc1 = &snvs_rtc;
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};
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chosen {
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stdout-path = &uart2;
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};
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reg_usb0_host_vbus: regulator-usb0-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb0_host_vbus";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_vbus>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb1_host_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb1_host_vbus";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1_vbus>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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reg_flexcan1_xceiver: regulator-flexcan1 {
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compatible = "regulator-fixed";
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regulator-name = "flexcan1-xceiver";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_flexcan2_xceiver: regulator-flexcan2 {
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compatible = "regulator-fixed";
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regulator-name = "flexcan2-xceiver";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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lcd0_backlight: backlight-0 {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd0_backlight>;
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pwms = <&pwm1 0 100000 0>;
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brightness-levels = <0 255>;
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num-interpolated-steps = <255>;
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default-brightness-level = <255>;
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enable-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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lcd1_backlight: backlight-1 {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcd1_backlight>;
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pwms = <&pwm2 0 100000 0>;
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brightness-levels = <0 255>;
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num-interpolated-steps = <255>;
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default-brightness-level = <255>;
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enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_leds>;
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status = "okay";
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led-sw {
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label = "sw-led";
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gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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linux,default-trigger = "heartbeat";
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};
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};
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extcon_usb0: extcon-usb0 {
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compatible = "linux,extcon-usb-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_extcon>;
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id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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};
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&A53_0 {
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cpu-supply = <&vcc_arm>;
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};
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&A53_1 {
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cpu-supply = <&vcc_arm>;
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};
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&A53_2 {
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cpu-supply = <&vcc_arm>;
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};
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&A53_3 {
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cpu-supply = <&vcc_arm>;
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};
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&ecspi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <0>, <&gpio2 8 GPIO_ACTIVE_LOW>;
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};
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&ecspi2 {
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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cs-gpios = <0>, <&gpio2 9 GPIO_ACTIVE_LOW>;
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-gpios = <&tca6424 16 GPIO_ACTIVE_LOW>;
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reset-assert-us = <1000>;
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reset-deassert-us = <1000>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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reset-gpios = <&tca6424 17 GPIO_ACTIVE_LOW>;
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reset-assert-us = <1000>;
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reset-deassert-us = <1000>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <400000>;
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status = "okay";
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id_eeprom: eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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pagesize = <32>;
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c5>;
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clock-frequency = <400000>;
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status = "disabled";
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};
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&i2c6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c6>;
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clock-frequency = <400000>;
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status = "okay";
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tca6424: gpio@22 {
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compatible = "ti,tca6424";
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reg = <0x22>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tca6424>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "BOOT_SEL0#", "BOOT_SEL1#", "BOOT_SEL2#",
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"gbe0_int", "gbe1_int", "pmic_int", "rtc_int", "lvds_int",
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"PCIE_WAKE#", "cam2_rst", "cam2_pwr", "SLEEP#",
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"wifi_pd", "tpm_int", "wifi_int", "PCIE_A_RST#",
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"gbe0_rst", "gbe1_rst", "LID#", "BATLOW#", "CHARGING#",
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"CHARGER_PRSNT#";
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interrupt-parent = <&gpio1>;
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interrupts = <9 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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dsi_lvds_bridge: bridge@2d {
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compatible = "ti,sn65dsi83";
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reg = <0x2d>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lvds_bridge>;
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enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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pmic: pmic@30 {
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compatible = "ricoh,rn5t567";
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reg = <0x30>;
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interrupt-parent = <&tca6424>;
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
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regulators {
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DCDC1 {
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regulator-name = "VCC_SOC";
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regulator-always-on;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <950000>;
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};
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DCDC2 {
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regulator-name = "VCC_DRAM";
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regulator-always-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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};
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vcc_arm: DCDC3 {
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regulator-name = "VCC_ARM";
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regulator-always-on;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <950000>;
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};
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DCDC4 {
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regulator-name = "VCC_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDO1 {
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regulator-name = "VCC_LDO1_2V5";
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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LDO2 {
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regulator-name = "VCC_LDO2_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDO3 {
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regulator-name = "VCC_ETH_2V5";
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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LDO4 {
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regulator-name = "VCC_DDR4_2V5";
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regulator-always-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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};
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LDO5 {
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regulator-name = "VCC_LDO5_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDORTC1 {
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regulator-name = "VCC_SNVS_1V8";
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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LDORTC2 {
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regulator-name = "VCC_SNVS_3V3";
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regulator-always-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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sys_rtc: rtc@32 {
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compatible = "ricoh,r2221tl";
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reg = <0x32>;
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interrupt-parent = <&tca6424>;
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interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
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};
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tmp_sensor: temperature-sensor@71 {
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compatible = "ti,tmp103";
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reg = <0x71>;
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_flexcan1_xceiver>;
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status = "disabled";
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};
|
||||
|
||||
&flexcan2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
xceiver-supply = <®_flexcan2_xceiver>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&flexspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi0>;
|
||||
status = "okay";
|
||||
|
||||
qspi_flash: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <80000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb3_phy0 {
|
||||
vbus-supply = <®_usb0_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
vbus-supply = <®_usb1_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_0 {
|
||||
dr_mode = "otg";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
extcon = <&extcon_usb0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82>,
|
||||
<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82>,
|
||||
<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82>,
|
||||
<MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x40000>,
|
||||
<MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x40000>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82>,
|
||||
<MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82>,
|
||||
<MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82>,
|
||||
<MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000>,
|
||||
<MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x40000>;
|
||||
};
|
||||
|
||||
pinctrl_eqos: eqosgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
|
||||
<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
|
||||
<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
|
||||
<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
|
||||
<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
|
||||
<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
|
||||
<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
|
||||
<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
|
||||
<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
|
||||
<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
|
||||
<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
|
||||
<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
|
||||
<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
|
||||
<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>,
|
||||
<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>,
|
||||
<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>,
|
||||
<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>,
|
||||
<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154>,
|
||||
<MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154>,
|
||||
<MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi0: flexspi0grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>,
|
||||
<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>,
|
||||
<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>,
|
||||
<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>,
|
||||
<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>,
|
||||
<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>,
|
||||
<MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>,
|
||||
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>,
|
||||
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>,
|
||||
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>,
|
||||
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>;
|
||||
};
|
||||
|
||||
pinctrl_i2c5: i2c5grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>,
|
||||
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>;
|
||||
};
|
||||
|
||||
pinctrl_i2c6: i2c6grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>,
|
||||
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>;
|
||||
};
|
||||
|
||||
pinctrl_lcd0_backlight: lcd0-backlightgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41>;
|
||||
};
|
||||
|
||||
pinctrl_lcd1_backlight: lcd1-backlightgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x41>;
|
||||
};
|
||||
|
||||
pinctrl_leds: ledsgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19>;
|
||||
};
|
||||
|
||||
pinctrl_lvds_bridge: lvds-bridgegrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x41>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x116>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116>;
|
||||
};
|
||||
|
||||
pinctrl_tca6424: tca6424grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x41>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49>,
|
||||
<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c4>,
|
||||
<MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c4>,
|
||||
<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49>,
|
||||
<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>,
|
||||
<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4>,
|
||||
<MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49>,
|
||||
<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49>,
|
||||
<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49>;
|
||||
};
|
||||
|
||||
pinctrl_usb0_extcon: usb0-extcongrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x19>;
|
||||
};
|
||||
|
||||
pinctrl_usb0_vbus: usb0-vbusgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19>;
|
||||
};
|
||||
|
||||
pinctrl_usb1_vbus: usb1-vbusgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>,
|
||||
<MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>,
|
||||
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>,
|
||||
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>,
|
||||
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>,
|
||||
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>,
|
||||
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_vmmc: usdhc2-vmmcgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
|
||||
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
|
||||
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
|
||||
<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
|
||||
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
|
||||
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
|
||||
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
|
||||
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>,
|
||||
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
|
||||
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
|
||||
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
|
||||
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
|
||||
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
|
||||
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6>,
|
||||
<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins =
|
||||
<MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>;
|
||||
};
|
||||
};
|
||||
@ -285,6 +285,13 @@ config TARGET_IMX8MP_RSB3720A1_6G
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_MSC_SM2S_IMX8MP
|
||||
bool "MSC SMARC2 i.MX8MPLUS"
|
||||
select BINMAN
|
||||
select IMX8MP
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_LIBREM5
|
||||
bool "Purism Librem5 Phone"
|
||||
select BINMAN
|
||||
@ -312,6 +319,7 @@ source "board/google/imx8mq_phanbell/Kconfig"
|
||||
source "board/kontron/pitx_imx8m/Kconfig"
|
||||
source "board/kontron/sl-mx8mm/Kconfig"
|
||||
source "board/menlo/mx8menlo/Kconfig"
|
||||
source "board/msc/sm2s_imx8mp/Kconfig"
|
||||
source "board/phytec/phycore_imx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mp/Kconfig"
|
||||
source "board/purism/librem5/Kconfig"
|
||||
|
||||
15
board/msc/sm2s_imx8mp/Kconfig
Normal file
15
board/msc/sm2s_imx8mp/Kconfig
Normal file
@ -0,0 +1,15 @@
|
||||
if TARGET_MSC_SM2S_IMX8MP
|
||||
|
||||
config SYS_BOARD
|
||||
default "sm2s_imx8mp"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "msc"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "msc_sm2s_imx8mp"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg"
|
||||
|
||||
endif
|
||||
11
board/msc/sm2s_imx8mp/Makefile
Normal file
11
board/msc/sm2s_imx8mp/Makefile
Normal file
@ -0,0 +1,11 @@
|
||||
#
|
||||
# Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o lpddr4_timing.o
|
||||
else
|
||||
obj-y += sm2s_imx8mp.o
|
||||
endif
|
||||
8
board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg
Normal file
8
board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg
Normal file
@ -0,0 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
ROM_VERSION v2
|
||||
BOOT_FROM sd
|
||||
LOADER u-boot-spl-ddr.bin 0x920000
|
||||
1842
board/msc/sm2s_imx8mp/lpddr4_timing.c
Normal file
1842
board/msc/sm2s_imx8mp/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load Diff
60
board/msc/sm2s_imx8mp/sm2s_imx8mp.c
Normal file
60
board/msc/sm2s_imx8mp/sm2s_imx8mp.c
Normal file
@ -0,0 +1,60 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Based on vendor support provided by AVNET Embedded
|
||||
*
|
||||
* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
|
||||
* Copyright 2021 General Electric Company
|
||||
* Copyright 2021 Collabora Ltd.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Enable RGMII TX clk output */
|
||||
setbits_le32(&gpr->gpr[1], BIT(22));
|
||||
}
|
||||
|
||||
static int setup_eqos(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* set INTF as RGMII, enable RGMII TXC clock */
|
||||
clrsetbits_le32(&gpr->gpr[1],
|
||||
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
|
||||
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
|
||||
|
||||
return set_clk_eqos(ENET_125MHZ);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
setup_fec();
|
||||
|
||||
setup_eqos();
|
||||
|
||||
return 0;
|
||||
}
|
||||
273
board/msc/sm2s_imx8mp/spl.c
Normal file
273
board/msc/sm2s_imx8mp/spl.c
Normal file
@ -0,0 +1,273 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Based on vendor support provided by AVNET Embedded
|
||||
*
|
||||
* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
|
||||
* Copyright 2021 General Electric Company
|
||||
* Copyright 2021 Collabora Ltd.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <cpu_func.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <hang.h>
|
||||
#include <i2c.h>
|
||||
#include <image.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <mmc.h>
|
||||
#include <spl.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/rn5t567_pmic.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
return BOOT_DEVICE_BOOTROM;
|
||||
}
|
||||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
/*
|
||||
* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
|
||||
* not allow to change it. Should set the clock after PMIC
|
||||
* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
|
||||
* set by ROM for ND VDD_SOC
|
||||
*/
|
||||
clock_enable(CCGR_GIC, 0);
|
||||
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
|
||||
clock_enable(CCGR_GIC, 1);
|
||||
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE \
|
||||
| PAD_CTL_PE | PAD_CTL_FSEL2)
|
||||
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
|
||||
#define USDHC_CD_PAD_CTRL (PAD_CTL_PE | PAD_CTL_PUE | PAD_CTL_HYS \
|
||||
| PAD_CTL_DSE4)
|
||||
|
||||
static const iomux_v3_cfg_t usdhc2_pads[] = {
|
||||
MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
|
||||
MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
|
||||
#define USDHC2_RESET_GPIO IMX_GPIO_NR(2, 19)
|
||||
|
||||
static const iomux_v3_cfg_t usdhc3_pads[] = {
|
||||
MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
};
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[] = {
|
||||
{ USDHC2_BASE_ADDR, 0, 4 },
|
||||
{ USDHC3_BASE_ADDR, 0, 8 },
|
||||
};
|
||||
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
int i, ret;
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-Boot device node) (Physical Port)
|
||||
* mmc0 (sd) USDHC2
|
||||
* mmc1 (emmc) USDHC3
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
init_clk_usdhc(1);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
|
||||
ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_request(USDHC2_RESET_GPIO, "usdhc2_reset");
|
||||
gpio_direction_output(USDHC2_RESET_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC2_RESET_GPIO, 1);
|
||||
gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
break;
|
||||
case 1:
|
||||
init_clk_usdhc(2);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
|
||||
ARRAY_SIZE(usdhc3_pads));
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
|
||||
i + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
|
||||
static const iomux_v3_cfg_t wdog_pads[] = {
|
||||
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
||||
|
||||
static const iomux_v3_cfg_t ser0_pads[] = {
|
||||
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(ser0_pads, ARRAY_SIZE(ser0_pads));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const iomux_v3_cfg_t reset_out_pad[] = {
|
||||
MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 | MUX_PAD_CTRL(0x19)
|
||||
};
|
||||
|
||||
#define RESET_OUT_GPIO IMX_GPIO_NR(4, 27)
|
||||
|
||||
static void pulse_reset_out(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(reset_out_pad, ARRAY_SIZE(reset_out_pad));
|
||||
|
||||
gpio_request(RESET_OUT_GPIO, "reset_out_gpio");
|
||||
gpio_direction_output(RESET_OUT_GPIO, 0);
|
||||
udelay(10);
|
||||
gpio_direction_output(RESET_OUT_GPIO, 1);
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
struct i2c_pads_info i2c_dev_pads = {
|
||||
.scl = {
|
||||
.i2c_mode = MX8MP_PAD_SAI5_RXFS__I2C6_SCL | PC,
|
||||
.gpio_mode = MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 19),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX8MP_PAD_SAI5_RXC__I2C6_SDA | PC,
|
||||
.gpio_mode = MX8MP_PAD_SAI5_RXC__GPIO3_IO20 | PC,
|
||||
.gp = IMX_GPIO_NR(3, 20),
|
||||
},
|
||||
};
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_seq(UCLASS_PMIC, 0, &dev);
|
||||
if (ret) {
|
||||
printf("Error: Failed to get PMIC\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* set VCC_DRAM (buck2) to 1.1V */
|
||||
pmic_reg_write(dev, RN5T567_DC2DAC, 0x28);
|
||||
|
||||
/* set VCC_ARM (buck2) to 0.95V */
|
||||
pmic_reg_write(dev, RN5T567_DC3DAC, 0x1C);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(1);
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
pulse_reset_out();
|
||||
|
||||
timer_init();
|
||||
|
||||
ret = spl_early_init();
|
||||
if (ret) {
|
||||
printf("Error: failed to initialize SPL!\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
power_init_board();
|
||||
|
||||
spl_dram_init();
|
||||
}
|
||||
105
configs/msc_sm2s_imx8mp_defconfig
Normal file
105
configs/msc_sm2s_imx8mp_defconfig
Normal file
@ -0,0 +1,105 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s"
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_TARGET_MSC_SM2S_IMX8MP=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_BOOT_GET_CMDLINE=y
|
||||
CONFIG_SYS_BARGSIZE=2048
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb"
|
||||
CONFIG_SPL_MAX_SIZE=0x26000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x0098FC00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK=0x960000
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="eth1"
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_SPL_CLK_IMX8MP=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHY_TI=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RN5T567=y
|
||||
CONFIG_SPL_PMIC_RN5T567=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
64
include/configs/msc_sm2s_imx8mp.h
Normal file
64
include/configs/msc_sm2s_imx8mp.h
Normal file
@ -0,0 +1,64 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Based on vendor support provided by AVNET Embedded
|
||||
*
|
||||
* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
|
||||
* Copyright 2021 General Electric Company
|
||||
* Copyright 2021 Collabora Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __MSC_SM2S_IMX8MP_H
|
||||
#define __MSC_SM2S_IMX8MP_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 2)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#endif
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
BOOTENV \
|
||||
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc1,115200\0" \
|
||||
"fdt_addr_r=0x43000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
||||
|
||||
/* Link Definitions */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
|
||||
#define PHYS_SDRAM_2 0xc0000000
|
||||
#define PHYS_SDRAM_2_SIZE 0x0
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user