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Author SHA1 Message Date
Kever Yang
82763349a2 rockchip: ram: rk3399: update for TPL 
Init the ddr sdram in TPL instead of SPL, update the code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
6bbf5e1a94 rockchip: rk3399: add tpl support 
Rockchip platform suppose to use TPL(run in SRAM) as dram init and
SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be
limited by SRAM size.
This patch add rk3399-board-tpl.c and its common configs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
3cbec0ad09 rockchip: add u-boot-tpl-v8.lds 
We don't have both sram and sdram in TPL, so update from:
arch/arm/cpu/armv8/u-boot-spl.lds

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
 2019-05-08 17:34:12 +08:00
Kever Yang
615e9b3cce rockchip: px5: add timer0 dts node as tick timer 
Let's use rockchip timer before stimer patches can be merged.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
6459e7f588 rockchip: rk3368: remove uart iomux init in SPL 
The iomux should have been set in board_debug_uart_init(),
do not set in board_init_f(), remove it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
99a1a5b195 rockchip: dmc: rk3368: update rank number for evb-px5 
evb-px5 has only 1 CS, update for it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
6b780e441b rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL only 
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add
condition to limit it not affect TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
259afb1692 rockchip: px5: update defconfig for TPL/SPL 
Add options to support TPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
cd193462ee rockchip: px5: update SPL size for spl/tpl 
Use larger space for load bl31 in SPL

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
4d9dd40d68 rockchip: px5 update dts for spl/tpl 
TPL need dmc to init ddr sdram, and emmc, boot-order.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
579a168466 rockchip: rk3368: support UART2/4 in board_debug_uart_init() 
evb-rk3368 is using UART2 and PX5 evb is using UART4

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
a5fd9a7e1e rockchip: evb-rk322x: update defconfig with tpl and optee support 
Enable all the options for TPL/SPL and OPTEE.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
7c2a754235 rockchip: evb-rk3229: add README file for OP-TEE support 
Detail of step by step to bring up the board with OP-TEE support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
26f3814e02 rockchip: evb-rk3229: remove unnecessary defines 
Prefer to use default setting like other SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
d55dbfed16 rockchip: rk322x: dts: enable uart2 for SPL/TPL 
When we use DM_SERIAL for serial driver, we need enable the
dts node for the debug console.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
09259fce1e sysreset: enable driver support in SPL/TPL 
SPL/TPL also need use sysreset for some feature like panic callback.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
c34643e0db rockchip: rk322x: add tpl support 
Move original spl to tpl, and add spl to load next stage firmware,
adapt all the address and option for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
5793e8c271 rockchip: clk: rk322x: fix assert clock value 
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
e4d0d61275 rockchip: rk322x: add CLK_EMMC_SAMPLE clock support 
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
a0a0d04f32 arm: add a separate stack for TPL 
TPL stack may different from SPL and sys stack, add support for
separate one when the board defines it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
1e32c5194f arm: add option for TPL support in arm 32bit 
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY
and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
2f52378736 Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL" 
This reverts commit f338cca1d2.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
dc23c27aa5 arm: remove ARCH_ROCKCHIP macro in common code 
This is fix to:
e2a12f590d rockchip: use 'arch-rockchip' as header file path

The V2 of origin patch set has fix this, but we merge V1 by
mistake, so lets correct it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
 2019-05-08 17:34:12 +08:00
Kever Yang
93557bd260 rockchip: add common header boot0.h and gpio.h for soc 
boot0.h and gpio.h will be used by system and include by
'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
 2019-05-08 17:34:12 +08:00
Tom Rini
8d7f06bbbe Merge branch 'master' of git://git.denx.de/u-boot-sh 
- RZ/A1 addition.
- Old board removal.
 2019-05-07 09:38:00 -04:00
Tom Rini
6984044d05 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 
- Assorted stratix10 fixes.
- DDR driver DM migration.
 2019-05-07 09:37:11 -04:00
Chris Brandt
ba932bc846 ARM: dts: renesas: Add RZ/A1 GR-Peach board 
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach,
which is a cheap development platform with RZ/A1H SoC. The
DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Currently supported are UART, ethernet and RPC SPI. The board
can be booted from RPC SPI by writing the u-boot.bin binary
to the beginning of the SPI NOR, e.g. using the "sf" command.
The board can also be booted via JTAG by setting text base to
0x20020000, loading u-boot.bin there via JTAG and executing it
from that address.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Chris Brandt
3529596442 ARM: dts: renesas: Add RZ/A1 platform code 
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).

The DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
b5b6656794 spi: rpc: Add support for operation without clock framework 
Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
24b3247e24 net: sh_eth: Add support for operation without clock framework 
Add ifdeffery to allow operation without the clock framework
enabled. This is required on RZ/A1, as it does not have clock
driver yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
31650cf4b0 net: sh_eth: Add RZ/A1 support 
Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
67180fe101 serial: sh: Add RZ/A1 support 
Add support for RZ/A1 SoC specifics.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
4d0732bf3c timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver 
Add OSTM timer driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
cbde9dea09 pinctrl: renesas: Add RZ/A1 R7S72100 pin control driver 
Add pin control driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
86b8e7d61a gpio: renesas: Add RZ/A1 R7S72100 GPIO driver 
Add GPIO driver for RZ/A1 SoC. The IP is very different from the
R-Car Gen2/Gen3 one already present in the tree, hence a custom
driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 2019-05-07 05:41:32 +02:00
Marek Vasut
99156cd9d3 sh: 7785: Remove CPU support 
There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 2019-05-07 05:41:32 +02:00
Marek Vasut
06480665aa sh: sh7785lcr: Remove the board 
Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 2019-05-07 05:41:31 +02:00
Marek Vasut
d13a6144ff sh: 7724: Remove CPU support 
There are no more boards using this CPU and there is no prospect
of any boards showing up soon, remove it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 2019-05-07 05:41:31 +02:00
Marek Vasut
e4f01b5133 sh: ecovec: Remove the board 
Last change to this board was done in 2016, it uses non-DM USB
with no prospects of ever being converted to DM USB, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 2019-05-07 05:41:31 +02:00
Marek Vasut
b3c27c9429 sh: sh7757lcr: Fix copy-paste error in README 
Update the README to use the correct defconfig.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 2019-05-07 05:41:31 +02:00
Tom Rini
44237e272f Merge branch 'master' of git://git.denx.de/u-boot-sh 
- Various pinctrl / gpio fixes for R-Car
 2019-05-06 07:19:31 -04:00
Tom Rini
8b77ea90a7 Merge branch 'master' of git://git.denx.de/u-boot-spi 
- Important spi-mem fix
 2019-05-06 07:18:28 -04:00
Ang, Chee Hong
32e308dd79 ARM: socfpga: stratix10: Probe FPGA status before bridge enable 
Send CONFIG_STATUS and RECONFIG_STATUS mailbox commands to Secure
Device Manager (SDM) to get the status of FPGA and make sure the
FPGA is in user mode before enable the bridge.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
 2019-05-06 12:44:45 +02:00
Ang, Chee Hong
a03e9d9fe5 ARM: socfpga: stratix10: Disable FPGA2SOC reset 
Software must never reset FPGA2SOC bridge. This bridge must only be
reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software
can cause the SoC to lock-up if there are traffics being drived into
FPGA2SOC bridge.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
 2019-05-06 12:44:45 +02:00
Ley Foon Tan
6bf238a461 arm: socfpga: Move Stratix 10 SDRAM driver to DM 
Convert Stratix 10 SDRAM driver to device model.

Get rid of call to socfpga_per_reset() and use reset
framework.

SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.

Move sdram_s10.h from arch to driver/ddr/altera directory.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
 2019-05-06 12:44:17 +02:00
Ley Foon Tan
bc17990876 arm: dts: Stratix10: Add SDRAM node 
Add SDRAM device tree node.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
 2019-05-06 12:44:17 +02:00
Ley Foon Tan
5918afda9d ddr: altera: Compile ALTERA SDRAM in SPL only 
Compile ALTERA_SDRAM driver in SPL only.
Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
 2019-05-06 12:44:17 +02:00
Tom Rini
abad176da1 Merge branch '2019-05-05-master-imports' 
- Various assorted fixes
- btrfs zstd compression support
- Enable hardware DDR levelling on am43xx platforms.
- pl310 cache controller driver
 2019-05-05 12:25:39 -04:00
Philip Molloy
9337a08768 env: add missing newline 
Signed-off-by: Philip Molloy <philip@philipmolloy.com>
 2019-05-05 08:48:50 -04:00
Marcel Ziswiler
aeaa4b8f31 board: toradex: drop support.arm maintainer email 
Drop Toradex ARM Support <support.arm@toradex.com> from maintainer email
list as this just clogs our support ticketing system.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
 2019-05-05 08:48:50 -04:00