The new environment variable "korat_usbcf" selects the USB
port used by the Korat board's CompactFlash controller.
Signed-off-by: Larry Johnson <lrj@acm.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Import the is_valid_ether_addr() function from the Linux kernel.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This fixes an error which raises just a warning:
sbc8560.c:250: warning: passing argument 2 of 'strmhz' makes integer from pointer without a cast
Signed-off-by: Wolfgang Denk <wd@denx.de>
Add BeagleBoard support, common power code and README.
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Configuring for MPC8540EVAL board...
mpc8540eval.c: In function 'checkboard':
mpc8540eval.c:53: error: invalid operands to binary /
make[1]: *** [mpc8540eval.o] Error 1
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Enabling DM6446 (TI DaVinci) USB module power and MUSB low-level
controller hook up to USB core layer.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
Signed-off-by: Thomas Abraham <t-abraham@ti.com>
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
The old swap function tended to clobber unrelated pins and screw up masks.
Rewrite the thing from scratch so it only uses the resources it needs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This video driver used to live in the Blackfin cpu directory, but it was
lost during the unification process. This brings it back.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The DEBUG code in initdram() is quite old and was never really useful, so
just drop it altogether. Common Blackfin debug code does a better job.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some of the flash defines weren't in the correct location and caused build
problems in some configurations, so let's move types and defines to better
local locations.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Remove command name from all command "usage" fields and update
common/command.c to display "name - usage" instead of
just "usage". Also remove newlines from command usage fields.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
The pcs440ep's led command usage formatting is non-standard. It
was made standard in preparation for larger command usage updates.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
The diufb command usage formatting is non-standard. It was
made standard in preparation for larger command usage updates.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Rather than have the board code initialize SATA automatically during boot,
make the user manually run "sata init". This brings the SATA subsystem in
line with common U-Boot policy.
Rather than having a dedicated weak function "is_sata_supported", people
can override sata_initialize() to do their weird board stuff. Then they
can call the actual __sata_initialize().
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Board support for the Guntermann & Drunck PowerPC 440 ETX module.
Based on the AMCC Yosemite board support by Stefan Roese.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The NMDK8815 board is distributed by ST Microelectornics.
Other (proprietary) code must be run to unlock the CPU before
U-Boot runs. doc/README.nmdk8815 outlines the boot sequence.
This is the initial port, with basic infrastructure and
a working serial port.
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Brings i386 in line with other CPUs with a reset vector and frees up reset.c
for CPU reset functions
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Check the presence of the PIGGY on the keymile boards mgcoge,
mgsuvd and kmeter1. If the PIGGY is not present, dont register
this Ethernet device.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
This patch adds support for the kmeter1 board from Keymile,
based on a Freescale MPC8360 CPU.
- serial console on UART 1
- 256 MB DDR2 RAM
- 64 MB NOR Flash
- Ethernet RMII Mode over UCC4
- PHY SMSC LAN8700
Signed-off-by: Heiko Schocher <hs@denx.de>
The wake up ARP feature need use the memory to process
wake up packet, we enable auto self refresh to support it.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields
of TLBs. This is what we should have always been using from the start.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and
maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash.
This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Added a PIXIS_BASE_PHYS for use as the physical address and maintain
PIXIS_BASE as the virtual address of the PIXIS fpga registers.
This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
This patch will create a new board, SIMPC8313, from Sheldon Instruments. This
board boots from NAND devices and is configureable for either large or small
page devices. The board supports non-soldered DDR2, one ethernet port, a
Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected
to the eLBC providing glue logic to a TMS320C67xx DSP.
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card
provides two PCI-E (x2) ports. Though, only one port can be used in x2
mode. Two ports can function simultaneously in x1 mode.
PCI-E x1/x2 modes can be switched via "pex_x2" environment variable.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's
support them.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do
not enable them. See the MPC8349EA Reference Manual, Section 4.4.2
"Clocking in PCI Agent Mode".
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
lowlevel_init of SH was corrected to use the write/readXX macro.
However, there was a problem that was not able to be compiled partially.
This patch corrected this.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch adds esd's loadpci BSP command to CPCI4052 and
CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch cleans up CPCI405 board support:
- wrap long lines
- unification of spaces in function calls
- remove dead code
Use correct io accessors on peripherals.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch turns on the auto RS485 mode in the 2nd external
uart on PLU405 boards. This is a special mode of the used
Exar XR16C2850 uart. Because these boards only have a 485 physical
layer connected it's a good idea to turn it on by default.
Signed-off-by: Matthias Fuchs <mf@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
The IO port selection for MPC8544DS board:
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2 0x4, 0x5, 0x6, 0x7
PCIE3 0x6, 0x7
This patch changes the PCIE12 and PCIE2 logic more readable.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
PCIE1 bit.
On MPC8572DS board, PCIE refers to PCIE1.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
The IO port selection is not correct on MPC8572DS and MPC8544DS board.
This patch fixes this issue.
For MPC8572
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf
PCIE2 0x3, 0x7
PCIE3 0x7
For MPC8544
Port cfg_io_ports
PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
PCIE2 0x4, 0x5, 0x6, 0x7
PCIE3 0x6, 0x7
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Rename _BASE to _BUS, as it's actually a PCI bus address,
separate virtual and physical addresses into _VIRT and _PHYS,
and use each appopriately. This makes the code easier to read
and understand, and facilitates mapping changes going forward.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Many of the Blackfin board linker scripts are preprocessed, so make sure we
output the linker script into the build tree rather than the source tree.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Make sure all .text sections get pulled in and the entry point is properly
referenced so they don't get discarded when linking with --gc-sections.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
In order to boot an LDR out of parallel flash, the ldr utility needs a few
flags to tell it to generate the right header.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.
In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
should be safe as the fifth bit was defined as reserved and set to 0.
Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
Initial support for Extreme Engineering Solutions XPedite5200 -
a MPC8548-based PMC single board computer.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Update X-ES Freescale boards to allow inbound PCI configuration
cycles when configured as agent/endpoint.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Initial support for Extreme Engineering Solutions XPedite5370 -
a MPC8572-based 3U VPX single board computer with a PMC/XMC
site.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Apply changes from commit 44b4dbed to board/trab/memory.c, too.
Actually we'd need a major cleanup here - as it turns out,
board/trab/memory.c is more or less a verbatim copy of
post/drivers/memory.c ... but then, trab is EOL anyway,r
so this is not worth the effort.
Signed-off-by: Wolfgang Denk <wd@denx.de>
A value of BSC CS4 was wrong, Fixed it.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch fixes building U-Boot for CPCI405 boards.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
Microblaze platforms use generic settings and to have
many platforms is confusing that's why I decided to remove this
platform from U-BOOT. ml401 tree is sufficient for covering
all Microblaze platforms.
This change will go through microblaze custodian tree.
Commit 6b59e03e02
lcd: Let the board code show board-specific info
introduced some bugs which prevent U-Boot building
for lwmon board if CONFIG_LCD_INFO_BELOW_LOGO will
be defined in the board configuration.
Also "LCD enabled" building for TQM823L doesn't work
since this commit.
This patch fixes above-mentioned issues.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add define used to determine if PCI1 interface is in PCI or PCIX mode.
Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
since commit be0bd8234b
tlb entry for socrates DDR SDRAM will be reconfigured
by setup_ddr_tlbs() from initdram() causing an
inconsistency with previously configured DDR SDRAM tlb
entry from tlb_table:
socrates>l2cam 7 9
IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS
7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX
8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX
9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX
This patch makes the presence of the DDR SDRAM tlb entry in
the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this
inconsistency.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
This BSP should be outside u-boot source tree.
The second reason is that xilinx ppc405 was moved to generic platform.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Check the presence of the PIGGY on the keymile boards mgcoge,
mgsuvd and kmeter1. If the PIGGY is not present, dont register
this Ethernet device.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Expanded OCM TLB to allow access to 64K OCM as well as 256K of
internal SRAM.
Adjusted internal SRAM initialization to match updated user
manual recommendation.
OCM & ISRAM are now mapped as follows:
physical virtual size
ISRAM 0x4_0000_0000 0xE300_0000 256k
OCM 0x4_0004_0000 0xE304_0000 64k
A single TLB was used for this mapping.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.
Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.
Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Introduce AT91_CPU_CLOCK and use it for displaying the CPU
speed in the LCD driver.
Also make AT91_MAIN_CLOCK and AT91_MASTER_CLOCK reflect the
corresponding board clocks.
Signed-off-by: Stelian Pop <stelian@popies.net>
This patch adds support for the kmeter1 board from Keymile,
based on a Freescale MPC8360 CPU.
- serial console on UART 1
- 256 MB DDR2 RAM
- 64 MB NOR Flash
- Ethernet RMII Mode over UCC4
- PHY SMSC LAN8700
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
To enable UBI on Apollon you need to uncomment the CONFIG_SYS_USE_UBI
macro.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Most of the bss initialization loop increments 4 bytes
at a time. And the loop end is checked for an 'equal'
condition. Make the bss end address aligned by 4, so
that the loop will end as expected.
Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
address-cells defaults to 2, not 1; so in the unlikely
event that it isn't specified, this patch is required
for correct operation.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Since we've changed the memory map of the board, be nice and
add some checking to try to catch out-of-date .dts files. We do
this by checking the CCSRBAR location in the .dts and comparing
it to the CCSRBAR location in u-boot. If they don't match, a
warning msg is printed. This isn't foolproof, but it's simple and
will catch most of the cases where an out-of-date .dts is present,
including all of the cases where a new u-boot is used with an old
standard MPC8641 .dts file as supplied with Linux.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
This patch creates a memory map with all the devices
in 36-bit physical space, in addition to the 32-bit map.
The CCSR relocation is moved (again, sorry) to
allow for the physical address to be 36 bits - this
requires translation to be enabled. With 36-bit physical
addressing enabled, we are no longer running with VA=PA
translations. This means we have to distinguish between
the two in the config file. The existing region name is
used to indicate the virtual address, and a _PHYS variety
is created to represent the physical address.
Large physical addressing is not enabled by default.
Set CONFIG_PHYS_64BIT in the config file to turn this on.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.
The regions for some of the mappings were far larger than they
needed to be. I have reduced the mappings to match the
actual sizes supported by the hardware.
In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them. These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.
Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
There's a lot of setup and foo for the second flash
bank. The problem is, this board doesn't actually have one.
Clean this up. Also, the flash is 8M in size. Get rid
of the confusing aliased overmapping, and just map 8M.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Also changed path in all linker scripts that reference this driver
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
AT91_BASE_EMAC is never used outside the board specific files,
so replace its usage by the board specific AT91xxx_BASE_EMAC.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
AT91_ID_US0 / AT91_ID_US1 / AT91_ID_US2 were used but never defined.
Since they are never used outside the board specific files, they can
be replaced by the board specific AT91xxx_ID_US0 / AT91xxx_ID_US1 /
AT91xxx_ID_US2.
Bug spotted by Jesus Alvarez <jalvarez@micromint.com>.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This patch provides support for AFEB9260 board, a product of
OpenSource hardware and software. Some commertial projects
are made with this design. A board is basically AT91SAM9260-EK
with some modifications and different peripherals and different
parts used. Main purpose of this project is to gain experience in
hardware design.
More info: http://groups.google.com/group/arm9fpga-evolution-board
(In Russian only, sorry).
Subversion repository: svn://194.85.238.22/home/users/george/svn/arm9eb
Signed-off-by: Sergey Lapin <slapin@ossfans.org>
You can't actually have both, and with some coming changes to
change the memory map for the board and support 36-bit physical,
we need the extra BAT that is being consumed by having both.
I also make non-PCI configs build cleanly, for the sake of sanity.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
