sh: use write{8,16,32} in all lowlevel_init
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
Nobuhiro Iwamatsu
parent
e443077962
commit
f7e78f3b74
@ -22,6 +22,7 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/macro.h>
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.global lowlevel_init
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@ -33,59 +34,35 @@ lowlevel_init:
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/*
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* Set frequency multipliers and dividers in FRQCR.
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*/
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mov.l WTCSR_A, r1
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mov.l WTCSR_D, r0
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mov.w r0, @r1
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write16 WTCSR_A, WTCSR_D
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mov.l WTCNT_A, r1
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mov.l WTCNT_D, r0
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mov.w r0, @r1
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write16 WTCNT_A, WTCNT_D
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mov.l FRQCR_A, r1
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mov.l FRQCR_D, r0
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mov.w r0, @r1
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write16 FRQCR_A, FRQCR_D
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/*
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* Setup CS0 (Flash).
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*/
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mov.l CS0BCR_A, r1
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mov.l CS0BCR_D, r0
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mov.l r0, @r1
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write32 CS0BCR_A, CS0BCR_D
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mov.l CS0WCR_A, r1
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mov.l CS0WCR_D, r0
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mov.l r0, @r1
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write32 CS0WCR_A, CS0WCR_D
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/*
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* Setup CS3 (SDRAM).
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*/
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mov.l CS3BCR_A, r1
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mov.l CS3BCR_D, r0
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mov.l r0, @r1
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write32 CS3BCR_A, CS3BCR_D
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mov.l CS3WCR_A, r1
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mov.l CS3WCR_D, r0
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mov.l r0, @r1
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write32 CS3WCR_A, CS3WCR_D
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mov.l SDCR_A, r1
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mov.l SDCR_D1, r0
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mov.l r0, @r1
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write32 SDCR_A, SDCR_D1
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mov.l RTCSR_A, r1
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mov.l RTCSR_D, r0
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mov.l r0, @r1
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write32 RTCSR_A, RTCSR_D
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mov.l RTCNT_A, r1
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mov.l RTCNT_D, r0
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mov.l r0, @r1
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write32 RTCNT_A, RTCNT_D
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mov.l RTCOR_A, r1
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mov.l RTCOR_D, r0
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mov.l r0, @r1
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write32 RTCOR_A, RTCOR_D
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mov.l SDCR_A, r1
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mov.l SDCR_D2, r0
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mov.l r0, @r1
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write32 SDCR_A, SDCR_D2
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mov.l SDMR3_A, r1
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mov.l SDMR3_D, r0
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@ -27,6 +27,7 @@
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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/*
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* Board specific low level init code, called _very_ early in the
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@ -43,165 +44,94 @@
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lowlevel_init:
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/* Address of Cache Control Register */
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mov.l CCR_A, r1
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/*Instruction Cache Invalidate */
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mov.l CCR_D, r0
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mov.l r0, @r1
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/*
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* Cache Control Register
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* Instruction Cache Invalidate
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*/
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write32 CCR_A, CCR_D
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/* Address of MMU Control Register */
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mov.l MMUCR_A, r1
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/* TI == TLB Invalidate bit */
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mov.l MMUCR_D, r0
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mov.l r0, @r1
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/*
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* Address of MMU Control Register
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* TI == TLB Invalidate bit
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*/
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write32 MMUCR_A, MMUCR_D
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/* Address of Power Control Register 0 */
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mov.l MSTPCR0_A, r1
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mov.l MSTPCR0_D, r0
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mov.l r0, @r1
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write32 MSTPCR0_A, MSTPCR0_D
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/* Address of Power Control Register 2 */
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mov.l MSTPCR2_A, r1
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mov.l MSTPCR2_D, r0
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mov.l r0, @r1
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write32 MSTPCR2_A, MSTPCR2_D
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mov.l SBSCR_A, r1
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mov.w SBSCR_D, r0
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mov.w r0, @r1
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write16 SBSCR_A, SBSCR_D
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mov.l PSCR_A, r1
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mov.w PSCR_D, r0
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mov.w r0, @r1
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write16 PSCR_A, PSCR_D
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/* 0xA4520004 (Watchdog Control / Status Register) */
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! mov.l RWTCSR_A, r1
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/* 0xA507 -> timer_STOP/WDT_CLK=max */
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! mov.w RWTCSR_D_1, r0
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! mov.w r0, @r1
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! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
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/* 0xA4520000 (Watchdog Count Register) */
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mov.l RWTCNT_A, r1
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/*0x5A00 -> Clear */
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mov.w RWTCNT_D, r0
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mov.w r0, @r1
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write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
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/* 0xA4520004 (Watchdog Control / Status Register) */
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mov.l RWTCSR_A, r1
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/* 0xA504 -> timer_STOP/CLK=500ms */
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mov.w RWTCSR_D_2, r0
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mov.w r0, @r1
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write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
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/* 0xA4150000 Frequency control register */
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mov.l FRQCR_A, r1
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mov.l FRQCR_D, r0 !
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mov.l r0, @r1
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write32 FRQCR_A, FRQCR_D
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mov.l CCR_A, r1
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mov.l CCR_D_2, r0
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mov.l r0, @r1
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write32 CCR_A, CCR_D_2
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bsc_init:
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mov.l PSELA_A, r1
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mov.w PSELA_D, r0
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mov.w r0, @r1
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write16 PSELA_A, PSELA_D
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mov.l DRVCR_A, r1
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mov.w DRVCR_D, r0
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mov.w r0, @r1
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write16 DRVCR_A, DRVCR_D
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mov.l PCCR_A, r1
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mov.w PCCR_D, r0
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mov.w r0, @r1
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write16 PCCR_A, PCCR_D
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mov.l PECR_A, r1
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mov.w PECR_D, r0
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mov.w r0, @r1
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write16 PECR_A, PECR_D
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mov.l PJCR_A, r1
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mov.w PJCR_D, r0
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mov.w r0, @r1
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write16 PJCR_A, PJCR_D
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mov.l PXCR_A, r1
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mov.w PXCR_D, r0
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mov.w r0, @r1
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write16 PXCR_A, PXCR_D
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mov.l CMNCR_A, r1 ! CMNCR address -> R1
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mov.l CMNCR_D, r0 ! CMNCR data -> R0
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mov.l r0, @r1 ! CMNCR set
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write32 CMNCR_A, CMNCR_D
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mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
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mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
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mov.l r0, @r1 ! CS0BCR set
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write32 CS0BCR_A, CS0BCR_D
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mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
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mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
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mov.l r0, @r1 ! CS2BCR set
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write32 CS2BCR_A, CS2BCR_D
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mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
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mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
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mov.l r0, @r1 ! CS4BCR set
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write32 CS4BCR_A, CS4BCR_D
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mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
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mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
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mov.l r0, @r1 ! CS5ABCR set
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write32 CS5ABCR_A, CS5ABCR_D
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mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
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mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
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mov.l r0, @r1 ! CS5BBCR set
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write32 CS5BBCR_A, CS5BBCR_D
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mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
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mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
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mov.l r0, @r1 ! CS6ABCR set
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write32 CS6ABCR_A, CS6ABCR_D
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mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
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mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
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mov.l r0, @r1 ! CS0WCR set
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write32 CS0WCR_A, CS0WCR_D
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mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
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mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
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mov.l r0, @r1 ! CS2WCR set
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write32 CS2WCR_A, CS2WCR_D
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mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
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mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
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mov.l r0, @r1 ! CS4WCR set
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write32 CS4WCR_A, CS4WCR_D
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mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
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mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
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mov.l r0, @r1 ! CS5AWCR set
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write32 CS5AWCR_A, CS5AWCR_D
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mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
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mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
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mov.l r0, @r1 ! CS5BWCR set
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write32 CS5BWCR_A, CS5BWCR_D
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mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
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mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
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mov.l r0, @r1 ! CS6AWCR set
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write32 CS6AWCR_A, CS6AWCR_D
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! SDRAM initialization
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mov.l SDCR_A, r1 ! SB_SDCR address -> R1
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mov.l SDCR_D, r0 ! SB_SDCR data -> R0
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mov.l r0, @r1 ! SB_SDCR set
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write32 SDCR_A, SDCR_D
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mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
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mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
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mov.l r0, @r1 ! SB_SDWCR set
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write32 SDWCR_A, SDWCR_D
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mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
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mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
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mov.l r0, @r1 ! SB_SDPCR set
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write32 SDPCR_A, SDPCR_D
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mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
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mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
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mov.l r0, @r1 ! SB_RTCOR set
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write32 RTCOR_A, RTCOR_D
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mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
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mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
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mov.l r0, @r1 ! SB_RTCSR set
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write32 RTCSR_A, RTCSR_D
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mov.l SDMR3_A, r1 ! SDMR3 address -> R1
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mov #0x00, r0 ! SDMR3 data -> R0
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mov.b r0, @r1 ! SDMR3 set
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write8 SDMR3_A, #0x00
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! BL bit off (init = ON) (?!?)
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@ -29,6 +29,7 @@
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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#ifdef CONFIG_CPU_SH7751
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#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
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@ -65,61 +66,37 @@
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lowlevel_init:
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mov.l CCR_A, r1 ! CCR Address
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mov.l CCR_D_DISABLE, r0 ! CCR Data
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mov.l r0, @r1
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write32 CCR_A, CCR_D_DISABLE
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init_bsc:
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mov.l FRQCR_A, r1 /* FRQCR Address */
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mov.l FRQCR_D, r0 /* FRQCR Data */
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mov.w r0, @r1
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write16 FRQCR_A, FRQCR_D
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mov.l BCR1_A, r1 /* BCR1 Address */
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mov.l BCR1_D, r0 /* BCR1 Data */
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mov.l r0, @r1
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write32 BCR1_A, BCR1_D
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mov.l BCR2_A, r1 /* BCR2 Address */
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mov.l BCR2_D, r0 /* BCR2 Data */
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mov.w r0, @r1
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write16 BCR2_A, BCR2_D
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mov.l WCR1_A, r1 /* WCR1 Address */
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mov.l WCR1_D, r0 /* WCR1 Data */
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mov.l r0, @r1
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write32 WCR1_A, WCR1_D
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mov.l WCR2_A, r1 /* WCR2 Address */
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mov.l WCR2_D, r0 /* WCR2 Data */
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mov.l r0, @r1
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write32 WCR2_A, WCR2_D
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mov.l WCR3_A, r1 /* WCR3 Address */
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mov.l WCR3_D, r0 /* WCR3 Data */
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mov.l r0, @r1
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write32 WCR3_A, WCR3_D
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mov.l MCR_A, r1 /* MCR Address */
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mov.l MCR_D1, r0 /* MCR Data1 */
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mov.l r0, @r1
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write32 MCR_A, MCR_D1
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mov.l SDMR3_A, r1 /* Set SDRAM mode */
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mov #0, r0
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mov.b r0, @r1
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/* Set SDRAM mode */
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write8 SDMR3_A, #0
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! Do you need PCMCIA setting?
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! If so, please add the lines here...
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mov.l RTCNT_A, r1 /* RTCNT Address */
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mov.l RTCNT_D, r0 /* RTCNT Data */
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mov.w r0, @r1
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write16 RTCNT_A, RTCNT_D
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mov.l RTCOR_A, r1 /* RTCOR Address */
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mov.l RTCOR_D, r0 /* RTCOR Data */
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mov.w r0, @r1
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write16 RTCOR_A, RTCOR_D
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mov.l RTCSR_A, r1 /* RTCSR Address */
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mov.l RTCSR_D, r0 /* RTCSR Data */
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mov.w r0, @r1
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write16 RTCSR_A, RTCSR_D
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write16 RFCR_A, RFCR_D
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mov.l RFCR_A, r1 /* RFCR Address */
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mov.l RFCR_D, r0 /* RFCR Data */
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mov.w r0, @r1 /* Clear reflesh counter */
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/* Wait DRAM refresh 30 times */
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mov #30, r3
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1:
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@ -128,13 +105,10 @@ init_bsc:
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cmp/hi r3, r2
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bf 1b
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mov.l MCR_A, r1 /* MCR Address */
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mov.l MCR_D2, r0 /* MCR Data2 */
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mov.l r0, @r1
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write32 MCR_A, MCR_D2
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mov.l SDMR3_A, r1 /* Set SDRAM mode */
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mov #0, r0
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mov.b r0, @r1
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/* Set SDRAM mode */
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write8 SDMR3_A, #0
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rts
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nop
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@ -27,6 +27,7 @@
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#include <version.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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/*
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* Board specific low level init code, called _very_ early in the
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@ -42,139 +43,81 @@
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.align 2
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lowlevel_init:
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mov.l CCR_A, r1 ! Address of Cache Control Register
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mov.l CCR_D, r0 ! Instruction Cache Invalidate
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mov.l r0, @r1
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write32 CCR_A, CCR_D ! Address of Cache Control Register
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! Instruction Cache Invalidate
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mov.l MMUCR_A, r1 ! Address of MMU Control Register
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mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
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mov.l r0, @r1
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write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
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! TI == TLB Invalidate bit
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mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
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mov.l MSTPCR0_D, r0 !
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mov.l r0, @r1
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write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
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mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
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mov.l MSTPCR2_D, r0 !
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mov.l r0, @r1
|
||||
write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
|
||||
|
||||
mov.l PFC_PULCR_A, r1
|
||||
mov.w PFC_PULCR_D, r0
|
||||
mov.w r0,@r1
|
||||
write16 PFC_PULCR_A, PFC_PULCR_D
|
||||
|
||||
mov.l PFC_DRVCR_A, r1
|
||||
mov.w PFC_DRVCR_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PFC_DRVCR_A, PFC_DRVCR_D
|
||||
|
||||
mov.l SBSCR_A, r1 !
|
||||
mov.w SBSCR_D, r0 !
|
||||
mov.w r0, @r1
|
||||
write16 SBSCR_A, SBSCR_D
|
||||
|
||||
mov.l PSCR_A, r1 !
|
||||
mov.w PSCR_D, r0 !
|
||||
mov.w r0, @r1
|
||||
write16 PSCR_A, PSCR_D
|
||||
|
||||
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
|
||||
mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
|
||||
mov.w r0, @r1
|
||||
write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
|
||||
! 0xA507 -> timer_STOP / WDT_CLK = max
|
||||
|
||||
mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
|
||||
mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
|
||||
mov.w r0, @r1
|
||||
write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
|
||||
! 0x5A00 -> Clear
|
||||
|
||||
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
|
||||
mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
|
||||
mov.w r0, @r1
|
||||
write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
|
||||
! 0xA504 -> timer_STOP / CLK = 500ms
|
||||
|
||||
mov.l DLLFRQ_A, r1 ! 20080115
|
||||
mov.l DLLFRQ_D, r0 ! 20080115
|
||||
mov.l r0, @r1
|
||||
write32 DLLFRQ_A, DLLFRQ_D ! 20080115
|
||||
! 20080115
|
||||
|
||||
mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
|
||||
mov.l FRQCR_D, r0 ! 20080115
|
||||
mov.l r0, @r1
|
||||
write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
|
||||
! 20080115
|
||||
|
||||
mov.l CCR_A, r1 ! Address of Cache Control Register
|
||||
mov.l CCR_D_2, r0 ! ??
|
||||
mov.l r0, @r1
|
||||
write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
|
||||
! ??
|
||||
|
||||
bsc_init:
|
||||
mov.l CMNCR_A, r1 ! CMNCR address -> R1
|
||||
mov.l CMNCR_D, r0 ! CMNCR data -> R0
|
||||
mov.l r0, @r1 ! CMNCR set
|
||||
write32 CMNCR_A, CMNCR_D
|
||||
|
||||
mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
|
||||
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
|
||||
mov.l r0, @r1 ! CS0BCR set
|
||||
write32 CS0BCR_A, CS0BCR_D
|
||||
|
||||
mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
|
||||
mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
|
||||
mov.l r0, @r1 ! CS4BCR set
|
||||
write32 CS4BCR_A, CS4BCR_D
|
||||
|
||||
mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
|
||||
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
|
||||
mov.l r0, @r1 ! CS5ABCR set
|
||||
write32 CS5ABCR_A, CS5ABCR_D
|
||||
|
||||
mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
|
||||
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
|
||||
mov.l r0, @r1 ! CS5BBCR set
|
||||
write32 CS5BBCR_A, CS5BBCR_D
|
||||
|
||||
mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
|
||||
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
|
||||
mov.l r0, @r1 ! CS6ABCR set
|
||||
write32 CS6ABCR_A, CS6ABCR_D
|
||||
|
||||
mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
|
||||
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
|
||||
mov.l r0, @r1 ! CS0WCR set
|
||||
write32 CS0WCR_A, CS0WCR_D
|
||||
|
||||
mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
|
||||
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
|
||||
mov.l r0, @r1 ! CS4WCR set
|
||||
write32 CS4WCR_A, CS4WCR_D
|
||||
|
||||
mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
|
||||
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
|
||||
mov.l r0, @r1 ! CS5AWCR set
|
||||
write32 CS5AWCR_A, CS5AWCR_D
|
||||
|
||||
mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
|
||||
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
|
||||
mov.l r0, @r1 ! CS5BWCR set
|
||||
write32 CS5BWCR_A, CS5BWCR_D
|
||||
|
||||
mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
|
||||
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
|
||||
mov.l r0, @r1 ! CS6AWCR set
|
||||
write32 CS6AWCR_A, CS6AWCR_D
|
||||
|
||||
! SDRAM initialization
|
||||
mov.l SDCR_A, r1 ! SB_SDCR address -> R1
|
||||
mov.l SDCR_D, r0 ! SB_SDCR data -> R0
|
||||
mov.l r0, @r1 ! SB_SDCR set
|
||||
write32 SDCR_A, SDCR_D
|
||||
|
||||
mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
|
||||
mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
|
||||
mov.l r0, @r1 ! SB_SDWCR set
|
||||
write32 SDWCR_A, SDWCR_D
|
||||
|
||||
mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
|
||||
mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
|
||||
mov.l r0, @r1 ! SB_SDPCR set
|
||||
write32 SDPCR_A, SDPCR_D
|
||||
|
||||
mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
|
||||
mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
|
||||
mov.l r0, @r1 ! SB_RTCOR set
|
||||
write32 RTCOR_A, RTCOR_D
|
||||
|
||||
mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1
|
||||
mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0
|
||||
mov.l r0, @r1
|
||||
write32 RTCNT_A, RTCNT_D
|
||||
|
||||
mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
|
||||
mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
|
||||
mov.l r0, @r1 ! SB_RTCSR set
|
||||
write32 RTCSR_A, RTCSR_D
|
||||
|
||||
mov.l RFCR_A, r1 ! SB_RFCR address -> R1
|
||||
mov.l RFCR_D, r0 ! SB_RFCR data -> R0
|
||||
mov.l r0, @r1
|
||||
write32 RFCR_A, RFCR_D
|
||||
|
||||
mov.l SDMR3_A, r1 ! SDMR3 address -> R1
|
||||
mov #0x00, r0 ! SDMR3 data -> R0
|
||||
mov.b r0, @r1 ! SDMR3 set
|
||||
write8 SDMR3_A, #0x00
|
||||
|
||||
! BL bit off (init = ON) (?!?)
|
||||
|
||||
|
||||
@ -23,6 +23,7 @@
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
/*
|
||||
* Board specific low level init code, called _very_ early in the
|
||||
@ -38,113 +39,59 @@
|
||||
.align 2
|
||||
|
||||
lowlevel_init:
|
||||
mov.l DRVCRA_A, r1
|
||||
mov.l DRVCRA_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 DRVCRA_A, DRVCRA_D
|
||||
|
||||
mov.l DRVCRB_A, r1
|
||||
mov.l DRVCRB_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 DRVCRB_A, DRVCRB_D
|
||||
|
||||
mov.l RWTCSR_A, r1
|
||||
mov.l RWTCSR_D1, r0
|
||||
mov.w r0, @r1
|
||||
write16 RWTCSR_A, RWTCSR_D1
|
||||
|
||||
mov.l RWTCNT_A, r1
|
||||
mov.l RWTCNT_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 RWTCNT_A, RWTCNT_D
|
||||
|
||||
mov.l RWTCSR_A, r1
|
||||
mov.l RWTCSR_D2, r0
|
||||
mov.w r0, @r1
|
||||
write16 RWTCSR_A, RWTCSR_D2
|
||||
|
||||
mov.l FRQCR_A, r1
|
||||
mov.l FRQCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 FRQCR_A, FRQCR_D
|
||||
|
||||
mov.l CMNCR_A, r1
|
||||
mov.l CMNCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CMNCR_A, CMNCR_D
|
||||
|
||||
mov.l CS0BCR_A, r1
|
||||
mov.l CS0BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS0BCR_A, CS0BCR_D
|
||||
|
||||
mov.l CS4BCR_A, r1
|
||||
mov.l CS4BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS4BCR_A, CS4BCR_D
|
||||
|
||||
mov.l CS5ABCR_A, r1
|
||||
mov.l CS5ABCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5ABCR_A, CS5ABCR_D
|
||||
|
||||
mov.l CS5BBCR_A, r1
|
||||
mov.l CS5BBCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5BBCR_A, CS5BBCR_D
|
||||
|
||||
mov.l CS6ABCR_A, r1
|
||||
mov.l CS6ABCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6ABCR_A, CS6ABCR_D
|
||||
|
||||
mov.l CS6BBCR_A, r1
|
||||
mov.l CS6BBCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6BBCR_A, CS6BBCR_D
|
||||
|
||||
mov.l CS0WCR_A, r1
|
||||
mov.l CS0WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS0WCR_A, CS0WCR_D
|
||||
|
||||
mov.l CS4WCR_A, r1
|
||||
mov.l CS4WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS4WCR_A, CS4WCR_D
|
||||
|
||||
mov.l CS5AWCR_A, r1
|
||||
mov.l CS5AWCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5AWCR_A, CS5AWCR_D
|
||||
|
||||
mov.l CS5BWCR_A, r1
|
||||
mov.l CS5BWCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5BWCR_A, CS5BWCR_D
|
||||
|
||||
mov.l CS6AWCR_A, r1
|
||||
mov.l CS6AWCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6AWCR_A, CS6AWCR_D
|
||||
|
||||
mov.l CS6BWCR_A, r1
|
||||
mov.l CS6BWCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6BWCR_A, CS6BWCR_D
|
||||
|
||||
mov.l SBSC_SDCR_A, r1
|
||||
mov.l SBSC_SDCR_D1, r0
|
||||
mov.l r0, @r1
|
||||
write32 SBSC_SDCR_A, SBSC_SDCR_D1
|
||||
|
||||
mov.l SBSC_SDWCR_A, r1
|
||||
mov.l SBSC_SDWCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SBSC_SDWCR_A, SBSC_SDWCR_D
|
||||
|
||||
mov.l SBSC_SDPCR_A, r1
|
||||
mov.l SBSC_SDPCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SBSC_SDPCR_A, SBSC_SDPCR_D
|
||||
|
||||
mov.l SBSC_RTCSR_A, r1
|
||||
mov.l SBSC_RTCSR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SBSC_RTCSR_A, SBSC_RTCSR_D
|
||||
|
||||
mov.l SBSC_RTCNT_A, r1
|
||||
mov.l SBSC_RTCNT_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SBSC_RTCNT_A, SBSC_RTCNT_D
|
||||
|
||||
mov.l SBSC_RTCOR_A, r1
|
||||
mov.l SBSC_RTCOR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SBSC_RTCOR_A, SBSC_RTCOR_D
|
||||
|
||||
mov.l SBSC_SDMR3_A1, r1
|
||||
mov.l SBSC_SDMR3_D, r0
|
||||
mov.b r0, @r1
|
||||
write8 SBSC_SDMR3_A1, SBSC_SDMR3_D
|
||||
|
||||
mov.l SBSC_SDMR3_A2, r1
|
||||
mov.l SBSC_SDMR3_D, r0
|
||||
mov.b r0, @r1
|
||||
write8 SBSC_SDMR3_A2, SBSC_SDMR3_D
|
||||
|
||||
mov.l SLEEP_CNT, r1
|
||||
2: tst r1, r1
|
||||
@ -152,17 +99,11 @@ lowlevel_init:
|
||||
bf/s 2b
|
||||
dt r1
|
||||
|
||||
mov.l SBSC_SDMR3_A3, r1
|
||||
mov.l SBSC_SDMR3_D, r0
|
||||
mov.b r0, @r1
|
||||
write8 SBSC_SDMR3_A3, SBSC_SDMR3_D
|
||||
|
||||
mov.l SBSC_SDCR_A, r1
|
||||
mov.l SBSC_SDCR_D2, r0
|
||||
mov.l r0, @r1
|
||||
write32 SBSC_SDCR_A, SBSC_SDCR_D2
|
||||
|
||||
mov.l CCR_A, r1
|
||||
mov.l CCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CCR_A, CCR_D
|
||||
|
||||
! BL bit off (init = ON) (?!?)
|
||||
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
#include <version.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
.global lowlevel_init
|
||||
.text
|
||||
@ -15,73 +16,39 @@
|
||||
|
||||
lowlevel_init:
|
||||
|
||||
mov.l CCR_A, r1
|
||||
mov.l CCR_D_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CCR_A, CCR_D_D
|
||||
|
||||
mov.l MMUCR_A, r1
|
||||
mov.l MMUCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 MMUCR_A, MMUCR_D
|
||||
|
||||
mov.l BCR1_A, r1
|
||||
mov.l BCR1_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BCR1_A, BCR1_D
|
||||
|
||||
mov.l BCR2_A, r1
|
||||
mov.l BCR2_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 BCR2_A, BCR2_D
|
||||
|
||||
mov.l BCR3_A, r1
|
||||
mov.l BCR3_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 BCR3_A, BCR3_D
|
||||
|
||||
mov.l BCR4_A, r1
|
||||
mov.l BCR4_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BCR4_A, BCR4_D
|
||||
|
||||
mov.l WCR1_A, r1
|
||||
mov.l WCR1_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 WCR1_A, WCR1_D
|
||||
|
||||
mov.l WCR2_A, r1
|
||||
mov.l WCR2_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 WCR2_A, WCR2_D
|
||||
|
||||
mov.l WCR3_A, r1
|
||||
mov.l WCR3_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 WCR3_A, WCR3_D
|
||||
|
||||
mov.l PCR_A, r1
|
||||
mov.l PCR_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCR_A, PCR_D
|
||||
|
||||
mov.l LED_A, r1
|
||||
mov #0xff, r0
|
||||
mov.w r0, @r1
|
||||
write16 LED_A, #0xff
|
||||
|
||||
mov.l MCR_A, r1
|
||||
mov.l MCR_D1, r0
|
||||
mov.l r0, @r1
|
||||
write32 MCR_A, MCR_D1
|
||||
|
||||
mov.l RTCNT_A, r1
|
||||
mov.l RTCNT_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 RTCNT_A, RTCNT_D
|
||||
|
||||
mov.l RTCOR_A, r1
|
||||
mov.l RTCOR_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 RTCOR_A, RTCOR_D
|
||||
|
||||
mov.l RFCR_A, r1
|
||||
mov.l RFCR_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 RFCR_A, RFCR_D
|
||||
|
||||
mov.l RTCSR_A, r1
|
||||
mov.l RTCSR_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 RTCSR_A, RTCSR_D
|
||||
|
||||
mov.l SDMR3_A, r1
|
||||
mov #0x55, r0
|
||||
mov.b r0, @r1
|
||||
write8 SDMR3_A, #0x55
|
||||
|
||||
/* Wait DRAM refresh 30 times */
|
||||
mov.l RFCR_A, r1
|
||||
@ -92,21 +59,13 @@ lowlevel_init:
|
||||
cmp/hi r3, r2
|
||||
bf 1b
|
||||
|
||||
mov.l MCR_A, r1
|
||||
mov.l MCR_D2, r0
|
||||
mov.l r0, @r1
|
||||
write32 MCR_A, MCR_D2
|
||||
|
||||
mov.l SDMR3_A, r1
|
||||
mov #0, r0
|
||||
mov.b r0, @r1
|
||||
write8 SDMR3_A, #0
|
||||
|
||||
mov.l IRLMASK_A, r1
|
||||
mov.l IRLMASK_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 IRLMASK_A, IRLMASK_D
|
||||
|
||||
mov.l CCR_A, r1
|
||||
mov.l CCR_D_E, r0
|
||||
mov.l r0, @r1
|
||||
write32 CCR_A, CCR_D_E
|
||||
|
||||
rts
|
||||
nop
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
/*
|
||||
* Board specific low level init code, called _very_ early in the
|
||||
@ -38,63 +39,36 @@
|
||||
|
||||
lowlevel_init:
|
||||
|
||||
mov.l CCR_A, r1 /* Address of Cache Control Register */
|
||||
mov.l CCR_D, r0 /* Instruction Cache Invalidate */
|
||||
mov.l r0, @r1
|
||||
write32 CCR_A, CCR_D /* Address of Cache Control Register */
|
||||
/* Instruction Cache Invalidate */
|
||||
|
||||
mov.l FRQCR_A, r1 /* Frequency control register */
|
||||
mov.l FRQCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 FRQCR_A, FRQCR_D /* Frequency control register */
|
||||
|
||||
/* pin_multi_setting */
|
||||
mov.l BBG_PMMR_A, r1
|
||||
mov.l BBG_PMMR_D_PMSR1, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
|
||||
|
||||
mov.l BBG_PMSR1_A, r1
|
||||
mov.l BBG_PMSR1_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMSR1_A, BBG_PMSR1_D
|
||||
|
||||
mov.l BBG_PMMR_A, r1
|
||||
mov.l BBG_PMMR_D_PMSR2, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
|
||||
|
||||
mov.l BBG_PMSR2_A, r1
|
||||
mov.l BBG_PMSR2_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMSR2_A, BBG_PMSR2_D
|
||||
|
||||
mov.l BBG_PMMR_A, r1
|
||||
mov.l BBG_PMMR_D_PMSR3, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
|
||||
|
||||
mov.l BBG_PMSR3_A, r1
|
||||
mov.l BBG_PMSR3_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMSR3_A, BBG_PMSR3_D
|
||||
|
||||
mov.l BBG_PMMR_A, r1
|
||||
mov.l BBG_PMMR_D_PMSR4, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
|
||||
|
||||
mov.l BBG_PMSR4_A, r1
|
||||
mov.l BBG_PMSR4_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMSR4_A, BBG_PMSR4_D
|
||||
|
||||
mov.l BBG_PMMR_A, r1
|
||||
mov.l BBG_PMMR_D_PMSRG, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
|
||||
|
||||
mov.l BBG_PMSRG_A, r1
|
||||
mov.l BBG_PMSRG_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BBG_PMSRG_A, BBG_PMSRG_D
|
||||
|
||||
/* cpg_setting */
|
||||
mov.l FRQCR_A, r1
|
||||
mov.l FRQCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 FRQCR_A, FRQCR_D
|
||||
|
||||
mov.l DLLCSR_A, r1
|
||||
mov.l DLLCSR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 DLLCSR_A, DLLCSR_D
|
||||
|
||||
nop
|
||||
nop
|
||||
@ -117,69 +91,37 @@ repeat0:
|
||||
nop
|
||||
|
||||
/* bsc_setting */
|
||||
mov.l MMSELR_A, r1
|
||||
mov.l MMSELR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 MMSELR_A, MMSELR_D
|
||||
|
||||
mov.l BCR_A, r1
|
||||
mov.l BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BCR_A, BCR_D
|
||||
|
||||
mov.l CS0BCR_A, r1
|
||||
mov.l CS0BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS0BCR_A, CS0BCR_D
|
||||
|
||||
mov.l CS1BCR_A, r1
|
||||
mov.l CS1BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS1BCR_A, CS1BCR_D
|
||||
|
||||
mov.l CS2BCR_A, r1
|
||||
mov.l CS2BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS2BCR_A, CS2BCR_D
|
||||
|
||||
mov.l CS4BCR_A, r1
|
||||
mov.l CS4BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS4BCR_A, CS4BCR_D
|
||||
|
||||
mov.l CS5BCR_A, r1
|
||||
mov.l CS5BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5BCR_A, CS5BCR_D
|
||||
|
||||
mov.l CS6BCR_A, r1
|
||||
mov.l CS6BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6BCR_A, CS6BCR_D
|
||||
|
||||
mov.l CS0WCR_A, r1
|
||||
mov.l CS0WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS0WCR_A, CS0WCR_D
|
||||
|
||||
mov.l CS1WCR_A, r1
|
||||
mov.l CS1WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS1WCR_A, CS1WCR_D
|
||||
|
||||
mov.l CS2WCR_A, r1
|
||||
mov.l CS2WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS2WCR_A, CS2WCR_D
|
||||
|
||||
mov.l CS4WCR_A, r1
|
||||
mov.l CS4WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS4WCR_A, CS4WCR_D
|
||||
|
||||
mov.l CS5WCR_A, r1
|
||||
mov.l CS5WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5WCR_A, CS5WCR_D
|
||||
|
||||
mov.l CS6WCR_A, r1
|
||||
mov.l CS6WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6WCR_A, CS6WCR_D
|
||||
|
||||
mov.l CS5PCR_A, r1
|
||||
mov.l CS5PCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5PCR_A, CS5PCR_D
|
||||
|
||||
mov.l CS6PCR_A, r1
|
||||
mov.l CS6PCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6PCR_A, CS6PCR_D
|
||||
|
||||
/* ddr_setting */
|
||||
/* wait 200us */
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
#include <version.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
.global lowlevel_init
|
||||
|
||||
@ -29,140 +30,76 @@
|
||||
|
||||
lowlevel_init:
|
||||
/* Cache setting */
|
||||
mov.l CCR1_A, r1
|
||||
mov.l CCR1_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CCR1_A ,CCR1_D
|
||||
|
||||
/* ConfigurePortPins */
|
||||
mov.l PECRL3_A, r1
|
||||
mov.l PECRL3_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PECRL3_A, PECRL3_D
|
||||
|
||||
mov.l PCCRL4_A, r1
|
||||
mov.l PCCRL4_D0, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCCRL4_A, PCCRL4_D0
|
||||
|
||||
mov.l PECRL4_A, r1
|
||||
mov.l PECRL4_D0, r0
|
||||
mov.w r0, @r1
|
||||
write16 PECRL4_A, PECRL4_D0
|
||||
|
||||
mov.l PEIORL_A, r1
|
||||
mov.l PEIORL_D0, r0
|
||||
mov.w r0, @r1
|
||||
write16 PEIORL_A, PEIORL_D0
|
||||
|
||||
mov.l PCIORL_A, r1
|
||||
mov.l PCIORL_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCIORL_A, PCIORL_D
|
||||
|
||||
mov.l PFCRH2_A, r1
|
||||
mov.l PFCRH2_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PFCRH2_A, PFCRH2_D
|
||||
|
||||
mov.l PFCRH3_A, r1
|
||||
mov.l PFCRH3_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PFCRH3_A, PFCRH3_D
|
||||
|
||||
mov.l PFCRH1_A, r1
|
||||
mov.l PFCRH1_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PFCRH1_A, PFCRH1_D
|
||||
|
||||
mov.l PFIORH_A, r1
|
||||
mov.l PFIORH_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PFIORH_A, PFIORH_D
|
||||
|
||||
mov.l PECRL1_A, r1
|
||||
mov.l PECRL1_D0, r0
|
||||
mov.w r0, @r1
|
||||
write16 PECRL1_A, PECRL1_D0
|
||||
|
||||
mov.l PEIORL_A, r1
|
||||
mov.l PEIORL_D1, r0
|
||||
mov.w r0, @r1
|
||||
write16 PEIORL_A, PEIORL_D1
|
||||
|
||||
/* Configure Operating Frequency */
|
||||
mov.l WTCSR_A, r1
|
||||
mov.l WTCSR_D0, r0
|
||||
mov.w r0, @r1
|
||||
write16 WTCSR_A, WTCSR_D0
|
||||
|
||||
mov.l WTCSR_A, r1
|
||||
mov.l WTCSR_D1, r0
|
||||
mov.w r0, @r1
|
||||
write16 WTCSR_A, WTCSR_D1
|
||||
|
||||
mov.l WTCNT_A, r1
|
||||
mov.l WTCNT_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 WTCNT_A, WTCNT_D
|
||||
|
||||
/* Set clock mode*/
|
||||
mov.l FRQCR_A, r1
|
||||
mov.l FRQCR_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 FRQCR_A, FRQCR_D
|
||||
|
||||
/* Configure Bus And Memory */
|
||||
init_bsc_cs0:
|
||||
mov.l PCCRL4_A, r1
|
||||
mov.l PCCRL4_D1, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCCRL4_A, PCCRL4_D1
|
||||
|
||||
mov.l PECRL1_A, r1
|
||||
mov.l PECRL1_D1, r0
|
||||
mov.w r0, @r1
|
||||
write16 PECRL1_A, PECRL1_D1
|
||||
|
||||
mov.l CMNCR_A, r1
|
||||
mov.l CMNCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CMNCR_A, CMNCR_D
|
||||
|
||||
mov.l SC0BCR_A, r1
|
||||
mov.l SC0BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SC0BCR_A, SC0BCR_D
|
||||
|
||||
mov.l CS0WCR_A, r1
|
||||
mov.l CS0WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS0WCR_A, CS0WCR_D
|
||||
|
||||
init_bsc_cs1:
|
||||
mov.l PECRL4_A, r1
|
||||
mov.l PECRL4_D1, r0
|
||||
mov.w r0, @r1
|
||||
write16 PECRL4_A, PECRL4_D1
|
||||
|
||||
mov.l CS1WCR_A, r1
|
||||
mov.l CS1WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS1WCR_A, CS1WCR_D
|
||||
|
||||
init_sdram:
|
||||
mov.l PCCRL2_A, r1
|
||||
mov.l PCCRL2_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCCRL2_A, PCCRL2_D
|
||||
|
||||
mov.l PCCRL4_A, r1
|
||||
mov.l PCCRL4_D2, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCCRL4_A, PCCRL4_D2
|
||||
|
||||
mov.l PCCRL1_A, r1
|
||||
mov.l PCCRL1_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCCRL1_A, PCCRL1_D
|
||||
|
||||
mov.l PCCRL3_A, r1
|
||||
mov.l PCCRL3_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PCCRL3_A, PCCRL3_D
|
||||
|
||||
mov.l CS3BCR_A, r1
|
||||
mov.l CS3BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS3BCR_A, CS3BCR_D
|
||||
|
||||
mov.l CS3WCR_A, r1
|
||||
mov.l CS3WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS3WCR_A, CS3WCR_D
|
||||
|
||||
mov.l SDCR_A, r1
|
||||
mov.l SDCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SDCR_A, SDCR_D
|
||||
|
||||
mov.l RTCOR_A, r1
|
||||
mov.l RTCOR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 RTCOR_A, RTCOR_D
|
||||
|
||||
mov.l RTCSR_A, r1
|
||||
mov.l RTCSR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 RTCSR_A, RTCSR_D
|
||||
|
||||
/* wait 200us */
|
||||
mov.l REPEAT_D, r3
|
||||
|
||||
@ -25,6 +25,7 @@
|
||||
#include <version.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
.global lowlevel_init
|
||||
|
||||
@ -33,44 +34,33 @@
|
||||
|
||||
lowlevel_init:
|
||||
|
||||
mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */
|
||||
mov.l WDTCSR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
|
||||
|
||||
mov.l WDTST_A, r1 /* Watchdog Stop Time Register */
|
||||
mov.l WDTST_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
|
||||
|
||||
mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */
|
||||
mov.l WDTBST_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 WDTBST_A, WDTBST_D /*
|
||||
* 0xFFCC0008
|
||||
* Watchdog Base Stop Time Register
|
||||
*/
|
||||
|
||||
mov.l CCR_A, r1 /* Address of Cache Control Register */
|
||||
mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */
|
||||
mov.l r0, @r1
|
||||
write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
|
||||
/* Instruction Cache Invalidate */
|
||||
|
||||
mov.l MMUCR_A, r1 /* Address of MMU Control Register */
|
||||
mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */
|
||||
mov.l r0, @r1
|
||||
write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
|
||||
/* TI == TLB Invalidate bit */
|
||||
|
||||
mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */
|
||||
mov.l MSTPCR0_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
|
||||
|
||||
mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */
|
||||
mov.l MSTPCR1_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
|
||||
|
||||
mov.l RAMCR_A, r1
|
||||
mov.l RAMCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 RAMCR_A, RAMCR_D
|
||||
|
||||
mov.l MMSELR_A, r1
|
||||
mov.l MMSELR_D, r0
|
||||
synco
|
||||
mov.l r0, @r1
|
||||
|
||||
mov.l @r1, r2 /* execute two reads after setting MMSELR*/
|
||||
mov.l @r1, r2 /* execute two reads after setting MMSELR */
|
||||
mov.l @r1, r2
|
||||
synco
|
||||
|
||||
@ -79,75 +69,47 @@ lowlevel_init:
|
||||
mov.l @r1, r0
|
||||
synco
|
||||
|
||||
mov.l MIM8_A, r1
|
||||
mov.l MIM8_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 MIM8_A, MIM8_D
|
||||
|
||||
mov.l MIMC_A, r1
|
||||
mov.l MIMC_D1, r0
|
||||
mov.l r0, @r1
|
||||
write32 MIMC_A, MIMC_D1
|
||||
|
||||
mov.l STRC_A, r1
|
||||
mov.l STRC_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 STRC_A, STRC_D
|
||||
|
||||
mov.l SDR4_A, r1
|
||||
mov.l SDR4_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SDR4_A, SDR4_D
|
||||
|
||||
mov.l MIMC_A, r1
|
||||
mov.l MIMC_D2, r0
|
||||
mov.l r0, @r1
|
||||
write32 MIMC_A, MIMC_D2
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
mov.l SCR4_A, r1
|
||||
mov.l SCR4_D3, r0
|
||||
mov.l r0, @r1
|
||||
write32 SCR4_A, SCR4_D3
|
||||
|
||||
mov.l SCR4_A, r1
|
||||
mov.l SCR4_D2, r0
|
||||
mov.l r0, @r1
|
||||
write32 SCR4_A, SCR4_D2
|
||||
|
||||
mov.l SDMR02000_A, r1
|
||||
mov.l SDMR02000_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SDMR02000_A, SDMR02000_D
|
||||
|
||||
mov.l SDMR00B08_A, r1
|
||||
mov.l SDMR00B08_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SDMR00B08_A, SDMR00B08_D
|
||||
|
||||
mov.l SCR4_A, r1
|
||||
mov.l SCR4_D2, r0
|
||||
mov.l r0, @r1
|
||||
write32 SCR4_A, SCR4_D2
|
||||
|
||||
mov.l SCR4_A, r1
|
||||
mov.l SCR4_D4, r0
|
||||
mov.l r0, @r1
|
||||
write32 SCR4_A, SCR4_D4
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
mov.l SCR4_A, r1
|
||||
mov.l SCR4_D4, r0
|
||||
mov.l r0, @r1
|
||||
write32 SCR4_A, SCR4_D4
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
mov.l SDMR00308_A, r1
|
||||
mov.l SDMR00308_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 SDMR00308_A, SDMR00308_D
|
||||
|
||||
mov.l MIMC_A, r1
|
||||
mov.l MIMC_D3, r0
|
||||
mov.l r0, @r1
|
||||
write32 MIMC_A, MIMC_D3
|
||||
|
||||
mov.l SCR4_A, r1
|
||||
mov.l SCR4_D1, r0
|
||||
@ -159,70 +121,38 @@ delay_loop_60:
|
||||
bf delay_loop_60
|
||||
nop
|
||||
|
||||
mov.l CCR_A, r1 /* Address of Cache Control Register */
|
||||
mov.l CCR_CACHE_D_2, r0
|
||||
mov.l r0, @r1
|
||||
write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
|
||||
|
||||
bsc_init:
|
||||
mov.l BCR_A, r1
|
||||
mov.l BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 BCR_A, BCR_D
|
||||
|
||||
mov.l CS0BCR_A, r1
|
||||
mov.l CS0BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS0BCR_A, CS0BCR_D
|
||||
|
||||
mov.l CS1BCR_A, r1
|
||||
mov.l CS1BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS1BCR_A, CS1BCR_D
|
||||
|
||||
mov.l CS2BCR_A, r1
|
||||
mov.l CS2BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS2BCR_A, CS2BCR_D
|
||||
|
||||
mov.l CS4BCR_A, r1
|
||||
mov.l CS4BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS4BCR_A, CS4BCR_D
|
||||
|
||||
mov.l CS5BCR_A, r1
|
||||
mov.l CS5BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5BCR_A, CS5BCR_D
|
||||
|
||||
mov.l CS6BCR_A, r1
|
||||
mov.l CS6BCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6BCR_A, CS6BCR_D
|
||||
|
||||
mov.l CS0WCR_A, r1
|
||||
mov.l CS0WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS0WCR_A, CS0WCR_D
|
||||
|
||||
mov.l CS1WCR_A, r1
|
||||
mov.l CS1WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS1WCR_A, CS1WCR_D
|
||||
|
||||
mov.l CS2WCR_A, r1
|
||||
mov.l CS2WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS2WCR_A, CS2WCR_D
|
||||
|
||||
mov.l CS4WCR_A, r1
|
||||
mov.l CS4WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS4WCR_A, CS4WCR_D
|
||||
|
||||
mov.l CS5WCR_A, r1
|
||||
mov.l CS5WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5WCR_A, CS5WCR_D
|
||||
|
||||
mov.l CS6WCR_A, r1
|
||||
mov.l CS6WCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6WCR_A, CS6WCR_D
|
||||
|
||||
mov.l CS5PCR_A, r1
|
||||
mov.l CS5PCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS5PCR_A, CS5PCR_D
|
||||
|
||||
mov.l CS6PCR_A, r1
|
||||
mov.l CS6PCR_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 CS6PCR_A, CS6PCR_D
|
||||
|
||||
mov.l DELAY200_D, r3
|
||||
|
||||
@ -231,17 +161,11 @@ delay_loop_200:
|
||||
bf delay_loop_200
|
||||
nop
|
||||
|
||||
mov.l PSEL0_A, r1
|
||||
mov.l PSEL0_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PSEL0_A, PSEL0_D
|
||||
|
||||
mov.l PSEL1_A, r1
|
||||
mov.l PSEL1_D, r0
|
||||
mov.w r0, @r1
|
||||
write16 PSEL1_A, PSEL1_D
|
||||
|
||||
mov.l ICR0_A, r1
|
||||
mov.l ICR0_D, r0
|
||||
mov.l r0, @r1
|
||||
write32 ICR0_A, ICR0_D
|
||||
|
||||
stc sr, r0 /* BL bit off(init=ON) */
|
||||
mov.l SR_MASK_D, r1
|
||||
|
||||
@ -19,33 +19,7 @@
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
.macro write32, addr, data
|
||||
mov.l \addr ,r1
|
||||
mov.l \data ,r0
|
||||
mov.l r0, @r1
|
||||
.endm
|
||||
|
||||
.macro write16, addr, data
|
||||
mov.l \addr ,r1
|
||||
mov.l \data ,r0
|
||||
mov.w r0, @r1
|
||||
.endm
|
||||
|
||||
.macro write8, addr, data
|
||||
mov.l \addr ,r1
|
||||
mov.l \data ,r0
|
||||
mov.b r0, @r1
|
||||
.endm
|
||||
|
||||
.macro wait_timer, time
|
||||
mov.l \time ,r3
|
||||
1:
|
||||
nop
|
||||
tst r3, r3
|
||||
bf/s 1b
|
||||
dt r3
|
||||
.endm
|
||||
#include <asm/macro.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
|
||||
|
||||
52
include/asm-sh/macro.h
Normal file
52
include/asm-sh/macro.h
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __MACRO_H__
|
||||
#define __MACRO_H__
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
.macro write32, addr, data
|
||||
mov.l \addr ,r1
|
||||
mov.l \data ,r0
|
||||
mov.l r0, @r1
|
||||
.endm
|
||||
|
||||
.macro write16, addr, data
|
||||
mov.l \addr ,r1
|
||||
mov.l \data ,r0
|
||||
mov.w r0, @r1
|
||||
.endm
|
||||
|
||||
.macro write8, addr, data
|
||||
mov.l \addr ,r1
|
||||
mov.l \data ,r0
|
||||
mov.b r0, @r1
|
||||
.endm
|
||||
|
||||
.macro wait_timer, time
|
||||
mov.l \time ,r3
|
||||
1:
|
||||
nop
|
||||
tst r3, r3
|
||||
bf/s 1b
|
||||
dt r3
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __MACRO_H__ */
|
||||
Loading…
Reference in New Issue
Block a user