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3 Commits

Author SHA1 Message Date
Simon Glass
984639039f Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE 
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
 2022-10-31 11:01:31 -04:00
Tianrui Wei
c9135d5a7a riscv: dts: add OpenPiton RISC-V board dts support 
Previous device tree for OpenPiton emits a warning during compilation.
This commit fixes the previous warning adds dts to the OpenPiton RISC-V
board and added the device tree to MAINTAINER file.

Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2021-07-07 20:34:02 +08:00
Tianrui Wei
8a44fe6943 board: riscv: add openpiton-riscv64 SoC support 
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper

Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2021-07-06 13:50:56 +08:00