Added new ext fields to IFC
In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -44,12 +44,18 @@ void init_early_memctl_regs(void)
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set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
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#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
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#ifdef CONFIG_SYS_CSPR0_EXT
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set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT);
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#endif
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set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
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set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
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set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
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#endif
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#endif
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#ifdef CONFIG_SYS_CSPR1_EXT
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set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT);
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#endif
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#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
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set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
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set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
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@ -61,6 +67,9 @@ void init_early_memctl_regs(void)
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set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
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#endif
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#ifdef CONFIG_SYS_CSPR2_EXT
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set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT);
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#endif
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#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
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set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
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set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
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@ -72,6 +81,9 @@ void init_early_memctl_regs(void)
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set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
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#endif
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#ifdef CONFIG_SYS_CSPR3_EXT
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set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT);
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#endif
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#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
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set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
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set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
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@ -783,12 +783,16 @@ extern void init_early_memctl_regs(void);
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#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
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#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
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#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
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#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
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#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
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#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
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#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
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#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
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#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
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#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
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#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
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#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
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#define set_ifc_ftim(i, j, v) \
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@ -909,22 +913,24 @@ struct fsl_ifc_gpcm {
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*/
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struct fsl_ifc {
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u32 ifc_rev;
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u32 res1[0x3];
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u32 res1[0x2];
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struct {
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u32 cspr_ext;
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u32 cspr;
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u32 res2[0x2];
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u32 res2;
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} cspr_cs[FSL_IFC_BANK_COUNT];
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u32 res3[0x18];
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u32 res3[0x19];
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struct {
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u32 amask;
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u32 res4[0x2];
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} amask_cs[FSL_IFC_BANK_COUNT];
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u32 res5[0x18];
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u32 res5[0x17];
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struct {
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u32 csor_ext;
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u32 csor;
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u32 res6[0x2];
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u32 res6;
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} csor_cs[FSL_IFC_BANK_COUNT];
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u32 res7[0x18];
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u32 res7[0x19];
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struct {
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u32 ftim[4];
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u32 res8[0x8];
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