imx: mx8m: add soc related settings and files
Add SoC level initialization code - arch_cpu_init - mmu table - detect cpu revision - reset cpu and wdog settings - timer init - wdog settings - lowlevel init to save/restore registers - a few dummy header file to avoid build failure - ft_system_setup Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
c1ef486327
commit
fcdbde7ce0
10
arch/arm/include/asm/arch-mx8m/crm_regs.h
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10
arch/arm/include/asm/arch-mx8m/crm_regs.h
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@ -0,0 +1,10 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
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#define _ASM_ARCH_MX8M_CRM_REGS_H
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/* Dummy header, some imx-common code needs this file */
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#endif
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12
arch/arm/include/asm/arch-mx8m/gpio.h
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arch/arm/include/asm/arch-mx8m/gpio.h
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX8M_GPIO_H
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#define __ASM_ARCH_MX8M_GPIO_H
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#include <asm/mach-imx/gpio.h>
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#endif
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arch/arm/include/asm/arch-mx8m/sys_proto.h
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arch/arm/include/asm/arch-mx8m/sys_proto.h
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/*
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* Copyright (C) 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARCH_MX8M_SYS_PROTO_H
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#define __ARCH_MX8M_SYS_PROTO_H
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#include <asm/mach-imx/sys_proto.h>
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void set_wdog_reset(struct wdog_regs *wdog);
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void enable_tzc380(void);
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void restore_boot_params(void);
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extern unsigned long rom_pointer[];
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enum boot_device get_boot_device(void);
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bool is_usb_boot(void);
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#endif
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@ -132,4 +132,4 @@ obj-$(CONFIG_MX5) += mx5/
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obj-$(CONFIG_MX6) += mx6/
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obj-$(CONFIG_MX7) += mx7/
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obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
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obj-$(CONFIG_MX8M) += mx8m/
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@ -4,4 +4,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += clock.o clock_slice.o
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obj-y += lowlevel_init.o
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obj-y += clock.o clock_slice.o soc.o
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63
arch/arm/mach-imx/mx8m/lowlevel_init.S
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arch/arm/mach-imx/mx8m/lowlevel_init.S
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@ -0,0 +1,63 @@
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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.align 8
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.global rom_pointer
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rom_pointer:
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.space 256
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/*
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* Routine: save_boot_params (called after reset from start.S)
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*/
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.global save_boot_params
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save_boot_params:
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/* The firmware provided ATAG/FDT address can be found in r2/x0 */
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adr x0, rom_pointer
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stp x1, x2, [x0], #16
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stp x3, x4, [x0], #16
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stp x5, x6, [x0], #16
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stp x7, x8, [x0], #16
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stp x9, x10, [x0], #16
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stp x11, x12, [x0], #16
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stp x13, x14, [x0], #16
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stp x15, x16, [x0], #16
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stp x17, x18, [x0], #16
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stp x19, x20, [x0], #16
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stp x21, x22, [x0], #16
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stp x23, x24, [x0], #16
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stp x25, x26, [x0], #16
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stp x27, x28, [x0], #16
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stp x29, x30, [x0], #16
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mov x30, sp
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str x30, [x0], #8
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/* Returns */
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b save_boot_params_ret
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.global restore_boot_params
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restore_boot_params:
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adr x0, rom_pointer
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ldp x1, x2, [x0], #16
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ldp x3, x4, [x0], #16
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ldp x5, x6, [x0], #16
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ldp x7, x8, [x0], #16
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ldp x9, x10, [x0], #16
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ldp x11, x12, [x0], #16
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ldp x13, x14, [x0], #16
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ldp x15, x16, [x0], #16
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ldp x17, x18, [x0], #16
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ldp x19, x20, [x0], #16
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ldp x21, x22, [x0], #16
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ldp x23, x24, [x0], #16
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ldp x25, x26, [x0], #16
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ldp x27, x28, [x0], #16
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ldp x29, x30, [x0], #16
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ldr x0, [x0]
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mov sp, x0
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ret
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227
arch/arm/mach-imx/mx8m/soc.c
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227
arch/arm/mach-imx/mx8m/soc.c
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/*
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* Copyright 2017 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/hab.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/syscounter.h>
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#include <asm/armv8/mmu.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <fsl_wdog.h>
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#include <imx_sip.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_SECURE_BOOT)
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struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
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.bank = 1,
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.word = 3,
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};
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#endif
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int timer_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
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unsigned long freq = readl(&sctr->cntfid0);
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/* Update with accurate clock frequency */
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asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
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clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
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SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
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#endif
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gd->arch.tbl = 0;
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gd->arch.tbu = 0;
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return 0;
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}
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void enable_tzc380(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable TZASC and lock setting */
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setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
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setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
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}
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void set_wdog_reset(struct wdog_regs *wdog)
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{
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/*
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* Output WDOG_B signal to reset external pmic or POR_B decided by
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* the board design. Without external reset, the peripherals/DDR/
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* PMIC are not reset, that may cause system working abnormal.
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* WDZST bit is write-once only bit. Align this bit in kernel,
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* otherwise kernel code will have no chance to set this bit.
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*/
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setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
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}
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static struct mm_region imx8m_mem_map[] = {
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{
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/* ROM */
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* OCRAM */
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.virt = 0x900000UL,
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.phys = 0x900000UL,
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.size = 0x200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* AIPS */
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.virt = 0xB00000UL,
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.phys = 0xB00000UL,
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.size = 0x3f500000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* DRAM1 */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0xC0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* DRAM2 */
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.virt = 0x100000000UL,
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.phys = 0x100000000UL,
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.size = 0x040000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = imx8m_mem_map;
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u32 get_cpu_rev(void)
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{
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struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
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u32 reg = readl(&ana_pll->digprog);
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u32 type = (reg >> 16) & 0xff;
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u32 rom_version;
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reg &= 0xff;
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if (reg == CHIP_REV_1_0) {
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/*
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* For B0 chip, the DIGPROG is not updated, still TO1.0.
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* we have to check ROM version further
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*/
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rom_version = readl((void __iomem *)ROM_VERSION_A0);
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if (rom_version != CHIP_REV_1_0) {
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rom_version = readl((void __iomem *)ROM_VERSION_B0);
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if (rom_version >= CHIP_REV_2_0)
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reg = CHIP_REV_2_0;
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}
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}
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return (type << 12) | reg;
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}
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static void imx_set_wdog_powerdown(bool enable)
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{
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struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
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struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
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struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
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/* Write to the PDE (Power Down Enable) bit */
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writew(enable, &wdog1->wmcr);
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writew(enable, &wdog2->wmcr);
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writew(enable, &wdog3->wmcr);
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}
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int arch_cpu_init(void)
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{
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/*
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* Init timer at very early state, because sscg pll setting
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* will use it
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*/
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timer_init();
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if (IS_ENABLED(CONFIG_SPL_BUILD)) {
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clock_init();
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imx_set_wdog_powerdown(false);
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}
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return 0;
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}
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bool is_usb_boot(void)
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{
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return get_boot_device() == USB_BOOT;
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}
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#ifdef CONFIG_OF_SYSTEM_SETUP
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int ft_system_setup(void *blob, bd_t *bd)
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{
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int i = 0;
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int rc;
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int nodeoff;
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/* Disable the CPU idle for A0 chip since the HW does not support it */
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if (is_soc_rev(CHIP_REV_1_0)) {
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static const char * const nodes_path[] = {
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"/cpus/cpu@0",
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"/cpus/cpu@1",
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"/cpus/cpu@2",
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"/cpus/cpu@3",
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};
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for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
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nodeoff = fdt_path_offset(blob, nodes_path[i]);
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if (nodeoff < 0)
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continue; /* Not found, skip it */
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printf("Found %s node\n", nodes_path[i]);
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rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
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if (rc) {
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printf("Unable to update property %s:%s, err=%s\n",
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nodes_path[i], "status", fdt_strerror(rc));
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return rc;
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}
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printf("Remove %s:%s\n", nodes_path[i],
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"cpu-idle-states");
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}
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}
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return 0;
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}
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#endif
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void reset_cpu(ulong addr)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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/* Clear WDA to trigger WDOG_B immediately */
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writew((WCR_WDE | WCR_SRS), &wdog->wcr);
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while (1) {
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/*
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* spin for .5 seconds before reset
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*/
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}
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}
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