riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.

When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

arch/riscv/cpu/cpu.c

@@ -15,7 +15,9 @@
  * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
+#ifdef CONFIG_OF_PRIOR_STAGE
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
 #ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 

arch/riscv/cpu/start.S

@@ -111,8 +111,10 @@ call_board_init_f_0:
 	bnez	tp, secondary_hart_loop
 #endif
 
+#ifdef CONFIG_OF_PRIOR_STAGE
 	la	t0, prior_stage_fdt_address
 	SREG	s1, 0(t0)
+#endif
 
 	jal	board_init_f_init_reserve